Solar cell and method of manufacturing the same, photovoltaic module
By employing a resonant tunneling structure and a complete passivation layer in the TOPCon battery, the problems of insufficient electron transport efficiency and passivation quality are solved, series resistance and diffusion defects are reduced, battery efficiency is improved, and production costs are controlled.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JINKO SOLAR (HAINING) CO LTS
- Filing Date
- 2023-01-03
- Publication Date
- 2026-07-21
AI Technical Summary
Existing TOPCon cells have shortcomings in electron transport efficiency and passivation quality, and their production costs are high. Furthermore, phosphorus diffusion and metal burn-through problems are prone to occur after the polycrystalline silicon layer is thinned, leading to a decrease in cell efficiency.
A first oxide layer and a second oxide layer with different via densities are sequentially stacked on a silicon substrate to form a resonant tunneling structure. The high-density vias improve electron transport efficiency, and a complete passivation layer is formed through the second oxide layer to hinder phosphorus diffusion and metal burn-through.
It improves electron transport efficiency, reduces series resistance and diffusion defect density, enhances passivation quality, reduces production costs, avoids phosphorus diffusion and metal burn-through problems, and improves battery efficiency.
Smart Images
Figure CN115863452B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of photovoltaic technology, and more specifically, to a solar cell, a method for preparing the same, and a photovoltaic module. Background Technology
[0002] TOPCon cells (short for Tunnel Oxide Passivated Contact) are fabricated using a tubular LPCVD (Low Pressure Chemical Vapor Deposition) device. The tunnel oxide layer and the doped polycrystalline silicon layer together form the passivation contact structure. This tunnel oxide passivation contact structure allows majority carriers to pass through the oxide layer while blocking minority carriers, effectively achieving selective carrier passage and thus greatly reducing the recombination rate of minority carriers and improving the cell efficiency.
[0003] The current TOPCon battery structure design has the following two problems: First, from a technical perspective, when the battery absorbs light energy and generates photogenerated carriers, these carriers separate at the pn junction. Positive charges are collected by the front electrode, and negative charges are collected by the back electrode. However, there are many obstacles when negative charges flow from the pn junction to the back electrode. Among these obstacles, the tunneling oxide layer SiO2 is particularly prominent. X Electrons tunnel through the SiO oxide layer X It conforms to the Schrödinger uncertainty principle, exhibiting randomness and chance. This randomness and chance in electron passage is related to the tunneling of the SiO oxide layer. X The increase in thickness leads to a decrease in series resistance, which is reflected in macroscopic data. Therefore, reducing series resistance is a crucial way to improve the efficiency of TOPCon cells. Secondly, from a cost perspective, TOPCon cell production typically involves depositing a polycrystalline silicon (poly-Si) layer using LPCVD. The raw material, silane, is expensive, and a thicker poly-Si layer has a strong parasitic absorption effect. Thinning the poly-Si layer is therefore essential for cost reduction and efficiency improvement. However, thinning the poly-Si layer presents several problems. First, after thinning, during subsequent phosphorus diffusion, if the temperature, pressure, and time are not properly controlled, phosphorus atoms can penetrate the tunnel oxide layer into the silicon substrate. These phosphorus atoms are in an inactive state, forming intermediate energy levels and generating Shockley-Ryder-Hall recombination (SRH recombination), reducing minority carrier lifetime and thus cell efficiency. Second, after thinning the poly-Si layer, during subsequent metal sintering, temperature changes and limitations of the metal paste material can cause the metal to burn through into the substrate, forming intermediate energy levels and generating SRH recombination, further reducing minority carrier lifetime and cell efficiency.
[0004] Therefore, there is an urgent need to provide a solar cell and its preparation method, as well as a photovoltaic module, that can not only improve electron transport efficiency and reduce series resistance, but also improve passivation quality and prevent phosphorus from entering the silicon substrate. Summary of the Invention
[0005] In view of this, the present invention provides a solar cell, comprising a silicon substrate, a first electrode, and a second electrode;
[0006] One side of the silicon substrate is provided with a first oxide layer, a semiconductor layer, a second oxide layer, a polysilicon layer and a first passivation layer stacked sequentially along a direction away from the silicon substrate. Both the first oxide layer and the second oxide layer have vias, and the via density in the first oxide layer is greater than the via density in the second oxide layer.
[0007] The first electrode penetrates the first passivation layer and is electrically connected to the polysilicon layer; alternatively, the first electrode sequentially penetrates the first passivation layer, the polysilicon layer, and the second oxide layer and is electrically connected to the semiconductor layer.
[0008] The silicon substrate includes a base region and an emitter, the emitter being located on the side of the base region away from the first oxide layer; a second passivation layer is disposed on the side of the emitter away from the base region.
[0009] The second electrode penetrates the second passivation layer and is electrically connected to the emitter.
[0010] Optionally, the first oxide layer has a first region and a second region, wherein in a direction perpendicular to the silicon substrate, the first region at least partially overlaps with the first electrode, and the second region does not overlap with the second electrode, and the via density in the first region is greater than the via density in the second region.
[0011] Optionally, the pore density in the first oxide layer is in the range of 10. 8 ~10 12 cm -2 .
[0012] Optionally, the diameter of the vias in the first oxide layer ranges from 1 to 100 nm.
[0013] Optionally, the semiconductor layer is polycrystalline silicon, silicon carbide, or a germanium-silicon alloy.
[0014] Optionally, the thickness of the semiconductor layer in a direction perpendicular to the silicon substrate ranges from 1 to 3 nm.
[0015] Optionally, the thickness of the polycrystalline silicon layer is 30-200 nm along a direction perpendicular to the silicon substrate.
[0016] Optionally, the thickness of the first oxide layer and the second oxide layer ranges from 0.5 to 2 nm along a direction perpendicular to the silicon substrate.
[0017] This invention also provides a method for preparing a solar cell, comprising the following steps:
[0018] 1) Cleaning and texturing the silicon substrate;
[0019] 2) Boron diffusion;
[0020] 3) Remove the BSG from the back;
[0021] 4) Alkali polishing on the back;
[0022] 5) A first oxide layer is deposited on the back side, and then the first oxide layer is annealed;
[0023] 6) Backside fabrication: On the side of the first oxide layer away from the silicon substrate, a semiconductor layer, a second oxide layer, and a polysilicon layer are sequentially deposited;
[0024] 7) Remove the polysilicon layer coating on the front side;
[0025] 8) Backside doping;
[0026] 9) Annealing to crystallize the polycrystalline silicon layer and activate impurities;
[0027] 10) Coating on both sides;
[0028] 11) Generate the first electrode and the second electrode.
[0029] The present invention also provides a photovoltaic module, comprising stacked glass, a first encapsulating film, a battery string, a second encapsulating film and a backsheet, wherein the battery string is formed by electrically connecting multiple solar cells as described above.
[0030] Compared with the prior art, the solar cell, its preparation method, and photovoltaic module provided by the present invention achieve at least the following beneficial effects:
[0031] The solar cell and its fabrication method, as well as the photovoltaic module provided in this invention, have a first oxide layer, a semiconductor layer, a second oxide layer, a polycrystalline silicon layer, and a first passivation layer sequentially stacked on one side of a silicon substrate along a direction away from the silicon substrate. Both the first and second oxide layers have through holes, with the through hole density in the first oxide layer being greater than that in the second oxide layer. Resonant tunneling is formed by the first and second oxide layers. Based on the resonant tunneling, a high density of through holes is formed by the first oxide layer. The high density of through holes improves electron transport efficiency, thereby reducing series resistance, increasing the cell fill factor and cell efficiency, while also reducing diffusion defect density and improving passivation quality. A complete passivation layer is formed by the second oxide layer, thereby ensuring passivation quality. At the same time, the two oxide layers form a wall-like structure during phosphorus diffusion, which can prevent phosphorus from entering the silicon substrate and also prevent metal sintering burn-through.
[0032] Of course, any product implementing this invention does not necessarily need to achieve all of the technical effects described above at the same time.
[0033] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description
[0034] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.
[0035] Figure 1 This is a schematic diagram of a solar cell structure provided by the present invention;
[0036] Figure 2 This is a schematic diagram of a structure of the first oxide layer provided by the present invention;
[0037] Figure 3 This is a schematic diagram of a structure of the second oxide layer provided by the present invention;
[0038] Figure 4 This is another structural schematic diagram of the solar cell provided by the present invention;
[0039] Figure 5 This is a schematic diagram of a structure of the first region in the first oxide layer provided by the present invention;
[0040] Figure 6 This is a schematic diagram of a structure of the second region in the first oxide layer provided by the present invention;
[0041] Figure 7 This is a schematic flowchart of a method for preparing a solar cell provided by the present invention;
[0042] Figure 8This is a schematic diagram of a photovoltaic module provided by the present invention. Detailed Implementation
[0043] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values of the components and steps set forth in these embodiments do not limit the scope of the invention.
[0044] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.
[0045] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.
[0046] In all the examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.
[0047] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.
[0048] Figure 1 This is a schematic diagram of a solar cell structure provided by the present invention; Figure 2 This is a schematic diagram of a structure of the first oxide layer provided by the present invention; Figure 3 This is a schematic diagram of a structure of the second oxide layer provided by the present invention; Figure 4 This is another structural schematic diagram of the solar cell provided by the present invention; see also Figures 1-4 As shown, this embodiment provides a solar cell, including: a silicon substrate 1, a first electrode 2, and a second electrode 3;
[0049] On one side of the silicon substrate 1, along the direction away from the silicon substrate 1, a first oxide layer 10, a semiconductor layer 11, a second oxide layer 12, a polysilicon layer 13 and a first passivation layer 14 are stacked in sequence. The first oxide layer 10 and the second oxide layer 12 both have through holes 110. The density of through holes 110 in the first oxide layer 10 is greater than the density of through holes 110 in the second oxide layer 12.
[0050] The first electrode 2 passes through the first passivation layer 14 and is electrically connected to the polysilicon layer 13, or the first electrode 2 sequentially passes through the first passivation layer 14, the polysilicon layer 13, and the second oxide layer 12 and is electrically connected to the semiconductor layer 11.
[0051] The silicon substrate 1 includes a base region 15 and an emitter 16, with the emitter 16 located on the side of the base region 15 away from the first oxide layer 10; a second passivation layer 17 is disposed on the side of the emitter 16 away from the base region 15.
[0052] The second electrode 3 penetrates the second passivation layer 17 and is electrically connected to the emitter 16.
[0053] Specifically, the solar cell can be a TOPCon cell, including a silicon substrate 1, which can be an N-type silicon substrate, a first electrode 2, and a second electrode 3;
[0054] On one side of a silicon substrate 1, along a direction away from the silicon substrate 1, a first oxide layer 10, a semiconductor layer 11, a second oxide layer 12, a polysilicon layer 13, and a first passivation layer 14 are sequentially stacked. Both the first oxide layer 10 and the second oxide layer 12 have vias 110, with a higher density of vias 110 in the first oxide layer 10 than in the second oxide layer 12. Both the first oxide layer 10 and the second oxide layer 12 can be tunneling oxides. The semiconductor layer 11 is made of polysilicon, silicon carbide, or a germanium-silicon alloy. To reduce series resistance, it is necessary to... Introducing a resonant tunneling double-barrier two-dimensional quantum well passivation contact is an effective method. In this embodiment, resonant tunneling is formed by the first oxide layer 10 and the second oxide layer 12. Resonant tunneling is the process by which electrons pass through the quasi-bound energy levels in the double-barrier quantum well without loss. There are three main conditions for the realization of resonant tunneling: (1) the two quantum well layers have the same thickness to ensure the matching of quantum energy level positions; (2) the Fermi level of the quantum well layer cannot be pinned to the Fermi level of the adjacent electrode; (3) the voltage dropped on the intermediate barrier layer must be very small to ensure the matching of the two layers. The quantum well state energy levels in the quantum well are aligned. Based on resonant tunneling, the first oxide layer 10 is optimized to form high-density vias 110. These vias 110 can be small-diameter pinholes. The high-density vias 110 improve electron transport efficiency while reducing diffusion defect density and improving passivation quality. Through this quantum well, similar to a sandwich structure, the first oxide layer 10 is rapidly heated and cooled to form high-density vias 110, allowing electrons to pass through more effectively. Meanwhile, the intact second oxide layer 12 provides better passivation. This process ensures smooth electron transport. In other words, the high-density vias 110 on the first oxide layer 10 form pinhole tunneling. This pinhole tunneling facilitates the transport of a small number of charge carriers, which will increase the forward current and reverse saturation current. When a certain number of charge carriers pass through the vias 110 of the first oxide layer 10, the current density versus voltage JV characteristic curve will exhibit linear or ohmic behavior. When the second oxide layer 12 is introduced, it acts as a barrier, which can also reduce the diffusion defect density and improve the passivation quality to a certain extent.
[0055] In summary, in the two tunneling oxide layers mentioned above, the first oxide layer 10 forms high-density vias 110, which improves electron transport efficiency. The second oxide layer 12 forms a complete passivation layer, thereby ensuring passivation quality. At the same time, the two tunneling oxide layers also act as a resonant tunnel double barrier, allowing electrons to pass through without loss, thus improving electron transport efficiency.
[0056] Because the first oxide layer 10 has a high density of vias 110, forming pinhole tunneling, when pinhole tunneling is combined with resonant tunneling, it will have an additional chemical reaction. For example, if the semiconductor layer 11 is polycrystalline silicon, the P concentration of the silicon substrate 1 is five orders of magnitude different from the P-doped polycrystalline silicon concentration. Through resonant tunneling, that is, by introducing vias 110 in the first oxide layer 10, the P concentration at the junction of the first oxide layer 10 and the silicon substrate 1 is increased accordingly, and the Fermi level potential difference at that point is increased accordingly, so as to better satisfy the resonant tunneling condition (2). The resonant tunneling condition (2) is that the Fermi level of the quantum well layer cannot be pinned to the Fermi level of the adjacent electrode.
[0057] like Figure 1 As shown, the first electrode 2 can penetrate the first passivation layer 14 and be electrically connected to the polysilicon layer 13, forming a good ohmic contact between the first electrode 2 and the polysilicon layer 13, which is beneficial for carrier transport; or,
[0058] like Figure 4 As shown, the first electrode 2 can also pass through the first passivation layer 14, the polysilicon layer 13 and the second oxide layer 12 in sequence and be electrically connected to the semiconductor layer 11. The first electrode 2 and the semiconductor layer 11 form a good ohmic contact, which is beneficial to the transport of charge carriers.
[0059] A silicon substrate 1 is placed in a tubular LPCVD chamber, and a second passivation layer 17 is deposited on the front side of the silicon substrate 1. A second electrode 3 penetrates the second passivation layer 17 and is electrically connected to an emitter 16. Along the direction away from the base region 15, the second passivation layer 17 may include an aluminum oxide layer 171 and a silicon nitride layer 172 stacked sequentially. That is, the silicon substrate 1 is placed in a tubular LPCVD chamber, and an aluminum oxide layer 171 and a silicon nitride layer 172 are deposited sequentially on the front side of the silicon substrate 1. The second electrode 3 penetrates the silicon nitride layer 172 and the aluminum oxide layer 171 sequentially and is electrically connected to the emitter 16.
[0060] As can be seen from the above embodiments, the solar cell provided in this embodiment achieves at least the following beneficial effects:
[0061] The solar cell provided in this embodiment has a first oxide layer 10, a semiconductor layer 11, a second oxide layer 12, a polycrystalline silicon layer 13, and a first passivation layer 14 sequentially stacked on one side of a silicon substrate 1 along a direction away from the silicon substrate 1. Both the first oxide layer 10 and the second oxide layer 12 have through holes 110. The density of through holes 110 in the first oxide layer 10 is greater than that in the second oxide layer 12. Resonant tunneling is formed by the first oxide layer 10 and the second oxide layer 12. Based on the resonant tunneling, the first oxide layer 10 forms a high density of through holes 110. The high density of through holes 110 improves electron transport efficiency, thereby reducing series resistance, increasing the cell fill factor and cell efficiency, and also reducing diffusion defect density and improving passivation quality. The second oxide layer 12 forms a complete passivation layer, thereby ensuring passivation quality. At the same time, the two oxide layers form a wall-like structure during phosphorus diffusion, which can prevent phosphorus from entering the silicon substrate 1 and also prevent metal sintering burn-through.
[0062] In some alternative embodiments, Figure 5 This is a schematic diagram of a structure of the first region in the first oxide layer provided by the present invention; Figure 6 This is a schematic diagram of a structure of the second region in the first oxide layer provided by the present invention; see reference. Figures 5-6 As shown, in this embodiment, the first oxide layer 10 has a first region 120 and a second region 130. In the direction perpendicular to the silicon substrate 1, the first region 120 overlaps at least partially with the first electrode 2, and the second region 130 does not overlap with the second electrode 3. The density of vias 110 in the first region 120 is greater than the density of vias 110 in the second region 130.
[0063] Specifically, the first oxide layer 10 is subdivided into a first region 120 and a second region 130. In the direction perpendicular to the silicon substrate 1, the first region 120 can partially overlap with the first electrode 2, while the second region 130 does not overlap with the second electrode 3. The density of through holes 110 in the first region 120 is greater than that in the second region 130. Since the first region 120 overlaps with the first electrode 2 at least partially, it is more conducive to the transport of charge carriers, further improving the electron transport efficiency, thereby improving the efficiency of the solar cell.
[0064] In some alternative embodiments, reference continues to be made to... Figure 2 As shown, the density range of the through-holes 110 in the first oxide layer 10 is 10. 8 cm -2 ~10 12 cm -2 .
[0065] Specifically, the through-holes 110 in the first oxide layer 10 can be high-density, small-diameter pinholes. If the density of the through-holes 110 in the first oxide layer 10 is less than 10...8 cm -2 This reduces electron transport efficiency, which is detrimental to reducing series resistance. If the density of vias 110 in the first oxide layer 10 is higher than 10... 12 cm -2 This leads to a high density of defects, which in turn causes a decrease in passivation quality. Therefore, the density range of vias 110 in the first oxide layer 10 is designed to be within 10. 8 ~10 12 cm -2 This not only improves electron transport efficiency, thus reducing series resistance, but also reduces diffusion defect density, thereby improving passivation quality. Specifically, the density of vias 110 in the first oxide layer 10 can be 10-1. 8 cm -2 10 9 cm -2 10 10 cm -2 10 11 cm -2 Or 10 12 cm -2 .
[0066] In some alternative embodiments, reference continues to be made to... Figure 2 As shown, the diameter of the through-hole 110 in the first oxide layer 10 ranges from 1 nm to 100 nm.
[0067] Specifically, if the diameter of the via 110 in the first oxide layer 10 is less than 1 nm, or if the diameter of the via 110 in the first oxide layer 10 is greater than 100 nm, the P concentration at the junction of the first oxide layer 10 and the silicon substrate 1 will be reduced accordingly, and the Fermi level potential difference at that location will be reduced accordingly, which is not conducive to satisfying the resonance tunneling condition (2). Therefore, designing the diameter range of the via 110 in the first oxide layer 10 to be between 1 nm and 100 nm can not only increase the P concentration at the junction of the first oxide layer 10 and the silicon substrate 1, but also increase the Fermi level potential difference at that location, thus better satisfying the resonance tunneling condition (2). Specifically, the diameter of the via 110 in the first oxide layer 10 can be 1 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm.
[0068] In some alternative embodiments, reference continues to be made to... Figure 1 and Figure 4 As shown, the thickness of the semiconductor layer 11 ranges from 1 nm to 3 nm along the direction perpendicular to the silicon substrate 1.
[0069] Specifically, along the direction perpendicular to the silicon substrate 1, if the thickness of the semiconductor layer 11 is less than 1 nm, or if the thickness of the semiconductor layer 11 is greater than 3 nm, the resonant tunneling condition (3) cannot be satisfied. The resonant tunneling condition (3) requires that the voltage dropped on the intermediate barrier layer must be very small in order to ensure that the quantum well state energy level positions in the two quantum wells are aligned. Therefore, the thickness of the semiconductor layer 11 along the direction perpendicular to the silicon substrate 1 is designed to be in the range of 1 nm to 3 nm, which can satisfy the above resonant tunneling condition (3). Specifically, the thickness of the semiconductor layer 11 along the direction perpendicular to the silicon substrate 1 can be 1 nm, 2 nm or 3 nm.
[0070] In some alternative embodiments, reference continues to be made to... Figure 1 and Figure 4 As shown, the thickness of the polycrystalline silicon layer 13 along the direction perpendicular to the silicon substrate 1 ranges from 30 to 200 nm.
[0071] Specifically, by using a semiconductor layer 11 and a polysilicon layer 13, the total thickness of the polysilicon layer 13 can be reduced. The semiconductor layer 11 is located between the first oxide layer 10 and the second oxide layer 12. If the thickness of the polysilicon layer 13 is less than 30 nm along a direction perpendicular to the silicon substrate 1, on the one hand, phosphorus will tunnel through the oxide layer into the silicon substrate. These phosphorus atoms are in an inactive state, forming intermediate energy levels and generating SRH recombination, reducing minority carrier lifetime and thus reducing battery efficiency. On the other hand, during subsequent metal sintering, temperature changes and limitations of the metal paste material can cause the metal to burn through to the substrate layer, forming intermediate energy levels and generating SRH recombination, reducing minority carrier lifetime and battery efficiency. If the thickness of the polysilicon layer 13 is less than 30 nm along a direction perpendicular to the silicon substrate 1, on the other hand, this will allow phosphorus to tunnel through the oxide layer into the silicon substrate. These phosphorus atoms, being in an inactive state, will form intermediate energy levels, generating SRH recombination, reducing minority carrier lifetime and reducing battery efficiency. If the thickness of the polycrystalline silicon layer 13 is greater than 200 nm in the direction of the substrate 1, it will increase the cost and prolong the process time. Therefore, the thickness of the polycrystalline silicon layer 13 in the direction perpendicular to the silicon substrate 1 is designed to be 30-200 nm. This not only prevents phosphorus from passing through the tunneling oxide layer into the silicon substrate, but also prevents the metal from burning through to the substrate layer due to temperature changes and the limitations of the metal paste material during subsequent metal sintering, thereby avoiding SRH recombination, increasing minority carrier lifetime, and improving cell efficiency, but also reduces the cost and shortens the process time. Specifically, the thickness of the polycrystalline silicon layer 13 in the direction perpendicular to the silicon substrate 1 can be 30 nm, 50 nm, 100 nm, 150 nm or 200 nm.
[0072] In some alternative embodiments, reference continues to be made to... Figure 1 and Figure 4 As shown, along the direction perpendicular to the silicon substrate 1, the thickness of the first oxide layer 10 and the second oxide layer 12 ranges from 0.5 nm to 2 nm.
[0073] Specifically, along the direction perpendicular to the silicon substrate 1, the thickness of the first oxide layer 10 is the same as the thickness of the second oxide layer 12, so that it can better satisfy the resonant tunneling condition (1). The resonant tunneling condition (1) is that the thickness of the two quantum well layers is the same to ensure the matching of quantum energy level positions.
[0074] If the thickness of the first oxide layer 10 is less than 0.5 nm or greater than 2 nm along the direction perpendicular to the silicon substrate 1, it is not conducive to forming a high density of pinholes in the first oxide layer 10, thus affecting the reduction of series resistance. Therefore, the thickness of the first oxide layer 10 along the direction perpendicular to the silicon substrate 1 is designed to be in the range of 0.5 nm to 2 nm, which is conducive to forming a high density of pinholes in the first oxide layer 10, reducing series resistance, and increasing photocurrent.
[0075] If the thickness of the second oxide layer 12 is less than 0.5 nm or greater than 2 nm along the direction perpendicular to the silicon substrate 1, it will be detrimental to the barrier function of the second oxide layer 12, reducing passivation quality and increasing cost. Therefore, the thickness range of the second oxide layer 12 along the direction perpendicular to the silicon substrate 1 is designed to be 0.5 nm to 2 nm, which is beneficial for the second oxide layer 12 to play a barrier function, reducing passivation quality and cost.
[0076] Figure 7 This is a schematic flowchart of a method for preparing a solar cell provided by the present invention; see reference. Figure 7 As shown, this embodiment provides a method for preparing a solar cell, including the following steps:
[0077] 1) Cleaning and texturing the silicon substrate;
[0078] 2) Boron diffusion;
[0079] 3) Remove the BSG from the back;
[0080] 4) Alkali polishing on the back;
[0081] 5) A first oxide layer is deposited on the back side, and then the first oxide layer is annealed;
[0082] 6) Backside fabrication: On the side of the first oxide layer away from the silicon substrate, a semiconductor layer, a second oxide layer, and a polysilicon layer are sequentially deposited;
[0083] 7) Remove the polysilicon layer coating on the front side;
[0084] 8) Backside doping;
[0085] 9) Annealing, which crystallizes the polycrystalline silicon layer and activates impurities;
[0086] 10) Coating on both sides;
[0087] 11) Generate the first electrode and the second electrode.
[0088] Specifically, this embodiment also provides a method for fabricating a solar cell. This method can be a TOPCon cell fabrication method, using an n-type monocrystalline silicon wafer with a resistivity range of 0.8–1.5 Ohm·cm and a minority carrier lifetime >2.5 ms. The damaged layer on the silicon wafer surface is removed in a mixed solution of KOH and H₂O₂, followed by texturing in a KOH solution to form a pyramidal textured surface. The size of the pyramidal textured surface is controlled to be 1–5 µm. After texturing, the emitter is fabricated on the front side of the silicon wafer using boron diffusion, with a sheet resistance of 110–150 Ohm·cm and a front-side BSG thickness of 50–120 nm. m. After removing BSG from the back side of the silicon wafer, alkaline polishing is performed to achieve a reflectivity greater than 40% on the back side. Following alkaline polishing, a first oxide layer is deposited on the back side using LPCVD. This first oxide layer is then oxidized and annealed to form high-density, small-aperture vias. The oxidizing and annealing time ranges from 30 to 120 minutes, and the oxidizing and annealing temperature ranges from 600°C to 1100°C. A semiconductor layer, a second oxide layer, and a polysilicon layer are sequentially deposited on the side of the first oxide layer away from the silicon substrate using LPCVD on the back side. After the polysilicon layer deposition is complete, the front-side polysilicon layer (with BSG as a barrier layer) is removed using alkaline washing.
[0089] The silicon wafer is then placed flat on a carrier plate, and a liquid dopant containing phosphorus (P) is rolled onto the back side of the wafer. It is then dried at 100–200°C for 10–120 seconds. Annealing is then performed in a tube furnace to crystallize the polycrystalline silicon and promote and activate the impurities (P). The annealing conditions are: 700–900°C for 3–20 minutes at atmospheric pressure under a nitrogen atmosphere. An aluminum oxide layer is then deposited on the front side of the wafer using ALD, and a silicon nitride layer is prepared using PECVD. A first passivation layer is deposited on the back side of the wafer to complete the cell precursor preparation. After surface passivation, metallization is performed on both the front and back sides of the wafer. The first electrode is printed sequentially on the back side and the second electrode on the front side using screen printing. Finally, the wafer is sintered to complete the cell fabrication.
[0090] As can be seen from the above embodiments, the method for preparing solar cells provided by the present invention achieves at least the following beneficial effects:
[0091] The solar cell fabrication method provided in this embodiment involves depositing a first oxide layer on the back side after alkaline polishing, followed by annealing the first oxide layer to form high-density, small-aperture vias. On the back side, a semiconductor layer, a second oxide layer, and a polycrystalline silicon layer are sequentially deposited on the side of the first oxide layer away from the silicon substrate. The high-density, small-aperture vias help improve electron transport efficiency, thereby reducing series resistance, increasing the cell fill factor and cell efficiency, while also reducing diffusion defect density and improving passivation quality. The second oxide layer forms a complete passivation layer, thus ensuring passivation quality. At the same time, the two oxide layers form a wall-like structure during phosphorus diffusion, which can prevent phosphorus from entering the silicon substrate and also prevent metal sintering burn-through.
[0092] Figure 8 This is a schematic diagram of a photovoltaic module provided by the present invention, with reference to... Figure 8 As shown, this embodiment provides a photovoltaic module, including a stacked glass 201, a first encapsulating film 202, a cell string 203, a second encapsulating film 204, and a backsheet 205. The cell string 203 is formed by electrically connecting multiple of the above-mentioned solar cells (not shown in the figure).
[0093] Specifically, the photovoltaic module includes a stacked glass 201, a first encapsulating film 202, a cell string 203, a second encapsulating film 204, and a backsheet 205. The glass 201 can be tempered glass with high light transmittance, reaching over 92%, and is generally made of low-iron tempered patterned glass. The backsheet 205 can be made of glass, TPT (polyvinyl fluoride composite film), or TPE (thermoplastic elastomer). The backsheet 205 protects the internal encapsulation materials and cells from mechanical damage and external environmental corrosion, and also has good insulation properties. The weathering properties of the components largely determine their service life. They possess excellent weather resistance, low water vapor permeability, good electrical insulation, and a certain bonding strength. The first encapsulating film 202 and the second encapsulating film 204 can be made of EVA (ethylene-vinyl acetate copolymer), POE (random copolymer elastomer of ethylene and high-carbon α-olefins), or PVB (polyvinyl butyral). EVA material, due to the introduction of vinyl acetate monomers into the molecular chain, can reduce high crystallinity and improve toughness, impact resistance, filler compatibility, and heat-sealing performance. The molecular structure of POE material gives it excellent mechanical properties, rheological properties, and UV resistance. It also features good affinity with polyolefins, good low-temperature toughness, and a high performance-price ratio. PVB material is soluble in methanol, ethanol, ketones, haloalkanes, and aromatic solvents. It has good compatibility with phthalates, sebacic acid esters, benzene plasticizers, nitrocellulose, phenolic resins, and epoxy resins. It has high transparency, cold resistance, impact resistance, and UV radiation resistance. It also has good adhesion to metals, glass, wood, ceramics, and fiber products. The first encapsulation film 202 and the second encapsulation film 204 are used to encapsulate and protect the solar cells, preventing external environmental factors from affecting their performance. They bond the glass 201, solar cells, and backsheet 205 together, exhibiting a certain bonding strength, high light transmittance, reasonable cross-linking degree, excellent UV aging resistance, excellent damp heat aging resistance, extremely low shrinkage rate, long-term strong adhesion to various backsheets 205 and glass 201, and high volume resistivity. The battery string 203 is formed by electrically connecting multiple solar cells (not shown in the figure) of the above type. Two adjacent solar cells are electrically connected by solder strips.
[0094] As can be seen from the above embodiments, the solar cell, its preparation method, and photovoltaic module provided by the present invention achieve at least the following beneficial effects:
[0095] The solar cell and its fabrication method, as well as the photovoltaic module provided in this invention, have a first oxide layer, a semiconductor layer, a second oxide layer, a polycrystalline silicon layer, and a first passivation layer sequentially stacked on one side of a silicon substrate along a direction away from the silicon substrate. Both the first and second oxide layers have through holes, with the through hole density in the first oxide layer being greater than that in the second oxide layer. Resonant tunneling is formed by the first and second oxide layers. Based on the resonant tunneling, a high density of through holes is formed by the first oxide layer. The high density of through holes improves electron transport efficiency, thereby reducing series resistance, increasing the cell fill factor and cell efficiency, while also reducing diffusion defect density and improving passivation quality. A complete passivation layer is formed by the second oxide layer, thereby ensuring passivation quality. At the same time, the two oxide layers form a wall-like structure during phosphorus diffusion, which can prevent phosphorus from entering the silicon substrate and also prevent metal sintering burn-through.
[0096] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims
1. A solar cell, characterized in that, include: Silicon substrate, first electrode and second electrode; One side of the silicon substrate is provided with a first oxide layer, a semiconductor layer, a second oxide layer, a polysilicon layer and a first passivation layer stacked sequentially along a direction away from the silicon substrate. Both the first oxide layer and the second oxide layer have vias, and the via density in the first oxide layer is greater than the via density in the second oxide layer. The first electrode penetrates the first passivation layer and is electrically connected to the polysilicon layer; alternatively, the first electrode sequentially penetrates the first passivation layer, the polysilicon layer, and the second oxide layer and is electrically connected to the semiconductor layer. The silicon substrate includes a base region and an emitter, the emitter being located on the side of the base region away from the first oxide layer; a second passivation layer is disposed on the side of the emitter away from the base region. The second electrode penetrates the second passivation layer and is electrically connected to the emitter. The first oxide layer has a first region and a second region. In a direction perpendicular to the silicon substrate, the first region at least partially overlaps with the first electrode, and the second region does not overlap with the second electrode. The via density in the first region is greater than the via density in the second region.
2. The solar cell according to claim 1, characterized in that, The pore density in the first oxide layer ranges from 10. 8 ~10 12 cm -2 .
3. The solar cell according to claim 1, characterized in that, The diameter of the pores in the first oxide layer ranges from 1 to 100 nm.
4. The solar cell according to claim 1, characterized in that, The semiconductor layer is polycrystalline silicon, silicon carbide, or a germanium-silicon alloy.
5. The solar cell according to claim 1, characterized in that, Along a direction perpendicular to the silicon substrate, the thickness of the semiconductor layer ranges from 1 to 3 nm.
6. The solar cell according to claim 1, characterized in that, Along a direction perpendicular to the silicon substrate, the thickness of the polycrystalline silicon layer ranges from 30 to 200 nm.
7. The solar cell according to claim 1, characterized in that, Along a direction perpendicular to the silicon substrate, the thickness of the first oxide layer and the second oxide layer ranges from 0.5 to 2 nm.
8. A method for preparing a solar cell, characterized in that, The method for preparing the solar cell according to any one of claims 1 to 7 includes the following steps: 1) Cleaning and texturing the silicon substrate; 2) Boron diffusion; 3) Remove the BSG from the back; 4) Alkali polishing on the back; 5) A first oxide layer is deposited on the back side, and then the first oxide layer is annealed; 6) Backside fabrication: On the side of the first oxide layer away from the silicon substrate, a semiconductor layer, a second oxide layer, and a polysilicon layer are sequentially deposited; 7) Remove the polysilicon layer coating on the front side; 8) Backside doping; 9) Annealing to crystallize the polycrystalline silicon layer and activate impurities; 10) Coating on both sides; 11) Generate the first electrode and the second electrode.
9. A photovoltaic module, characterized in that, It includes stacked glass, a first encapsulating film, a battery string, a second encapsulating film, and a backsheet, wherein the battery string is formed by electrical connections of a solar cell as described in any one of claims 1-7.