A gallium nitride-based avalanche photodetector that can be integrated on a chip and a preparation method thereof

Abstract

The application relates to a gallium nitride-based avalanche photodetector which can be integrated on a chip and a preparation method thereof, and the gallium nitride-based avalanche photodetector comprises the following steps: preparing a P-doped gallium nitride layer; preparing a first N-doped gallium nitride layer on the P-doped gallium nitride layer; preparing a second N-doped gallium nitride layer on the first N-doped gallium nitride layer; depositing a cathode material on the second N-doped gallium nitride layer to form a cathode; bonding the cathode of an epitaxial wafer on an SOI substrate through an organic bonding method; depositing an anode material on the P-doped gallium nitride layer to form an anode; and preparing a silicon local oxidation isolation layer in the P-doped gallium nitride layer at both ends of the P-doped gallium nitride layer, and the bottom end of the silicon local oxidation isolation layer is located in the first N-doped gallium nitride layer. The application uses a semiconductor bonding technology and a III-V group material and an SOI substrate design, improves the integration and performance of a device, solves the problem of poor substrate epitaxial crystal quality, and the device has deep ultraviolet band detection capability and stronger anti-radiation characteristics.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to an on-chip integrateable gallium nitride-based avalanche photodetector and its fabrication method. Background Technology

[0002] Ultraviolet (UV) light refers to electromagnetic waves or light rays with wavelengths between 10 and 400 nm. Invisible to the human eye, it is present in all aspects of life, such as in UV sterilization, counterfeit money detection, and medical examinations. This invisible UV light is applied to various fields and tasks. Because UV light is widely present and serves as an important indicator, specialized photoelectric devices for detecting it—UV photodetectors—have been developed, holding significant value in multiple fields. With the development of science and technology, our understanding of UV detection has deepened, and we have gradually realized the importance of UV detectors. Therefore, in-depth research has led to the development of various UV detector structures. Among them, the UV avalanche detector is characterized by its rapid response to weak UV signals and its large bandwidth, making it widely used in biological detection, medicine, and communications.

[0003] Gallium nitride (GaN)-based materials possess properties such as a large bandgap, high thermal conductivity, high temperature resistance, radiation resistance, acid and alkali resistance, high strength, and high hardness, making them widely applicable and promising in fields such as high-brightness blue, green, violet, ultraviolet, and white light-emitting diodes, blue and violet lasers, and radiation-resistant, high-temperature-resistant, and high-power microwave devices. In the field of ultraviolet detection, compared to traditional vacuum multiplier tubes and silicon semiconductor detectors, GaN-based ultraviolet avalanche photodetectors offer advantages such as small size, light weight, long lifespan, good shock resistance, low operating voltage, high temperature resistance, corrosion resistance, radiation resistance, high quantum efficiency, and the elimination of the need for filters, making them a research hotspot in photoelectric detection.

[0004] In recent years, the emergence of new semiconductor epitaxial technologies such as MBE (Molecular Beam Epitaxy), MOCVD (Metal-Organic Chemical Vapor Deposition), and ALD (Atom Layer Deposition) has made it possible to precisely control the growth of semiconductor materials, the deposition process of metal materials has become more mature, and the material growth is more uniform. These epitaxial technologies have been applied to the growth of III-V compound semiconductor materials and have mature process technologies in various process plants.

[0005] Currently, most ultraviolet avalanche photodetectors fabricated using gallium nitride (GaN)-based materials are epitaxially grown on sapphire, SiC, or Si substrates to form the desired device structure. For example, patent CN105655437A discloses an ultraviolet avalanche photodetector with a silicon substrate, silicon as the avalanche region, AlGaN as the absorption layer, and GaN as a buffer layer, exhibiting a relatively low breakdown voltage. Patent CN104051561A discloses a gallium nitride-based ultraviolet avalanche photodetector with a sapphire substrate and AlInGaN as the absorption and multiplication regions, separated by a quaternary compound AlInGaN with a gradually changing Al composition. Patent CN102244135A discloses a PIN-inverted structure ultraviolet avalanche photodetector and its fabrication method. A high-performance gallium nitride avalanche photodetector was realized by using AlInGaN as the absorption layer and avalanche region of the device and lightly doped P-type GaN as the guard ring.

[0006] With the development of the microelectronics industry and the increasingly demanding performance requirements of various application fields, higher requirements are being placed on the integration of optoelectronic devices. However, the integration method of the avalanche photodetector mentioned above, which involves chip-to-chip connections of discrete devices, reduces the integration density of the device, while also reducing its response speed and bandwidth, and increasing the speed-to-weight ratio. Secondly, the epitaxial growth process on silicon, sapphire, or silicon carbide substrates, due to lattice mismatch between the substrate and epitaxial materials, will generate a large number of defects in the critical areas of the device, which will seriously affect the device's performance and lifespan. Although it has good detection capabilities in the visible and near-infrared bands, it lacks detection capabilities in the deep ultraviolet band and electromagnetic interference resistance. Summary of the Invention

[0007] To address the aforementioned problems in the prior art, this invention provides an on-chip integrateable gallium nitride-based avalanche photodetector and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0008] One embodiment of the present invention provides a method for fabricating an on-chip integrateable gallium nitride-based avalanche photodetector, the method comprising:

[0009] Fabrication of a p-type doped gallium nitride layer;

[0010] A first N-type doped gallium nitride layer is prepared on the P-type doped gallium nitride layer;

[0011] A second N-type doped gallium nitride layer is prepared on the first N-type doped gallium nitride layer;

[0012] A cathode is formed by depositing cathode material on the second N-type doped gallium nitride layer to prepare an epitaxial wafer comprising a stacked P-type doped gallium nitride layer, a first N-type doped gallium nitride layer, a second N-type doped gallium nitride layer, and a cathode.

[0013] The cathode of the epitaxial wafer is bonded to the SOI substrate using an organic bonding method;

[0014] An anode material is deposited on the p-type doped gallium nitride layer to form an anode;

[0015] A silicon localized oxide isolation layer is fabricated within both ends of the P-type doped gallium nitride layer, with the bottom end of the silicon localized oxide isolation layer located within the first N-type doped gallium nitride layer, thus completing the fabrication of a gallium nitride-based avalanche photodetector.

[0016] In one embodiment of the present invention, the doping concentration of the P-type doped gallium nitride layer is greater than the doping concentration of the second N-type doped gallium nitride layer, and the doping concentration of the second N-type doped gallium nitride layer is greater than the doping concentration of the first N-type doped gallium nitride layer.

[0017] In one embodiment of the present invention, the doping concentration of the p-type doped gallium nitride layer is 4 × 10⁻⁶. 17 ~5×10 17 cm -3 The doping concentration of the first N-type doped gallium nitride layer is 1×10⁻⁶. 15 ~4×10 15 cm -3 The doping concentration of the second N-type doped gallium nitride layer is 1×10⁻⁶. 17 ~4×10 17 cm -3 .

[0018] In one embodiment of the present invention, fabricating a first N-type doped gallium nitride layer on the P-type doped gallium nitride layer includes:

[0019] Ga(CH3)3 and NH3 are uniformly diffused onto the surface of the p-type doped gallium nitride layer;

[0020] The P-type doped gallium nitride layer is heated to grow a first GaN material on the surface of the P-type doped gallium nitride layer, and the first GaN material is doped with H2Se to make the first GaN material N-type.

[0021] At a first preset temperature, the first GaN material is repeatedly grown to a first preset thickness using an epitaxial process, and then ion implantation is performed on the first GaN material of the first preset thickness to prepare a first N-type doped gallium nitride layer.

[0022] In one embodiment of the present invention, fabricating a second N-type doped gallium nitride layer on the first N-type doped gallium nitride layer includes:

[0023] Ga(CH3)3 and NH3 are uniformly diffused onto the surface of the first N-type doped gallium nitride layer;

[0024] The first N-type doped gallium nitride layer is heated to grow a second GaN material on the surface of the first N-type doped gallium nitride layer, and the second GaN material is doped with H2Se to make the second GaN material N-type.

[0025] At a first preset temperature, the second GaN material is repeatedly grown to a preset thickness using an epitaxial process, and then the first GaN material of the preset thickness is ion implanted to prepare a first N-type doped gallium nitride layer.

[0026] In one embodiment of the present invention, the cathode of the epitaxial wafer is bonded to the SOI substrate by an organic bonding method, including:

[0027] The epitaxial wafer is divided into several epitaxial sub-wafers;

[0028] The epitaxial wafer is mounted on a glass carrier using thermoplastic adhesive or thermal release tape;

[0029] The epitaxial wafer and the SOI substrate are cleaned;

[0030] SOG was spin-coated onto the SOI substrate;

[0031] The SOI substrate with spin-coated SOG is heated at a second preset temperature to remove the liquid solvent from the SOG.

[0032] In a vacuum environment, the cathode of the epitaxial sub-wafer is bonded to the side of the SOI substrate coated with SOG.

[0033] At a third preset temperature, the bonded epitaxial sub-wafer is heated for repair, so as to complete the bonding of the epitaxial sub-wafer on the SOI substrate.

[0034] In one embodiment of the present invention, a silicon localized oxide isolation layer is formed within both ends of the p-type doped gallium nitride layer, comprising:

[0035] After patterning the device surface using photolithography and dry etching processes, TEOS is deposited at both ends of the P-type doped gallium nitride layer to prepare a silicon local oxide isolation layer, and the bottom end of the silicon local oxide isolation layer is located within the first N-type doped gallium nitride layer.

[0036] In one embodiment of the present invention, the thickness of the P-type doped gallium nitride layer is less than the thickness of the second N-type doped gallium nitride layer, and the thickness of the second N-type doped gallium nitride layer is less than the thickness of the first N-type doped gallium nitride layer.

[0037] In one embodiment of the present invention, the thickness of the P-type doped gallium nitride layer is 0.2~1μm, the thickness of the first N-type doped gallium nitride layer is 5~9μm, and the thickness of the second N-type doped gallium nitride layer is 2~5μm.

[0038] This invention also provides an on-chip integrateable gallium nitride-based avalanche photodetector, which is fabricated using the fabrication method described in any of the above embodiments. The gallium nitride-based avalanche photodetector includes:

[0039] SOI substrate;

[0040] The cathode is located on the SOI substrate;

[0041] A second N-type doped gallium nitride layer is located on the cathode;

[0042] The first N-type doped gallium nitride layer is located on the second N-type doped gallium nitride layer;

[0043] A P-type doped gallium nitride layer is located on the first N-type doped gallium nitride layer;

[0044] A silicon localized oxide isolation layer is located at both ends of the p-type doped gallium nitride layer, and the lower surface of the silicon localized oxide isolation layer is below the upper surface of the p-type doped gallium nitride layer.

[0045] The anode is located on the P-type doped gallium nitride layer.

[0046] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0047] 1. This invention utilizes semiconductor bonding technology to integrate gallium nitride epitaxial substrates onto SOI substrates, thereby significantly improving the integration density of the devices. Compared to chip-to-chip connections of discrete devices, it offers a lower speed adaptation ratio, higher response rate, and greater bandwidth.

[0048] 2. The present invention uses a semiconductor bonding process between the substrate and the epitaxial substrate to replace the process of directly fabricating the device on the substrate by epitaxial growth. Therefore, it can avoid the problem of poor crystal quality caused by high lattice mismatch and large difference in expansion coefficient between the substrate material and the epitaxial growth material, and ensure the complete transmission of electrical signals of the avalanche photodetector to the TIA circuit.

[0049] 3. Through a novel structural design and the use of III-V group materials, the avalanche region and light absorption layer of the device are made of gallium nitride material with N-type and P-type doping, thus enabling detection capability and electromagnetic interference resistance in the deep ultraviolet band. Furthermore, by optimizing the doping concentration and thickness of the P-type and N-type regions, the device has a deeper detection depth and a lower breakdown voltage. At the same time, the SOI substrate gives the avalanche optoelectronic device stronger radiation resistance.

[0050] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0051] Figure 1 This is a schematic flowchart of a method for fabricating an on-chip integrateable gallium nitride-based avalanche photodetector provided in an embodiment of the present invention.

[0052] Figures 2a-2g This is a schematic diagram illustrating the process of fabricating an on-chip integrateable gallium nitride-based avalanche photodetector according to an embodiment of the present invention.

[0053] Figure 3 This is a schematic diagram of the structure of an on-chip gallium nitride-based avalanche photodetector provided in an embodiment of the present invention. Detailed Implementation

[0054] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0055] It should be noted that, in this embodiment, "up," "down," "left," and "right" refer to the positional relationship of the avalanche photodetector when it is in the illustrated state, "length" refers to the lateral dimension of the avalanche photodetector when it is in the illustrated state, and "thickness" refers to the longitudinal dimension of the avalanche photodetector when it is in the illustrated state.

[0056] Example 1

[0057] Currently, existing gallium nitride-based avalanche photodetectors suffer from low integration density, high speed-to-weight ratio, small bandwidth, and slow response speed. Epitaxial growth processes on silicon, sapphire, or silicon carbide substrates lead to numerous defects in critical areas due to lattice mismatch between the substrate and epitaxial materials, severely impacting device performance and lifespan. While they offer good detection capabilities in the visible and near-infrared bands, they lack detection capabilities in the deep ultraviolet band and electromagnetic interference resistance. Therefore, this invention provides a method for fabricating an on-chip, integrateable gallium nitride-based avalanche photodetector. For details, please refer to [link to details]. Figure 1 , Figures 2a-2g , Figure 1 This is a schematic flowchart illustrating a method for fabricating an on-chip integrateable gallium nitride-based avalanche photodetector according to an embodiment of the present invention. Figures 2a-2g This is a schematic diagram illustrating the fabrication process of an on-chip integrateable gallium nitride-based avalanche photodetector according to an embodiment of the present invention. The present invention provides a method for fabricating an on-chip integrateable gallium nitride-based avalanche photodetector (GaN APD), the method comprising:

[0058] Step 1, please refer to Figure 2a , Prepare a P-type doped gallium nitride layer 1.

[0059] Specifically, a P-type doped gallium nitride layer 1 was obtained by using MOCVD (Metal-organic Chemical Vapor Deposition), Mg ion implantation, and high-temperature annealing.

[0060] Step 2, please refer to Figure 2b A first N-type doped gallium nitride layer 2 is prepared on a P-type doped gallium nitride layer 1.

[0061] In an optional embodiment, step 2 may specifically include steps 2.1-2.3, wherein:

[0062] Step 2.1: Uniformly diffuse Ga(CH3)3 and NH3 onto the surface of the p-type doped gallium nitride layer 1.

[0063] Specifically, Ga(CH3)3 and NH3 are introduced into the MOCVD system and uniformly diffused onto the surface of the P-type doped gallium nitride layer 1 through the stagnation layer.

[0064] Step 2.2: Heat the P-type doped gallium nitride layer 1 to grow a first GaN material on the surface of the P-type doped gallium nitride layer, and dope the first GaN material with H2Se to make the first GaN material N-type.

[0065] Step 2.3: At the first preset temperature, the first GaN material is grown to the first preset thickness by repeated epitaxial processes. Then, the first GaN material of the first preset thickness is subjected to multiple ion implantation and drive-in processes to prepare the first N-type doped gallium nitride layer 2.

[0066] Optionally, the first preset temperature is 1100℃.

[0067] Step 3, please refer to Figure 2c A second N-type doped gallium nitride layer 3 is prepared on the first N-type doped gallium nitride layer 2.

[0068] In an optional embodiment, step 3 may specifically include steps 3.1-3.3, wherein:

[0069] Step 3.1: Uniformly diffuse Ga(CH3)3 and NH3 onto the surface of the p-type doped gallium nitride layer 1.

[0070] Specifically, Ga(CH3)3 and NH3 are introduced into the MOCVD system and uniformly diffused onto the surface of the P-type doped gallium nitride layer 1 through the stagnation layer.

[0071] Step 3.2: Heat the first N-type doped gallium nitride layer 2 to grow a second GaN material on the surface of the first N-type doped gallium nitride layer 2, and dope the second GaN material with H2Se to make the second GaN material N-type.

[0072] Step 3.3: At the first preset temperature, the second GaN material is repeatedly grown to the second preset thickness using epitaxial technology. Then, the second GaN material of the second preset thickness is subjected to multiple ion implantation and drive-in processes to prepare the second N-type doped gallium nitride layer 3.

[0073] Optionally, the doping concentration of the P-type doped gallium nitride layer 1 is greater than the doping concentration of the second N-type doped gallium nitride layer 3, and the doping concentration of the second N-type doped gallium nitride layer 3 is greater than the doping concentration of the first N-type doped gallium nitride layer 2. This allows the formation of a PIN junction, which can generate an avalanche photoelectric effect.

[0074] Preferably, the doping concentration of the p-type doped gallium nitride layer 1 is 4 × 10⁻⁶. 17 ~5×10 17 cm -3 The doping concentration of the first N-type doped gallium nitride layer 2 is 1×10⁻⁶. 15 ~4×10 15 cm -3 The doping concentration of the second N-type doped gallium nitride layer 3 is 1×10⁻⁶. 17 ~4×10 17 cm -3 .

[0075] More preferably, the doping concentration of the p-type doped gallium nitride layer 1 is 5 × 10⁻⁶. 17 cm -3 The doping concentration of the first N-type doped gallium nitride layer 2 is 4 × 10⁻⁶. 15 cm -3 The doping concentration of the second N-type doped gallium nitride layer 3 is 4 × 10⁻⁶. 17 cm -3 .

[0076] Optionally, the thickness of the P-type doped gallium nitride layer 1 is less than the thickness of the second N-type doped gallium nitride layer 3, and the thickness of the second N-type doped gallium nitride layer 3 is less than the thickness of the first N-type doped gallium nitride layer 2. This allows the first N-type doped gallium nitride layer 2 to be closer to intrinsic doping, and the avalanche region to be closer to the second N-type doped gallium nitride layer 3, achieving the effect of absorbing deep ultraviolet light of the corresponding wavelength.

[0077] Preferably, the thickness of the P-type doped gallium nitride layer 1 is 0.2~1μm, the thickness of the first N-type doped gallium nitride layer 2 is 5~9μm, and the thickness of the second N-type doped gallium nitride layer 3 is 2~5μm.

[0078] More preferably, the thickness of the P-type doped gallium nitride layer 1 is 0.5 μm, the thickness of the first N-type doped gallium nitride layer 2 is 7.5 μm, and the thickness of the second N-type doped gallium nitride layer 3 is 4 μm.

[0079] Therefore, in this embodiment, the avalanche region and light absorption layer of the gallium nitride-based avalanche photodetector device are fabricated by N-type doping and P-type doping of gallium nitride material. It has radiation resistance and thus electromagnetic interference resistance. At the same time, it has a high absorption coefficient in the deep ultraviolet band, so it can realize deep ultraviolet band detection and electromagnetic interference resistance. By setting the doping concentration and thickness of the P-type and N-type regions as described above, the avalanche region of the device is wide. At the same time, the PN junction formed by setting the doping concentration can have a low breakdown voltage. Therefore, the formed device has both a deep detection depth and a low breakdown voltage.

[0080] Step 4, please refer to Figure 2d A cathode material is deposited on the second N-type doped gallium nitride layer 3 to form a cathode 4, thereby preparing an epitaxial wafer comprising a stacked P-type doped gallium nitride layer 1, a first N-type doped gallium nitride layer 2, a second N-type doped gallium nitride layer 3, and a cathode 4.

[0081] Specifically, AlN is deposited on the second N-type doped gallium nitride layer 3 using the CVD (Chemical Vapor Deposition) process to form the cathode 4.

[0082] Step 5, please refer to Figure 2e The cathode of the epitaxial wafer is bonded to the SOI (Silicon-On-Insulator) substrate 5 by an organic bonding method.

[0083] In an optional embodiment, step 5 may specifically include steps 5.1-5.7, wherein:

[0084] Step 5.1: Divide the epitaxial wafer into several epitaxial sub-wafers.

[0085] Step 5.2: Mount the epitaxial wafer onto the glass carrier using thermoplastic adhesive or pyrolytic tape.

[0086] Step 5.3: Clean the epitaxial sub-wafer and SOI substrate.

[0087] Step 5.4: Spin-coat SOG (Spin On Glass) onto the SOI substrate.

[0088] Step 5.5: In a Rapid Thermal Processing (RTP) device, the SOI substrate with spin-coated SOG is heated at a second preset temperature to remove the liquid solvent in the SOG and leave the cured material on the surface of the SOI substrate.

[0089] Optionally, the second preset temperature is 150°C.

[0090] Step 5.6: In a vacuum environment, bond the cathode of the epitaxial sub-wafer to the side of the SOI substrate coated with SOG.

[0091] Step 5.7: At the third preset temperature, heat repair the bonded epitaxial sub-wafer to complete the bonding of the epitaxial sub-wafer on the SOI substrate.

[0092] Optionally, in order to remove defects and stress generated during the process, the bonded epitaxial sub-wafer is heated and repaired at 300°C, thereby obtaining high-strength, low-stress and stable bonding.

[0093] Therefore, this embodiment utilizes semiconductor bonding technology to integrate a gallium nitride epitaxial substrate onto an SOI substrate, thereby significantly improving the device's integration density. Compared to chip-to-chip connections of discrete devices, it offers a lower speed tolerance, higher response rate, and greater bandwidth. Simultaneously, the semiconductor bonding process replaces the direct epitaxial growth process on the substrate, avoiding the problem of poor crystal quality caused by high lattice mismatch and significant difference in expansion coefficients between the substrate and epitaxial growth materials. This ensures the complete transmission of the avalanche photodetector's electrical signal to the TIA circuit.

[0094] It should be noted that the glass substrate needs to be removed before step 5.7.

[0095] Step 6, please refer to Figure 2f Anode material is deposited on the P-type doped gallium nitride layer 1 to form anode 6.

[0096] Specifically, AlN was deposited on the P-type doped gallium nitride layer 1 using the CVD (Chemical Vapor Deposition) process to form the anode 6.

[0097] Step 7, please refer to Figure 2g Local Oxidation of Silicon (LOCOS) layers 7 are fabricated within both ends of the P-type doped gallium nitride layer 1, with the bottom end of the LOCOS layer 7 located within the first N-type doped gallium nitride layer 2, thus completing the fabrication of the gallium nitride-based avalanche photodetector.

[0098] Specifically, after patterning the device surface using photolithography and dry etching processes, TEOS (ethyl silicate) is deposited at both ends of the P-type doped gallium nitride layer 1 to prepare a silicon local oxide isolation layer 7, and the bottom end of the silicon local oxide isolation layer 7 is located within the first N-type doped gallium nitride layer 2.

[0099] Optoelectronic devices need to be integrated with control circuits. The bonding technology used in this invention simplifies existing processes and reduces the difficulty of photonic integration. This invention uses an SOI substrate, which is conducive to device integration. SOI-based devices are flat multilayer structures, and gallium nitride epitaxial wafers are directly integrated onto the SOI substrate using semiconductor bonding technology. This makes it easy to achieve three-dimensional integration, making full use of the silicon wafer area and achieving higher density integration. Therefore, the SOI and GaN bonding technology of this invention effectively improves the integration of devices and realizes on-chip GaN APD. Compared with the chip-to-chip connection of discrete devices in existing gallium nitride avalanche photodetectors, the gallium nitride avalanche photodetector of this invention has a lower speed fit ratio, a higher response rate, and a larger bandwidth.

[0100] Currently, in existing gallium nitride-based avalanche photodetector manufacturing processes, lattice mismatch occurs due to the difference in lattice constants between the substrate material and the epitaxial material. Furthermore, the significant difference in the thermal expansion coefficients of the two materials ultimately leads to poor quality of the epitaxial layer grown on the substrate. This severely affects the operating performance and lifespan of the optoelectronic device. Based on this, this invention employs bonding technology between the GaN APD and the SOI substrate instead of the direct epitaxial growth process on the substrate. Therefore, it avoids the problem of poor crystal quality caused by high lattice mismatch and significant difference in thermal expansion coefficients between the substrate material and the epitaxial growth material, ensuring the complete transmission of electrical signals from the GaN APD device to the TIA circuit in the substrate.

[0101] The avalanche photodetector fabricated in this invention uses GaN material (i.e., a first N-type doped gallium nitride layer and a second N-type doped gallium nitride layer) to form the active region (i.e., the avalanche region). When deep ultraviolet light irradiates the light-absorbing layer (i.e., a P-type doped gallium nitride layer), electrons located in the semiconductor valence band absorb sufficient photon energy, thereby undergoing energy level transitions into the conduction band to form electron-hole pairs (photogenerated carriers). Due to the electric field formed by the applied operating voltage, the generated electron-hole pairs will accelerate under the action of the electric field, injecting carriers into the active region and continuously colliding with the covalent bonds in the crystal lattice, exciting new electron-hole pairs. This process will continue, eventually causing an avalanche-like multiplication of the number of carriers. This invention ensures that the device can generate an avalanche effect under breakdown voltage, thereby converting the received optical signal into an electrical signal. This electrical signal is transmitted to the TIA (Trans-Impedance Amplifier) ​​circuit through the Si material layer on the SOI substrate, guaranteeing the complete transmission of the avalanche photodetector's electrical signal to the TIA circuit. Therefore, through a novel structural design and the use of III-V group materials—specifically, the avalanche region and light absorption layer are fabricated using N-type and P-type doping of gallium nitride—this invention enables deep ultraviolet detection and electromagnetic interference immunity. Furthermore, by optimizing the doping concentration and thickness of the P-type and N-type regions, the device achieves a deeper detection depth and a lower breakdown voltage.

[0102] Furthermore, the use of SOI substrate as the substrate material in this invention enables gallium nitride avalanche photodetectors to have stronger radiation resistance, and therefore can also be applied to aerospace communications, quantum communications and other fields.

[0103] This invention provides a manufacturing solution for on-chip GaN APD devices and integrated circuits to share an SOI substrate, laying the foundation for large-scale or even ultra-large-scale photonic integration compatible with CMOS processes, thereby promoting the development of high-reliability, low-loss and low-cost high-density data transmission systems.

[0104] Example 2

[0105] Please see Figure 3 , Figure 3 This is a schematic diagram of an on-chip integrateable gallium nitride-based avalanche photodetector provided in an embodiment of the present invention. Based on the above embodiments, the present invention further provides an on-chip integrateable gallium nitride-based avalanche photodetector, which is fabricated by the fabrication method of the above embodiments. The gallium nitride-based avalanche photodetector specifically includes:

[0106] SOI substrate 5;

[0107] Cathode 4 is located on SOI substrate 5;

[0108] The second N-type doped gallium nitride layer 3 is located on the cathode 4;

[0109] The first N-type doped gallium nitride layer 2 is located on the second N-type doped gallium nitride layer 3;

[0110] A p-type doped gallium nitride layer 1 is located on a first n-type doped gallium nitride layer 2;

[0111] A silicon local oxide isolation layer 7 is located at both ends of the p-type doped gallium nitride layer 1, and the lower surface of the silicon local oxide isolation layer 7 is below the upper surface of the p-type doped gallium nitride layer 1.

[0112] Anode 6 is located on P-type doped gallium nitride layer 1.

[0113] The avalanche region, or active region, is composed of a first N-type doped gallium nitride layer 2 and a second N-type doped gallium nitride layer 3. The P-type doped gallium nitride layer 1 is a light absorption layer that operates in the deep ultraviolet band of 200-365nm and has a very good avalanche effect.

[0114] Preferably, the thicknesses of the first N-type doped gallium nitride layer 2 and the second N-type doped gallium nitride layer 3 are 7.5 μm and 4 μm, respectively, and the doping concentrations are 4 × 10⁻⁶. 15 and 4×10 17 cm -3 The thickness of the p-type doped gallium nitride layer 1 is 0.5 μm, and the doping concentration is 5 × 10⁻⁶. 17 cm -3 The thickness of the silicon localized oxide isolation layer 7 is 1 μm; the thickness of the SOI substrate is 725 μm. The avalanche region of the gallium nitride-based avalanche photodetector is mainly located in the lower part of the first N-type doped gallium nitride layer 2 and the second N-type doped gallium nitride layer 3. Therefore, the gallium nitride-based avalanche photodetector designed in this invention can ensure that the avalanche region is mainly concentrated in the first N-type doped gallium nitride layer 2 and the second N-type doped gallium nitride layer 3.

[0115] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0116] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0117] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0118] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, any modifications made without departing from the inventive concept should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating an on-chip integrateable gallium nitride-based avalanche photodetector, characterized in that, The preparation method includes: Fabrication of a p-type doped gallium nitride layer; A first N-type doped gallium nitride layer is prepared on the P-type doped gallium nitride layer; A second N-type doped gallium nitride layer is prepared on the first N-type doped gallium nitride layer; A cathode is formed by depositing cathode material on the second N-type doped gallium nitride layer to prepare an epitaxial wafer comprising a stacked P-type doped gallium nitride layer, a first N-type doped gallium nitride layer, a second N-type doped gallium nitride layer, and a cathode. The cathode of the epitaxial wafer is bonded to the SOI substrate using an organic bonding method; An anode material is deposited on the p-type doped gallium nitride layer to form an anode; A silicon localized oxide isolation layer is prepared within both ends of the P-type doped gallium nitride layer, and the bottom end of the silicon localized oxide isolation layer is located within the first N-type doped gallium nitride layer, thereby completing the fabrication of a gallium nitride-based avalanche photodetector. The process of bonding the cathode of the epitaxial wafer to the SOI substrate using an organic bonding method includes: The epitaxial wafer is divided into several epitaxial sub-wafers; The epitaxial wafer is mounted on a glass carrier using thermoplastic adhesive or thermal release tape; The epitaxial wafer and the SOI substrate are cleaned; SOG was spin-coated onto the SOI substrate; The SOI substrate with spin-coated SOG is heated at a second preset temperature to remove the liquid solvent from the SOG. In a vacuum environment, the cathode of the epitaxial sub-wafer is bonded to the side of the SOI substrate coated with SOG. At a third preset temperature, the bonded epitaxial sub-wafer is heated for repair, so as to complete the bonding of the epitaxial sub-wafer on the SOI substrate.

2. The method for fabricating an on-chip integrateable gallium nitride-based avalanche photodetector according to claim 1, characterized in that, The doping concentration of the P-type doped gallium nitride layer is greater than that of the second N-type doped gallium nitride layer, and the doping concentration of the second N-type doped gallium nitride layer is greater than that of the first N-type doped gallium nitride layer.

3. The method for fabricating an on-chip integrateable gallium nitride-based avalanche photodetector according to claim 2, characterized in that, The doping concentration of the p-type doped gallium nitride layer is 4 × 10⁻⁶. 17 ~5×10 17 cm -3 The doping concentration of the first N-type doped gallium nitride layer is 1×10⁻⁶. 15 ~4×10 15 cm -3 The doping concentration of the second N-type doped gallium nitride layer is 1×10⁻⁶. 17 ~×10 17 cm -3 .

4. The method for fabricating an on-chip integrateable gallium nitride-based avalanche photodetector according to claim 1, characterized in that, Fabricating a first N-type doped gallium nitride layer on the P-type doped gallium nitride layer includes: Ga(CH3)3 and NH3 are uniformly diffused onto the surface of the p-type doped gallium nitride layer; The P-type doped gallium nitride layer is heated to grow a first GaN material on the surface of the P-type doped gallium nitride layer, and the first GaN material is doped with H2Se to make the first GaN material N-type. At a first preset temperature, the first GaN material is repeatedly grown to a first preset thickness using an epitaxial process, and then ion implantation is performed on the first GaN material of the first preset thickness to prepare a first N-type doped gallium nitride layer.

5. The method for fabricating an on-chip integrateable gallium nitride-based avalanche photodetector according to claim 1, characterized in that, Fabricating a second N-type doped gallium nitride layer on the first N-type doped gallium nitride layer includes: Ga(CH3)3 and NH3 are uniformly diffused onto the surface of the first N-type doped gallium nitride layer; The first N-type doped gallium nitride layer is heated to grow a second GaN material on the surface of the first N-type doped gallium nitride layer, and the second GaN material is doped with H2Se to make the second GaN material N-type. At a first preset temperature, the second GaN material is repeatedly grown to a preset thickness using an epitaxial process, and then ion implantation is performed on the second GaN material of the preset thickness to prepare a second N-type doped gallium nitride layer.

6. The method for fabricating an on-chip integrateable gallium nitride-based avalanche photodetector according to claim 1, characterized in that, A silicon localized oxide isolation layer is fabricated within both ends of the p-type doped gallium nitride layer, comprising: After patterning the device surface using photolithography and dry etching processes, TEOS is deposited at both ends of the P-type doped gallium nitride layer to prepare a silicon local oxide isolation layer, and the bottom end of the silicon local oxide isolation layer is located within the first N-type doped gallium nitride layer.

7. The method for fabricating an on-chip integrateable gallium nitride-based avalanche photodetector according to claim 1, characterized in that, The thickness of the P-type doped gallium nitride layer is less than the thickness of the second N-type doped gallium nitride layer, and the thickness of the second N-type doped gallium nitride layer is less than the thickness of the first N-type doped gallium nitride layer.

8. The method for fabricating an on-chip integrateable gallium nitride-based avalanche photodetector according to claim 7, characterized in that, The thickness of the P-type doped gallium nitride layer is 0.2~1μm, the thickness of the first N-type doped gallium nitride layer is 5~9μm, and the thickness of the second N-type doped gallium nitride layer is 2~5μm.

9. An on-chip integrateable gallium nitride-based avalanche photodetector, characterized in that, The gallium nitride-based avalanche photodetector is fabricated using the fabrication method according to any one of claims 1 to 8, and the gallium nitride-based avalanche photodetector comprises: SOI substrate; The cathode is located on the SOI substrate; A second N-type doped gallium nitride layer is located on the cathode; The first N-type doped gallium nitride layer is located on the second N-type doped gallium nitride layer; A P-type doped gallium nitride layer is located on the first N-type doped gallium nitride layer; A silicon localized oxide isolation layer is located at both ends of the p-type doped gallium nitride layer, and the lower surface of the silicon localized oxide isolation layer is below the upper surface of the p-type doped gallium nitride layer. The anode is located on the P-type doped gallium nitride layer.

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