power supply circuit

Abstract

The power supply circuit of the embodiment has: a series circuit of a first resistor and a second transistor connected in parallel with a first transistor between an input terminal and an output terminal; a second resistor having one end connected to the input terminal; a first operational amplifier having a first input to which the other end of the second resistor is connected and a second input to which a connection node of the first resistor and the second transistor is connected, outputting a signal corresponding to a voltage difference between the first input and the second input; a third transistor outputting a current corresponding to the signal output from the first operational amplifier; a third resistor generating a voltage corresponding to the current; and a second operational amplifier outputting a signal corresponding to a voltage difference between the voltage and a reference voltage to a gate of the first transistor and a gate of the second transistor.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-155491 (filed on September 24, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] The implementation method involves a power supply circuit. Background Technology

[0003] The power supply circuit includes a current limiting circuit. For example, the current limiting circuit includes a current detection circuit that uses an operational amplifier to detect the output current, detects the current flowing to the output terminal, and limits the output current so that the detected current does not exceed a predetermined value.

[0004] However, when the output voltage VOUT of the power supply circuit is near 0 volts, the current sensing circuit may no longer be able to properly detect the output current. When the output current can no longer be properly detected, the current limiting circuit cannot properly limit the output current. Summary of the Invention

[0005] The implementation provides a power supply circuit that can appropriately limit current even when the output voltage is near 0 volts.

[0006] The power supply circuit of the embodiment includes: a first transistor connected between an input terminal and an output terminal; a series circuit of a first resistor and a second transistor connected in parallel with the first transistor between the input terminal and the output terminal; a second resistor, one end of which is connected to the input terminal; a first operational amplifier having a first input connected to the other end of the second resistor and a second input connecting the connection node of the first resistor and the second transistor, and outputting a first signal corresponding to a first voltage difference between the first input and the second input; a third transistor outputting a current corresponding to the first signal output from the first operational amplifier; a third resistor generating a voltage corresponding to the current; and a second operational amplifier having a third input to which the voltage is input and a fourth input to which a reference voltage is input, and outputting a second signal corresponding to a second voltage difference between the third input and the fourth input to the gate of the first transistor and the gate of the second transistor. Attached Figure Description

[0007] Figure 1 This is a circuit diagram of the power supply circuit according to the first embodiment.

[0008] Figure 2 This is a circuit diagram of the power supply circuit that shows the internal circuitry of the two operational amplifiers according to the first embodiment.

[0009] Figure 3 This is a circuit diagram of the power supply circuit according to the second embodiment. Detailed Implementation

[0010] The embodiments will now be described with reference to the accompanying drawings.

[0011] (First Embodiment)

[0012] (constitute)

[0013] Figure 1 This is a circuit diagram of the power supply circuit according to this embodiment. The power supply circuit 1 has an input terminal 11 for receiving an input voltage VIN as an external power source, an output terminal 12 for outputting an output voltage VOUT, a charge pump circuit 13, an on / off input circuit 14, transistors M1, M2, and M3, operational amplifiers Amp1 and Amp2, and resistors R1, R2, and R3. Transistors M1 and M2 are NMOS transistors, and transistor M3 is a PMOS transistor.

[0014] Transistor M1 is connected between input terminal 11 and output terminal 12. The drain of transistor M1 is connected to input terminal 11, and the source of transistor M1 is connected to output terminal 12.

[0015] A series circuit of resistor R1 and transistor M2 is also connected between input terminal 11 and output terminal 12. The drain of transistor M2 is connected to input terminal 11 via resistor R1, and the source of transistor M2 is connected to output terminal 12.

[0016] That is, the series circuit of transistor M1 and resistor R1 with transistor M2 is connected in parallel between input terminal 11 and output terminal 12.

[0017] Transistors M1 and M2 have a size ratio such that the current flowing in transistor M1 is N times the current flowing in transistor M2. Figure 1 In this context, "N:1" represents the ratio of the two currents flowing in transistors M1 and M2.

[0018] The sources of transistors M1 and M2 are connected to a common output terminal 12, and the gates of transistors M1 and M2 are connected. The gate-source voltage Vgs applied between the source and gate of transistor M1 and the gate-source voltage Vgs applied between the source and gate of transistor M2 are equal. Therefore, transistors M1 and M2 constitute a current mirror circuit.

[0019] The on / off input circuit 14 has transistors M4 and M5 connected in series. Transistor M4 is a PMOS transistor, and transistor M5 is an NMOS transistor. The source of transistor M4 is connected to the output of charge pump circuit 13. The source of transistor M5 is connected to ground potential GND. The input of charge pump circuit 13 is connected to input terminal 11. Charge pump circuit 13 generates a predetermined voltage and outputs to on / off input circuit 14.

[0020] The voltage at the connection node N1 between the drains of transistors M4 and M5 varies according to the on / off input of the conduction / cutoff input circuit 14. When the voltage at connection node N1 becomes High, transistors M1 and M2 are turned on, and the power supply circuit 1 outputs the output voltage VOUT to the output terminal 12.

[0021] The connection node N2 between resistor R1 and the drain of transistor M2 is connected to the non-inverting input terminal of operational amplifier Amp1.

[0022] One end of resistor R2 is connected to input terminal 11. The other end of resistor R2 is connected to the source of transistor M3. The connection node N3 between the other end of resistor R2 and the source of transistor M3 is connected to the inverting input terminal of operational amplifier Amp1. Thus, operational amplifier Amp1 has a first input connected to the other end of resistor R2 and a second input connected to the connection node N2 of resistor R1 and transistor M2, and outputs a signal corresponding to the voltage difference between the first and second inputs.

[0023] The output of operational amplifier Amp1 is connected to the gate of transistor M3. Resistor R3 is connected between the drain of transistor M3 and ground potential GND.

[0024] Operational amplifier Amp1 controls transistor M3 so that the input voltage A at the inverting input terminal and the input voltage B at the non-inverting input terminal become equal. Transistor M3 outputs a current corresponding to the signal output from operational amplifier Amp1. The resistance values ​​of resistor R1 and resistor R2 are equal. Therefore, the current flowing in transistor M3 is equal to the current flowing in resistor R1, and also flows to resistor R3. Consequently, resistor R3 generates a voltage corresponding to the current flowing in resistor R1.

[0025] The inverting input of operational amplifier Amp2 is connected to node N4, which is the connection point between the drain of transistor M3 and one end of resistor R3. A predetermined reference voltage VREF is input to the non-inverting input of operational amplifier Amp2. The output of operational amplifier Amp2 is connected to the gates of transistors M1 and M2. Thus, operational amplifier Amp2 has a first input that receives the voltage generated at node N4 and a second input that receives the reference voltage VREF, outputting a signal corresponding to the voltage difference between the first and second inputs to the gates of transistors M1 and M2.

[0026] Figure 2 This is a circuit diagram of power supply circuit 1, which shows the internal circuitry of operational amplifiers Amp1 and Amp2. (Example) Figure 2 As shown, the operational amplifier Amp1 includes two transistors M6 and M7 and two constant current sources CCS1 and CCS2. Both transistors M6 and M7 are PMOS transistors.

[0027] The source of transistor M6 is connected to node N3. The source of transistor M7 is connected to node N2. The gates of transistor M6 and M7 are connected.

[0028] Constant current source CCS1 is connected between the drain of transistor M6 and ground potential GND. Constant current source CCS2 is connected between the drain of transistor M7 and ground potential GND.

[0029] The drain of transistor M6 is connected to the gate of transistor M6 and the gate of transistor M7 via the connection node N5 of the constant current source CCS1. Thus, transistors M6 and M7 constitute a current mirror circuit.

[0030] The drain of transistor M7 is connected to the gate of transistor M3 via the connection node N6 of the constant current source CCS2.

[0031] Operational amplifier Amp1 operates to make the gate-source voltage Vgs applied between the source and gate of transistor M6 equal to the gate-source voltage Vgs applied between the source and gate of transistor M7.

[0032] For example, when the gate-source voltage Vgs of transistor M7 becomes greater than that of transistor M6, the on-resistance of transistor M7 decreases, and the gate voltage of transistor M3 increases. As a result, the on-resistance of transistor M3 increases, and the current flowing in transistor M3 decreases.

[0033] As a result, the source voltage of transistor M6 becomes higher, and therefore, the gate-source voltage Vgs of transistor M6 becomes higher, and the gate-source voltage Vgs of transistor M6 and transistor M7 become equal.

[0034] In this way, the operational amplifier Amp1 operates so that the gate-source voltage Vgs applied between the source and gate of transistor M6 and the gate-source voltage Vgs applied between the source and gate of transistor M7 become equal.

[0035] Additionally, operational amplifier Amp2 includes operational amplifier Amp21 and transistor M8. Transistor M8 is an NMOS transistor.

[0036] Connection node N4 is connected to the non-inverting input terminal of operational amplifier Amp21. The reference voltage VREF is input to the inverting input terminal of operational amplifier Amp21. The output of operational amplifier Amp21 is connected to the gate of transistor M8, which is an NMOS transistor. The drain of transistor M8 is connected to the gates of transistors M1 and M2.

[0037] Two resistors R1 and R2 connected to input terminal 11 and two operational amplifiers Amp1 whose inputs are connected to connection nodes N2 and N3 constitute an input current detection circuit ICDC for detecting the input current. That is, the input current detection circuit ICDC detects the input current input from input terminal 11. Furthermore, transistor M3 outputs the current detected by the input current detection circuit ICDC, corresponding to the input current.

[0038] The voltage corresponding to the current value detected by the input current detection circuit ICDC is compared with the reference voltage by the operational amplifier Amp2, and the gate voltages of transistors M1 and M2 are adjusted based on the comparison result.

[0039] (effect)

[0040] Next, the operation of the power supply circuit 1 described above will be explained.

[0041] When power circuit 1 is turned on, transistors M1 and M2 conduct, generating an output voltage VOUT at output terminal 12. The current flowing in transistor M2 also flows to resistor R1.

[0042] A pair of transistors M1 and M2 form a current mirror circuit, therefore, the current flowing in transistor M1 is proportional to the current flowing in transistor M2. Furthermore, operational amplifier Amp1 controls transistor M3 so that the voltage B at node N2 and the voltage A at node N3 become equal. That is, the current flowing in resistor R1 and the current flowing in resistor R2 are controlled to become equal.

[0043] The current flowing in transistor M3 also flows to resistor R3, thus generating a voltage at connection node N4 corresponding to the current flowing in transistor M2. Operational amplifier Amp21 controls the gate voltages (VGATE) of transistors M1 and M2 so that the voltage at connection node N4 becomes equal to the reference voltage VREF.

[0044] Thus, for example, when the current flowing to the circuit connected to the output terminal 12 increases or the input current increases, the gate voltage (VGATE) of transistors M1 and M2 is reduced to limit the amount of current flowing in transistor M1.

[0045] As described above, the input current detection circuit ICDC detects the current input from input terminal 11. The current flowing in transistors M1 and M2 is controlled so that the voltage corresponding to the detected current matches the reference voltage VREF. Even if the output voltage VOUT decreases and the current flowing in transistors M1 and M2 increases, the output current is limited to a limit value determined by the reference voltage VREF by controlling the gates of transistors M1 and M2 through operational amplifier Amp2.

[0046] As described above, according to this embodiment, a power supply circuit that can appropriately limit current even when the output voltage is near 0 volts can be provided.

[0047] (Second Implementation)

[0048] In the first embodiment, an operational amplifier Amp1 is used to detect the current input from input terminal 11. However, when there is an input offset between the two inputs of the operational amplifier Amp1, the current input from input terminal 11 cannot be detected correctly. The second embodiment relates to an offset adjustment circuit for eliminating the input offset between the two inputs of the operational amplifier Amp1.

[0049] The structure of the power supply circuit 1A in this embodiment is substantially the same as that of the power supply circuit 1 in the first embodiment. Therefore, the same numbers, labels, etc. are assigned to the same constituent elements as those in the first embodiment, and the description is omitted. The constituent elements that are different from those in the first embodiment are described.

[0050] Figure 3 This is a circuit diagram of the power supply circuit involved in this embodiment. Furthermore, in Figure 3 The middle part is omitted Figure 1 The charge pump circuit 13 and the on / off input circuit 14 are shown.

[0051] Figure 3The power supply circuit 1A includes an operational amplifier Amp1A. Operational amplifier Amp1A has resistors R4 and R5 and an offset adjustment circuit OAC. The source of transistor M6 in operational amplifier Amp1A is connected to node N3 via resistor R4. The source of transistor M7 in operational amplifier Amp1A is connected to node N2 via resistor R5.

[0052] The offset adjustment circuit OAC has two variable current sources, VCS1 and VCS2. One end of variable current source VCS1 is connected to ground potential GND, and the other end is connected to the connection node N8 between the source of transistor M7 and resistor R5. One end of variable current source VCS2 is connected to ground potential GND, and the other end is connected to the connection node N7 between the source of transistor M6 and resistor R4. Variable current source VCS1 draws current from connection node N8. Variable current source VCS2 draws current from connection node N7. The current drawn by variable current sources VCS1 and VCS2 is preset to eliminate the input offset between the two inputs of operational amplifier Amp1p.

[0053] That is, the operational amplifier Amp1A includes an offset adjustment circuit OAC that adjusts the input offset between the two inputs. Through the offset adjustment circuit OAC, the offset between the two inputs of the operational amplifier Amp1A is eliminated, therefore, the current input from input terminal 11 can be correctly detected.

[0054] The other operations are the same as those of the power supply circuit 1 described in the first embodiment.

[0055] Furthermore, the offset adjustment circuit OAC here has two resistors R4 and R5 and two variable current sources VCS1 and VCS2, but it can also have only one resistor and one variable current source. For example, a resistor can be placed only on the source side of either transistor M6 or M7, and a variable current source can be placed at the connection node between the resistor and the source of either transistor M6 or M7. By adjusting the current introduced by this variable current source, the input offset between the two inputs of the operational amplifier Amp1A can be eliminated.

[0056] Therefore, according to the above embodiments, a power supply circuit that can appropriately limit current even when the output voltage is near 0 volts can be provided.

[0057] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A power supply circuit, comprising: The first transistor is connected between the input terminal and the output terminal; A series circuit of the first resistor and the second transistor is connected in parallel with the first transistor between the input terminal and the output terminal; The second resistor has one end connected to the input terminal; The first operational amplifier has a first input connected to the other end of the second resistor and a second input connected to the connection node of the first resistor and the second transistor, and outputs a first signal corresponding to a first voltage difference between the first input and the second input; The third transistor outputs a current corresponding to the first signal output from the first operational amplifier; A third resistor, which generates a voltage corresponding to the current; and The second operational amplifier, having a third input to which the voltage is input and a fourth input to which a reference voltage is input, outputs a second signal to the gate of the first transistor and the gate of the second transistor, corresponding to a second voltage difference between the third input and the fourth input.

2. The power supply circuit according to claim 1, The first operational amplifier includes an offset adjustment circuit that adjusts the input offset between the first input and the second input.

3. The power supply circuit according to claim 1, The first transistor and the second transistor are NMOS transistors.

4. The power supply circuit according to claim 1, The third transistor is a PMOS transistor.

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