Synchronous rectifier circuit

Abstract

The present invention provides a synchronous rectification circuit, which couples a first reference signal and a second reference signal to a multiplexer, so that the multiplexer selects to input the first reference signal or the second reference signal to a comparator, compares it with a detection signal of a switching element and generates a comparison result signal to the switching element, thereby controlling the switching element for synchronous rectification.

Description

Technical Field

[0001] This invention relates to a rectifier circuit, and more particularly to a synchronous rectifier circuit for a power supply device. Background Technology

[0002] In existing switching power supplies, a rectifier is typically connected in series at the output to control the DC output voltage. The rectifier can be a rectifier diode; however, with the advancement of electronic device technology, the forward voltage of rectifier diodes has gradually become a limitation for power supply devices.

[0003] To meet the demands of low output voltage and high output power, synchronous rectification circuits were developed to replace rectifier diodes. However, existing synchronous rectification circuits require at least two comparators to compare with two reference signals to output corresponding control signals to control the switching on and off of the transistors used for rectification. This forces the power supply device to handle the error values ​​of the two comparators during development, increases the power consumption of the power supply device, and the circuit area occupied by the two comparators leads to an increase in the overall circuit area.

[0004] More specifically, the two reference signals mentioned above are used to determine when to turn on and off the transistors in the synchronous rectification circuit. When these two reference signals are processed by two different circuits such as two comparators, the error components of the two different circuits may overlap, thus seriously affecting the accuracy of synchronous rectification. Therefore, there is indeed a need to improve the existing technology. Summary of the Invention

[0005] One object of the present invention is to provide a synchronous rectification circuit to address the aforementioned problems. By using a multiplexer to select a first reference signal or a second reference signal to a comparator, the comparator compares a detection signal of a switching element and generates a comparison result signal, which is used to control the switching element and rectify the output voltage of the power supply device. Thus, the present invention can reduce the power consumption of the power supply device and reduce the overall circuit area by using a single comparator.

[0006] To achieve the aforementioned objectives, the present invention provides a synchronous rectification circuit comprising a multiplexer, a comparator, and a switching element. The multiplexer includes two input terminals and an output terminal. The output terminal of the multiplexer is coupled to a control terminal of the switching element and connected to the comparator. The two input terminals of the multiplexer are coupled to a first reference signal and a second reference signal. Therefore, the multiplexer selects to input either the first reference signal or the second reference signal to the comparator based on a comparison reference signal of the comparator. The comparator then compares a detection signal of the switching element based on the first reference signal or the second reference signal and generates a comparison result signal to the switching element. Thus, the present invention achieves synchronous rectification by controlling a switching element through a multiplexer and a comparator, thereby reducing the efficiency of the power supply device and minimizing the area occupied by the synchronous rectification circuit. Attached Figure Description

[0007] Figure 1 This is a circuit diagram of the first embodiment of the present invention;

[0008] Figure 2 This is a schematic diagram of the signal operation of the first embodiment of the present invention;

[0009] Figure 3 This is a circuit diagram of the second embodiment of the present invention;

[0010] Figure 4 This is a schematic diagram of the signal operation of the second embodiment of the present invention;

[0011] Figure 5 This is a circuit diagram of the third embodiment of the present invention;

[0012] Figure 6 This is a schematic diagram of the signal operation of the third embodiment of the present invention;

[0013] Figure 7 This is a circuit diagram of the fourth embodiment of the present invention; and

[0014] Figure 8 This is a circuit diagram of the fifth embodiment of the present invention.

[0015] [Figure Number Reference Guide]

[0016] 10 Synchronous Rectifier Circuit

[0017] 102 Rectifier Output Terminal

[0018] 104 Rectifier Input Terminal

[0019] 12-way multiplexer

[0020] 122 First Input Terminal

[0021] 124 Second Input Terminal

[0022] 126 First Output Terminal

[0023] 128 Third Input Terminal

[0024] 130 Third Output Terminal

[0025] 14 Comparators

[0026] 142 Positive Input Terminal

[0027] 144 Negative Input Terminal

[0028] 146 Second Output Terminal

[0029] 16 Switching elements

[0030] 162 Control Terminal

[0031] 164 Switch Output Terminal

[0032] 166 Switch Input Terminal

[0033] 18 Delay Circuit

[0034] 20. Drive circuit

[0035] D1 Parasitic Diode

[0036] DLY preset time

[0037] M transistor

[0038] OUT Comparison result signal

[0039] OUTT drive signal

[0040] SET Delay Signal

[0041] VD detection signal

[0042] VR1 First Reference Signal

[0043] VR2 Second Reference Signal Detailed Implementation

[0044] To provide a better understanding of the structural features and effects achieved by the present invention, preferred embodiments and detailed descriptions are provided below:

[0045] The invention will be described in detail below by way of the drawings illustrating various embodiments thereof. However, the concept of the invention may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein.

[0046] First, please refer to Figure 1 This is a circuit diagram of a first embodiment of the present invention. As shown in the figure, a synchronous rectification circuit 10 of this embodiment includes a multiplexer 12, a comparator 14, and a switching element 16. The multiplexer 12 includes a first input terminal 122, a second input terminal 124, and a first output terminal 126, that is, the multiplexer 12 includes two input terminals and one output terminal. In this embodiment, the first input terminal 122 is coupled to a first reference signal VR1, the second input terminal 124 is coupled to a second reference signal VR2, and the output terminal 126 is coupled to the comparator 14, thereby coupling the multiplexer 12 to the comparator 14. Therefore, in this embodiment, the first reference signal VR1 and the second reference signal VR2 are respectively coupled to the two input terminals of the multiplexer 12.

[0047] Furthermore, the comparator 14 includes a positive input terminal 142, a negative input terminal 144, and a second output terminal 146. That is, the comparator 14 also includes two input terminals and one output terminal. However, the signals at the two input terminals of the comparator 14 are subtracted and compared, so they are named the positive input terminal 142 and the negative input terminal 144 respectively. In this embodiment, the positive input terminal 142 is coupled to the first output terminal 126, and the negative input terminal 144 is coupled to one end of the switching element 16 to receive a detection signal VD.

[0048] Furthermore, a control terminal 162 of the switching element 16 is coupled to the second output terminal 146, and controls the switching element 16 to be turned on or off upon receiving a comparison result signal. The switching element 16 may include a metal-oxide-semiconductor field-effect transistor (MOSFET), and the control terminal 162 is equivalent to a gate terminal of the transistor M of the switching element 16 coupled to the second output terminal 146. The switching element 16 has a switching output terminal 164 coupled to a rectifier output terminal 102 of the synchronous rectifier circuit 10, which is equivalent to the drain terminal of the transistor M being coupled to the rectifier output terminal 102 of the synchronous rectifier circuit 10. In this embodiment, the drain terminal can provide the detection signal VD to the comparator 14. The switching element 16 has a switching input terminal 166 coupled to a rectifier input terminal 104 of the synchronous rectifier circuit 10, which is equivalent to the source terminal of the transistor M being coupled to the rectifier input terminal 104 of the synchronous rectifier circuit 10.

[0049] In particular, the detection signal VD in this embodiment is taken from the drain terminal of the transistor M of the switching element 16, that is, a drain voltage signal of the transistor M. Alternatively, the present invention can obtain a signal representing the drain voltage of the switching element 16 as the detection signal VD through other voltage acquisition methods such as impedance voltage division or parallel connection of a capacitor. In this embodiment, the transistor M of the switching element 16 is a synchronous rectified MOSFET, and the transistor M has a parasitic diode D1 between its source and drain terminals.

[0050] See also Figure 1 For further information Figure 2 The multiplexer 12 further receives a comparison reference signal from the switching element 16 and selects to output the first reference signal VR1 or the second reference signal VR2 to the comparator 14. Therefore, the comparator 14 will compare the detection signal VD according to the first reference signal VR1 or the second reference signal VR2, and generate a comparison result signal OUT to the switching element 16 according to the comparison result after comparing the detection signal VD with the first reference signal VR1 or the second reference signal VR2. That is, the comparison result signal OUT is transmitted to the control terminal 162 of the switching element 16 to further control the switching element 16 to turn on or off. That is, the comparison result signal OUT is applied to the gate terminal of the transistor M to drive the source terminal and the drain terminal of the transistor M to turn on or off, thereby turning on or off the rectified output terminal 102 and the rectified input terminal 104. The comparator 14 compares the first reference signal VR1 with the detection signal VD. When the detection signal VD is less than the first reference signal VR1, the comparison result signal OUT controls the switching element 16 to turn on. The comparator 14 compares the second reference signal VR2 with the detection signal VD. When the detection signal VD is greater than the second reference signal VR2, the comparison result signal OUT controls the switching element 16 to turn off.

[0051] In this embodiment, the comparison result signal OUT is fed back to the multiplexer 12, thus forming the comparison reference signal received by the multiplexer 12. This makes the control of the multiplexer 12 simpler and the signal implementation less complicated.

[0052] In addition to directly feeding back the comparison result signal OUT to the multiplexer 12 to form the comparison reference signal received by the multiplexer 12, the present invention can further form the comparison reference signal received by the multiplexer 12 by delaying the comparison result signal OUT. This allows the multiplexer 12 to be controlled to select and output the first reference signal VR1 or the second reference signal VR2 to the comparator 14, thereby avoiding malfunctions of the multiplexer 12 due to circuit parasitic effects or insufficient processing speed. Details are as follows:

[0053] Please see Figure 3 This is a circuit diagram of the second embodiment of the present invention. Figure 1 and Figure 3 The difference lies in Figure 3 The synchronous rectification circuit 10 further includes a delay circuit 18, which is coupled between the multiplexer 12 and the comparator 14. The delay circuit 18 receives the comparison result signal OUT from the comparator 14 and delays the comparison result signal OUT to generate a delayed comparison result signal OUT, which is a delayed signal SET, and transmits it to the multiplexer 12 as the comparison reference signal input to the multiplexer 12.

[0054] See also Figure 3 And further reading Figure 4 In this embodiment, the synchronous rectification circuit 10 generates the comparison reference signal received by the multiplexer 12 by delaying the comparison result signal OUT, i.e., generating the delayed signal SET. This controls the multiplexer 12 to select and output either the first reference signal VR1 or the second reference signal VR2 to the comparator 14, causing the comparator 14 to generate the corresponding comparison result signal OUT. When the delayed signal SET, i.e., the comparison reference signal received by the multiplexer 12, is at a first level (low level in this embodiment), the multiplexer transmits the first reference signal VR1 to the comparator; when the delayed signal SET, i.e., the comparison reference signal received by the multiplexer 12, is at a second level (high level in this embodiment), the multiplexer transmits the second reference signal VR2 to the comparator 14. Furthermore, depending on the design of the multiplexer 12, the present invention can also swap the first level and the second level, that is, the multiplexer 12 can receive the inverse signal of the delayed signal SET.

[0055] Compared to the previous embodiment, in this embodiment, the comparison result signal OUT generated by the comparator 14 is transmitted to the delay circuit 18, thus delaying it by a preset time DLY, and forming the delayed signal SET as the comparison reference signal input to the multiplexer 12. Therefore, the multiplexer 12 selects to output the first reference signal VR1 or the second reference signal VR2 to the comparator 14 based on the delayed comparison result signal OUT, thereby avoiding the multiplexer 12 from malfunctioning and causing the comparator 14 to output an incorrect or unstable comparison result signal OUT to the switching element 16.

[0056] As described above, the synchronous rectification circuit 10 of the present invention uses the multiplexer 12 to select and output the first reference signal VR1 or the second reference signal VR2 to the comparator 14. In addition, in other embodiments of the present invention, the multiplexer 12 can be further coupled with the detection signal VD, so that the multiplexer 12 can further select and output the detection signal VD to the comparator 14.

[0057] like Figure 5 The diagram shown is a circuit schematic of the third embodiment of the present invention. Figure 1 and Figure 5 The difference lies in Figure 5 To couple the detection signal VD, the first reference signal VR1, and the second reference signal VR2 to the multiplexer 12 of the synchronous rectifier circuit 10, the multiplexer 12 selectively outputs either the detection signal VD and the first reference signal VR1 to the comparator 14, or selectively outputs either the detection signal VD and the second reference signal VR2 to the comparator 14. Furthermore, it includes a drive circuit 20 coupled to the comparator 14 and the control terminal 162 of the switching element 16. Details are as follows:

[0058] The multiplexer 12 in this embodiment includes three input terminals and two output terminals. That is, in addition to the first input terminal 122, the second input terminal 124, and the first output terminal 126 included in the multiplexer 12 in the previous embodiment, the multiplexer 12 in this embodiment further includes another input terminal and another output terminal, namely a third input terminal 128 and a third output terminal 130. The third input terminal 128 of the multiplexer 12 is coupled to the detection signal VD, and the third output terminal 130 is coupled to the negative input terminal 144 of the comparator 14. The remaining connection relationships of the multiplexer 12 are the same as those in the above embodiments, and therefore will not be described again.

[0059] like Figure 5 As shown, and further refer to Figure 6The comparison result signal OUT generated by the comparator 14 is output to the drive circuit 20. The drive circuit 20 generates a drive signal OUTT based on the comparison result signal OUT and sends it to the control terminal 162 of the switching element 16 to control the switching element 16 to turn on or off. This avoids the comparator 14 from being affected by noise and outputting an unstable comparison result signal OUT to the switching element 16. In addition, the drive circuit 20 can generate the drive signal OUTT based on the waveform characteristics such as the rising edge and falling edge of the comparison result signal OUT, making the control of the switching element 16 easier to calibrate. The multiplexer 12 selects and outputs the detection signal VD, the first reference signal VR1, and the second reference signal VR2 to the comparator 14 based on the received comparison reference signal. When the comparison reference signal is at the first level (low level in this embodiment), the multiplexer 12 transmits the first reference signal VR1 to the positive input terminal 142 of the comparator 14 and transmits the detection signal VD to the negative input terminal 144 of the comparator 14. When the detection signal VD is less than the first reference signal VR1, the comparator 14, based on the comparison result signal OUT, turns the drive circuit 20. When the comparison reference signal is at the second level (high level in this embodiment), the multiplexer 12 transmits the detection signal VD to the positive input terminal 142 of the comparator 14 and transmits the second reference signal VR2 to the negative input terminal 144 of the comparator 14. Therefore, when the detection signal VD is greater than the second reference signal VR2, the drive circuit 20 generates another pulse in the drive signal OUTT based on the comparison result signal OUT to control the switching element 16 to turn off.

[0060] In the third embodiment described above, the comparison reference signal input to the multiplexer 12 can be generated by the driving circuit 20, and the driving circuit 20 can also integrate the function of the delay circuit 18 of the previous embodiment, thereby generating the delay signal SET, which is equivalent to delaying the comparison result signal OUT, and transmitting it to the multiplexer 12 as the comparison reference signal input to the multiplexer 12.

[0061] In addition, such as Figure 7 The diagram shown is a circuit diagram of the fourth embodiment of the present invention. It is based on the circuit of the third embodiment, but the comparison result signal OUT is fed back to the multiplexer 12 as the comparison reference signal input to the multiplexer 12. The operation of the other signals is the same as that of the third embodiment described above, so it will not be described again.

[0062] Even more so, such as Figure 8The diagram shown is a circuit diagram of the fifth embodiment of the present invention. It is based on the circuit of the third embodiment, but the driving signal OUTT is fed back to the multiplexer 12 as the comparison reference signal input to the multiplexer 12. The operation of the other signals is the same as in the above embodiments, so it will not be described again.

[0063] Compared to existing synchronous rectification circuits that rely on two different circuits to process two reference signals, the error components of the two different circuits may overlap, severely affecting the accuracy of synchronous rectification. This invention proposes an improved synchronous rectification circuit in the embodiments described above. By using a multiplexer to couple a first reference signal and a second reference signal, the multiplexer selects either the first or the second reference signal as input to the comparator. The comparator then compares a detection signal of a switching element and generates a comparison result signal to the switching element, thereby controlling the switching element for synchronous rectification. Thus, this invention reduces the power consumption of the power supply device and reduces the overall circuit area using a single comparator. More importantly, even if the comparator has errors, these errors will be completely or at least partially eliminated because they act on both the first and second reference signals simultaneously. Furthermore, the overlapping errors of the two circuits will not occur, significantly reducing the need for error calibration in the synchronous rectification circuits of this invention.

[0064] In the embodiments described above, the synchronous rectification circuit of the present invention selects the output signal to the comparator through a multiplexer, and uses the comparison result signal output by the comparator to control the control terminal of the switching element of the synchronous rectification, thereby achieving synchronous rectification, saving energy consumption, and reducing the circuit area occupied.

[0065] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. All equivalent variations and modifications made in accordance with the shape, structure, features and spirit described in the claims of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A synchronous rectifier circuit, characterized in that, It includes: A multiplexer comprising two inputs and one output; A comparator coupled to the output of the multiplexer; and A switching element includes a control terminal coupled to the comparator; A first reference signal and a second reference signal are respectively coupled to the two input terminals of the multiplexer. The multiplexer selects to output either the first reference signal or the second reference signal to the comparator based on a comparison reference signal. The comparator compares a detection signal of the switching element based on the first reference signal or the second reference signal and generates a comparison result signal to the switching element. The comparator compares the first reference signal with the detection signal. When the detection signal is less than the first reference signal, the comparison result signal controls the switching element to turn on. The comparator compares the second reference signal with the detection signal. When the detection signal is greater than the second reference signal, the comparison result signal controls the switching element to turn off.

2. The synchronous rectifier circuit as described in claim 1, characterized in that, in, The detection signal is a signal representing the voltage at one of the switch output terminals of the switching element.

3. The synchronous rectifier circuit as described in claim 1, characterized in that, in, The comparison reference signal is the comparison result signal.

4. The synchronous rectifier circuit as described in claim 1, characterized in that, in, The comparison reference signal is the delayed comparison result signal.

5. The synchronous rectifier circuit as described in claim 4, characterized in that, It further includes: a delay circuit coupled between the multiplexer and the comparator to delay the comparison result signal by a default time and form the comparison reference signal to be transmitted to the multiplexer.

6. The synchronous rectifier circuit as described in claim 1, characterized in that, It further includes: a drive circuit coupled to the control terminal of the comparator and the switching element, so as to output a drive signal to the switching element according to the comparison result signal output by the comparator.

7. The synchronous rectifier circuit as described in claim 1, characterized in that, in, When the comparison reference signal is at a first level, the multiplexer transmits the first reference signal to the comparator; when the comparison reference signal is at a second level, the multiplexer transmits the second reference signal to the comparator.

8. The synchronous rectifier circuit as described in claim 1, characterized in that, in, The comparator includes a positive input and a negative input. The detection signal is coupled to the negative input, and the output of the multiplexer is coupled to the positive input.

9. The synchronous rectifier circuit as described in claim 1, characterized in that, in, The comparator includes a positive input and a negative input. The output of the multiplexer is coupled to the positive input. The multiplexer also includes another input and another output. The detection signal is coupled to the other input, and the other output is coupled to the negative input.

10. The synchronous rectifier circuit as described in claim 9, characterized in that, in, When the comparison reference signal is at a first level, the multiplexer transmits the first reference signal to the positive input of the comparator and transmits the detection signal to the negative input of the comparator; when the comparison reference signal is at a second level, the multiplexer transmits the detection signal to the positive input of the comparator and transmits the second reference signal to the negative input of the comparator.

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