Low power flip-flop

Abstract

The application provides a low-power flip-flop, a clock control module, comprising an input signal end, an output signal end and a clock signal end; the clock control module is configured to input an input signal D through the input signal end, input a clock signal Clock through the clock signal end and connect an output signal Q through the output signal end to control the clock signal Clock to generate a controlled clock signal; a flip-flop module is selectively latched by the input signal and the controlled clock signal generated by the clock control module to generate the output signal. Compared with the common flip-flop without the clock control module, the dynamic power consumption of the low-power flip-flop of the application is small with the decrease of the signal flip rate, and the dynamic power consumption can be significantly reduced when the switch activity rate is low.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a low-power trigger. Background Technology

[0002] In current circuit design, flip-flops are widely used. In very large-scale integrated circuits (VLSI), reducing energy consumption is the direct goal of low-power design, and the main reason for energy consumption is the constant switching between 0 and 1 at high frequencies. Other energy consumption consists of dynamic and static components depending on the circuit characteristics. Dynamic circuits consume energy by pre-charging the capacitors at circuit nodes, while static circuits mainly consume energy in the form of subthreshold leakage current. Therefore, the clock network composed of timing units (flip-flops and latches) is the main source of energy consumption in VLSI systems.

[0003] In typical integrated circuit designs, approximately 30% to 60% of the energy consumption is in the clock network. Reducing the energy consumption of flip-flops directly reduces the overall system energy consumption. Furthermore, improving flip-flop performance directly reduces the distributed constraints of the clock network and enhances the overall system performance. Therefore, the proper design and selection of flip-flops have a significant impact on the overall system performance and energy consumption. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a low-power trigger to solve the problem of high dynamic power consumption of triggers in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a low-power trigger, comprising at least:

[0006] A clock control module includes an input signal terminal, an output signal terminal, and a clock signal terminal; the clock control module is configured to control the clock signal Clock by receiving an input signal D through the input signal terminal, receiving the clock signal Clock through the clock signal terminal, and connecting an output signal Q through the output signal terminal, so as to generate a controlled clock signal;

[0007] The trigger module selectively latches the input signal D using the input signal D and the controlled clock signal generated by the clock control module to generate the output signal Q.

[0008] Preferably, the first to fifth PMOS and the first to fifth NMOS are used; wherein one end of the first and second PMOS and the first and second NMOS are connected to the gate of the fourth PMOS and the fourth NMOS respectively; the other ends of the first PMOS and the first NMOS are connected to each other, and the connection end serves as the input signal end; the gate of the first NMOS and the gate of the second PMOS are connected to each other, and the connection end serves as the output signal end; the fourth PMOS, the fifth PMOS and the fifth NMOS are connected in series from end to end; the connection end CKN of the fifth PMOS and the fifth NMOS is connected to the drain of the fourth NMOS, the gate of the third PMOS and the gate of the third NMOS; the gate of the fifth PMOS and the gate of the fifth NMOS are connected to each other, and the connection end serves as the clock signal end CLK; the drain of the third PMOS and the drain of the third NMOS are connected to form the connection end CKP.

[0009] Preferably, the drain of the fourth PMOS is connected to the source of the fifth PMOS; the drain of the fifth PMOS is connected to the drain of the fifth NMOS; the source of the fifth NMOS is connected to the source of the fourth NMOS and grounded; and the source of the third NMOS is grounded.

[0010] Preferably, the other end of the second PMOS is connected to the other end of the second NMOS, and the connection terminal outputs a signal DB that is opposite in level to the input signal D.

[0011] Preferably, the gate output of the first NMOS is a signal QB that is opposite in level to the output signal Q.

[0012] Preferably, when the input signal D and the output signal Q are the same, the fourth PMOS is turned off, the fourth NMOS is turned on, the signal at the connection terminal CKN is pulled down to a low level, and the signal at the connection terminal CKP is correspondingly high.

[0013] Preferably, when the input signal D is different from the output signal Q, the fourth PMOS is turned on and the fourth NMOS is turned off, and the signals of the connection terminal CKN and the connection terminal CKP follow the clock signal Clock of the clock signal terminal CLK.

[0014] As described above, the low-power trigger of the present invention has the following beneficial effects: Compared with ordinary triggers without a clock control module, the low-power trigger of the present invention has low dynamic power consumption as the signal switching rate decreases, and can significantly reduce dynamic power consumption when the switching activity rate is low. Attached Figure Description

[0015] Figure 1The diagram shown is a schematic of the low-power trigger circuit of the present invention;

[0016] Figure 2 The diagram shows the circuit structure of the clock control module in this invention.

[0017] Figure 3 The diagram shows a power consumption comparison between the trigger of the present invention and a common trigger in the prior art.

[0018] Figure 4 The diagram shows a functional simulation of a trigger in the prior art with a switching activity rate of 25%.

[0019] Figure 5 The diagram shown is a functional simulation of the low-power trigger of this invention when the switching activity rate is 25%. Detailed Implementation

[0020] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0021] Please see Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0022] This invention provides a low-power trigger, such as... Figure 1 As shown, Figure 1 The diagram shows a low-power trigger circuit of the present invention. The trigger includes at least a clock control module (CLK_CONTROL), which includes an input signal terminal, an output signal terminal, and a clock signal terminal. The clock control module is configured to control the clock signal Clock by connecting an input signal D through the input signal terminal, connecting the clock signal Clock through the clock signal terminal, and connecting an output signal Q through the output signal terminal, thereby generating a controlled clock signal.

[0023] The trigger module (DFF) selectively latches the input signal D using the input signal D and the controlled clock signal generated by the clock control module to generate the output signal Q.

[0024] Further, in this embodiment, the clock control module includes: first to fifth PMOS and first to fifth NMOS; wherein one end of the first and second PMOS and the first and second NMOS are interconnected with the gate of the fourth PMOS and the fourth NMOS; the other ends of the first PMOS and the first NMOS are interconnected, and the connection end serves as the input signal terminal; the gate of the first NMOS and the gate of the second PMOS are interconnected, and the connection end serves as the output signal terminal; the fourth PMOS, the fifth PMOS, and the fifth NMOS are connected in series from beginning to end; the connection terminal CKN of the fifth PMOS and the fifth NMOS is connected to the drain of the fourth NMOS, the gate of the third PMOS, and the gate of the third NMOS; the gate of the fifth PMOS and the gate of the fifth NMOS are interconnected, and the connection end serves as the clock signal terminal CLK; the drain of the third PMOS and the drain of the third NMOS are connected to form the connection terminal CKP.

[0025] like Figure 2 As shown, Figure 2 The diagram shows the circuit structure of the clock control module in this invention. The clock control module includes: first to fifth PMOS and first to fifth NMOS; wherein one end of the first PMOS (01), second PMOS (03), first NMOS (02), and second NMOS (04) is interconnected with the gate of the fourth PMOS (P_C) and fourth NMOS (N_C); the other ends of the first PMOS (01) and first NMOS (02) are interconnected, and the connection end serves as the input signal terminal; the gate of the first NMOS (02) is interconnected with the gate of the second PMOS (03), and the connection end serves as the output signal terminal; the fourth... The PMOS (P_C), the fifth PMOS (07), and the fifth NMOS (08) are connected in series. The first and last connection terminals CKN of the fifth PMOS (07) and the fifth NMOS (08) are connected to the drain of the fourth NMOS (N_C), the gate of the third PMOS (05), and the gate of the third NMOS (06). The gate of the fifth PMOS (07) and the gate of the fifth NMOS (08) are connected to each other, and the connection terminal serves as the clock signal terminal CLK. The drain of the third PMOS (05) and the drain of the third NMOS (06) are connected to form the connection terminal CKP.

[0026] Further, as in the present invention Figure 2As shown, in this embodiment, the drain of the fourth PMOS (P_C) is connected to the source of the fifth PMOS (07); the drain of the fifth PMOS (07) is connected to the drain of the fifth NMOS (08); the source of the fifth NMOS (08) is connected to the source of the fourth NMOS (N_C) and grounded; the source of the third NMOS (06) is grounded.

[0027] In this embodiment, the source of the fourth PMOS (P_C) is connected to the power supply voltage; the source of the third PMOS is connected to the power supply voltage.

[0028] In a further embodiment of the present invention, the other end of the second PMOS (03) is connected to the other end of the second NMOS, and the connection end outputs a signal DB that is opposite to the level of the input signal D.

[0029] Furthermore, in this embodiment, the gate output of the second NMOS is a signal QB that is opposite in level to the output signal Q.

[0030] Furthermore, in this embodiment, the gate output of the first NMOS is a signal QB that is opposite in level to the output signal Q.

[0031] Furthermore, in this embodiment, when the input signal D and the output signal Q are the same, the fourth PMOS is turned off, the fourth NMOS is turned on, the signal at the connection terminal CKN is pulled down to a low level, and the signal at the connection terminal CKP is correspondingly high.

[0032] Furthermore, in this embodiment, when the input signal D is different from the output signal Q, the fourth PMOS is turned on and the fourth NMOS is turned off, and the signals of the connection terminal CKN and the connection terminal CKP follow the clock signal Clock of the clock signal terminal CLK.

[0033] In other words, from Figure 1 and Figure 2 As can be seen from the diagram, when the input signal D matches the output signal Q, the P_C transistor is off and the N_C transistor is on; CKN is pulled down to 0, and CKP is correspondingly 1, and it will not change as long as the input signal D matches the output signal Q. When the input signal D is different from the output signal Q, the P_C transistor is on and the N_C transistor is off; the CKN and CKP signals normally follow the changes of the CLK signal.

[0034] like Figure 3 As shown, Figure 3 The graph shows a power consumption comparison between the trigger of this invention and a conventional trigger in the prior art. It can be seen that as the signal switching rate decreases, the dynamic power consumption of the low-power trigger of this invention is significantly lower.

[0035] like Figure 4 and Figure 5 As shown, Figure 4 The diagram shows a functional simulation of a trigger in the prior art with a switching activity rate of 25%. Figure 5 The diagram shown is a functional simulation of the low-power trigger of this invention at a switching activity rate of 25%. It can be seen that when the switching activity rate is low, the low-power trigger of this invention can significantly reduce dynamic power consumption.

[0036] In summary, compared with ordinary triggers without a clock control module, the low-power trigger of this invention exhibits lower dynamic power consumption as the signal switching rate decreases, and can significantly reduce dynamic power consumption when the switching activity rate is low. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0037] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A low power flip-flop, characterized by, At least including: The clock control module includes an input signal terminal, an output signal terminal, and a clock signal terminal; The clock control module is configured to control the clock signal Clock by receiving an input signal D through the input signal terminal, receiving the clock signal Clock through the clock signal terminal, and connecting an output signal Q through the output signal terminal, so as to generate a controlled clock signal. The trigger module selectively latches the input signal D using the input signal D and the controlled clock signal generated by the clock control module to generate the output signal Q. The clock control module includes: first to fifth PMOS and first to fifth NMOS; wherein one end of the first and second PMOS and the first and second NMOS are interconnected with the gate of the fourth PMOS and the fourth NMOS; the other ends of the first PMOS and the first NMOS are interconnected, and the connection end serves as the input signal terminal; the gate of the first NMOS and the gate of the second PMOS are interconnected, and the connection end serves as the output signal terminal; the fourth PMOS, the fifth PMOS, and the fifth NMOS are connected in series from beginning to end; the connection terminal CKN between the fifth PMOS and the fifth NMOS is connected to the drain of the fourth NMOS, the gate of the third PMOS, and the third NMOS. The gates of the fifth PMOS and the fifth NMOS are connected to each other, and the connection terminal serves as the clock signal terminal CLK. The drain of the third PMOS and the drain of the third NMOS are connected to form the connection terminal CKP. When the input signal D is the same as the output signal Q, the fourth PMOS is turned off and the fourth NMOS is turned on. The signal of the connection terminal CKN is pulled down to a low level, and the signal of the connection terminal CKP is correspondingly high. When the input signal D is different from the output signal Q, the fourth PMOS is turned on and the fourth NMOS is turned off. The signals of the connection terminals CKN and CKP follow the clock signal Clock of the clock signal terminal CLK.

2. The low power flip-flop according to claim 1, wherein: The drain of the fourth PMOS is connected to the source of the fifth PMOS; the drain of the fifth PMOS is connected to the drain of the fifth NMOS; the source of the fifth NMOS is connected to the source of the fourth NMOS and grounded; the source of the third NMOS is grounded.

3. The low power flip-flop according to claim 1, wherein: The other end of the second PMOS is connected to the other end of the second NMOS, and the connection terminal outputs a signal DB that is opposite in level to the input signal D.

4. The low power flip-flop of claim 1, wherein: The gate output of the second NMOS is a signal QB that is opposite in level to the output signal Q.

5. The low power consumption flip-flop according to claim 1, wherein: The gate output of the first NMOS is a signal QB that is opposite in level to the output signal Q.

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