A resettable radiation-hardened scan structure D flip-flop

Abstract

The application belongs to the field of flip-flops, and particularly relates to a resettable anti-radiation reinforced scanning structure D flip-flop. The D flip-flop comprises sequentially connected data input buffer circuit, scanning control circuit, main latch, main latch error repair circuit, slave latch, slave latch error repair circuit and output circuit, and further comprises clock circuit and reset buffer circuit connected with the main latch and the slave latch respectively. When single event upsets occur in sensitive nodes of the main latch or the slave latch in the D flip-flop, the main latch error repair circuit and the slave latch error repair circuit can detect the generation of transient pulses of the internal sensitive nodes, and then process the transient pulses generated by the sensitive nodes through a circuit structure formed by starting a delay unit and a Miller C unit, so as to ensure the stability of the output signal.

Description

Technical Field

[0001] This invention belongs to the field of triggers, specifically a resettable, radiation-hardened scanning structure D trigger. Background Technology

[0002] The continuous reduction in integrated circuit supply voltage and node capacitance leads to a gradual decrease in signal charge, making nanoscale integrated circuits increasingly sensitive to single-event effects. Single-event transients (SETs) are primarily caused by alpha particles and atmospheric neutrons, mainly originating from packaging materials and cosmic rays. These particles generate additional electron-hole pairs through reaction with the silicon substrate. Sensitive nodes in integrated circuits collect these electron-hole pairs, generating transient pulses at the sensitive nodes. When the amplitude and duration of the generated transient pulse are sufficiently large, they can cause changes in the data values ​​stored in latches, resulting in single-event upsets (SEUs). Flip-flops are fundamental storage elements widely used in digital systems, which include pipelined structures and modules composed of flip-flops, such as shift registers, counters, and FIFO units. In microcontrollers and network memory chips, timing elements such as flip-flops account for nearly 50% of soft errors, making soft error reliability design increasingly critical. However, unlike memory which can use error correction coding or parity checking for error checking, flip-flops are randomly distributed across the entire chip, making these techniques difficult to apply. Typically, hardening design techniques employ redundancy or hardening by design (HBD). Redundancy can be divided into temporal redundancy and spatial redundancy. The most widely used spatial redundancy technique in the industry is Triple Modular Redundancy (TMR). This involves copying the circuit to be protected three times and then voting on the results to output the correct logic state. Temporal redundancy involves sampling data at different times and storing the sampled values ​​in different latches, then using a voter to output the correct data. Both redundancy techniques consume significant area and power in the copied circuitry and also increase transmission delays in the sampling and voting circuits. Hardening by design, on the other hand, through careful design of the internal structure of the flip-flop circuit, can effectively prevent the data stored in sensitive nodes from being corrupted, achieving flip-flop hardening with less area, power consumption, and performance. Summary of the Invention

[0003] This invention employs circuit design hardening technology to propose a resettable, radiation-hardened scanning structure D flip-flop. This D flip-flop can resist the effects of single-event upsets and single-event transient pulses on the circuit, thereby solving the reliability problem of scanning D flip-flops resisting both single-event upsets and single-event transients. This invention can be applied to high-reliability circuit chips.

[0004] The technical solution adopted by the present invention to achieve the above objectives is as follows:

[0005] A resettable radiation-hardened scanning structure D flip-flop includes: a data input buffer circuit, a scan control circuit, a master latch, a master latch error repair circuit, a slave latch, a slave latch error repair circuit, and an output circuit, all connected in sequence; and a clock circuit and a reset buffer circuit, which are respectively connected to the master latch and the slave latch.

[0006] The reset buffer circuit consists of four sets of series-connected reverse MOS units M1 to M4 and one set of double-layer reverse MOS units DM1. The input terminal of the reverse MOS unit M1 is connected to the first input terminal of the double-layer reverse MOS unit DM1, and together they serve as the input terminal of the reset buffer circuit. The output terminal of the reverse MOS unit M4 is connected to the second and third input terminals of the double-layer reverse MOS unit DM1, and the output terminal of the double-layer reverse MOS unit DM1 serves as the output terminal of the reset buffer circuit.

[0007] The master latch and slave latch have the same structure. The master latch includes: the first input terminal of the double-layer inverted MOS unit DM2 serves as the scan control signal input terminal of the master latch and is connected to the output terminal of the scan control circuit; the second input terminal of the double-layer inverted MOS unit DM2 and the third input terminal of the double-layer inverted MOS unit DM3 together serve as the positive clock signal input terminal of the master latch and are connected to the positive clock output terminal of the clock circuit; the third input terminal of the double-layer inverted MOS unit DM2 and the second input terminal of the double-layer inverted MOS unit DM3 together serve as the inverted clock signal input terminal of the master latch and are connected to the inverted clock output terminal of the clock circuit; the output terminal of the double-layer inverted MOS unit DM2 and the double-layer inverted MOS unit DM3 together serve as the inverted clock signal input terminal of the master latch and are connected to the inverted clock output terminal of the clock circuit; and the output terminal of the double-layer inverted MOS unit DM2 and the double-layer inverted MOS unit DM3 together serve as the inverted clock signal input terminal of the master latch. The output terminals of unit DM3 serve as the first output terminal of the main latch, and are connected to the gates of PMOS transistor P1 and NMOS transistor N1 respectively. The source of PMOS transistor P1 is connected to the power supply VDD, and the drain of PMOS transistor P1 is connected to the source of PMOS transistor P2. The gates of PMOS transistor P2 and NMOS transistor N2 serve as the reset buffer signal input terminal of the main latch, and are connected to the output terminal of the reset buffer circuit. The drain of PMOS transistor P2 is connected to the source of NMOS transistor N1, the source of NMOS transistor N2, and the output terminal of the double-layer reverse MOS unit DM3, and together serve as the second output terminal of the main latch. The drains of NMOS transistor N1 and NMOS transistor N2 are both grounded.

[0008] The master latch error repair circuit and the slave latch error repair circuit have the same structure. The master latch error repair circuit includes: the first and second input terminals of the error detection unit are respectively connected to the first and second output terminals of the master latch error repair circuit; the first output terminal of the error detection unit is connected to the third input terminal of the double-layer reverse MOS unit DM4 and the fourth input terminal of the triple-layer reverse MOS unit TM1; the second output terminal of the error detection unit is connected to the second input terminal of the double-layer reverse MOS unit DM4, the third input terminal of the triple-layer reverse MOS unit TM1, and the gate of the NMOS transistor N4; the first input terminal of the double-layer reverse MOS unit DM4 is connected to the second input terminal of the error detection unit, the first input terminal of the triple-layer reverse MOS unit TM1, the drain of the PMOS transistor P4, and the gate of the NMOS transistor N4. The drain of S-channel transistor N4 is connected. The output of the dual-layer reverse MOS unit DM4 is connected to the first input of the dual-layer reverse MOS unit DM5, the gate and drain of PMOS transistor P3, and the gate and drain of NMOS transistor N3. The second input of the dual-layer reverse MOS unit DM5 is connected to its third input, the source of PMOS transistor P3, and the source of NMOS transistor N3. The output of the dual-layer reverse MOS unit DM5 is connected to the input of the reverse MOS unit M5. The output of the reverse MOS unit M5 is connected to the input of the reverse MOS unit M6. The output of the reverse MOS unit M6 is connected to the second input of the triple-layer reverse MOS unit TM1. The output of the triple-layer reverse MOS unit TM1, the source of PMOS transistor P4, and the source of NMOS transistor N4 together serve as the output of the main latch error repair circuit.

[0009] The error detection unit includes: the input terminal of the reverse MOS unit M7 serves as the first input terminal of the error detection unit; the output terminal of the reverse MOS unit M7 is connected to the first input terminal of the double-layer reverse MOS unit DM6, the source of PMOS transistor P5, and the source of NMOS transistor N5, respectively; the input terminal of the reverse MOS unit M8 serves as the second input terminal of the main latch error detection circuit, and is connected to the third input terminal of the double-layer reverse MOS unit DM6 and the gate of PMOS transistor P5, respectively; the output terminal of the reverse MOS unit M8 is connected to the second input terminal of the double-layer reverse MOS unit DM6 and the gate of NMOS transistor N5, respectively; the output terminal of the double-layer reverse MOS unit DM6 is connected to the drain of PMOS transistor P5, the drain of NMOS transistor N5, and the input terminal of the reverse MOS unit M9, respectively; the output terminal of the reverse MOS unit M9 serves as the first output terminal of the error detection unit and is connected to the input terminal of the reverse MOS unit M10; and the output terminal of the reverse MOS unit M10 serves as the second output terminal of the error detection unit.

[0010] The reverse MOS unit includes a PMOS transistor and an NMOS transistor. The gates of the PMOS transistor and the NMOS transistor are connected as the input terminal of the reverse MOS unit, and the drains of the PMOS transistor and the NMOS transistor are connected as the output terminal of the reverse MOS unit. The source of the PMOS transistor is connected to the power supply VDD, and the source of the NMOS transistor is grounded.

[0011] The dual-layer reverse MOS unit includes two PMOS transistors and two NMOS transistors. The source of the first PMOS transistor is connected to the power supply VDD, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, and the gate of the first PMOS transistor is connected to the gate of the first NMOS transistor, serving as the first input terminal of the dual-layer reverse MOS unit. The gate of the second PMOS transistor serves as the second input terminal of the dual-layer reverse MOS unit, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, serving as the output terminal of the dual-layer reverse MOS unit. The gate of the second NMOS transistor serves as the third input terminal of the dual-layer reverse MOS unit, and the source of the second NMOS transistor is connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is grounded.

[0012] The three-layer reverse MOS unit includes three PMOS transistors and three NMOS transistors. The source of the third PMOS transistor is connected to the power supply VDD, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor, and the gate of the third PMOS transistor is connected to the gate of the third NMOS transistor, serving as the first input terminal of the three-layer reverse MOS unit. The gate of the fourth PMOS transistor is connected to the gate of the fourth NMOS transistor, serving as the second input terminal of the three-layer reverse MOS unit. The gate of the fourth PMOS transistor is connected to the gate of the fifth NMOS transistor, serving as the third input terminal of the three-layer reverse MOS unit. The drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor, serving as the output terminal of the three-layer reverse MOS unit. The gate of the fifth NMOS transistor serves as the fourth input terminal of the two-layer reverse MOS unit. The source of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor is connected to the drain of the third NMOS transistor. The source of the third NMOS transistor is grounded.

[0013] The present invention has the following beneficial effects and advantages:

[0014] 1. The present invention provides a resettable radiation-hardened scanning structure D flip-flop. When the data input signal D or the clock signal CK is affected by a single-event transient, resulting in glitches or ripples on the data input signal and the clock signal, the structure in the data input buffer circuit and the clock circuit achieves suppression of the single-event transient through the connection of the delay unit and the Miller C unit.

[0015] 2. The present invention discloses a resettable radiation-hardened scanning structure D flip-flop. When a single-event flip occurs at the sensitive node of the master latch or slave latch inside the D flip-flop, the error repair circuit of the master latch and the error repair circuit of the slave latch will detect the generation of transient pulses at the internal sensitive node. Then, through the circuit structure formed by the start-up delay unit and the Miller C unit, the transient pulses generated by the sensitive node are processed to ensure the stability of the output signal. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the overall logical structure of the present invention;

[0017] Figure 2 This is a schematic diagram of the clock circuit in this invention;

[0018] Figure 3 This is a schematic diagram of the data input buffer circuit in this invention;

[0019] Figure 4 This is a schematic diagram of the scanning control circuit in this invention;

[0020] Figure 5 This is a schematic diagram of the reset buffer circuit in this invention;

[0021] Figure 6 This is a schematic diagram of the main latch circuit in this invention;

[0022] Figure 7 This is a schematic diagram of the main latch error repair circuit in this invention;

[0023] Figure 8 This is a schematic diagram of the latch circuit in this invention;

[0024] Figure 9 This is a schematic diagram of the latch error repair circuit in this invention;

[0025] Figure 10 This is a schematic diagram of the output circuit in this invention;

[0026] Figure 11 A schematic diagram of the SEU fault injection simulation results for a standard scanning structure D trigger without radiation hardening design;

[0027] Figure 12 This is a schematic diagram of the simulation results of SEU fault injection in this invention;

[0028] Figure 13 A schematic diagram of simulation results for injecting a fault into the data terminal SET of a general-type scan-structure D flip-flop;

[0029] Figure 14 This is a schematic diagram of the simulation results for the data terminal SET fault injection of the present invention;

[0030] Figure 15 A schematic diagram of the simulation results for injecting a fault SET at the clock terminal of a general-type scan structure D flip-flop;

[0031] Figure 16 This is a schematic diagram of the simulation results for clock terminal SET fault injection in this invention;

[0032] Figure 17 A schematic diagram of the simulation results for injecting a fault into the reset terminal (SET) of a general-type scan structure D flip-flop;

[0033] Figure 18 This is a schematic diagram of the simulation results for fault injection at the reset terminal (SET) of the present invention. Detailed Implementation

[0034] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0035] A resettable, radiation-hardened scanning structure D flip-flop has five inputs and two outputs. The five inputs are clock signal input CK, data signal input D, scan input select SE, scan input data SI, and reset signal input RN; the outputs are Q and QN.

[0036] The clock circuit receives the system clock signal CK, connects to the master latch and slave latch, and generates an output signal C and CN that are the same as and opposite to the logic state of the clock signal CK.

[0037] The data input buffer circuit receives the data signal D, which is connected to the scan control circuit.

[0038] The scan control circuit receives the output signal DS from the data input buffer circuit and connects it to the main latch.

[0039] The reset buffer circuit receives the reset signal RN and outputs the reset control signal R1 to the master latch and the slave latch.

[0040] The main latch receives the output signal S from the scan control circuit, is connected to the main latch error repair circuit, and outputs signals M1 and M2.

[0041] The main latch error correction circuit receives signals M1 and M2 from the main latch circuit and outputs signal MC.

[0042] The slave latch receives the output signal MC from the master latch error repair circuit, connects to the slave latch error repair circuit, and outputs signals S1 and S2.

[0043] The latch error repair circuit receives signals S1 and S2 from the latch circuit, and the output terminal SC is connected to the output circuit.

[0044] The output circuit outputs Q and QN after buffering.

[0045] Figure 1 This is a schematic diagram of the overall logic structure of a resettable, radiation-hardened scanning structure D flip-flop according to the present invention. The present invention comprises a clock circuit (such as...) Figure 2 As shown), data input buffer circuit (such as...) Figure 3 (as shown), scanning control circuit (such as) Figure 4 As shown), reset buffer circuit (such as) Figure 5 As shown), the main latch circuit (such as...) Figure 6 (as shown), main latch error repair circuit (such as) Figure 7 As shown), from the latch circuit (such as Figure 8 As shown), from the latch error repair circuit (such as...) Figure 9 As shown), output circuit (such as) Figure 10 (As shown)

[0046] This invention discloses a resettable, radiation-hardened scanning structure D flip-flop with five inputs and two outputs. The five inputs are: clock signal input CK, data signal input D, scan input selection input SE, scan input data input SI, and reset signal input RN; the outputs are Q and QN. The clock circuit receives CK, buffers the CK signal, and outputs CN and C. The data input buffer circuit receives the data signal D, buffers D, and outputs DS. The scan control circuit receives the DS signal, the scan input selection signal SE, and the scan input data signal SI. When SE is high, the scan input data signal is valid; when SE is low, the buffered data input signal DS is valid. The reset buffer circuit receives the reset signal RN, buffers it, and performs a logic flip before inputting it to the master latch and slave latch. The master latch receives the valid signal S from the scan control circuit and sends it into its internal circuitry. When a transient pulse is generated in an internal storage node, causing a single-event upset (SET) that triggers a change in the logic state, the master latch's error correction circuit, through the combined action of its internal delay unit and Miller C unit, releases the transient pulse, thereby restoring the circuit's logic level. The slave latch receives the output signal MC from the master latch's pulse filtering circuit and sends it into its internal circuitry. When a SET occurs in a storage node within the slave latch, its error correction circuit similarly activates its internal circuitry to release the charge pulse of the upset node, restoring the circuit's logic level. The output circuit receives the output signal SC from the slave latch's error correction circuit, buffers it, and then outputs Q and QN.

[0047] like Figure 2As shown, the clock circuit includes nine PMOS transistors and nine NMOS transistors. The substrates of all PMOS transistors are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg1 of the first PMOS transistor is connected to CK, its drain Pd1 is connected to the drain Nd1 of the first NMOS transistor, and its source Ps1 is connected to the power supply VDD. The gate Pg2 of the second PMOS transistor is connected to the drain Pd1 of the first PMOS transistor, the drain Nd1 of the first NMOS transistor, and the gate Ng2 of the second NMOS transistor, and its source Ps2 is connected to the power supply VDD. The gate Pg3 of the third PMOS transistor is connected to the drain Pd2 of the second PMOS transistor, the drain Nd2 of the second NMOS transistor, and the gate Ng3 of the third NMOS transistor, and its source Pg2 is connected to the power supply VDD. S3 is connected to power supply VDD; the gate Pg4 of the fourth PMOS transistor is connected to the drain Pd3 of the third PMOS transistor, the drain Nd3 of the third NMOS transistor, and the gate Ng4 of the fourth NMOS transistor, and its source Ps4 is connected to power supply VDD; the gate Pg5 of the fifth PMOS transistor is connected to the input clock signal CK and the gate Ng5 of the fifth NMOS transistor, and its drain Pd5 is connected to the source Ps6 of the sixth PMOS transistor, which is also connected to power supply VDD; the gate Pg6 of the sixth PMOS transistor is connected to the drain Pd4 of the fourth PMOS transistor, the drain Nd4 of the fourth NMOS transistor, and the gate Ng6 of the sixth NMOS transistor, which is also connected to the source Ps6 of the sixth NMOS transistor. The drain of the sixth PMOS transistor is Nd6, and the source of the sixth PMOS transistor is connected to the drain of the fifth PMOS transistor, Pd5. The gate of the seventh PMOS transistor, Pg7, is connected to the gates of the eighth PMOS transistor, Pg8, Ng7, and Ng8, as well as the output terminal C of the clock circuit. The drain of the seventh PMOS transistor, Pd7, is connected to the source of the eighth PMOS transistor, Ps8. The source of the seventh PMOS transistor, Ps7, is connected to VDD. The drain of the eighth PMOS transistor, Pg8, is connected to the drain of the eighth NMOS transistor, Nd8, Pg9, and Ng9, as well as the output terminal CN of the clock circuit. The gate of the eighth PMOS transistor, Pg8, is connected to the gate of the seventh PMOS transistor, Pg7. The gates of the seventh NMOS transistor (Ng7) and the eighth NMOS transistor (Ng8), and the source of the eighth PMOS transistor (Ps8) are connected to the drain of the seventh PMOS transistor (Pd7). The drain of the ninth PMOS transistor (Pd9) is connected to the drain of the ninth NMOS transistor (Nd9) and the output terminal C of the clock buffer circuit. The gate of the ninth PMOS transistor (Pg9) is connected to the gate of the ninth NMOS transistor (Ng9), the drain of the eighth PMOS transistor (Pd8), the drain of the eighth NMOS transistor (Nd8), and the inverted output terminal CN of the clock circuit. The gate of the first NMOS transistor (Ng1) is connected to the gate of the first PMOS transistor (Pg1), the drain of the first NMOS transistor (Nd1) is connected to the drain of the first PMOS transistor (Pd1), and the source of the first NMOS transistor is connected to ground (VSS).The gate of the second NMOS transistor is connected to the drain Pd1 of the first PMOS transistor, the drain Nd1 of the first NMOS transistor, and the gate Ng2 of the second NMOS transistor. The drain of the second NMOS transistor is connected to the drain Pd2 of the second PMOS transistor, the gate Pg3 of the third PMOS transistor, and the gate Ng3 of the third NMOS transistor. The source of the second NMOS transistor is connected to ground VSS. The gate Ng3 of the third NMOS transistor is connected to the drain Pd2 of the second PMOS transistor, the drain Nd2 of the second NMOS transistor, and the gate Pg3 of the third PMOS transistor. The drain Nd3 of the third NMOS transistor is connected to the drain Pd3 of the third PMOS transistor, the gate Pg4 of the fourth PMOS transistor, and the gate Ng4 of the fourth NMOS transistor. The source of the fourth NMOS transistor is connected to ground VSS; the gate Ng4 of the fourth NMOS transistor is connected to the drain Pd3 of the third PMOS transistor, the drain Nd3 of the third NMOS transistor, and the gate Pg4 of the fourth PMOS transistor; the drain of the fourth NMOS transistor is connected to the logic Pd4 of the fourth PMOS transistor, the gate Pg6 of the sixth PMOS transistor, and the gate Ng6 of the sixth NMOS transistor; the source of the fourth NMOS transistor is connected to ground VSS; the gate Ng5 of the fifth NMOS transistor is connected to the gate Pg5 of the fifth PMOS transistor, the drain Pd4 of the fourth PMOS transistor, and the drain Nd4 of the fourth NMOS transistor; the drain Nd5 of the fifth NMOS transistor is connected to the drain Nd6 of the sixth NMOS transistor; the source Ns5 of the fifth NMOS transistor is connected to VSS; the sixth NMOS transistor... The drain of the transistor is connected to the drain of the sixth PMOS transistor (Pd6), the gate of the ninth PMOS transistor (Pg9), and the gate of the ninth NMOS transistor (Ng9). The gate of the sixth NMOS transistor (Ng6) is connected to the gate of the sixth PMOS transistor (Pg6), the drain of the fourth PMOS transistor (Pd4), and the drain of the fourth NMOS transistor (Nd4). The source of the sixth NMOS transistor (Ns6) is connected to the drain of the fifth NMOS transistor (Nd5). The drain of the seventh NMOS transistor (Nd7) is connected to the source of the eighth NMOS transistor (Ns8). The gate of the seventh NMOS transistor (Ng7) is connected to the gate of the eighth NMOS transistor (Ng8), the gate of the eighth PMOS transistor (Pg8), and the gate of the seventh PMOS transistor (Pg7). The source of the seventh NMOS transistor (Ns7) is connected to VSS. The drain Nd8 is connected to the drain Pd8 of the eighth PMOS transistor, the gate Pg9 of the ninth PMOS transistor, the gate Ng9 of the ninth NMOS transistor, and the inverted output terminal CN of the clock circuit. The gate Ng8 of the eighth NMOS transistor is connected to the gate Ng7 of the seventh NMOS transistor, the gate Pg8 of the eighth PMOS transistor, and the gate Pg7 of the seventh PMOS transistor. The source Ns8 of the eighth NMOS transistor is connected to the drain Nd7 of the seventh NMOS transistor. The drain Nd9 of the ninth NMOS transistor is connected to the drain Pd9 of the ninth PMOS transistor and the output terminal C of the clock circuit. The gate of the ninth NMOS transistor is connected to the gate Ps9 of the ninth PMOS transistor and the inverted output terminal CN of the clock circuit. The source Ns9 of the ninth NMOS transistor is connected to VSS.

[0048] like Figure 3As shown, the data input buffer circuit has one input terminal and one output terminal. One input terminal is connected to the input data signal D, and the other output terminal DS is connected to the scan control circuit. The data input buffer circuit includes eight PMOS transistors and eight NMOS transistors. The substrates of all PMOS transistors are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg10 of the tenth PMOS transistor is connected to the gate Ng10 of the tenth NMOS transistor and the input signal D. The drain Pd10 of the tenth PMOS transistor is connected to the drain Nd10 of the tenth NMOS transistor, and the source Ps10 of the tenth PMOS transistor is connected to the power supply VDD. The gate Pg11 of the eleventh PMOS transistor is connected to the gate Ng11 of the eleventh NMOS transistor. The drain of the 10th PMOS transistor (Pd10) and the drain of the 10th NMOS transistor (Nd10) are connected. The drain of the 11th PMOS transistor (Pd11) is connected to the drain of the 11th NMOS transistor (Nd11), the gate of the 12th PMOS transistor (Pg12), and the gate of the 12th NMOS transistor (Ng12). The source of the 11th PMOS transistor (Ps11) is connected to the power supply VDD. The gate of the 12th PMOS transistor (Pg12) is connected to the gate of the 12th NMOS transistor (Ng12), the drain of the 11th PMOS transistor (Pd11), and the drain of the 11th NMOS transistor (Nd11). The drain of the 12th PMOS transistor (Pd12) is connected to the drain of the 12th NMOS transistor (Nd12), the gate of the 13th PMOS transistor (Pg13), and the gate of the 13th NMOS transistor (Ng13). Ng13, the source Ps12 of the twelfth PMOS transistor is connected to the power supply VDD; the gate Pg13 of the thirteenth PMOS transistor is connected to the gate Ng13 of the thirteenth NMOS transistor, the drain Pd12 of the twelfth PMOS transistor, and the drain Nd12 of the twelfth NMOS transistor; the drain Pd13 of the thirteenth PMOS transistor is connected to the drain Nd13 of the thirteenth NMOS transistor, the gate Pg14 of the fourteenth PMOS transistor, and the gate Ng14 of the fourteenth NMOS transistor; the source Ps13 of the thirteenth PMOS transistor is connected to the power supply VDD; the gate Pg14 of the fourteenth PMOS transistor is connected to the gate Ng14 of the fourteenth NMOS transistor, the drain Pd13 of the thirteenth PMOS transistor, and the drain Nd12 of the thirteenth NMOS transistor. 13. The drain Pd13 of the fourteenth PMOS transistor is connected to the drain Nd14 of the fourteenth NMOS transistor, the gate Pg15 of the fifteenth PMOS transistor, and the gate Ng15 of the fifteenth NMOS transistor. The source Ps14 of the fourteenth PMOS transistor is connected to the power supply VDD. The gate Pg15 of the fifteenth PMOS transistor is connected to the gate Ng15 of the fifteenth NMOS transistor, the drain Pd14 of the fourteenth PMOS transistor, and the drain Nd14 of the fourteenth NMOS transistor. The drain Pd15 of the fifteenth PMOS transistor is connected to the drain Nd15 of the fifteenth NMOS transistor, the gate Pg16 of the sixteenth PMOS transistor, and the gate Ng16 of the sixteenth NMOS transistor. The source Ps15 of the fifteenth PMOS transistor is connected to the power supply VDD.The gate Pg16 of the sixteenth PMOS transistor is connected to the gate Ng16 of the sixteenth NMOS transistor, the drain Pd15 of the fifteenth PMOS transistor, and the drain Nd15 of the fifteenth NMOS transistor. The drain Pd16 of the sixteenth PMOS transistor is connected to the drain Nd16 of the sixteenth NMOS transistor, the gate Pg17 of the seventeenth PMOS transistor, and the gate Ng17 of the seventeenth NMOS transistor. The source Ps16 of the sixteenth PMOS transistor is connected to the power supply VDD. The gate Pg17 of the seventeenth PMOS transistor is connected to the gate Ng17 of the seventeenth NMOS transistor, the drain Pd16 of the sixteenth PMOS transistor, and the drain Nd16 of the sixteenth NMOS transistor. The drain Pd17 of the seventeenth PMOS transistor is connected to the drain of the seventeenth NMOS transistor. The output signal DS of Nd17 and the data input buffer circuit; the source Ps17 of the seventeenth PMOS transistor is connected to the power supply VDD; the gate Ng10 of the tenth NMOS transistor is connected to the gate Pg10 of the tenth PMOS transistor and the input signal D; the drain Nd10 of the tenth NMOS transistor is connected to the drain Pd10 of the tenth PMOS transistor; the source Ns10 of the tenth NMOS transistor is connected to ground VSS; the gate Ng11 of the eleventh NMOS transistor is connected to the gate Pg11 of the eleventh PMOS transistor, the drain Nd10 of the tenth NMOS transistor, and the drain Pd10 of the tenth PMOS transistor; the drain Nd11 of the eleventh NMOS transistor is connected to the drain Pd11 of the eleventh PMOS transistor, the gate Pg12 of the twelfth PMOS transistor, and the... The gate Ng12 of the 12th NMOS transistor and the source Ns11 of the 11th NMOS transistor are connected to ground VSS. The gate Ng12 of the 12th NMOS transistor is connected to the gate Pg12 of the 12th PMOS transistor, the drain Pd11 of the 11th PMOS transistor, and the drain Nd11 of the 11th NMOS transistor. The drain Nd12 of the 12th NMOS transistor is connected to the drain Pd12 of the 12th PMOS transistor, the gate Pg13 of the 13th PMOS transistor, and the gate Ng13 of the 13th NMOS transistor. The source Ns12 of the 12th NMOS transistor is connected to ground VSS. The gate Ng13 of the 13th NMOS transistor is connected to the gate Pg13 of the 13th PMOS transistor, the drain Pd12 of the 12th PMOS transistor, and the gate Ng13 of the 12th NMOS transistor. The drain of the thirteenth NMOS transistor is Nd12, and the drain of the thirteenth NMOS transistor is Nd13. The drain of the thirteenth NMOS transistor is Pd13, the gate of the fourteenth PMOS transistor is Pg14, and the gate of the fourteenth NMOS transistor is Ng14. The source of the thirteenth NMOS transistor is Ns13 connected to ground VSS. The gate of the fourteenth NMOS transistor is Ng14, and the drain of the fourteenth PMOS transistor is Pg14, the drain of the thirteenth PMOS transistor is Pd13, and the drain of the thirteenth NMOS transistor is Nd13. The drain of the fourteenth NMOS transistor is Nd13, and the drain of the fourteenth PMOS transistor is Pd14, the gate of the fifteenth PMOS transistor is Pg15, and the gate of the fifteenth NMOS transistor is Ng15. The source of the fourteenth NMOS transistor is Ns14 connected to ground VSS.The gate Ng15 of the fifteenth NMOS transistor is connected to the gate Pg15 of the fifteenth PMOS transistor, the drain Pd14 of the fourteenth PMOS transistor, and the drain Nd14 of the fourteenth NMOS transistor. The drain Nd15 of the fifteenth NMOS transistor is connected to the drain Pd15 of the fifteenth PMOS transistor, the gate Pg16 of the sixteenth PMOS transistor, and the gate Ng16 of the sixteenth NMOS transistor. The source Ns15 of the fifteenth NMOS transistor is connected to ground VSS. The gate Ng16 of the sixteenth NMOS transistor is connected to the gate Pg16 of the sixteenth PMOS transistor, the drain Pd15 of the fifteenth PMOS transistor, and the drain Nd15 of the fifteenth NMOS transistor. The drain Nd16 of the NMOS transistor is connected to the drain Pd16 of the sixteenth PMOS transistor, the gate Pg17 of the seventeenth PMOS transistor, and the gate Ng17 of the seventeenth NMOS transistor. The source Ns16 of the sixteenth NMOS transistor is connected to ground VSS. The gate Ng17 of the seventeenth NMOS transistor is connected to the gate Pg17 of the seventeenth PMOS transistor, the drain Pd16 of the sixteenth PMOS transistor, and the drain Nd16 of the sixteenth NMOS transistor. The drain Nd17 of the seventeenth NMOS transistor is connected to the drain Pd17 of the seventeenth PMOS transistor and the output signal DS of the data input buffer circuit. The source Ns17 of the seventeenth NMOS transistor is connected to ground VSS.

[0049] like Figure 4As shown, the scan control circuit has three input terminals and one output terminal. The three input terminals are respectively connected to the output terminal DS of the data input buffer circuit, the scan input selection terminal SE, and the scan input data terminal SI. The output terminal S is connected to the main latch. The scan control circuit includes six PMOS transistors and six NMOS transistors. The substrates of all PMOS transistors in the circuit are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg18 of the eighteenth PMOS transistor is connected to the gate Ng18 of the eighteenth NMOS transistor, the gate Ng22 of the twenty-second NMOS transistor, and the scan input selection terminal. The drain of the eighteenth PMOS transistor... Pd18 is connected to the drain Nd18 of the 18th NMOS transistor, the gate Pg22 of the 22nd PMOS transistor, and the gate Ng19 of the 19th NMOS transistor. The source Ps18 of the 18th PMOS transistor is connected to the power supply VDD. The gate Pg19 of the 19th PMOS transistor is connected to the scan input selection terminal, and the drain Pd19 of the 19th PMOS transistor is connected to the drain Pd20 of the 20th PMOS transistor. The source Ps19 of the 19th PMOS transistor is connected to the power supply VDD. The gate Pg20 of the 20th PMOS transistor is connected to the gate Ng20 of the 20th NMOS transistor and the output terminal DS of the data input buffer circuit. The drain Pd20 of the PMOS transistor is connected to the drain Nd20 of the twentieth NMOS transistor, the drain Pd22 of the twenty-second PMOS transistor, the drain Nd22 of the twenty-second NMOS transistor, the gate Pg23 of the twenty-third PMOS transistor, and the gate Ng23 of the twenty-third NMOS transistor. The source Ps20 of the twentieth PMOS transistor is connected to the drain Pd19 of the nineteenth PMOS transistor. The gate Pg21 of the twenty-first PMOS transistor is connected to the gate Pg21 of the twenty-first NMOS transistor and the scan input data terminal SI. The drain Pd21 of the twenty-first PMOS transistor is connected to the source Ps22 of the twenty-second PMOS transistor. The source Ps21 of the 21st PMOS transistor is connected to the power supply VDD; the gate Pg22 of the 22nd PMOS transistor is connected to the drain Nd18 of the 18th PMOS transistor and the drain Nd18 of the 18th NMOS transistor; the drain Pd22 of the 22nd PMOS transistor is connected to the drain Nd22 of the 22nd NMOS transistor, the gate Pg23 of the 23rd PMOS transistor, the gate Ng23 of the 23rd NMOS transistor, the drain Pd20 of the 20th PMOS transistor and the drain Nd20 of the 20th NMOS transistor; and the source Ps22 of the 22nd PMOS transistor is connected to the drain Pd21 of the 21st PMOS transistor.The gate Pg23 of the 23rd PMOS transistor is connected to the gate Pg23 of the 23rd NMOS transistor, the drain Pd22 of the 22nd PMOS transistor, the drain Nd22 of the 22nd NMOS transistor, the drain Pd20 of the 20th PMOS transistor, and the drain Nd20 of the 20th NMOS transistor. The drain Pd23 of the 23rd PMOS transistor is connected to the drain Nd23 of the 23rd NMOS transistor. The source Ps23 of the 23rd PMOS transistor is connected to the power supply VDD. The gate Ng18 of the 18th NMOS transistor is connected to the gate Pg18 of the 18th PMOS transistor, the gate Ng22 of the 22nd NMOS transistor, and the scan input selection terminal. The drain Nd18 of the eight NMOS transistor is connected to the drain Pd18 of the eighteenth PMOS transistor, the gate Pg22 of the twenty-second PMOS transistor, and the gate Ng19 of the nineteenth NMOS transistor. The source Ns18 of the eighteenth NMOS transistor is connected to ground VSS. The gate Ng19 of the nineteenth NMOS transistor is connected to the drain Pd18 of the eighteenth PMOS transistor and the drain Nd18 of the eighteenth NMOS transistor. The drain Nd19 of the nineteenth NMOS transistor is connected to the drain Nd20 of the twentieth NMOS transistor. The source Ns19 of the nineteenth NMOS transistor is connected to ground VSS. The gate Ng20 of the twentieth NMOS transistor is connected to the gate Pg22 of the twentieth PMOS transistor. The output terminal DS of the data input buffer circuit is connected to the drain Nd20 of the twentieth NMOS transistor, which is connected to the drain Pd20 of the twentieth PMOS transistor, the drain Pd22 of the twenty-second PMOS transistor, the drain Nd22 of the twenty-second NMOS transistor, the gate Pg23 of the twenty-third PMOS transistor, and the gate Ng23 of the twenty-third NMOS transistor. The source Ns20 of the twentieth NMOS transistor is connected to the drain Nd19 of the nineteenth NMOS transistor. The gate Ng21 of the twenty-first NMOS transistor is connected to the gate Pg21 of the twenty-first PMOS transistor and the scan input data terminal SI. The drain Nd21 of the twenty-first NMOS transistor is connected to the drain Nd19 of the twenty-second PMOS transistor. The source Ns22 of the MOSFET and the source Ns21 of the 21st NMOS transistor are connected to ground VSS; the gate Ng22 of the 22nd NMOS transistor is connected to the drain Nd18 of the 18th PMOS transistor and the drain Nd18 of the 18th NMOS transistor; the drain Nd22 of the 22nd NMOS transistor is connected to the drain Pd22 of the 22nd PMOS transistor, the gate Pg23 of the 23rd PMOS transistor, the gate Ng23 of the 23rd NMOS transistor, the drain Pd20 of the 20th PMOS transistor and the drain Nd20 of the 20th NMOS transistor; and the source Ns22 of the 22nd NMOS transistor is connected to the drain Nd21 of the 21st NMOS transistor.The gate Ng23 of the 23rd NMOS transistor is connected to the gate Pg23 of the 23rd PMOS transistor, the drain Pd22 of the 22nd PMOS transistor, the drain Nd22 of the 22nd NMOS transistor, the drain Pd20 of the 20th PMOS transistor, and the drain Nd20 of the 20th NMOS transistor. The drain Nd23 of the 23rd NMOS transistor is connected to the drain Pd23 of the 23rd PMOS transistor. The source Ns23 of the 23rd NMOS transistor is connected to ground VSS.

[0050] like Figure 5As shown, the reset buffer circuit includes one input terminal and one output terminal. The input terminal receives the reset signal, and the output terminal receives the inverted reset signal. The reset buffer circuit includes six PMOS transistors and six NMOS transistors. The substrates of all PMOS transistors are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg24 of the 24th PMOS transistor is connected to the gate Ng24 of the 24th NMOS transistor, the gate Pg28 of the 28th PMOS transistor, and the gate Ng28 of the 28th NMOS transistor. The drain Pd24 of the 24th PMOS transistor is connected to the drain Nd24 of the 24th NMOS transistor, the gate Pg25 of the 25th PMOS transistor, and the gate Ng25 of the 25th NMOS transistor. The source Ps25 of the 24-pMOS transistor is connected to the power supply VDD; the gate Pg25 of the 25th PMOS transistor is connected to the gate Ng25 of the 25th NMOS transistor, the drain Pd24 of the 24th PMOS transistor, and the drain Nd24 of the 24th NMOS transistor; the drain of the 25th PMOS transistor is connected to the drain Nd25 of the 25th NMOS transistor, the gate Pg26 of the 26th PMOS transistor, and the gate Ng26 of the 26th NMOS transistor; the source of the 25th PMOS transistor is connected to the power supply VDD; the gate Pg26 of the 26th PMOS transistor is connected to the gate Ng26 of the 26th NMOS transistor, the drain Pd25 of the 25th PMOS transistor, and the drain Nd25 of the 25th NMOS transistor. The drain Pd26 of the sixth PMOS transistor is connected to the drain Nd26 of the twenty-sixth NMOS transistor, the gate Pg27 of the twenty-seventh PMOS transistor, and the gate Ng27 of the twenty-seventh NMOS transistor. The source of the twenty-sixth PMOS transistor is connected to the power supply VDD. The gate Pg27 of the twenty-seventh PMOS transistor is connected to the gate Ng27 of the twenty-seventh NMOS transistor. The drain Pd26 of the twenty-sixth PMOS transistor is connected to the drain Nd27 of the twenty-seventh NMOS transistor, the gate Pg29 of the twenty-ninth PMOS transistor, and the gate Ng29 of the twenty-ninth NMOS transistor. The source of the twenty-seventh PMOS transistor is connected to the power supply VDD. The twenty-eighth PMOS transistor... The gate Pg28 of the OS transistor is connected to the gate Ng28 of the 28th NMOS transistor and the input signal RN of the reset buffer circuit. The drain Pd28 of the 28th PMOS transistor is connected to the source Ps29 of the 29th PMOS transistor. The source of the 28th PMOS transistor is connected to the power supply VDD. The gate Pg29 of the 29th PMOS transistor is connected to the gate Ng29 of the 29th NMOS transistor, the drain Pd27 of the 27th PMOS transistor, and the drain Nd27 of the 27th NMOS transistor. The drain Pd29 of the 29th PMOS transistor is connected to the drain Nd29 of the 29th NMOS transistor and the output terminal of the reset buffer circuit. The source Ps29 of the 29th PMOS transistor is connected to the drain Pd28 of the 28th PMOS transistor.The gate Ng24 of the 24th NMOS transistor is connected to the gate Pg24 of the 24th PMOS transistor, the gate Pg28 of the 28th PMOS transistor, and the gate Ng28 of the 28th NMOS transistor. The drain Nd24 of the 24th NMOS transistor is connected to the drain Pd24 of the 24th PMOS transistor, the gate Pg25 of the 25th PMOS transistor, and the gate Ng25 of the 25th NMOS transistor. The source Ns25 of the 24th NMOS transistor is connected to ground VSS. The gate Ng25 of the 25th NMOS transistor is connected to the gate Pg25 of the 25th PMOS transistor, the drain Pd24 of the 24th PMOS transistor, and the source Ns25 of the 24th NMOS transistor. The drain of the 25th NMOS transistor, Nd24, is connected to the drain of the 25th PMOS transistor, Pd25, the gate of the 26th PMOS transistor, and Ng26, respectively. The source of the 25th NMOS transistor, Ns25, is connected to ground, VSS. The gate of the 26th NMOS transistor, Ng26, is connected to the gate of the 26th PMOS transistor, Pg25, and Nd25, respectively. The drain of the 26th NMOS transistor, Nd26, is connected to the drain of the 26th PMOS transistor, Pd26, the gate of the 27th PMOS transistor, and Ng26, respectively. The gate Ng27 of the NMOS transistor is connected to ground VSS; the source of the 26th NMOS transistor is connected to ground VSS; the gate Ng27 of the 27th NMOS transistor is connected to the gate Pg27 of the 27th PMOS transistor, the drain Pd26 of the 26th PMOS transistor, and the drain Nd26 of the 26th NMOS transistor; the drain Nd27 of the 27th NMOS transistor is connected to the drain Pd27 of the 27th PMOS transistor, the gate Pg29 of the 29th PMOS transistor, and the gate Ng29 of the 29th NMOS transistor; the source of the 27th NMOS transistor is connected to ground VSS; the gate Ng28 of the 28th NMOS transistor is connected to the gate Pg28 of the 28th PMOS transistor. The input signal RN of the reset buffer circuit is connected to the source Ns29 of the 28th NMOS transistor, and the source Ns29 of the 28th NMOS transistor is connected to ground VSS; the gate Ng29 of the 29th NMOS transistor is connected to the gate Pg29 of the 29th PMOS transistor, the drain Pd27 of the 27th PMOS transistor, and the drain Nd27 of the 27th NMOS transistor; the drain Nd29 of the 29th NMOS transistor is connected to the drain Pd29 of the 29th PMOS transistor and the output terminal of the reset buffer circuit; the source Ns29 of the 29th NMOS transistor is connected to the drain Nd28 of the 28th NMOS transistor.

[0051] like Figure 6As shown, the main latch circuit has four input terminals and two output terminals. The four input terminals are respectively connected to the output signal S of the scan control circuit, the positive clock signal C, the negative clock signal CN, and the output terminal R1 of the reset buffer circuit. The two output terminals are connected to the main latch fault detection circuit and the main latch pulse filtering circuit. The main latch circuit includes six PMOS transistors and six NMOS transistors. The substrates of all PMOS transistors in the circuit are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg30 of the 30th PMOS transistor is connected to the gate Ng30 of the 30th NMOS transistor and the output terminal S of the scan control circuit. The drain Pd30 of the 30th PMOS transistor is connected to the source Pd31 of the 31st PMOS transistor. The source Ps30 of the 30th PMOS transistor is connected to the power supply VDD. The gate Pg31 of the 31st PMOS transistor is connected to the positive output terminal C of the clock circuit. The drain Pd31 of the 31st PMOS transistor is connected to the drain Nd31 of the 31st NMOS transistor and the 32nd PMOS transistor. The gate Pg32 of the S-MOSFET and the gate Ng32 of the 32nd NMOS transistor are connected. The drain Pd35 of the 35th PMOS transistor is connected to the drain Nd35 of the 35th NMOS transistor. The gate Pg32 of the 32nd PMOS transistor is connected to the gate Ng26 of the 32nd NMOS transistor, the drain Pd31 of the 31st PMOS transistor, and the drain Nd31 of the 31st NMOS transistor. The drain Pd32 of the 32nd PMOS transistor is connected to the source Ns33 of the 33rd PMOS transistor. The source of the PMOS transistor is connected to the power supply VDD; the gate of the thirty-third PMOS transistor Pg33 is connected to the output terminal R1 of the reset buffer circuit; the drain of the thirty-third PMOS transistor Pd33 is connected to the drain of the thirty-second NMOS transistor Nd32, the drain of the thirty-third NMOS transistor Nd33, the gate of the thirty-fourth PMOS transistor Pg33, and the gate of the thirty-fourth NMOS transistor Ng33; and the source of the thirty-third PMOS transistor Ps33 is connected to the drain of the thirty-second PMOS transistor Pd33. The gate Pg34 of the 34th PMOS transistor is connected to the gate Ng34 of the 34th NMOS transistor, the drain Pd33 of the 33rd PMOS transistor, the drain Nd32 of the 32nd NMOS transistor, and the drain Nd33 of the 33rd NMOS transistor. The drain Pd34 of the 34th PMOS transistor is connected to the source Ps35 of the 35th PMOS transistor. The source of the 34th PMOS transistor is connected to the power supply VDD. The gate Pg35 of the 35th PMOS transistor is connected to the output terminal CN of the clock circuit. The drain Pd35 of the 35th PMOS transistor is connected to the drain Nd35 of the 35th NMOS transistor, the drain Pd31 of the 31st PMOS transistor, the drain Nd31 of the 31st NMOS transistor, the gate Pg32 of the 32nd PMOS transistor, and the gate Ng32 of the 32nd NMOS transistor. The source Ps35 of the 35th PMOS transistor is connected to the drain Pd34 of the 34th PMOS transistor.The gate Ng30 of the 30th NMOS transistor is connected to the gate Pg30 of the 30th PMOS transistor and the output terminal S of the scan control circuit. The drain Pd30 of the 30th NMOS transistor is connected to the source Nd31 of the 31st NMOS transistor. The source Ns30 of the 30th NMOS transistor is connected to ground VSS. The gate Ng31 of the 31st NMOS transistor is connected to the inverting output terminal CN of the clock circuit. The drain Nd31 of the 31st NMOS transistor is connected to the drain Pd31 of the 31st PMOS transistor, the gate Pg32 of the 32nd PMOS transistor, and the gate Ng3 of the 32nd NMOS transistor. 2. The drain Pd35 of the 35th PMOS transistor is connected to the drain Nd35 of the 35th NMOS transistor; the gate Ng32 of the 32nd NMOS transistor is connected to the gate Pg32 of the 32nd PMOS transistor, the drain Pd31 of the 31st PMOS transistor, and the drain Nd31 of the 31st NMOS transistor; the drain Nd32 of the 32nd NMOS transistor is connected to the drain Nd33 of the 33rd NMOS transistor; the source of the 32nd NMOS transistor is connected to ground VSS; the gate of the 33rd NMOS transistor Ng33 is connected to the output terminal R1 of the reset buffer circuit. The drain Nd33 of the OS transistor is connected to the drain Nd32 of the thirty-second NMOS transistor, the drain Nd33 of the thirty-third NMOS transistor, the gate Pg33 of the thirty-fourth PMOS transistor, and the gate Ng33 of the thirty-fourth NMOS transistor. The source of the thirty-third NMOS transistor is connected to ground VSS. The gate Ng34 of the thirty-fourth NMOS transistor is connected to the gate Pg34 of the thirty-fourth PMOS transistor, the drain Pd33 of the thirty-third PMOS transistor, the drain Nd32 of the thirty-second NMOS transistor, and the drain Nd33 of the thirty-third NMOS transistor. The drain Nd34 of the thirty-fourth NMOS transistor is connected to the third... The source of the 15th NMOS transistor, Ns35, and the source of the 34th NMOS transistor are connected to ground VSS. The gate of the 35th NMOS transistor, Ng35, is connected to the output terminal C of the clock circuit. The drain of the 35th NMOS transistor, Nd35, is connected to the drain of the 35th PMOS transistor, Pd31 of the 31st PMOS transistor, Nd31 of the 31st NMOS transistor, Pg32 of the 32nd PMOS transistor, and Ng32 of the 32nd NMOS transistor. The source of the 35th NMOS transistor, Ns35, is connected to the drain of the 34th NMOS transistor, Nd34.

[0052] like Figure 7As shown, the master latch error repair circuit has two input terminals and one output terminal. The two input terminals are connected to internal nodes M1 and M2 of the master latch, respectively, and the output terminal is connected to the input terminal of the slave latch. The master latch error repair circuit includes eighteen PMOS transistors and eighteen NMOS transistors. The substrates of all PMOS transistors in the circuit are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg36 of the thirty-sixth PMOS transistor is connected to internal node M1 of the master latch, and the drain Pd36 of the thirty-sixth PMOS transistor is connected to the drain Nd36 of the thirty-sixth NMOS transistor and the gate Pg38 of the thirty-eighth PMOS transistor. The gate Ng38 of the 38th NMOS transistor, the source Pg40 of the 40th PMOS transistor, and the source Ns40 of the 40th NMOS transistor are connected to the power supply VDD. The gate Pg37 of the 37th PMOS transistor is connected to the internal node M2 ​​of the main latch, and the drain Pd37 of the 37th PMOS transistor is connected to the drain Nd37 of the 37th NMOS transistor, the gate Pg39 of the 39th PMOS transistor, and the gate Ng40 of the 40th NMOS transistor. The source Ps37 of the 37th PMOS transistor is connected to the power supply VDD. The gate Pg38 of the 38th PMOS transistor is connected to the 30th NMOS transistor. The gate of the 8th NMOS transistor (Ng38), the drain of the 26th PMOS transistor (Pd36), and the drain of the 36th NMOS transistor (Nd36) are connected. The drain of the 38th PMOS transistor (Pd38) is connected to the source of the 39th PMOS transistor (Ps39), and the source of the 38th PMOS transistor is connected to the power supply VDD. The gate of the 39th PMOS transistor (Pg39) is connected to the drain of the 37th PMOS transistor (Pd37), the drain of the 37th NMOS transistor (Nd37), and the gate of the 40th NMOS transistor (Ng40). The drain of the 39th PMOS transistor (Pd39) is connected to the drain of the 39th NMOS transistor (Nd39), and the gate of the 40th PMOS transistor (Ng40). The drain Pd40 of the 40th NMOS transistor is connected to the drain Nd40 of the 39th PMOS transistor, and the source of the 39th PMOS transistor is connected to the drain of the 38th PMOS transistor. The gate Pg40 of the 40th PMOS transistor is connected to the gate Ng39 of the 39th NMOS transistor, the drain Pg37 of the 37th PMOS transistor, and the drain Ng37 of the 37th NMOS transistor. The drain of the 40th PMOS transistor is connected to the drain Pd40 of the 40th PMOS transistor, the drain Nd39 of the 39th NMOS transistor, the drain Pd39 of the 39th PMOS transistor, the gate Pg41 of the 41st PMOS transistor, and the gate Ng41 of the 41st NMOS transistor.The source Ps40 of the 40th PMOS transistor is connected to the source Ns40 of the 40th NMOS transistor, the drain Pd36 of the 36th PMOS transistor, the drain Nd36 of the 36th NMOS transistor, the gate Pg38 of the 38th PMOS transistor, and the gate Ng38 of the 38th NMOS transistor; the gate Pg41 of the 41st PMOS transistor is connected to the gate Ng41 of the 41st NMOS transistor, the drain Pd40 of the 40th PMOS transistor, and the drain Nd40 of the 40th NMOS transistor; the drain Pd41 of the 41st PMOS transistor is connected to the drain Nd41 of the 41st NMOS transistor, the gate Pg42 of the 42nd PMOS transistor, and the gate Ng42 of the 50th PMOS transistor. The gate of the MOS transistor Pg50 and the gate of the 53rd NMOS transistor Ng53 are connected to the power supply VDD. The source of the 41st PMOS transistor is connected to the power supply VDD. The gate of the 42nd PMOS transistor Pg42 is connected to the gate of the 42nd NMOS transistor Ng42, the drain of the 41st PMOS transistor Pd41 and the drain of the 41st NMOS transistor Nd41. The drain of the 42nd PMOS transistor Pd42 is connected to the drain of the 42nd NMOS transistor Nd42, the gate of the 50th NMOS transistor Ng50, the gate of the 53rd NMOS transistor Ng53 and the gate of the 44th PMOS transistor Pg44. The source of the 42nd PMOS transistor is connected to the power supply VDD. The gate of the 43rd PMOS transistor Pg43 is connected to... The gate of the 43rd NMOS transistor (Ng43), the drain of the 50th PMOS transistor (Pd50), and the drain of the 50th NMOS transistor (Nd50) are connected. The drain of the 43rd PMOS transistor (Pd43) is connected to the source of the 44th PMOS transistor (Ps44). The source of the 43rd PMOS transistor is connected to the power supply VDD. The gate of the 44th PMOS transistor (Pg44) is connected to the drain of the 42nd PMOS transistor (Pd42) and the drain of the 42nd NMOS transistor (Nd42). The drain of the 44th PMOS transistor is connected to the drain of the 44th NMOS transistor (Nd44). The source of the 44th PMOS transistor (Ps44) is connected to the drain of the 43rd PMOS transistor (Pd43). The gate of the 45th PMOS transistor (Pg45) is connected to... The drain of the 45th PMOS transistor (Pd45), the drain of the 44th PMOS transistor (Pd44), and the drain of the 44th NMOS transistor (Nd44) are connected. The source of the 45th PMOS transistor is connected to the source of the 45th NMOS transistor (Ns45), the gate of the 47th PMOS transistor (Pg47), and the gate of the 47th NMOS transistor (Ng47). The gate of the 46th PMOS transistor (Pg46) is connected to the gate of the 45th PMOS transistor (Pg45). The drain of the 46th PMOS transistor is connected to the drain of the 47th PMOS transistor (Pd47). The source of the 46th PMOS transistor (Ps46) is connected to the power supply VDD. The gate of the 47th PMOS transistor (Pg47) is connected to the gate of the 47th NMOS transistor (Ng47).The drain of the 47th PMOS transistor, Pd47, is connected to the drain of the 47th NMOS transistor, Nd47. The source of the 47th PMOS transistor, Ps47, is connected to the drain of the 46th PMOS transistor, Pd46. The gate of the 48th PMOS transistor, Pg48, is connected to the gate of the 48th NMOS transistor, Ng48. The drain of the 48th PMOS transistor, Pd48, is connected to the drain of the 48th NMOS transistor, Nd48. The source of the 48th PMOS transistor, Ps48, is connected to the power supply VDD. The gate of the 49th PMOS transistor, Pg49, is connected to the gate of the 49th NMOS transistor, Ng49. The drain of the 49th PMOS transistor, Pd49, is connected to the drain of the 49th NMOS transistor, Nd49. The source of the 49th PMOS transistor is connected to the power supply VDD. The gate of the 50th PMOS transistor, Pg50, is connected to the gate of the 53rd NMOS transistor, Ng53. The drain of the 50th PMOS transistor is connected to the drain of the 50th NMOS transistor, Nd50. The source Ps50 of the 50th NMOS transistor is connected to the source Ns50 of the 51st NMOS transistor. The gate Pg51 of the 51st PMOS transistor is connected to the gate Ng51 of the 51st NMOS transistor. The drain Pd51 of the 51st PMOS transistor is connected to the source Ps52 of the 52nd PMOS transistor. The source Ps51 of the 51st PMOS transistor is connected to the power supply VDD. The gate Pg52 of the 52nd PMOS transistor is connected to the gate Ng52 of the 52nd NMOS transistor. The drain Pd52 of the 52nd PMOS transistor is connected to the source Ps53 of the 53rd PMOS transistor. The source Ps52 of the 52nd PMOS transistor is connected to the drain Pd51 of the 51st PMOS transistor. The gate Pg53 of the 53rd PMOS transistor is connected to the gate Pg50 of the 50th PMOS transistor. The drain of the 53rd PMOS transistor is connected to the drain Nd53 of the 53rd NMOS transistor. The source Ps53 of the 53rd PMOS transistor is connected to the drain Pd52 of the 52nd PMOS transistor. The gate Ng36 of the 36th NMOS transistor is connected to the internal node M1 of the main latch. The drain Nd36 of the 36th NMOS transistor is connected to the drain Pd36 of the 36th PMOS transistor, the gate Pg38 of the 38th PMOS transistor, the gate Ng38 of the 38th NMOS transistor, the source Pg40 of the 40th PMOS transistor, and the source Ns40 of the 40th NMOS transistor. The source Ns36 of the 36th NMOS transistor is connected to ground VSS. The gate Ng37 of the 37th NMOS transistor is connected to... In the main latch's internal node M2, the drain Nd37 of the 37th NMOS transistor is connected to the drain Pd37 of the 37th PMOS transistor, the gate Pg39 of the 39th PMOS transistor, and the gate Ng40 of the 40th NMOS transistor; the source Ns37 of the 37th NMOS transistor is connected to ground VSS; the gate Ng38 of the 38th NMOS transistor is connected to the gate Pg38 of the 38th PMOS transistor, the drain Pd36 of the 36th PMOS transistor, and the drain Nd36 of the 36th NMOS transistor.The drain Nd38 of the 38th NMOS transistor is connected to the source Ns39 of the 39th NMOS transistor, and the source of the 38th NMOS transistor is connected to the power supply VDD. The gate Ng39 of the 39th NMOS transistor is connected to the gates Pg37, Pg37, and Pg40 of the 37th PMOS transistor. The drain Nd39 of the 39th NMOS transistor is connected to the drains Pd39, Pd40, and Nd40 of the 39th PMOS transistor and the 40th NMOS transistor. The source Ns39 of the 39th NMOS transistor is connected to the drain Nd38 of the 38th NMOS transistor. The gate Ng40 of the 40th NMOS transistor is connected to the... The gate Pg39 of the 19th PMOS transistor, the drain Pg37 of the 37th PMOS transistor, the drain Ng37 of the 37th NMOS transistor, and the drain Nd40 of the 40th NMOS transistor are connected to the drain Pd40 of the 40th PMOS transistor, the drain Nd39 of the 39th PMOS transistor, the gate Pg41 of the 41st PMOS transistor, and the gate Ng41 of the 41st NMOS transistor. The source Ns40 of the 40th NMOS transistor is connected to the source Ps40 of the 40th PMOS transistor, the drain Pd36 of the 36th PMOS transistor, the drain Nd36 of the 36th NMOS transistor, the gate Pg38 of the 38th PMOS transistor, and the gate Ng40 of the 38th NMOS transistor. The gate of the 41st NMOS transistor, Ng41, is connected to the gate of the 41st PMOS transistor, Pg41, the drain of the 40th PMOS transistor, and the drain of the 40th NMOS transistor, Nd40. The drain of the 41st NMOS transistor, Nd41, is connected to the drain of the 41st PMOS transistor, Pd41, the gate of the 42nd PMOS transistor, Pg42, and the gate of the 42nd NMOS transistor, Ng42. The source of the 41st NMOS transistor is connected to ground, VSS. The gate of the 42nd NMOS transistor, Ng42, is connected to the gate of the 42nd PMOS transistor, Pg42, the drain of the 41st PMOS transistor, Pd41, and the drain of the 41st NMOS transistor, Nd40. The drain of the 42nd NMOS transistor, Nd40, is connected to the gate of the 41st PMOS transistor, Pg42, the drain of the 41st PMOS transistor, and Nd41. 2. Connect the drain Pd42 of the 42nd PMOS transistor. Connect the source of the 42nd NMOS transistor to ground VSS. Connect the gate Ng43 of the 43rd NMOS transistor to the gate Pg43 of the 43rd PMOS transistor, the drain Pd50 of the 50th PMOS transistor, and the drain Nd50 of the 50th NMOS transistor. Connect the drain Nd43 of the 43rd NMOS transistor to the source Ns44 of the 44th NMOS transistor. Connect the source of the 43rd NMOS transistor to ground VSS. Connect the gate Ng44 of the 44th NMOS transistor to the drain Pd42 of the 42nd PMOS transistor and the drain Nd42 of the 42nd NMOS transistor. Connect the drain of the 44th NMOS transistor to the drain Pd44 of the 44th PMOS transistor.The source Ns44 of the 44th NMOS transistor is connected to the drain Nd43 of the 43rd NMOS transistor. The gate Ng45 of the 45th NMOS transistor is connected to the drain Nd45 of the 45th NMOS transistor, the drain Pd44 of the 44th PMOS transistor, and the drain Nd44 of the 44th NMOS transistor. The source of the 45th NMOS transistor is connected to the source Ps45 of the 45th PMOS transistor, the gate Pg47 of the 47th PMOS transistor, and the gate Ng47 of the 47th NMOS transistor. The gate Ng46 of the 46th NMOS transistor is connected to the gate Ng45 of the 45th NMOS transistor. The drain of the 46th NMOS transistor is connected to the drain Nd47 of the 47th NMOS transistor. The source Ns46 of the 46th NMOS transistor is connected to ground VSS; the gate Ng47 of the 47th NMOS transistor is connected to the gate Pg47 of the 47th PMOS transistor; the drain Nd47 of the 47th NMOS transistor is connected to the drain Pd47 of the 47th PMOS transistor; the source Ns47 of the 47th NMOS transistor is connected to the drain Nd46 of the 46th NMOS transistor; the gate Ng48 of the 48th NMOS transistor is connected to the gate Pg48 of the 48th PMOS transistor; the drain Nd48 of the 48th NMOS transistor is connected to the drain Pd48 of the 48th PMOS transistor; the source Ns48 of the 48th NMOS transistor is connected to ground VSS; the gate N of the 49th NMOS transistor... g49 is connected to the gate Pg49 of the 49th PMOS transistor; Nd49 of the 49th NMOS transistor is connected to the drain Pd49 of the 49th PMOS transistor; the source of the 49th NMOS transistor is connected to ground VSS; the gate Ng50 of the 50th NMOS transistor is connected to the gate Pg53 of the 53rd PMOS transistor; the drain of the 50th NMOS transistor is connected to the drain Pd50 of the 50th PMOS transistor; the source Ns50 of the 50th NMOS transistor is connected to the source Ps50 of the 50th PMOS transistor; the gate Ng51 of the 51st NMOS transistor is connected to the gate Pg51 of the 51st PMOS transistor; and the drain Nd51 of the 51st NMOS transistor is connected to the gate Pg51 of the 52nd NMOS transistor. The source Ns52 of the 51st NMOS transistor is connected to ground VSS. The gate Ng52 of the 52nd NMOS transistor is connected to the gate Pg52 of the 52nd PMOS transistor. The drain Nd52 of the 52nd NMOS transistor is connected to the source Ns53 of the 53rd NMOS transistor. The source Ns52 of the 52nd NMOS transistor is connected to the drain Nd51 of the 51st NMOS transistor. The gate Ng53 of the 53rd NMOS transistor is connected to the gate Ng50 of the 50th NMOS transistor. The drain of the 53rd NMOS transistor is connected to the drain Pd53 of the 53rd PMOS transistor. The source Ns53 of the 53rd NMOS transistor is connected to the drain Nd52 of the 52nd NMOS transistor.

[0053] like Figure 8As shown, the slave latch circuit has one input and two outputs. The four inputs are connected to the output signal MC of the master latch error correction circuit, the positive clock signal C, the negative clock signal CN, and the output signal R1 of the reset buffer circuit, respectively. The two outputs are connected to the slave latch error correction circuit. The slave latch circuit includes six PMOS transistors and six NMOS transistors. The substrates of all PMOS transistors are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg54 of the fifty-fourth PMOS transistor is connected to the gate Ng54 of the fifty-fourth NMOS transistor and the output terminal MC of the master latch error correction circuit. The drain Pd54 of the fifty-fourth PMOS transistor is connected to the fifty-fifth PMOS transistor. The source of the 54th PMOS transistor, Pd55, is connected to the power supply VDD; the gate of the 55th PMOS transistor, Pg55, is connected to the positive output terminal C of the clock circuit; the drain of the 55th PMOS transistor, Pd55, is connected to the source of the 55th NMOS transistor, Nd55; the gate of the 56th PMOS transistor, Pg56; the gate of the 56th NMOS transistor, Ng56; the drain of the 59th PMOS transistor, Pd59; and the drain of the 59th NMOS transistor, Nd59. The source of the 55th PMOS transistor, Ps55, is connected to the drain of the 54th PMOS transistor, Pd54; the gate of the 56th PMOS transistor, Pg56, is connected to the gate of the 56th NMOS transistor, Ng56; and the gate of the 57th PMOS transistor, Pg56, is connected to the gate of the 58th NMOS transistor, Ng56; and the gate of the 59th PMOS transistor, Pd55, Ps54, Pd55. The drain of the 59th PMOS transistor (Pd59) and the drain of the 59th NMOS transistor (Nd59), and the drain of the 56th PMOS transistor (Pd56) are connected to the source of the 57th PMOS transistor (Ns57). The source of the 56th PMOS transistor is connected to the power supply VDD. The gate of the 57th PMOS transistor (Pg57) is connected to the output terminal R1 of the reset buffer circuit. The drain of the 57th PMOS transistor (Pd57) is connected to the drain of the 57th NMOS transistor (Nd57), the drain of the 56th NMOS transistor (Nd49), the gate of the 58th PMOS transistor (Pg58), and the gate of the 58th NMOS transistor (Ng58). The source of the 57th PMOS transistor (Ps57) is connected to the drain of the 56th PMOS transistor (Pd4). 8; The gate Pg58 of the 58th PMOS transistor is connected to the gate Ng58 of the 57th NMOS transistor, the drain Pd57 of the 57th PMOS transistor, the drain Nd57 of the 57th NMOS transistor, and the drain Nd56 of the 56th NMOS transistor. The drain Pd58 of the 58th PMOS transistor is connected to the source Ps59 of the 59th PMOS transistor. The source of the 58th PMOS transistor is connected to VDD. The gate Pg59 of the 59th PMOS transistor is connected to the inverted output terminal CN of the clock circuit. The drain Pd59 of the 59th PMOS transistor is connected to the drain Nd59 of the 59th NMOS transistor. The source of the 59th PMOS transistor is connected to the drain Pd58 of the 58th PMOS transistor.The gate Ng54 of the 54th NMOS transistor is connected to the gate Pg54 of the 54th PMOS transistor and the output MC of the main latch error repair circuit. The drain Nd54 of the 54th NMOS transistor is connected to the source Nd55 of the 55th NMOS transistor, and the source Ns54 of the 54th NMOS transistor is connected to ground VSS. The gate Ng55 of the 55th NMOS transistor is connected to the inverting output CN of the clock circuit. The drain Nd55 of the 55th NMOS transistor is connected to the drain Pd55 of the 55th PMOS transistor, the gate Pg56 of the 56th PMOS transistor, and the gate of the 56th NMOS transistor. The gate Ng56 of the 59th PMOS transistor, the drain Pd59 of the 59th PMOS transistor, and the drain Nd59 of the 59th NMOS transistor are connected. The source Ns55 of the 55th NMOS transistor is connected to the drain Nd54 of the 54th NMOS transistor. The gate Ng56 of the 56th NMOS transistor is connected to the gate Pg56 of the 56th PMOS transistor, the drain Pd55 of the 55th PMOS transistor, and the drain Nd55 of the 55th NMOS transistor. The drain Nd56 of the 56th NMOS transistor is connected to the drain Nd57 of the 57th NMOS transistor. The source Ns56 of the 56th NMOS transistor is connected to ground VSS. The gate Ng57 of the 57th NMOS transistor is connected to the output terminal R1 of the reset buffer circuit. The drain Nd57 of the 57th NMOS transistor is connected to the drain Nd56 of the 56th NMOS transistor, the drain Pd57 of the 57th PMOS transistor, the gate Pg58 of the 58th PMOS transistor, and the gate Ng58 of the 58th NMOS transistor. The source of the 57th NMOS transistor is connected to ground VSS. The gate Ng58 of the 58th NMOS transistor is connected to the gate Pg58 of the 58th PMOS transistor, the drain Pd57 of the 57th PMOS transistor, and the drain Nd56 of the 57th NMOS transistor. The drains of NMOS transistors 7 and 56 (Nd56) and 58 (Nd58) are connected to the source of NMOS transistor 59 (Ns59). The source of NMOS transistor 58 is connected to ground (VSS). The gate of NMOS transistor 59 (Ng59) is connected to the positive output terminal C of the clock circuit. The drain of NMOS transistor 59 (Nd59) is connected to the drains of PMOS transistor 59 (Pd59), PMOS transistor 55 (Pd55), and NMOS transistor 55 (Nd55). The source of NMOS transistor 59 is connected to the drain of NMOS transistor 58 (Nd58).

[0054] like Figure 9As shown, the latch error repair circuit has two input terminals and one output terminal. The two input terminals are connected to the outputs S1 and S2 of the latch, respectively, and the output terminal is connected to the output circuit. The latch error repair circuit includes eighteen PMOS transistors and eighteen NMOS transistors. The substrates of all PMOS transistors are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg60 of the sixtieth PMOS transistor is connected to the latch output terminal S1, and the drain Pd60 of the sixtieth PMOS transistor is connected to the drain Nd60 of the sixtieth NMOS transistor, the gate Pg62 of the sixty-second PMOS transistor, and the gate of the sixty-second NMOS transistor. The source terminals of PMOS transistors Ng62 and 64 (Pg64 and Ns64 respectively) and NMOS transistor 64, and the source terminal of PMOS transistor 60 (Ps60) are connected to the power supply VDD. The gate terminal of PMOS transistor 61 (Pg61) is connected to the latch output terminal S2. The drain terminal of PMOS transistor 61 (Pd61) is connected to the drain terminal of NMOS transistor 61 (Nd61), the gate terminal of PMOS transistor 63, and the gate terminal of NMOS transistor 64 (Ng64). The source terminal of PMOS transistor 61 (Ps61) is connected to the power supply VDD. The gate terminal of PMOS transistor 62 (Pg62) is connected to the gate terminal of NMOS transistor 62 (Ng62). The drain of the 60th PMOS transistor (Pd60) and the drain of the 60th NMOS transistor (Nd60) are connected. The drain of the 62nd PMOS transistor (Pd62) is connected to the source of the 63rd PMOS transistor (Ps63), and the source of the 62nd PMOS transistor (Ps62) is connected to the power supply VDD. The gate of the 63rd PMOS transistor (Pg63) is connected to the drain of the 61st PMOS transistor (Pd61), the drain of the 61st NMOS transistor (Nd61), and the gate of the 64th NMOS transistor (Ng64). The drain of the 63rd PMOS transistor (Pd63) is connected to the drain of the 63rd NMOS transistor (Nd63), the drain of the 64th PMOS transistor (Pd64), and the gate of the 64th NMOS transistor (Ng64). The drain of the OS transistor is Nd64, and the source of the sixty-third PMOS transistor, Ps63, is connected to the drain of the sixty-second PMOS transistor, Pd62. The gate of the sixty-fourth PMOS transistor, Pg64, is connected to the gate of the sixty-third NMOS transistor, Ng63, the drain of the sixty-first PMOS transistor, and the drain of the sixty-first NMOS transistor, Ng61. The drain of the sixty-fourth PMOS transistor, Pd64, is connected to the drain of the sixty-fourth PMOS transistor, Nd63, and the drain of the sixty-third NMOS transistor, Pg65, and the gate of the sixty-fifth PMOS transistor, Ng65.The source Ps64 of the 64th PMOS transistor is connected to the source Ns64 of the 64th NMOS transistor, the drain Pd60 of the 60th PMOS transistor, the drain Nd60 of the 60th NMOS transistor, the gate Pg62 of the 62nd PMOS transistor, and the gate Ng62 of the 62nd NMOS transistor; the gate Pg65 of the 65th PMOS transistor is connected to the gate Ng65 of the 65th NMOS transistor, the drain Pd64 of the 64th PMOS transistor, and the drain Nd64 of the 64th NMOS transistor; the drain Pd65 of the 65th PMOS transistor is connected to the drain Nd65 of the 65th NMOS transistor, the gate Pg66 of the 66th PMOS transistor, the gate Ng66 of the 66th NMOS transistor, and the 74th PMOS transistor. The gates of the 74th and 77th NMOS transistors, Pg74 and Ng77, and the source Ps65 of the 65th PMOS transistor are connected to the power supply VDD. The gate Pg66 of the 66th PMOS transistor is connected to the gate Ng66 of the 66th NMOS transistor, the drain Pd65 of the 65th NMOS transistor, and the drain Nd65 of the 65th NMOS transistor. The drain Pd66 of the 66th PMOS transistor is connected to the drain Nd66 of the 66th NMOS transistor, the gates Ng74 and Ng77 of the 74th NMOS transistor, and the gate Pg78 of the 78th PMOS transistor. The source Ps66 of the 66th PMOS transistor is connected to the power supply VDD. The gate Pg67 of the 67th PMOS transistor is connected to the gate Pg78 of the 78th PMOS transistor. The gate of the 17th NMOS transistor (Ng67), the drain of the 74th PMOS transistor (Pd74), and the drain of the 74th NMOS transistor (Nd74) are connected. The drain of the 77th PMOS transistor (Pd77) is connected to the source of the 78th PMOS transistor (Ps78), and the source of the 77th PMOS transistor (Ps77) is connected to the power supply VDD. The gate of the 68th PMOS transistor (Pg68) is connected to the drain of the 66th PMOS transistor (Pd66) and the drain of the 66th NMOS transistor (Nd66). The drain of the 68th PMOS transistor (Pd68) is connected to the drain of the 68th NMOS transistor (Nd68). The source of the 68th PMOS transistor (Ps68) is connected to the drain of the 67th PMOS transistor (Pd67). The gate of the 69th PMOS transistor (Pg69) is connected to the drain of the 69th PMOS transistor (Pg69). Connect the drain Pd69 of the 69th PMOS transistor, the drain Pd68 of the 68th PMOS transistor, and the drain Nd68 of the 68th NMOS transistor. Connect the source Ps69 of the 69th PMOS transistor to the source Ns69 of the 69th NMOS transistor, the gate Pg71 of the 71st PMOS transistor, and the gate Ng71 of the 71st NMOS transistor. Connect the gate Pg70 of the 70th PMOS transistor to the gate Pg69 of the 69th PMOS transistor. Connect the drain Pd70 of the 70th PMOS transistor to the drain Pd71 of the 71st PMOS transistor. Connect the source Ps70 of the 70th PMOS transistor to the power supply VDD. Connect the gate Pg71 of the 71st PMOS transistor to the gate Ng71 of the 71st NMOS transistor.The drain Pd71 of the 71st PMOS transistor is connected to the drain Nd71 of the 71st NMOS transistor; the source Ps47 of the 71st PMOS transistor is connected to the drain Pd70 of the 70th PMOS transistor; the gate Pg72 of the 72nd PMOS transistor is connected to the gate Ng72 of the 72nd NMOS transistor; the drain Pd72 of the 72nd PMOS transistor is connected to the drain Nd72 of the 72nd NMOS transistor; the source Ps72 of the 72nd PMOS transistor is connected to the power supply VDD; the gate Pg73 of the 73rd PMOS transistor is connected to the gate Ng73 of the 73rd NMOS transistor; the drain Pd73 of the 73rd PMOS transistor is connected to the drain Nd73 of the 73rd NMOS transistor; the source Ps73 of the 73rd PMOS transistor is connected to the power supply VDD; the gate Pg74 of the 74th PMOS transistor is connected to the gate Ng77 of the 77th NMOS transistor; the drain Pd74 of the 74th PMOS transistor is connected to the drain Nd74 of the 74th NMOS transistor; the 74th PMOS transistor... The source Ps74 of the OS transistor is connected to the source Ns74 of the 74th NMOS transistor. The gate Pg75 of the 75th PMOS transistor is connected to the gate Ng75 of the 75th NMOS transistor. The drain Pd75 of the 75th PMOS transistor is connected to the source Ps76 of the 76th PMOS transistor. The source Ps76 of the 76th PMOS transistor is connected to the power supply VDD. The gate Pg76 of the 76th PMOS transistor is connected to the gate Ng76 of the 76th NMOS transistor. The drain Pd76 of the 76th PMOS transistor is connected to the source Ps77 of the 77th PMOS transistor. The source Ps76 of the 76th PMOS transistor is connected to the drain Pd75 of the 75th PMOS transistor. The gate Pg77 of the 77th PMOS transistor is connected to the gate Pg74 of the 74th PMOS transistor. The drain Pd77 of the 77th PMOS transistor is connected to the drain Nd77 of the 77th NMOS transistor. The source Ps77 of the 77th PMOS transistor is connected to the drain Pd76 of the 76th PMOS transistor. The gate Ng60 of the 60th NMOS transistor is connected to the output terminal S1 of the main latch. The drain Nd60 of the 60th NMOS transistor is connected to the drain Pd60 of the 60th PMOS transistor, the gate Pg62 of the 62nd PMOS transistor, the gate Ng64 of the 64th NMOS transistor, the source Pg64 of the 64th PMOS transistor, and the source Ns64 of the 64th NMOS transistor. The source Ns60 of the 60th NMOS transistor is connected to ground VSS. The gate Ng61 of the 61st NMOS transistor is connected to the output terminal S2 of the main latch. The drain Nd61 of the 61st NMOS transistor is connected to the drain Pd61 of the 61st PMOS transistor, the gate Pg63 of the 63rd PMOS transistor, and the gate Ng64 of the 64th NMOS transistor.The source Ns63 of the 63rd NMOS transistor is connected to ground VSS; the gate Ng62 of the 62nd NMOS transistor is connected to the gate Pg62 of the 62nd PMOS transistor, the drain Pd60 of the 60th PMOS transistor, and the drain Nd60 of the 60th NMOS transistor; the drain Nd62 of the 62nd NMOS transistor is connected to the source Ns63 of the 63rd NMOS transistor; the source Ns62 of the 62nd NMOS transistor is connected to the power supply VDD; the gate Ng63 of the 63rd NMOS transistor is connected to the gate Pg63 of the 63rd PMOS transistor, the gate Ng63 of the 63rd NMOS transistor, and the gate Pg64 of the 64th PMOS transistor; the drain Nd63 of the 63rd NMOS transistor is connected to the drain of the 63rd PMOS transistor. The source of the 63rd NMOS transistor, Ns63, is connected to the drain of the 62nd NMOS transistor, Nd62. The gate of the 64th NMOS transistor, Ng64, is connected to the gate of the 63rd PMOS transistor, Pg61 of the 61st PMOS transistor, and Ng61 of the 61st NMOS transistor. The drain of the 64th NMOS transistor, Nd64, is connected to the drain of the 64th PMOS transistor, Nd63 of the 63rd NMOS transistor, Pd63 of the 63rd PMOS transistor, Pg65 of the 65th PMOS transistor, and Ng65 of the 65th NMOS transistor. The source Ns64 of the 64th NMOS transistor is connected to the source Ps64 of the 64th PMOS transistor, the drain Pd60 of the 60th PMOS transistor, the drain Nd60 of the 60th NMOS transistor, the gate Pg62 of the 62nd PMOS transistor, and the gate Ng62 of the 62nd NMOS transistor. The gate Ng65 of the 65th NMOS transistor is connected to the gate Pg65 of the 65th PMOS transistor, the drain Pd64 of the 64th PMOS transistor, and the drain Nd64 of the 64th NMOS transistor. The drain Nd65 of the 65th NMOS transistor is connected to the drain Pd65 of the 65th PMOS transistor, the gate Pg66 of the 66th PMOS transistor, and the gate Ng66 of the 66th NMOS transistor. The source Ns65 of the transistor is connected to ground VSS; the gate Ng66 of the sixty-sixth NMOS transistor is connected to the gate Pg66 of the sixty-sixth PMOS transistor, the drain Pd65 of the sixty-fifth PMOS transistor, and the drain Nd65 of the sixty-fifth NMOS transistor; the drain Nd66 of the sixty-sixth NMOS transistor is connected to the drain Pd66 of the sixty-sixth PMOS transistor; the source Ns66 of the sixty-sixth NMOS transistor is connected to ground VSS; the gate Ng67 of the sixty-seventh NMOS transistor is connected to the gate Pg67 of the sixty-seventh PMOS transistor, the drain Pd74 of the seventy-fourth PMOS transistor, and the drain Nd74 of the seventy-fourth NMOS transistor; the drain Nd67 of the sixty-seventh NMOS transistor is connected to the source Ns68 of the sixty-eighth NMOS transistor.The source Ns67 of the 67th NMOS transistor is connected to ground VSS. The gate Ng68 of the 68th NMOS transistor is connected to the drain Pd66 of the 66th PMOS transistor and the drain Nd66 of the 66th NMOS transistor. The drain Nd68 of the 68th NMOS transistor is connected to the drain Pd68 of the 68th PMOS transistor. The source Ns68 of the 68th NMOS transistor is connected to the drain Nd67 of the 67th NMOS transistor. The gate Ng69 of the 69th NMOS transistor is connected to the drain Nd69 of the 69th NMOS transistor, the drain Pd68 of the 68th PMOS transistor, and the drain Nd68 of the 68th NMOS transistor. The source Ns68 of the 68th NMOS transistor is connected to the drain Nd67 of the 69th PMOS transistor. The source Ps69 of the S-MOSFET, the gate Pg71 of the 71st PMOS transistor, and the gate Ng71 of the 71st NMOS transistor are connected. The gate Ng70 of the 70th NMOS transistor is connected to the gate Ng69 of the 69th NMOS transistor. The drain Nd70 of the 70th NMOS transistor is connected to the drain Nd71 of the 71st NMOS transistor. The source Ns70 of the 70th NMOS transistor is connected to ground VSS. The gate Ng71 of the 71st NMOS transistor is connected to the gate Pg71 of the 71st PMOS transistor. The drain Nd71 of the 71st NMOS transistor is connected to the drain Pd71 of the 71st PMOS transistor. The source Ns71 of the 71st NMOS transistor is connected to the drain Nd70 of the 70th NMOS transistor. The 72nd... The gate Ng72 of the NMOS transistor is connected to the gate Pg72 of the 72nd PMOS transistor; the drain Nd72 of the 72nd NMOS transistor is connected to the drain Pd72 of the 72nd PMOS transistor; the source Ns72 of the 72nd NMOS transistor is connected to ground VSS. The gate Ng73 of the 73rd NMOS transistor is connected to the gate Pg73 of the 73rd PMOS transistor; the drain Nd73 of the 73rd NMOS transistor is connected to the drain Pd73 of the 73rd PMOS transistor; the source Ns73 of the 73rd NMOS transistor is connected to ground VSS. The gate Ng74 of the 74th NMOS transistor is connected to the gate Pg77 of the 77th PMOS transistor; the drain Nd74 of the 74th NMOS transistor is connected to the 74th PMOS transistor. The drain of the 74th NMOS transistor is Pd74, the source of the 74th PMOS transistor is Ns74, the gate of the 75th NMOS transistor is Ng75, the gate of the 75th PMOS transistor is Pg75, the drain of the 75th NMOS transistor is Nd75, the source of the 76th NMOS transistor is Ns76, the source of the 75th NMOS transistor is Ns75, ground is VSS, the gate of the 76th NMOS transistor is Ng76, the gate of the 76th PMOS transistor is Pg76, the drain of the 76th NMOS transistor is Nd76, the source of the 77th NMOS transistor is Ns77, and the source of the 76th NMOS transistor is Ns76, the drain of the 75th NMOS transistor is Nd75.The gate Ng77 of the 77th NMOS transistor is connected to the gate Ng74 of the 74th NMOS transistor; the drain Nd77 of the 77th NMOS transistor is connected to the drain Pd77 of the 77th PMOS transistor; and the source Ns77 of the 77th NMOS transistor is connected to the drain Nd76 of the 76th NMOS transistor.

[0055] like Figure 10 As shown, the output circuit has one input and two outputs. The input is connected to the output SC of the latch error repair circuit, and the two outputs are Q and its inverted output signal QN. SC is output to QN through a three-stage inverter consisting of the 78th PMOS and 78th NMOS, the 79th PMOS and 79th NMOS, and the 80th PMOS and 80th NMOS. SC is also output to Q through a two-stage inverter consisting of the 81st PMOS and 81st NMOS, and the 82nd PMOS and 82nd NMOS.

[0056] like Figure 11 The figure shows the SEU fault injection simulation results for a general-purpose resettable D flip-flop with scan input function. Fault injection is performed at node M1 inside the main latch, using a double exponential current source. The pulse amplitude is set to 120.36 μA, the duration to 500 picoseconds, and both the rise and fall times to 50 picoseconds. As can be seen from the figure, under the influence of the fault pulse generated after simulated particle bombardment, the output Q of the general-purpose D flip-flop with scan input function exhibits an erroneous flip.

[0057] like Figure 12 As shown, the simulation results of SEU fault injection for a resettable radiation-hardened scanning structure D flip-flop of the present invention are presented. A radiation pulse with the same parameters as above is used to inject a fault into the internal node M1 of the main latch of the proposed D flip-flop. The simulation results show that the injected fault pulse does not affect the output terminal Q.

[0058] like Figure 13 As shown, the simulation results of fault injection at the data terminal SET of a general-purpose resettable D flip-flop with scan input function are presented. Fault injection is performed at the input data terminal D, and the transient pulse duration is set to 660 picoseconds. As can be seen from the figure, under the influence of the fault pulse generated by the simulated particle bombardment at the data terminal, the output Q of the general-purpose D flip-flop with scan input function exhibits an erroneous flip.

[0059] like Figure 14As shown, simulation results of SET fault injection at the data terminal of a resettable, radiation-hardened scanning structure D trigger according to the present invention are presented. Fault injection is performed at the input data terminal D, and the transient pulse duration is set to 660 picoseconds. As can be seen from the figure, due to the formation of an anti-SET structure composed of delay units and Miller C units in the data input circuit, the transient pulse generated by particle bombardment at the data terminal is guaranteed not to affect the output signal Q.

[0060] like Figure 15 As shown, the simulation results of fault injection at the clock input SET of a general-purpose resettable D flip-flop with scan input function are presented. Fault injection is performed at the clock input CK, and the transient pulse duration is set to 350 picoseconds. As can be seen from the figure, under the influence of the fault pulse generated by simulated particle bombardment of the clock input, the output Q of the general-purpose D flip-flop with scan input function exhibits an erroneous flip.

[0061] like Figure 16 As shown, simulation results of SET fault injection at the clock input of a resettable, radiation-hardened scanning structure D flip-flop according to the present invention are presented. Fault injection is performed at the clock input CK, and the transient pulse duration is set to 350 picoseconds. As can be seen from the figure, due to the formation of an anti-SET structure composed of delay units and Miller C units in the clock circuit, the transient pulse generated by particle bombardment at the data terminal is guaranteed not to affect the output signal Q.

[0062] like Figure 17 As shown, the simulation results of fault injection at the reset terminal SET of a general-purpose resettable D flip-flop with scan input function are presented. Fault injection is performed at the input terminal RN of the reset buffer circuit, and the transient pulse duration is set to 100 picoseconds. As can be seen from the figure, under the influence of the fault pulse generated at the simulated particle bombardment clock input, the output terminal Q of the general-purpose D flip-flop with scan input function exhibits an erroneous flip.

[0063] like Figure 18 As shown, simulation results of the reset-terminal SET fault injection for a resettable radiation-hardened scanning structure D flip-flop according to the present invention are presented. Fault injection is performed at the input terminal RN of the reset buffer circuit, and the transient pulse duration is set to 100 picoseconds. As can be seen from the figure, since an anti-SET structure composed of delay units and Miller C units is formed in the reset buffer circuit, the transient pulse generated by the particle bombardment data terminal is guaranteed not to affect the output signal Q.

Claims

1. A resettable, radiation-hardened scanning structure D trigger, characterized in that, include: It includes a data input buffer circuit, a scan control circuit, a master latch, a master latch error repair circuit, a slave latch, a slave latch error repair circuit, and an output circuit connected in sequence. It also includes a clock circuit and a reset buffer circuit connected to the master latch and the slave latch respectively. The master latch error repair circuit and the slave latch error repair circuit have the same structure. The master latch error repair circuit includes: the first and second input terminals of the error detection unit are respectively connected to the first and second output terminals of the master latch error repair circuit; the first output terminal of the error detection unit is connected to the third input terminal of the double-layer reverse MOS unit DM4 and the fourth input terminal of the triple-layer reverse MOS unit TM1; the second output terminal of the error detection unit is connected to the second input terminal of the double-layer reverse MOS unit DM4, the third input terminal of the triple-layer reverse MOS unit TM1, and the gate of the NMOS transistor N4; the first input terminal of the double-layer reverse MOS unit DM4 is connected to the second input terminal of the error detection unit, the first input terminal of the triple-layer reverse MOS unit TM1, the drain of the PMOS transistor P4, and the gate of the NMOS transistor N4. The drain of S-channel transistor N4 is connected. The output of the dual-layer reverse MOS unit DM4 is connected to the first input of the dual-layer reverse MOS unit DM5, the gate and drain of PMOS transistor P3, and the gate and drain of NMOS transistor N3. The second input of the dual-layer reverse MOS unit DM5 is connected to its third input, the source of PMOS transistor P3, and the source of NMOS transistor N3. The output of the dual-layer reverse MOS unit DM5 is connected to the input of the reverse MOS unit M5. The output of the reverse MOS unit M5 is connected to the input of the reverse MOS unit M6. The output of the reverse MOS unit M6 is connected to the second input of the triple-layer reverse MOS unit TM1. The output of the triple-layer reverse MOS unit TM1, the source of PMOS transistor P4, and the source of NMOS transistor N4 together serve as the output of the main latch error repair circuit.

2. The resettable radiation-hardened scanning structure D trigger according to claim 1, characterized in that, The reset buffer circuit consists of four sets of series-connected reverse MOS units M1 to M4 and one set of double-layer reverse MOS units DM1. The input terminal of the reverse MOS unit M1 is connected to the first input terminal of the double-layer reverse MOS unit DM1, and together they serve as the input terminal of the reset buffer circuit. The output terminal of the reverse MOS unit M4 is connected to the second and third input terminals of the double-layer reverse MOS unit DM1, and the output terminal of the double-layer reverse MOS unit DM1 serves as the output terminal of the reset buffer circuit.

3. A resettable, radiation-hardened scanning structure D trigger according to claim 1, characterized in that, The master latch and slave latch have the same structure. The master latch includes: the first input terminal of the double-layer inverted MOS unit DM2 serves as the scan control signal input terminal of the master latch and is connected to the output terminal of the scan control circuit; the second input terminal of the double-layer inverted MOS unit DM2 and the third input terminal of the double-layer inverted MOS unit DM3 together serve as the positive clock signal input terminal of the master latch and are connected to the positive clock output terminal of the clock circuit; the third input terminal of the double-layer inverted MOS unit DM2 and the second input terminal of the double-layer inverted MOS unit DM3 together serve as the negative clock signal input terminal of the master latch and are connected to the negative clock output terminal of the clock circuit; the double-layer inverted MOS unit DM2... The output terminal and the output terminal of the double-layer inverted MOS unit DM3 together serve as the first output terminal of the main latch, and are respectively connected to the gate of PMOS transistor P1 and the gate of NMOS transistor N1. The source of PMOS transistor P1 is connected to the power supply VDD, and the drain of PMOS transistor P1 is connected to the source of PMOS transistor P2. The gate of PMOS transistor P2 and the gate of NMOS transistor N2 together serve as the reset buffer signal input terminal of the main latch, and are connected to the output terminal of the reset buffer circuit. The drain of PMOS transistor P2 is connected to the source of NMOS transistor N1, the source of NMOS transistor N2 and the output terminal of the double-layer inverted MOS unit DM3, and together serve as the second output terminal of the main latch. The drains of NMOS transistor N1 and NMOS transistor N2 are both grounded.

4. A resettable, radiation-hardened scanning structure D trigger according to claim 1, characterized in that, The error detection unit includes: the input terminal of the reverse MOS unit M7 serves as the first input terminal of the error detection unit; the output terminal of the reverse MOS unit M7 is connected to the first input terminal of the double-layer reverse MOS unit DM6, the source of PMOS transistor P5, and the source of NMOS transistor N5, respectively; the input terminal of the reverse MOS unit M8 serves as the second input terminal of the main latch error detection circuit, and is connected to the third input terminal of the double-layer reverse MOS unit DM6 and the gate of PMOS transistor P5, respectively; the output terminal of the reverse MOS unit M8 is connected to the second input terminal of the double-layer reverse MOS unit DM6 and the gate of NMOS transistor N5, respectively; the output terminal of the double-layer reverse MOS unit DM6 is connected to the drain of PMOS transistor P5, the drain of NMOS transistor N5, and the input terminal of the reverse MOS unit M9, respectively; the output terminal of the reverse MOS unit M9 serves as the first output terminal of the error detection unit and is connected to the input terminal of the reverse MOS unit M10; and the output terminal of the reverse MOS unit M10 serves as the second output terminal of the error detection unit.

5. A resettable radiation-hardened scanning structure D trigger according to any one of claims 1, 2, and 4, characterized in that, The reverse MOS unit includes a PMOS transistor and an NMOS transistor. The gates of the PMOS transistor and the NMOS transistor are connected as the input terminal of the reverse MOS unit, and the drains of the PMOS transistor and the NMOS transistor are connected as the output terminal of the reverse MOS unit. The source of the PMOS transistor is connected to the power supply VDD, and the source of the NMOS transistor is grounded.

6. A resettable radiation-hardened scanning structure D trigger according to any one of claims 1, 2, 3, and 4, characterized in that, The dual-layer reverse MOS unit includes two PMOS transistors and two NMOS transistors. The source of the first PMOS transistor is connected to the power supply VDD, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, and the gate of the first PMOS transistor is connected to the gate of the first NMOS transistor, serving as the first input terminal of the dual-layer reverse MOS unit. The gate of the second PMOS transistor serves as the second input terminal of the dual-layer reverse MOS unit, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, serving as the output terminal of the dual-layer reverse MOS unit. The gate of the second NMOS transistor serves as the third input terminal of the dual-layer reverse MOS unit, and the source of the second NMOS transistor is connected to the drain of the first NMOS transistor. The source of the first NMOS transistor is grounded.

7. A resettable, radiation-hardened scanning structure D trigger according to claim 1, characterized in that, The three-layer reverse MOS unit includes three PMOS transistors and three NMOS transistors. The source of the third PMOS transistor is connected to the power supply VDD, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor, and the gate of the third PMOS transistor is connected to the gate of the third NMOS transistor, serving as the first input terminal of the three-layer reverse MOS unit. The gate of the fourth PMOS transistor is connected to the gate of the fourth NMOS transistor, serving as the second input terminal of the three-layer reverse MOS unit. The gate of the fourth PMOS transistor is connected to the gate of the fifth NMOS transistor, serving as the third input terminal of the three-layer reverse MOS unit. The drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor, serving as the output terminal of the three-layer reverse MOS unit. The gate of the fifth NMOS transistor serves as the fourth input terminal of the two-layer reverse MOS unit. The source of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor, and the source of the fourth NMOS transistor is connected to the drain of the third NMOS transistor. The source of the third NMOS transistor is grounded.

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