An apparatus and method for synchronizing output clock signals across multiple phase-locked loops

Abstract

The invention relates to a device (100) and a method for synchronizing output clock signals on a plurality of phase-locked loops. The device (100) coupled within each phase-locked loop comprises a local counter (2) for providing a count upon receiving a reference clock signal and a comparator (4) for comparing the count provided by the local counter (2) with a predetermined or preconfigured value, characterized in that it further comprises a multiplexer (6) connected to the local counter (2) and to the counter (2) of an adjacent phase-locked loop for selecting the count provided by the local counter (2) or the count provided by the counter (2) of the adjacent phase-locked loop; incrementing and directly passing the count selected by the multiplexer (6) to the local counter (2); upon the count provided by the local counter (2) reaching the predetermined or preconfigured value, an output clock divider enable is activated so that the plurality of phase-locked loops initiates an output clock divider to generate an output clock signal.

Description

Technical Field

[0001] This invention relates to electronic systems, and more particularly to an apparatus and method for synchronously outputting clock signals on multiple phase-locked loops (PLLs). Background Technology

[0002] Phase-locked loops (PLLs) are used in a variety of applications to generate an output clock signal with a controlled phase and frequency relationship to a reference clock signal. For example, PLLs can be used in telecommunications systems and chip-to-chip communications.

[0003] Many efforts have been made to improve phase synchronization of phase-locked loops, and some of these efforts will be discussed in the following references.

[0004] US9503109B2 discloses an apparatus and method for synchronizing a phase-locked loop (PLL). In some embodiments, a fractional-N divider synthesizer includes a PLL and control circuitry that controls the PLL's division value. The control circuitry includes an interpolator, a reset phase adjustment calculator, and synchronization circuitry. The interpolator can control the fractional portion of the PLL's division value. The reset phase adjustment calculator may include a counter for counting the number of cycles of a reference clock signal since the fractional-N divider synthesizer was initialized, and the reset phase adjustment calculator may generate a phase adjustment signal based on the count. The synchronization circuitry can synchronize the PLL in response to the synchronization signal and can correct for synchronization phase errors indicated by the phase adjustment signal.

[0005] US9979408B2 teaches apparatus and methods for phase synchronization of a phase-locked loop (PLL). In some configurations, a radio frequency communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit for synchronizing the phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on the timing of a reference clock signal. The phase synchronization circuit also includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit also includes a phase adjustment control circuit that provides phase adjustment to the PLL based on the phase difference signal to synchronize the PLL.

[0006] While the aforementioned references and other related solutions attempt to improve phase synchronization of phase-locked loops (PLLs), they still have many limitations and drawbacks. For example, they do not provide a solution for synchronizing and aligning the phases of all output clock signals across two or more PLLs.

[0007] Figure 1The internal structure of a phase-locked loop (PLL) in the prior art is shown. The reference clock (refclk) signal passes through a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). The output of the VCO loop loops back to the phase detector via a feedback divider. The division factor N of the feedback divider is the factor that determines the multiplication effect of the VCO. The VCO from the PLL is typically not used directly because it is configured to have a very high frequency with a high multiplication factor N. Therefore, an output clock divider is applied at the VCO to generate a lower functional frequency output clock signal.

[0008] In a multi-phase-locked loop (PLL) system, even if the output clock dividers of multiple PLLs are configured with the same division frequency, the output clock signals are usually not aligned. Figure 2 Example timing diagrams of output clock signals generated by four prior art phase-locked loops (PLLs) are shown. These four prior art PLLs share the same reference clock signal, feedback divider division number, and output clock divider division number. However, four possible phase relationships still exist between the output clock signal at PLL-0 and the output clock signals at PLL-1 / PLL-2 / PLL-3. The output clock signal of any PLL can be at 0 degrees, 90 degrees, 180 degrees, or 270 degrees relative to other output clock signals, which poses a problem for systems requiring output clock signal phase alignment.

[0009] Therefore, there is still a need for an apparatus and method for synchronously outputting clock signals on multiple phase-locked loops. Summary of the Invention

[0010] To provide a basic understanding of some aspects of the invention, a brief summary is provided below. This summary is not a complete description of the invention, but merely presents some concepts in a simplified form as a prelude to the more detailed description that follows.

[0011] One object of the present invention is to provide an apparatus for synchronously outputting clock signals on multiple phase-locked loops (PLLs).

[0012] Another object of the present invention is to provide a configurable device that enables the creation and rearrangement of one or more phase-locked loop synchronization groups.

[0013] Another object of the present invention is to provide a method for synchronously outputting clock signals on multiple phase-locked loops.

[0014] Therefore, these objectives can be achieved by following the teachings of this invention. The present invention relates to an apparatus for synchronously outputting clock signals on multiple phase-locked loops (PLLs), wherein the apparatus coupled within each PLL includes a local counter for providing a count upon receiving a reference clock signal, and a comparator for comparing the count provided by the local counter with a predetermined or pre-configured value. The apparatus is characterized in that a multiplexer connected to the local counter and counters of adjacent PLLs is configured to select either the count provided by the local counter or the count provided by the counter of the adjacent PLL; the selected count of the multiplexer is incremented and directed to the local counter; when the count from the local counter reaches the predetermined or pre-configured value, an output clock divider enable is activated to cause the multiple PLLs to initiate the output clock divider to generate the output clock signal.

[0015] The present invention also provides a method for synchronously outputting clock signals on multiple phase-locked loops (PLLs), characterized by comprising: providing a count by a local counter when receiving a reference clock signal for each PLL; selecting the count provided by the local counter or the count provided by the counter of the adjacent PLL by a multiplexer connected to the local counter and a counter of an adjacent PLL; incrementing the count selected by the multiplexer; directing the incremented count to the local counter; comparing the count provided by the local counter with a predetermined or pre-configured value by a comparator; and activating an output clock divider enable when the count provided by the local counter reaches the predetermined or pre-configured value, so that the multiple PLLs can start the output clock divider to generate the output clock signal.

[0016] The foregoing and other objects, features, and beneficial effects of the present invention will become better understood by carefully reading the following detailed description provided appropriately in conjunction with the accompanying drawings. Attached Figure Description

[0017] To clearly illustrate the above-described features of the present invention, a more detailed description of the invention, which has been briefly summarized above, has been provided in conjunction with embodiments. Some embodiments are shown in the accompanying drawings; however, it should be noted that the drawings only illustrate typical embodiments of the invention, and the invention allows for other equally effective embodiments. Therefore, the drawings should not be considered as limiting the scope of the invention.

[0018] These and other features, benefits, and advantages of the invention will become apparent from the following accompanying drawings, wherein the same reference numerals denote the same structures throughout the views, wherein:

[0019] Figure 1 This is a schematic diagram of the internal structure of a prior art phase-locked loop (PLL).

[0020] Figure 2 Here is an example timing diagram of the output clock signal generated by four existing phase-locked loops;

[0021] Figure 3 An apparatus for synchronously outputting clock signals on multiple phase-locked loops, connected within a phase-locked loop according to an embodiment of the present invention, is shown.

[0022] Figure 4 The connection of the device on four phase-locked loops is shown in an illustrative embodiment according to the invention;

[0023] Figure 5 It shows Figure 4 Timing diagrams of the four phase-locked loops;

[0024] Figure 6 Timing diagrams of two phase-locked loops with different output clock divider division numbers are shown according to an illustrative embodiment of the present invention;

[0025] Figure 7 The diagram illustrates a schematic embodiment of the invention, showing the connection of six phase-locked loops divided into two groups for individual synchronization; and

[0026] Figure 8 Another connection of six phase-locked loops, divided into two groups for individual synchronization, is shown in an illustrative embodiment according to the invention. Detailed Implementation

[0027] Detailed embodiments of the invention are disclosed herein as needed; however, it should be understood that the disclosed embodiments are merely examples of the invention, which may be embodied in various forms. Therefore, the specific structural and functional details disclosed herein should not be construed as limiting the invention but rather as the basis for the claims. It should be understood that the accompanying drawings and their detailed description are not intended to limit the invention to the specific forms disclosed; rather, the invention covers all modifications, equivalents, and substitutions falling within the scope of the invention as defined by the appended claims. The word “may” as used in this application means permitted (i.e., it is possible), not mandatory (i.e., it must). Similarly, the words “include,” “includes,” and “including” mean including but not limited to. Furthermore, unless otherwise stated, “a” or “an” means “at least one,” and “plurality” means one or more. Abbreviations or technical terms used herein have meanings generally accepted in the art.

[0028] The invention is described below with reference to the accompanying drawings and various embodiments, wherein reference numerals used in the drawings correspond to similar elements throughout the specification. The invention may be embodied in many different forms and should not be construed as limited to the described embodiments. Rather, embodiments are provided to make the disclosure of the invention thorough and complete, and to fully convey the scope of the invention to those skilled in the art. In the following detailed description, numerical values ​​and ranges are provided for various aspects of the described embodiments. These numerical values ​​and ranges are considered merely examples and are not intended to limit the scope of the claims. Furthermore, many materials are identified as applicable to various aspects of the embodiments. These materials are considered exemplary and are not intended to limit the scope of the invention.

[0029] The invention will be described in more detail with reference to the accompanying drawings.

[0030] Figure 3 A device (100) for synchronously outputting clock signals on multiple phase-locked loops is shown, connected within a phase-locked loop according to an embodiment of the present invention. The device (100) includes: a local counter (2) for providing a count upon receiving a reference clock signal; a comparator (4) for comparing the count provided by the local counter (2) with a predetermined or pre-configured value; characterized in that it further includes a multiplexer (6) connected to the local counter (2) and the counters (2) of adjacent phase-locked loops for selecting the count provided by the local counter (2) or the count provided by the counters (2) of adjacent phase-locked loops; wherein the count selected from the multiplexer (6) is incremented and passed to the local counter (2); when the count provided by the local counter (2) reaches the predetermined or pre-configured value, an output clock divider enable is activated to enable the multiple phase-locked loops to start the output clock divider to generate an output clock signal.

[0031] According to an embodiment of the present invention, multiple phase-locked loops (PLLs) are divided into multiple synchronization groups by configuring multiplexers (6) for individual synchronization of output clock signals. For example, if it is necessary to divide five PLLs into two synchronization groups, each multiplexer (6) of the five PLLs can be configured such that the output clock signal of the first PLL can be synchronized with the output clock signal of the second PLL, and the output clock signal of the third PLL can be synchronized with the output clock signals of the fourth and fifth PLLs. Each multiplexer (6) of the five PLLs can be further configured such that the output clock signal of the first PLL can be synchronized with the output clock signal of the fifth PLL, and the output clock signal of the third PLL can be synchronized with the output clock signals of the second and fourth PLLs. By configuring the multiplexers (6), synchronization groups can be created and rearranged as needed.

[0032] According to embodiments of the present invention, the predetermined or pre-configured values ​​of each phase-locked loop (PLL) in the same synchronization group are identical. For example, if there are two synchronization groups, the predetermined or pre-configured values ​​of the PLLs in the first synchronization group are identical, while the predetermined or pre-configured values ​​of the PLLs in the second synchronization group are identical. Furthermore, the predetermined or pre-configured value may be at least a value that counts the number of reference clock signal cycles required to propagate across all PLLs in a synchronization group.

[0033] According to an embodiment of the present invention, the local counter (2) is enabled by a synchronization enable (sync_en) signal. For example, when the synchronization process of the phase-locked loop output clock signal is initiated, the local counter (2) is initially disabled and then enabled by the synchronization enable signal.

[0034] According to an embodiment of the present invention, the reference clock signal of the local counter (2) is the same as the clock signal driving the phase-locked loop.

[0035] According to embodiments of the present invention, the output clock divider of each phase-locked loop includes the same or different division numbers when dividing the output clock signal. For example, if the output clock signals of two phase-locked loops are being synchronized, and the first phase-locked loop's output divider has a division number of 4, then the second phase-locked loop's output divider can have a division number of 2 or 4.

[0036] The present invention also relates to a method for synchronously outputting clock signals on multiple phase-locked loops, the method comprising the following steps: upon receiving a reference clock signal for each phase-locked loop, providing a count via a local counter (2); selecting either the count provided by the local counter (2) or the count provided by the counter (2) of an adjacent phase-locked loop via a multiplexer (6) connected to the local counter (2) and the counters (2) of adjacent phase-locked loops; incrementing the count selected by the multiplexer (6); directing the incremented count to the local counter (2); comparing the count provided by the local counter (2) with a predetermined or pre-configured value via a comparator (4); and when the count provided by the local counter (2) reaches the predetermined or pre-configured value, activating an output clock divider to enable the phase-locked loops to start the output clock divider to generate an output clock signal.

[0037] According to an embodiment of the present invention, the method further includes dividing multiple phase-locked loops into multiple synchronization groups by configuring a multiplexer (6) for individual synchronization of the output clock signal.

[0038] The present invention will now be described in more detail with reference to embodiments thereof. These embodiments will make it easier to understand the advantages of the invention and to put it into practice. However, it should be understood that the following embodiments are not intended to limit the scope of the invention in any way.

[0039] Example

[0040] Figure 4 The diagram illustrates the connection of an apparatus (100) according to an illustrative embodiment of the invention across four phase-locked loops (PLLs). Each PLL multiplexer (6) is connected to its respective local counter (2) and the counters (2) of the adjacent PLLs. For example, the multiplexer (6) of PLL-2 is connected to the local counter (2) of PLL-2 and the counters (2) of PLL-1 and PLL-3.

[0041] To synchronize the output clock signals of the four phase-locked loops, each multiplexer (6) is configured such that the multiplexer (6) of PLL-0 selects a count from the counter (2) of PLL-1, while the multiplexer (6) of PLL-1 selects a count from its own local counter (2). The multiplexer (6) of PLL-2 selects a count from the counter (2) of PLL-1, while the multiplexer (6) of PLL-3 selects a count from the counter (2) of PLL-2.

[0042] Figure 5 It shows Figure 4The timing diagram of the four phase-locked loops is shown. Initially, the synchronization enable signal is activated at PLL-1. Since the multiplexer (6) of PLL-1 is configured to select a count from its own local counter (2), the multiplexer (6) of PLL-1 will select count 0 and count 0 will be incremented by 1 and directed to the local counter (2) of PLL-1 as count 1. Since the multiplexer (6) of PLL-0 is configured to select a count from the counter (2) of PLL-1, the multiplexer (6) of PLL-0 will select count 1 from the local counter (2) of PLL-1 and count 1 will be incremented by 1 and directly passed to the local counter (2) of PLL-0 as count 2. Similarly, since the multiplexer (6) of PLL-2 is configured to select a count from the counter (2) of PLL-1, the multiplexer (6) of PLL-2 will select count 1 from the local counter (2) of PLL-1, and count 1 will be incremented by 1 and directly passed to the local counter (2) of PLL-2 as count 2. Since the multiplexer (6) of PLL-3 is configured to select a count from the counter (2) of PLL-2, the multiplexer (6) of PLL-3 will select count 2 from the local counter (2) of PLL-2, and count 2 will be incremented by 1 and directly passed to the local counter (2) of PLL-3 as count 3. All counts in each local counter (2) will continue to increment. Furthermore, all counts from each local counter (2) will be evaluated continuously by each comparator (4). Once the count in each local counter (2) reaches a predetermined or pre-configured value (8 in this example) simultaneously, the output clock divider enable will be activated, causing each phase-locked loop to simultaneously start the output clock divider to generate the output clock signal, so that the output clock signals of all phase-locked loops are aligned.

[0043] In this embodiment, the minimum number of reference clock signal cycles required for the count to propagate across all phase-locked loops is 3, so the predetermined or pre-configured value can be set to 3 or greater.

[0044] In the aforementioned exemplary embodiments, each phase-locked loop's output clock divider has the same division number when dividing the output clock signal, thus the output clock signal has the same frequency. However, each phase-locked loop's output clock divider may also have different division numbers when dividing the output clock signal. Figure 6 Timing diagrams of two phase-locked loops with different output clock divider division numbers are shown according to an illustrative embodiment of the invention. PLL-0 has a 4-division output clock signal, while PLL-1 has a 2-division output clock signal. Even though PLL-0 has a slower output clock signal frequency, PLL-0 and PLL-1 are still considered to be synchronous, and the rising edges of the output clocks will be aligned with each other for every two PLL-1 cycles.

[0045] Because the selection input of the multiplexer (6) of the present invention is configurable, it is possible to create separate synchronous phase-locked loop (PLL) groups and rearrange them at any time. In one embodiment, as... Figure 7 As shown, the application needs to synchronize the output clock signals of PLL-0 and PLL-1 as one group, and the output clock signals of PLL-2, PLL-3, PLL-4, and PLL-5 as another group to meet system requirements. Therefore, the multiplexer (6) of PLL-0 can be configured to select counts from its own local counter (2), while the multiplexer (6) of PLL-1 can be configured to select counts from the counter (2) of PLL-0. This will make the output clock signal of PLL-1 aligned with the output clock signal of PLL-0. Subsequently, the multiplexer (6) of PLL-2 can be configured to select counts from its own local counter (2), while the multiplexer (6) of PLL-3 can be configured to select counts from the counter (2) of PLL-2. The multiplexer (6) of PLL-4 can be configured to select counts from the counter (2) of PLL-3, while the multiplexer (6) of PLL-5 can be configured to select counts from the counter (2) of PLL-4. This will align the output clock signals of PLL-3, PLL-4, and PLL-5 with the output clock signal of PLL-2.

[0046] Then, unlike the previous arrangement, such as Figure 8The application requires that the output clock signals of PLL-1, PLL-2, and PLL-3 be synchronized as one group, and the output clock signals of PLL-0, PLL-4, and PLL-5 be synchronized as another group to meet another system requirement. Therefore, the multiplexer (6) of PLL-1 can be reconfigured to select counts from its own local counter (2), while the multiplexer (6) of PLL-2 can be reconfigured to select counts from the counter (2) of PLL-1. The multiplexer (6) of PLL-3 can maintain selection counts from the counter (2) of PLL-2. This will align the output clock signals of PLL-2 and PLL-3 with the output clock signal of PLL-1. Subsequently, the multiplexer (6) of PLL-0 can be reconfigured to select counts from the local counter (2) of PLL-0, while the multiplexer (6) of PLL-5 can be reconfigured to select counts from the counter (2) of PLL-0. The multiplexer (6) of PLL-4 can be reconfigured to select counts from the counter (2) of PLL-5. This will align the output clock signals of PLL-4 and PLL-5 with the output clock signal of PLL-0. Even if the above two arrangements are connected in a ring topology, any other suitable topology, such as a star topology, mesh topology, or daisy-chain topology, can be used in this invention to synchronize the output clock signals, provided that the multiplexer (6) is configured accordingly.

[0047] Therefore, the above-described apparatus (100) and method overcome the problems and disadvantages of existing technologies. For example, the apparatus (100) and method of the present invention are capable of synchronously outputting clock signals on multiple phase-locked loops. Furthermore, the apparatus (100) of the present invention is configurable, making it easy to create and rearrange one or more phase-locked loop synchronization groups.

[0048] Various modifications to these embodiments will be apparent to those skilled in the art from the description and accompanying drawings. The principles associated with the various embodiments in the specification can be applied to other embodiments. Therefore, this description is not intended to be limited to the accompanying drawings. Figure 1 The embodiments shown are provided to represent the broadest scope consistent with the principles, novelty, and inventiveness of the invention as disclosed or proposed. Therefore, alternatives, modifications, and variations based on the invention should fall within the scope of the invention and the appended claims.

[0049] In the following claims and the foregoing description, unless otherwise stated, the term "comprise" or its variations "comprises" or "comprising" are used in the sense of inclusion, that is, specifying the presence of the said feature but not excluding the presence or addition of further features in various embodiments of the invention.

Claims

1. An apparatus (100) for synchronously outputting clock signals on multiple phase-locked loops, wherein the apparatus (100) coupled within each phase-locked loop comprises: A local counter (2) used to provide counting when a reference clock signal is received; and A comparator (4) for comparing the count provided by the local counter (2) with a predetermined or pre-configured value; Its characteristic is that it further includes: A multiplexer (6) connected to the local counter (2) and the counter (2) of the adjacent phase-locked loop is used to select the count provided by the local counter (2) or the count provided by the counter (2) of the adjacent phase-locked loop; The selected count of the multiplexer (6) is incremented and directly passed to the local counter (2); When the count provided by the local counter (2) reaches the predetermined or pre-configured value, the output clock divider enable is activated, causing the plurality of phase-locked loops to start the output clock divider to generate the output clock signal.

2. The apparatus (100) according to claim 1, characterized in that The multiple phase-locked loops are divided into multiple synchronization groups by configuring the multiplexer (6) for individual synchronization of the output clock signal.

3. The apparatus (100) according to claim 2, characterized in that, The predetermined or pre-configured values ​​are the same for each phase-locked loop in the same synchronization group.

4. The apparatus (100) according to claim 1, characterized in that, The local counter (2) is enabled by a synchronization enable signal.

5. The apparatus (100) according to claim 1, characterized in that: The reference clock signal of the local counter (2) is the same as the clock signal that drives the phase-locked loop.

6. The apparatus (100) according to claim 1, characterized in that, The output clock divider of each phase-locked loop includes the same or different division numbers when dividing the output clock signal.

7. A method for synchronously outputting clock signals on multiple phase-locked loops, characterized in that, include: A local counter (2) provides a count when a reference clock signal for each phase-locked loop is received; The count provided by the local counter (2) or the count provided by the counter (2) of the adjacent phase-locked loop is selected by a multiplexer (6) connected to the local counter (2) and the counter (2) of the adjacent phase-locked loop; Increment the count selected by the multiplexer (6); The incrementing count is directly passed to the local counter (2); The count provided by the local counter (2) is compared with a predetermined or pre-configured value by the comparator (4); and When the count provided by the local counter (2) reaches the predetermined or pre-configured value, the output clock divider is activated, enabling the phase-locked loop to start the output clock divider to generate the output clock signal.

8. The method according to claim 7, characterized in that, The method further includes dividing the plurality of phase-locked loops into multiple synchronization groups by configuring the multiplexer (6) for individual synchronization of the output clock signal.

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