Semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device that can be manufactured well. The semiconductor storage device of the embodiments includes: a substrate including a first region and a second region; a plurality of first conductive layers arranged in a direction intersecting a surface of the substrate; a first semiconductor layer provided in the first region and facing the plurality of first conductive layers; a charge storage layer provided between the plurality of first conductive layers and the first semiconductor layer; a contact electrode provided in the second region and connected to one of the plurality of first conductive layers; and a plurality of first structures and a plurality of second structures provided in the second region and surrounded by the plurality of first conductive layers. The first structure includes: a second semiconductor layer facing the plurality of first conductive layers and containing a semiconductor material common to the first semiconductor layer; and a first insulating layer provided between the plurality of first conductive layers and the second semiconductor layer and containing an insulating material common to the charge storage layer. The second structure does not contain the semiconductor material and the insulating material.

Description

[0001] [Reference to relevant applications]

[0002] This application claims priority to Japanese Patent Application No. 2021-153406 (filed on September 21, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A known semiconductor memory device includes: a substrate; a plurality of conductive layers arranged in a direction intersecting the surface of the substrate; a semiconductor layer extending in the direction intersecting the surface of the substrate and facing the plurality of conductive layers; and a charge storage layer disposed between the conductive layers and the semiconductor layer. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor memory device that can be manufactured well.

[0006] A semiconductor memory device according to one embodiment includes a substrate, a plurality of first conductive layers, a first semiconductor layer, a charge storage layer, a contact electrode, a plurality of first structures, and a plurality of second structures. The substrate has a first region and a second region arranged in a first direction. The plurality of first conductive layers are arranged in a second direction intersecting the substrate surface and extend throughout the first and second regions along the first direction. The first semiconductor layer is disposed in the first region, extends in the second direction, and faces the plurality of first conductive layers. The charge storage layer is disposed between the plurality of first conductive layers and the first semiconductor layer. The contact electrode is disposed in the second region, extends in the second direction, and is connected to one of the plurality of first conductive layers. The plurality of first structures and the plurality of second structures are disposed in the second region, extend in the second direction, and their outer peripheral surfaces are surrounded by the plurality of first conductive layers. The first structure includes a second semiconductor layer and a first insulating layer. The second semiconductor layer extends in the second direction, faces the plurality of first conductive layers, and includes a semiconductor material common to the first semiconductor layers. The first insulating layer is disposed between the plurality of first conductive layers and the second semiconductor layer, and includes an insulating material common to the charge storage layer. The second configuration does not include the semiconductor material or the insulating material. Attached Figure Description

[0007] Figure 1 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 It is Figure 1 A schematic top view shown in enlarged form.

[0009] Figure 3 It is Figure 2 A schematic top view shown in enlarged form.

[0010] Figure 4 It is Figure 2 The schematic cross-sectional view shown is obtained by cutting along line A-A' and observing the direction of the arrow.

[0011] Figure 5 yes Figure 4 A schematic enlarged view of part B shown.

[0012] Figure 6 It is Figure 2 The structure shown is cut along line C-C' and viewed in the direction of the arrow, resulting in a schematic cross-sectional view.

[0013] Figure 7 It is Figure 2 The schematic cross-sectional view shown is obtained by cutting along line D-D' and observing the direction of the arrow.

[0014] Figure 8 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0015] Figure 9 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0016] Figure 10 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0017] Figure 11 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0018] Figure 12 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0019] Figure 13 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0020] Figure 14 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0021] Figure 15 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0022] Figure 16 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0023] Figure 17 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0024] Figure 18 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0025] Figure 19 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0026] Figure 20 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0027] Figure 21 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0028] Figure 22 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0029] Figure 23 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0030] Figure 24 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0031] Figure 25 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0032] Figure 26 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0033] Figure 27 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0034] Figure 28 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0035] Figure 29 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0036] Figure 30 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0037] Figure 31 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0038] Figure 32 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to the second embodiment.

[0039] Figure 33 It is Figure 32 The structure shown is cut along line C-C' and viewed in the direction of the arrow, resulting in a schematic cross-sectional view.

[0040] Figure 34 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0041] Figure 35 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0042] Figure 36 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0043] Figure 37 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0044] Figure 38 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0045] Figure 39 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0046] Figure 40 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to the third embodiment.

[0047] Figure 41 It is Figure 40 The structure shown is cut along line C-C' and viewed in the direction of the arrow, resulting in a schematic cross-sectional view.

[0048] Figure 42 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0049] Figure 43 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0050] Figure 44 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0051] Figure 45 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0052] Figure 46 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0053] Figure 47 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0054] Figure 48 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0055] Figure 49It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0056] Figure 50 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0057] Figure 51 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0058] Figure 52 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0059] Figure 53 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0060] Figure 54 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0061] Figure 55 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0062] Figure 56 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0063] Figure 57 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0064] Figure 58 This is a schematic cross-sectional view showing a portion of the configuration of the semiconductor memory device according to the fourth embodiment.

[0065] Figure 59 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the fourth embodiment.

[0066] Figure 60 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0067] Figure 61 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0068] Figure 62 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0069] Figure 63 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0070] Figure 64 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0071] Figure 65It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0072] Figure 66 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0073] Figure 67 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0074] Figure 68 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0075] Figure 69 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0076] Figure 70 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0077] Figure 71 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0078] Figure 72 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0079] Figure 73 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0080] Figure 74 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0081] Figure 75 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0082] Figure 76 This is a schematic top view illustrating a portion of the configuration of a semiconductor memory device according to other embodiments.

[0083] Figure 77 This is a schematic top view illustrating a portion of the configuration of a semiconductor memory device according to other embodiments.

[0084] Figure 78 This is a schematic top view illustrating a portion of the configuration of a semiconductor memory device according to other embodiments.

[0085] Figure 79 This is a schematic top view illustrating a portion of the configuration of a semiconductor memory device according to other embodiments.

[0086] Figure 80 This is a schematic top view illustrating a portion of the configuration of a semiconductor memory device according to other embodiments.

[0087] Figure 81 This is a schematic top view illustrating a portion of the configuration of a semiconductor memory device according to other embodiments. Detailed Implementation

[0088] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. Additionally, the following drawings are schematic diagrams, and for ease of explanation, some components may be omitted. Furthermore, common parts in multiple embodiments are sometimes labeled with the same symbols, and descriptions may be omitted in these cases.

[0089] Furthermore, in this specification, when referring to "semiconductor memory device," it sometimes refers to a memory die, and sometimes to a memory system that includes a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). Moreover, it sometimes refers to a device that includes a host computer, such as a smartphone, tablet, or personal computer.

[0090] In addition, when referring to "control circuit" in this specification, it sometimes refers to peripheral circuits such as sequencers installed on the memory die, sometimes to controller dies or controller chips connected to the memory die, and sometimes to a configuration that includes both of these.

[0091] Furthermore, in this specification, when it is mentioned that the first component is "electrically connected" to the second component, it can mean that the first component is directly connected to the second component, or that the first component is connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF (disconnected) state, the first transistor will still be "electrically connected" to the third transistor.

[0092] Additionally, in this specification, when referring to the first component as being "connected" "between" the second and third components, it sometimes means that the first, second, and third components are connected in series, and the second component is connected to the third component via the first component.

[0093] In addition, in this specification, a specific direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0094] In addition, in this specification, the direction along a specific surface is sometimes referred to as the first direction, the direction along the specific surface that intersects the first direction is referred to as the second direction, and the direction that intersects the specific surface is referred to as the third direction. The first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0095] Furthermore, in this specification, expressions such as "upper" or "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Additionally, when referring to a lower surface or lower end for a particular configuration, it refers to the surface or end of that configuration on the substrate side; when referring to an upper surface or upper end, it refers to the surface or end of that configuration on the opposite side from the substrate. Furthermore, surfaces intersecting the X or Y direction are called side surfaces, etc.

[0096] In addition, when referring to "width", "length" or "thickness" in a specific direction in this specification, it sometimes refers to the width, length or thickness of a cross section observed using SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy).

[0097] [First Implementation]

[0098] [structure]

[0099] Figure 1 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to the first embodiment. Figure 2 It is Figure 1 A schematic top view shown in enlarged form. Figure 3 It is Figure 2 A schematic top view shown in enlarged form. Figure 4 It is Figure 2 The schematic cross-sectional view shown is obtained by cutting along line A-A' and observing the direction of the arrow. Figure 5 yes Figure 4 A schematic enlarged view of part B shown. Furthermore, Figure 5 The YZ section is shown, but when observing sections other than the YZ section along the central axis of semiconductor layer 120 (e.g., the XZ section), a similar effect is also observed. Figure 5 Same construction. Figure 6 It is Figure 2 The structure shown is cut along line C-C' and viewed in the direction of the arrow, resulting in a schematic cross-sectional view. Figure 7 It is Figure 2 The schematic cross-sectional view shown is obtained by cutting along line D-D' and observing the direction of the arrow.

[0100] The semiconductor memory device of the first embodiment includes a memory die (MD). For example, such as Figure 1As shown, the memory die MD includes a semiconductor substrate 100. In the illustrated example, four memory cell array regions R arranged in the X and Y directions are disposed in the semiconductor substrate 100. MCA Additionally, each memory cell array region R MCA It contains multiple storage blocks (BLKs) arranged in the Y direction.

[0101] For example, such as Figure 2 As shown, the memory block BLK has five string components SU arranged in the Y direction. Between two adjacent memory blocks BLK in the Y direction, an inter-block structure ST extending along the X direction is provided. Between two adjacent string components SU in the Y direction, an inter-string component insulating layer SHE of silicon oxide (SiO2) or the like extending along the X direction is provided.

[0102] In addition, the memory block BLK has memory hole regions R arranged in the X direction. MH and wiring area R HU .

[0103] For example, such as Figure 4 As shown, memory hole region R MH It includes a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor layers 120 extending along the Z direction, and a plurality of gate insulating layers 130 respectively disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0104] The conductive layer 110 is a generally plate-shaped conductive layer extending along the X direction. For example, as... Figure 5 As shown, the conductive layer 110 may also comprise a laminated film containing a barrier conductive layer 111 such as titanium nitride (TiN) and a metal layer 112 such as tungsten (W). Alternatively, the conductive layer 110 may also comprise a metal layer 112 such as molybdenum (Mo) or ruthenium (Ru). Furthermore, for example, when the conductive layer 110 comprises a metal layer 112 such as molybdenum (Mo), the conductive layer 110 may or may not include a barrier conductive layer 111 such as titanium nitride (TiN). Additionally, the conductive layer 110 may, for example, comprise polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is disposed between the plurality of conductive layers 110 arranged in the Z direction.

[0105] For example, such as Figure 4 As shown, a conductive layer 113 is disposed below the conductive layer 110. The conductive layer 113 may, for example, contain polycrystalline silicon containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). Furthermore, a conductive layer of a metal such as tungsten (W), a tungsten silicide, or other conductive layers may be disposed on the lower surface of the conductive layer 113. Additionally, an insulating layer 101, such as silicon oxide (SiO2), is disposed between the conductive layer 113 and the conductive layer 110.

[0106] The conductive layer 113 functions, for example, as the source line of a NAND (Not And) flash memory. The source line is, for example, directed towards the memory cell array region R. MCA ( Figure 1 All storage blocks (BLKs) contained in the ) have common settings.

[0107] Additionally, one or more of the bottommost conductive layers 110 among the plurality of conductive layers 110 function, for example, as the select gate line on the source side of the NAND flash memory and the gate electrode of the select transistor on the source side. The one or more conductive layers 110 are electrically independent according to each memory block BLK.

[0108] In addition, a plurality of conductive layers 110 located above the conductive layer 110 function as word lines of the NAND flash memory and gate electrodes of a plurality of storage transistors (memory cells). The plurality of conductive layers 110 are electrically independent according to each memory block BLK.

[0109] Additionally, one or more conductive layers 110 located above the conductive layer 110 function as the select gate line on the drain side of the NAND flash memory and the gate electrode of the select transistor on the drain side. The width of the plurality of conductive layers 110 in the Y direction is smaller than that of the other conductive layers 110. Furthermore, an inter-string insulating layer (SHE) is disposed between two adjacent conductive layers 110 in the Y direction. The plurality of conductive layers 110 are electrically independent according to each string of components (SU).

[0110] For example, such as Figure 3 As shown, the semiconductor layer 120 is arranged in a specific pattern along the X and Y directions. The semiconductor layer 120 functions as a channel region for multiple series-connected storage transistors (storage cells) and selection transistors. The semiconductor layer 120 is, for example, a semiconductor layer of polycrystalline silicon (Si). For example, such as... Figure 4 As shown, the semiconductor layer 120 has a generally cylindrical shape, and an insulating layer 125 such as silicon oxide is disposed in the central portion. In addition, the outer peripheral surfaces of the semiconductor layer 120 are surrounded by conductive layers 110 and face each other.

[0111] At the upper end of the semiconductor layer 120, an impurity region 121 containing N-type impurities such as phosphorus (P) is provided. Figure 4 In the example, the boundary line between the upper end of the semiconductor layer 120 and the lower end of the impurity region 121 is represented by a dashed line. The impurity region 121 is connected via contact electrode Ch and contact electrode Vy. Figure 3 ) connected to bit line BL ( Figure 3 ).

[0112] At the lower end of the semiconductor layer 120, an impurity region 122 containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B) is provided. Figure 4 In the example, the boundary line between the lower end of the semiconductor layer 120 and the upper end of the impurity region 122 is represented by a dashed line. The impurity region 122 is connected to the conductive layer 113.

[0113] The gate insulating layer 130 has a generally cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. For example, as Figure 5 As shown, the gate insulating layer 130 includes a tunnel insulating layer 131, a charge storage layer 132, a barrier insulating layer 133, and a portion of a plurality of high-dielectric-constant insulating layers 134 deposited between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating layer 131 and the barrier insulating layer 133 are, for example, insulating films such as silicon oxide (SiO2). The charge storage layer 132 is, for example, a charge-storing film such as silicon nitride (Si3N4). The high-dielectric-constant insulating layers 134 are, for example, films of aluminum oxide (Al2O3) or other metal oxides. The tunnel insulating layer 131, the charge storage layer 132, and the barrier insulating layer 133 have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120. A plurality of high-dielectric-constant insulating layers 134 are provided corresponding to the plurality of conductive layers 110, and are disposed on the upper surface, lower surface, and surface facing the semiconductor layer 120 of the conductive layers 110. The portion of the high dielectric constant insulating layer 134 disposed on the side of the conductive layer 110 opposite to the semiconductor layer 120 functions as part of the gate insulating layer 130.

[0114] also, Figure 5 The diagram shows an example where the gate insulating layer 130 includes an insulating charge storage layer 132 such as silicon nitride. However, the gate insulating layer 130 may also include a floating gate such as polysilicon containing N-type or P-type impurities.

[0115] For example, such as Figure 2 As shown, wiring area R HU The X-direction end has multiple conductive layers 110. Additionally, the wiring area R... HU It has multiple contact electrodes CC arranged in the X and Y directions. Additionally, the wiring area R... HU It has multiple (10 in the example shown) support structures HRR arranged in the Y direction.

[0116] like Figure 6 As shown, the contact electrode CC extends in the Z direction and its lower end is connected to the conductive layer 110. The contact electrode CC may also be, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) or a metal film such as tungsten (W). Figure 2In this example, multiple contact electrodes CC are arranged in three columns along the X direction. One column of these three columns contains multiple contact electrodes CC connected, for example, to the (3n+1)th conductive layer 110 (n being an integer greater than or equal to 0) from the top. Additionally, one column of these three columns contains multiple contact electrodes CC connected, for example, to the (3n+2)th conductive layer 110 from the top. Furthermore, one column of these three columns contains multiple contact electrodes CC connected, for example, to the (3n+3)th conductive layer 110 from the top.

[0117] Each of the multiple support structure regions HRR has multiple support structures HR arranged in the X direction.

[0118] Figure 2 In the example, the 1st and 10th support structure regions HRR, counting from one side in the Y direction (e.g., the negative side of the Y direction), have multiple support structures HRS arranged at specific intervals in the X direction. For example, as Figure 7 As shown, the support structure HRS has a generally cylindrical shape extending in the Z direction. The upper end of the support structure HRS is positioned above the upper surface of the uppermost conductive layer 110. The lower end of the support structure HRS is positioned below the lower surface of the lowermost conductive layer 110. The support structure HRS may contain, for example, silicon oxide (SiO2).

[0119] also, Figure 2 In the diagram, dotted lines are used to represent the boundaries of ranges separated by a distance d1 from the ends of the conductive layer 110 on one side (e.g., the negative side of the Y direction) and the other side (e.g., the positive side of the Y direction). The first and tenth support structure regions HRR, counting from one side of the Y direction, are located in the regions outside these two dotted lines. The second to ninth support structure regions HRR, counting from one side of the Y direction, are located in the regions inside these two dotted lines.

[0120] in addition, Figure 2 In the example, the 4th and 7th support structure regions (HRRs) counting from one side in the Y direction have multiple support structures (HRMs) arranged at specific intervals in the X direction. For example, as... Figure 7 As shown, the support structure HRM has a generally cylindrical shape extending in the Z direction. The upper end of the support structure HRM is located above the upper surface of the uppermost conductive layer 110. The lower end of the support structure HRM is located below the lower surface of the lowermost conductive layer 110. The support structure HRM includes, for example, a semiconductor layer 220 extending in the Z direction and an insulating layer 230 disposed between the plurality of conductive layers 110 and the semiconductor layer 220.

[0121] Semiconductor layer 220 is constructed in essentially the same manner as semiconductor layer 120. However, semiconductor layer 220 does not function as a channel region for storage transistors (memory cells) or selection transistors. Furthermore, semiconductor layer 220 is not connected to bit line BL (…). Figure 3 In addition, an insulating layer 225 of silicon oxide or the like is disposed in the center portion of the semiconductor layer 220.

[0122] The insulating layer 230 is constructed in the same manner as the gate insulating layer 130.

[0123] in addition, Figure 2 In the example, the 2nd, 3rd, 5th, 6th, 8th, and 9th support structure regions HRR, counting from one side in the Y direction, have multiple support structures HRM arranged in the X direction. In these support structure regions HRR, the multiple support structures HRM are arranged around the contact electrode CC. That is, the multiple support structures HRM contained in the support structure region HRR are separate from the contact electrode CC. Furthermore, the multiple support structures HRM are respectively disposed between two adjacent contact electrodes CC in the X direction.

[0124] In addition, it is set in the wiring area R HU More than 30% of the support structure HR can be the support structure HRM. More preferably, it is located in the wiring area R. HU More than 50% of the supporting structure HR is the supporting structure HRM.

[0125] For example, such as Figure 4 As shown, the inter-block structure ST includes a conductive layer 140 extending in the Z and X directions, and an insulating layer 141, such as silicon oxide, disposed on the Y-direction side of the conductive layer 140. The conductive layer 140 is connected to the conductive layer 113. The conductive layer 140 may, for example, comprise a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0126] [Manufacturing Method]

[0127] Next, refer to Figures 8 to 31 The manufacturing method of the semiconductor memory device according to the first embodiment will be described. Figure 8 , Figure 12 , Figure 14 , Figure 18 , Figure 20 ,and Figures 22-29 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 4 The corresponding cross-section. Figures 9-11 , Figure 30 ,and Figure 31 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 6 The corresponding cross-section. Figure 13 , Figures 15-17 , Figure 19 ,and Figure 21 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 7 The corresponding cross-section.

[0128] In manufacturing the semiconductor memory device of this embodiment, firstly, on the semiconductor substrate 100 ( Figure 1 (Not shown) Wiring, transistors, etc., that constitute peripheral circuitry (not shown). Additionally, an insulating layer 101 is formed on the upper surface of the structure.

[0129] Next, for example, such as Figure 8 and Figure 9 As shown, a semiconductor layer 113A of silicon or the like, a sacrificial layer 113B of silicon oxide or the like, a sacrificial layer 113C of silicon or the like, a sacrificial layer 113D of silicon oxide or the like, and a semiconductor layer 113E of silicon or the like are formed on the insulating layer 101. In addition, multiple insulating layers 101 and multiple sacrificial layers 110A are alternately formed. The sacrificial layer 110A may contain, for example, silicon nitride (Si3N4). This step is performed, for example, by a method such as CVD (Chemical Vapor Deposition).

[0130] Next, for example, such as Figure 10 As shown, in the wiring area R HU This forms a roughly stepped structure. In this step, for example, in reference... Figure 8 and Figure 9 A photoresist is formed on the upper surface of the structure described above, and the photoresist is patterned using methods such as photolithography. In addition, the following steps are repeatedly performed: selectively removing the sacrificial layer 110A, selectively removing the insulating layer 101, and isotropically removing the photoresist.

[0131] Next, for example, such as Figure 11 As shown, in reference Figure 10 An insulating layer 101 is formed on the upper surface of the described structure. This step is performed, for example, by a method such as CVD.

[0132] Next, for example, such as Figure 12 and Figure 13As shown, multiple memory holes MH are formed at positions corresponding to multiple semiconductor layers 120. Additionally, multiple vias HRH are formed at positions corresponding to multiple support structures HR. The memory holes MH and vias HRH are through-holes extending in the Z direction, penetrating the insulating layer 101, sacrificial layer 110A, semiconductor layer 113E, sacrificial layer 113D, sacrificial layer 113C, and sacrificial layer 113B, and exposing the upper surface of semiconductor layer 113A. This step is performed, for example, by a method such as RIE (Reactive Ion Etching).

[0133] Next, for example, such as Figure 14 and Figure 15 As shown, in reference Figure 12 and Figure 13 The upper surface of the described structure is covered with a photoresist 151. The photoresist 151 covers a plurality of memory holes MH and vias HRH corresponding to the support structure HRM. However, the photoresist 151 does not cover the vias HRH corresponding to the support structure HRS.

[0134] Next, for example, such as Figure 16 As shown, an insulating layer 152, such as silicon oxide (SiO2), is formed inside the via HRH corresponding to the support structure HRS. This step is performed, for example, by a method such as CVD.

[0135] Next, for example, such as Figure 17 As shown, a portion of the insulating layer 152 is removed to form the support structure HRS. Additionally, the photoresist 151 is stripped.

[0136] Next, for example, such as Figure 18 and Figure 19 As shown, insulating layers 130A, semiconductor layers 120 and 220, and insulating layers 125 and 225 are formed on the upper surface of the top insulating layer 101, the inner peripheral surface of the memory hole MH, and the inner peripheral surface of the via HRH corresponding to the support structure HRM. Insulating layer 130A, for example, includes a portion of the tunnel insulating layer 131, charge storage layer 132, and barrier insulating layer 133. This step is performed, for example, by a method such as CVD.

[0137] Next, for example, such as Figure 20 and Figure 21 As shown, insulating layers 125 and 225, semiconductor layers 120 and 220, and a portion of insulating layer 130A are removed. Additionally, impurity regions 121 are formed on the upper portions of semiconductor layers 120 and 220. This step is performed, for example, by methods such as RIE and CVD.

[0138] Next, for example, such as Figure 22As shown, a trench STA is formed. The trench STA extends in the Z and X directions and, in the Y direction, separates the insulating layer 101, the sacrificial layer 110A, the semiconductor layer 113E, and the sacrificial layer 113D, exposing the upper surface of the sacrificial layer 113C. This step is performed, for example, by a method such as RIE.

[0139] Next, for example, such as Figure 23 As shown, a protective film STSW, such as silicon nitride, is formed on the side surface of the trench STA in the Y direction. In this step, for example, an insulating film such as silicon nitride is formed on the side surface and bottom surface of the trench STA in the Y direction using a method such as CVD. Furthermore, the portion of this insulating film covering the bottom surface of the trench STA is removed using a method such as RIE.

[0140] Next, for example, such as Figure 24 As shown, a portion of the sacrificial layers 113B, 113C, 113D and the insulating layer 130A is removed to expose a portion of the semiconductor layer 120. This step is performed, for example, by a method such as wet etching.

[0141] Next, for example, such as Figure 25 As shown, a conductive layer 113 is formed. This step is performed, for example, by methods such as epitaxial growth.

[0142] Next, for example, such as Figure 26 As shown, the protective film STSW is removed. This step is performed, for example, by methods such as wet etching.

[0143] Next, for example, such as Figure 27 As shown, the sacrificial layer 110A is removed via the trench STA. This forms a hollow structure comprising a plurality of insulating layers 101 arranged in the Z direction, a memory via MH supporting the insulating layers 101 (semiconductor layer 120, insulating layer 130A, and insulating layer 125), and a supporting structure HR. This step is performed, for example, by a wet etching method.

[0144] Next, for example, such as Figure 28 As shown, a conductive layer 110 is formed. This step is performed, for example, by a method such as CVD. Furthermore, in this step, a high-dielectric-constant insulating layer 134 is formed before the conductive layer 110 is formed. Figure 5 ).

[0145] Next, for example, such as Figure 29 As shown, interblock structures ST are formed within the trench STA. This step is performed, for example, by methods such as CVD and RIE.

[0146] Next, for example, such as Figure 30 and Figure 31As shown, multiple contact holes CCH are formed at positions corresponding to multiple contact electrodes CC. The contact holes CCH are through holes extending in the Z direction, penetrating the insulating layer 101, and exposing the upper surface of the conductive layer 110. This step is performed, for example, by a method such as RIE.

[0147] Next, for example, such as Figure 6 As shown, a contact electrode CC is formed inside the contact hole CCH. This step is performed, for example, by CVD.

[0148] Then, by forming wiring and the like, the semiconductor memory device of the first embodiment is formed.

[0149] [Effect]

[0150] As mentioned above, in reference Figure 27 The described steps involve forming a structure comprising a plurality of insulating layers 101 arranged in the Z direction, a memory hole MH supporting the insulating layers 101, and a hollow structure of a supporting structure HR. When using this method, sometimes issues arise due to wiring area R... HU The expansion stress of the insulating layer 101 covering the upper surface of the stepped structure causes strain in the stepped structure. To suppress this strain in the stepped structure, in the wiring area R... HU Set up a support structure HR to support this stepped structure.

[0151] Here, with the increasing integration of semiconductor memory devices, the width of the memory block BLK in the Y direction (refer to...) Figure 1 , Figure 2 It will also continue to decrease. Consequently, the reference... Figure 2 As described above, the distance between the support structure HR and the inter-block structure ST continuously approaches. Here, when all support structures HR are taken as support structures HRM, and the charge storage layer 132 in the support structure HRM is exposed in the trench STA, the following situation occurs: the charge storage layer 132, at the reference... Figure 27 The steps described have been removed, thus failing to properly support the hollow structure.

[0152] On the other hand, the memory hole MH and the support structure HRM share a common film structure and have approximately the same thermal shrinkage rate. In contrast, the support structure HRS has a different film structure and a different thermal shrinkage rate. Therefore, when all support structures HR are considered as support structures HRS, referring to... Figure 27 The hollow structure formed in the described steps is in the wiring area R HU Significant deformation could lead to a step difference on the upper surface of the hollow structure (the upper surface of the uppermost insulating layer 101).

[0153] Therefore, in the first embodiment, a support structure HRS is configured in the region near the inter-block structure ST, and a support structure HRM is configured in the region outside of it. With this configuration, the hollow structure can be properly supported, and the generation of the step difference can be suppressed.

[0154] [Second Implementation]

[0155] Next, refer to Figure 32 and Figure 33 The semiconductor memory device of the second embodiment will be described. Figure 32 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to the second embodiment. Figure 33 It is Figure 32 The structure shown is cut along line C-C' and viewed in the direction of the arrow, resulting in a schematic cross-sectional view.

[0156] The semiconductor memory device of the second embodiment is configured in the same way as the semiconductor memory device of the first embodiment.

[0157] However, the semiconductor memory device of the second embodiment includes support structures HRM' and HRS' instead of support structures HRM and HRS. The support structures HRM' and HRS' are essentially constructed the same as the support structures HRM and HRS. However, as shown in the reference... Figure 7 As explained, the upper part of the support structure HRM and HRS is positioned above the upper surface of the uppermost conductive layer 110. On the other hand, as... Figure 33 As shown, the upper ends of the support structures HRM' and HRS' are respectively set at the height position of the upper surface of the corresponding conductive layer 110.

[0158] in addition, Figure 32 In the example, counting from one side in the Y direction, the 2nd, 3rd, 5th, 6th, 8th, and 9th support structure regions HRR have multiple support structures HR arranged at specific intervals in the X direction. A portion of these multiple support structures HR are positioned to overlap with the contact electrode CC when viewed from the Z direction. Support structures HRS are positioned at such locations to serve as support structures HR. Figure 33 As shown, the upper ends of the plurality of support structures HRS are connected to the lower end of the contact electrode CC. Additionally, a portion of the plurality of support structures HR are positioned where they do not overlap with the contact electrode CC when viewed from the Z direction. Support structures HRM are positioned in such locations to serve as support structures HR.

[0159] [Manufacturing Method]

[0160] Next, refer to Figures 34-39 The manufacturing method of the semiconductor memory device according to the second embodiment will be described. Figures 34-39This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 33 The corresponding cross-section.

[0161] When manufacturing the semiconductor memory device of this embodiment, firstly, the manufacturing steps of the semiconductor memory device of the first embodiment are performed according to the reference... Figure 8 and Figure 9 That concludes the steps described.

[0162] Next, as Figure 34 As shown, multiple memory vias MH and multiple vias HRH are formed. This step is, for example, similar to the reference... Figure 12 and Figure 13 The steps described are performed in the same manner.

[0163] Next, as Figure 35 As shown, multiple support structures HRS are formed. This step, for example, is similar to the reference... Figures 14-17 The steps described are performed in the same manner.

[0164] Next, as Figure 36 As shown, this involves forming multiple memory holes MH and multiple support structures HRM. This step is, for example, similar to the reference... Figures 18-21 The steps described are performed in the same manner.

[0165] Next, for example, such as Figure 37 As shown, in the wiring area R HU This forms a roughly stepped structure. This step is essentially the same as the reference... Figure 10 The steps described are performed in the same manner. However, in conjunction with... Figure 37 In the corresponding steps, not only are the sacrificial layer 110A and the insulating layer 101 removed, but also a portion of the supporting structures HRS and HRM are removed.

[0166] Next, refer to Figure 11 The steps described and the references Figures 22-29 The steps described. Thus, as follows: Figure 38 The structure shown.

[0167] Next, for example, such as Figure 39 As shown, multiple contact holes CCH' are formed at positions corresponding to multiple contact electrodes CC. The contact holes CCH' are through holes extending in the Z direction, penetrating the insulating layer 101, and exposing the upper surface of the conductive layer 110 and the support structure HRS'. This step is performed, for example, by a method such as RIE.

[0168] Next, for example, such as Figure 33 As shown, a contact electrode CC is formed inside the contact hole CCH'. This step is performed, for example, by CVD.

[0169] Then, by forming wiring, etc., the semiconductor memory device of the second embodiment is formed.

[0170] [Effect]

[0171] The semiconductor memory device according to the second embodiment, like the semiconductor memory device according to the first embodiment, can properly support the hollow structure and suppress the generation of the step difference.

[0172] Furthermore, in the manufacturing steps of the semiconductor memory device in the first embodiment, when referring to Figure 12 and Figure 13 In the described steps, multiple memory vias MH and multiple vias HRH are formed. Here, the multiple memory vias MH each penetrate the same number of sacrificial layers 110A. On the other hand, the multiple vias HRH each penetrate different numbers of sacrificial layers 110A. For this reason, it is sometimes difficult to form multiple vias HRH uniformly.

[0173] Here, in the manufacturing steps of the semiconductor memory device according to the second embodiment, referring to Figure 34 In the described steps, all of the multiple memory vias MH and multiple vias HRH are permeated with the same number of sacrificial layers 110A. Therefore, compared to the semiconductor manufacturing apparatus of the first embodiment, it is easier to uniformly form multiple vias HRH.

[0174] [Third Implementation]

[0175] Next, refer to Figure 40 and Figure 41 The semiconductor memory device of the third embodiment will be described. Figure 40 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to the third embodiment. Figure 41 It is Figure 40 The structure shown is cut along line C-C' and viewed in the direction of the arrow, resulting in a schematic cross-sectional view.

[0176] The semiconductor memory device of the third embodiment is configured in the same way as the semiconductor memory device of the first embodiment.

[0177] However, in the third embodiment, an insulating layer SW such as silicon oxide (SiO2) is provided on the outer peripheral surface of the contact electrode CC.

[0178] Furthermore, the semiconductor memory device of the third embodiment includes a conductive layer 110' instead of the conductive layer 110. The conductive layer 110' is basically constructed in the same way as the conductive layer 110. However, the conductive layer 110' surrounds the outer peripheral surfaces of the plurality of contact electrodes CC with respect to the plurality of insulating layers SW.

[0179] in addition, Figure 40In the example, counting from one side in the Y direction, the 2nd, 3rd, 5th, 6th, 8th, and 9th support structure regions HRR have multiple support structures HR arranged at specific intervals in the X direction. A portion of these multiple support structures HR is positioned to overlap with the contact electrode CC when viewed from the Z direction. A support structure HRS” is provided at this position as the support structure HR. The multiple support structures HRS” are connected to the lower end of the contact electrode CC and the outer peripheral surface of the insulating layer SW. Additionally, a portion of these multiple support structures HR is positioned to not overlap with the contact electrode CC when viewed from the Z direction. A support structure HRM is provided at this position as the support structure HR.

[0180] [Manufacturing Method]

[0181] Next, refer to Figures 42-57 The manufacturing method of the semiconductor memory device according to the third embodiment will be described. Figures 42-57 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 41 The corresponding cross-section.

[0182] When manufacturing the semiconductor memory device of this embodiment, firstly, the manufacturing steps of the semiconductor memory device of the second embodiment are performed according to the reference... Figure 36 That concludes the steps described.

[0183] Next, as Figure 42 As shown, in Figure 36 The upper surface of the structure shown is formed with a photoresist R1. The photoresist R1 exposes the positions corresponding to the multiple contact electrodes CC and covers the areas outside of them.

[0184] Next, as Figure 43 As shown, a portion of the topmost insulating layer 101 is removed, exposing the upper surface of the first sacrificial layer 110A counting from the top. This step is performed, for example, by a re-insulating layer (RIE).

[0185] Next, as Figure 44 As shown, resist R1 is stripped to form resist R2. Resist R2 exposes the position corresponding to the even-numbered conductive layer 110' from the top among the plurality of contact electrodes CC, and covers the area outside thereon.

[0186] Next, as Figure 45 As shown, one layer each of the sacrificial layer 110A and the insulating layer 101 is removed, exposing the upper surface of the sacrificial layer 110A. This step is performed, for example, by means of a re-insulating layer (RIE).

[0187] Next, as Figure 46As shown, resist R2 is stripped to form resist R3. Resist R3 exposes the positions corresponding to the contact electrodes CC of the plurality of contact electrodes CC connected to the 4n+3rd and 4n+4th (n is an integer greater than or equal to 0) conductive layers 110' from the top, and covers the areas outside of them.

[0188] Next, as Figure 47 As shown, two layers of sacrificial layer 110A and insulating layer 101 are removed alternately to expose the upper surface of sacrificial layer 110A. This step is performed, for example, by a re-insulating layer (RIE).

[0189] Next, as Figure 48 As shown, resist R3 is stripped to form resist R4. Resist R4 exposes the positions corresponding to the contact electrodes CC connected to the 8n+5th to 8n+8th (n is an integer greater than or equal to 0) conductive layers 110' from the top among the plurality of contact electrodes CC, and covers the areas outside of them.

[0190] Next, as Figure 49 As shown, four layers of sacrificial layer 110A and insulating layer 101 are removed alternately to expose the upper surface of sacrificial layer 110A. This step is performed, for example, by a re-insulating layer (RIE).

[0191] Next, as Figure 50 As shown, resist R4 is stripped to form resist R5. Resist R5 exposes the positions corresponding to the contact electrodes CC connected to the 16n+9th to 16n+16th (n is an integer greater than or equal to 0) conductive layers 110' from the top among the plurality of contact electrodes CC, and covers the areas outside of them.

[0192] Next, as Figure 51 As shown, eight layers of sacrificial layer 110A and insulating layer 101 are removed alternately to expose the upper surface of sacrificial layer 110A. This step is performed, for example, by a re-insulating layer (RIE).

[0193] Next, as Figure 52 As shown, resist R5 is stripped to form resist R6. Resist R6 exposes the positions corresponding to the contact electrodes CC connected to the 32n+17th to 32n+32nd (n is an integer greater than or equal to 0) conductive layers 110' from the top among the plurality of contact electrodes CC, and covers the areas outside of them.

[0194] Next, as Figure 53 As shown, 16 layers of sacrificial layer 110A and insulating layer 101 are removed alternately each, exposing the upper surface of sacrificial layer 110A. This step is performed, for example, by a re-insulating layer (RIE).

[0195] Next, as Figure 54 As shown, in the reference Figures 42-53An insulating layer SW is formed on the inner peripheral surface and bottom surface of the contact hole CCH” formed by the steps described. Additionally, a sacrificial layer CCA is formed inside the contact hole CCH”. This step is performed, for example, by CVD.

[0196] Next, the manufacturing steps of the semiconductor memory device according to the first embodiment are carried out, referring to... Figures 22-29 The steps described. Thus, as follows: Figure 55 The structure shown.

[0197] Next, as Figure 56 As shown, the sacrificial layer CCA is removed. This step is performed, for example, by wet etching.

[0198] Next, as Figure 57 As shown, the portion of the insulating layer SW formed on the bottom surface of the contact hole CCH” is removed, exposing the upper surface of the conductive layer 110'. This step is performed, for example, by means of a RIE (Reinforcing Interchange).

[0199] Next, for example, such as Figure 41 As shown, a contact electrode CC is formed inside the contact hole CCH. This step is performed, for example, by CVD.

[0200] Then, by forming wiring and the like, the semiconductor memory device of the third embodiment is formed.

[0201] [Effect]

[0202] The semiconductor memory device according to the third embodiment, like the semiconductor memory device according to the first embodiment, can properly support the hollow structure and suppress the generation of the step difference.

[0203] Furthermore, similarly to the semiconductor memory device of the second embodiment, the semiconductor memory device of the third embodiment can more easily and uniformly form multiple vias HRH compared to the semiconductor manufacturing apparatus of the first embodiment.

[0204] Furthermore, in the manufacturing steps of the semiconductor memory device in the second embodiment, when referring to Figure 37 In the steps described, in the wiring area R HU A roughly stepped structure is formed. In this step, in addition to removing multiple sacrificial layers 110A and insulating layer 101, a portion of the support structures HRS and HRM is also removed. However, the multiple sacrificial layers 110A, insulating layer 101, and support structures HRS and HRM contain different materials, which are sometimes difficult to process simultaneously.

[0205] Here, in the manufacturing steps of the semiconductor memory device according to the third embodiment, the reference is not performed. Figure 37 The steps described herein. Therefore, compared to the semiconductor manufacturing apparatus of the second embodiment, it can sometimes be manufactured more easily.

[0206] [Fourth Implementation]

[0207] Next, refer to Figure 58 The semiconductor memory device of the fourth embodiment will be described. Figure 58 This is a schematic cross-sectional view showing a portion of the configuration of the semiconductor memory device according to the fourth embodiment.

[0208] The semiconductor memory device of the fourth embodiment is configured in the same way as the semiconductor memory device of the third embodiment.

[0209] However, in the fourth embodiment, an insulating layer 105 is provided above the uppermost conductive layer 110', separated by an insulating layer 101. The insulating layer 105 may be, for example, an insulating metal oxide film comprising at least one of aluminum (Al), titanium (Ti), hafnium (Hf), or zirconium (Zr). Alternatively, the insulating layer 105 may be other insulating layers. The insulating layer 105 may also be, for example, a material with higher resistance to phosphoric acid than the sacrificial layer 110A. Furthermore, the insulating layer 105 may be, for example, a material that allows for a sufficiently high selectivity ratio with the insulating layer 101 when performing RIE (Residual Energy Equivalent).

[0210] Furthermore, in the fourth embodiment, the lower end of the insulating layer SW is disposed above the lower end of the contact electrode CC. Specifically, the lower end of the insulating layer SW is disposed on the upper surface of the insulating layer 101 disposed on the upper surface of the conductive layer 110' connected to the corresponding contact electrode CC.

[0211] [Manufacturing Method]

[0212] Next, refer to Figures 59-75 The manufacturing method of the semiconductor memory device according to the fourth embodiment will be described. Figures 59-75 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 58 The corresponding cross-section.

[0213] When manufacturing the semiconductor memory device of this embodiment, firstly, the manufacturing steps of the semiconductor memory device of the first embodiment are performed according to the reference... Figure 8 and Figure 9 That concludes the steps described.

[0214] Next, as Figure 59 As shown, in Figure 8 and Figure 9 The upper surface of the structure shown is formed with insulating layers 101, 105, and 101. This step is performed, for example, by CVD.

[0215] Next, the manufacturing steps of the semiconductor memory device according to the second embodiment are performed, referring to... Figure 36That concludes the steps described.

[0216] Next, as Figure 60 As shown, in Figure 36 The upper surface of the structure shown is covered with a resist R1.

[0217] Next, as Figure 61 As shown, a portion of the topmost insulating layer 101 is removed, exposing the upper surface of the insulating layer 105. Additionally, a portion of the insulating layer 105 is removed, exposing the upper surface of the insulating layer 101 directly beneath it.

[0218] Next, as Figure 62 As shown, resist R1 is peeled off to form resist R2.

[0219] Next, as Figure 63 As shown, one layer each of the insulating layer 101 and the sacrificial layer 110A is removed to expose the upper surface of the insulating layer 101. This step is performed, for example, by means of a re-insulating layer (RIE).

[0220] Next, as Figure 64 As shown, resist R2 is peeled off to form resist R3.

[0221] Next, as Figure 65 As shown, two layers of insulating layer 101 and sacrificial layer 110A are removed alternately each, exposing the upper surface of insulating layer 101. This step is performed, for example, by means of a re-insulating layer (RIE).

[0222] Next, as Figure 66 As shown, resist R3 is peeled off to form resist R4.

[0223] Next, as Figure 67 As shown, four layers of insulating layer 101 and sacrificial layer 110A are removed alternately each, exposing the upper surface of insulating layer 101. This step is performed, for example, by means of a re-insulating layer (RIE).

[0224] Next, as Figure 68 As shown, resist R4 is peeled off to form resist R5.

[0225] Next, as Figure 69 As shown, eight layers of insulating layer 101 and sacrificial layer 110A are removed alternately each, exposing the upper surface of insulating layer 101. This step is performed, for example, by means of a re-insulating layer (RIE).

[0226] Next, as Figure 70 As shown, resist R5 is peeled off to form resist R6.

[0227] Next, as Figure 71As shown, 16 layers of insulating layer 101 and sacrificial layer 110A are removed alternately each, exposing the upper surface of insulating layer 101. This step is performed, for example, by a re-insulating layer (RIE).

[0228] Next, as Figure 72 As shown, in the reference Figures 60-71 An insulating layer SW is formed on the inner peripheral surface and bottom surface of the contact hole CCH” formed by the steps described. Additionally, a sacrificial layer CCA is formed inside the contact hole CCH”. This step is performed, for example, by CVD.

[0229] Next, the manufacturing steps of the semiconductor memory device according to the first embodiment are carried out, referring to... Figures 22-29 The steps described. Thus, as follows: Figure 73 The structure shown.

[0230] Next, as Figure 74 As shown, the sacrificial layer CCA is removed. This step is performed, for example, by wet etching.

[0231] Next, as Figure 75 As shown, the portion of the insulating layer SW formed on the bottom surface of the contact hole CCH” is removed. Additionally, one insulating layer 101 is removed, exposing the upper surface of the conductive layer 110'. This step is performed, for example, by a resonant electrical interface (RIE).

[0232] Next, for example, such as Figure 58 As shown, a contact electrode CC is formed inside the contact hole CCH. This step is performed, for example, by CVD.

[0233] Then, by forming wiring, etc., the semiconductor memory device of the fourth embodiment is formed.

[0234] [Effect]

[0235] The semiconductor memory device according to the fourth embodiment, like the semiconductor memory device of the first embodiment, can properly support the hollow structure and suppress the generation of the step difference.

[0236] Furthermore, similarly to the semiconductor memory device of the second embodiment, the semiconductor memory device of the fourth embodiment can more easily and uniformly form multiple vias HRH compared to the semiconductor manufacturing apparatus of the first embodiment.

[0237] Furthermore, the semiconductor memory device of the fourth embodiment, like the semiconductor memory device of the third embodiment, can sometimes be manufactured more easily than the semiconductor manufacturing apparatus of the second embodiment.

[0238] Furthermore, in the manufacturing steps of the semiconductor memory device in the third embodiment, when referring to Figure 43 , Figure 45 , Figure 47 , Figure 49 , Figure 51 and Figure 53 In the described steps, the upper surface of the sacrificial layer 110A is exposed on the bottom surface of the contact hole CCH. In this step, the sacrificial layer 110A is used as an etch stop layer.

[0239] Here, with the increasing integration of semiconductor memory devices, the thickness of the sacrificial layer 110A in the Z direction is continuously decreasing. In this state, when the sacrificial layer 110A is used as an etch stop layer, at the reference... Figures 43-53 In the described steps, the thickness of the sacrificial layer 110A in the Z direction becomes smaller. In this case, for example, in the reference... Figure 27 In the described steps, sometimes the sacrificial layer 110A cannot be removed properly. Additionally, in reference... Figure 28 Sometimes, the conductive layer 110' cannot be properly formed during the described steps.

[0240] Here, to prevent the thickness of the sacrificial layer 110A from decreasing in the Z direction, it is considered to use the insulating layer 101 instead of the sacrificial layer 110A as the etch stop layer. However, in the manufacturing steps of the semiconductor memory device of the third embodiment, when referring to... Figure 43 In the steps described, the upper surface of the uppermost sacrificial layer 110A is exposed.

[0241] Therefore, in the manufacturing method of the semiconductor memory device in the fourth embodiment, referring to Figure 59 In the steps described, Figure 8 and Figure 9 The upper surface of the structure shown is formed with insulating layers 101, 105, and 101. Additionally, in reference... Figure 61 In the described steps, firstly, a portion of the uppermost insulating layer 101 is removed, exposing the upper surface of the insulating layer 105. Then, a portion of the insulating layer 105 is removed, exposing the upper surface of the insulating layer 101 directly beneath it. Additionally, referring to... Figures 62-71 In the steps described, insulating layer 101, rather than sacrificial layer 110A, is used as the etch stop layer.

[0242] According to this method, since the sacrificial layer 110A is not used as an etch stop layer, the reduction in thickness of the sacrificial layer 110A in the Z direction can be suppressed. Therefore, in reference... Figure 27 The described steps allow for the proper removal of the sacrificial layer 110A. Additionally, in reference... Figure 28 In the described steps, the conductive layer 110' can be properly formed. Therefore, the semiconductor memory device of the fourth embodiment can sometimes be manufactured more easily than the semiconductor memory device of the third embodiment.

[0243] [other]

[0244] The semiconductor memory devices according to the first to fourth embodiments have been described above. However, the configurations described above are merely illustrative, and the specific configurations may be adjusted appropriately.

[0245] For example, Figure 40 In the example, two support structures (HRMs) arranged in the Y direction are set between two adjacent CCs in the X direction. Additionally, two support structures (HRMs) arranged in the X direction are set between two adjacent CCs in the Y direction.

[0246] on the other hand, Figure 76 In the example, four support structures (HRMs) arranged in the X and Y directions are set between two adjacent CCs in the X direction. Additionally, four support structures (HRMs) arranged in the X and Y directions are set between two adjacent CCs in the Y direction.

[0247] In addition, for example, Figure 77 In the example, three support structures HR arranged in the Y direction are set between two adjacent CCs in the X direction. Additionally, three support structures HRM arranged in the X direction are set between two adjacent CCs in the Y direction.

[0248] In addition, for example, Figure 2 The example illustrates multiple ( ) arranged consecutively in the Y direction. Figure 2 In the example, there are 8 HRM support structures. Additionally, multiple HRM support structures arranged consecutively in the X direction are illustrated. In this configuration, HRMs are provided in the wiring area R. HU Approximately 67% of the supporting structure HR becomes the supporting structure HRM.

[0249] on the other hand, Figure 78 The illustration shows multiple support structures HRM and multiple support structures HRS arranged alternately in the Y direction. Figure 78 In the example, among the 10 support structure regions HRR arranged in the Y direction, the 3rd and 5th support structure regions HRR counting from one side of the Y direction (e.g., the negative side of the Y direction) have support structures HRM instead of support structures HRS. Furthermore, among the multiple support structures HR contained in the 7th support structure region HRR counting from one side of the Y direction, the 3n+1th (n is an integer greater than or equal to 0) support structure HR is the support structure HRS, and the 3n+2nd and 3n+3rd support structures HR are the support structures HRM. In this configuration, the wiring area R is provided with... HU Approximately 50% of the support structure HR becomes the support structure HRM.

[0250] in addition, Figure 79The illustration shows multiple support structures HRM and multiple support structures HRS arranged alternately in the X direction. Figure 79 In the example, among the 10 support structure regions HRR arranged in the Y direction, the 4th and 7th support structure regions HRR counting from one side in the Y direction have multiple support structures HRM and HRS arranged alternately in the X direction. In this configuration, a wiring area R is provided HU 50% of the support structure HR becomes the support structure HRM.

[0251] in addition, Figure 80 In the example, among the 10 support structure regions HRR arranged in the Y direction, the 4th and 7th support structures HR from one side of the Y direction, and the 3n+1th support structure HR (n is an integer greater than or equal to 0) from one side of the X direction, are support structures HRM, and the 3n+2nd and 3n+3rd support structures HR are support structures HRS. In addition, the other support structure regions HRR include multiple support structures HRS arranged in the X direction. In this configuration, the wiring area R is... HU Approximately 11% of the support structure HR becomes the support structure HRM.

[0252] in addition, Figure 81 In the example, the center positions of the first and third contact electrodes CC, counting from one side of the Y direction, in the XY plane of the three contact electrodes CC arranged in the Y direction are positioned further towards the positive side of the Y direction than the center positions of the stepped regions of each conductive layer 110 in the XY plane. Furthermore, the center position of the second contact electrode CC, counting from one side of the Y direction, in the XY plane is positioned further towards the negative side of the Y direction than the center positions of the stepped regions of each conductive layer 110 in the XY plane. Moreover, the stepped regions referred to here are areas on the upper surface of the conductive layer 110 that do not overlap with other conductive layers 110 when viewed from above.

[0253] in addition, Figure 81 In the example, the 1st, 3rd, 5th, 9th, and 10th support structure regions (HRR) counting from one side in the Y direction contain multiple support structures (HRS) arranged in the X direction. Additionally, the 2nd and 6th to 8th support structure regions (HRR) counting from one side in the Y direction contain multiple support structures (HRM) arranged in the X direction. Furthermore, in the 4th support structure (HR) counting from one side in the Y direction, the (3n+1)th support structure (HR) counting from one side in the X direction is a support structure (HRM), and the (3n+2)th and (3n+3)th support structures (HRS) are support structures. In this configuration, the wiring area R... HU Approximately 39% of the supporting structure HR becomes the supporting structure HRM.

[0254] [other]

[0255] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms and can be omitted, substituted, or modified in various ways without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included in the scope of the invention as described in the claims and its equivalents.

[0256] [Explanation of Symbols]

[0257] 100: Semiconductor substrate

[0258] 101: Insulation layer

[0259] 110: Conductive layer

[0260] 120: Semiconductor layer

[0261] 130: Gate insulating layer

[0262] 131: Tunnel insulation layer

[0263] 132: Charge storage layer

[0264] 133: Barrier Insulation Layer

[0265] 134: High dielectric constant insulating layer

[0266] CC: Contact Electrode

[0267] HR, HRM, HRS: Support structure.

Claims

1. A semiconductor memory device comprising: The substrate has a first region and a second region arranged in a first direction; Multiple first conductive layers are arranged in a second direction intersecting the surface of the substrate, covering the first region and the second region and extending along the first direction; A first semiconductor layer is disposed in the first region, extends in the second direction, and faces the plurality of first conductive layers; A charge storage layer is disposed between the plurality of first conductive layers and the first semiconductor layer; A contact electrode is disposed in the second region, extends in the second direction, and is connected to one of the plurality of first conductive layers; as well as A plurality of first structures and a plurality of second structures are disposed in the second region, extend in the second direction, and are surrounded by the plurality of first conductive layers on their outer peripheral surfaces; The first construction includes: The second semiconductor layer extends in the second direction, faces the plurality of first conductive layers, and contains a semiconductor material common to the first semiconductor layer; and The first insulating layer is disposed between the plurality of first conductive layers and the second semiconductor layer, and includes an insulating material common to the charge storage layer; The second structure does not include the semiconductor material and the insulating material; The second region has: The third region, in the third direction intersecting the first direction and the second direction, is located at a distance less than the first distance from one end of the plurality of first conductive layers. The fourth region, in the third direction, is located at a distance less than the first distance from the other end of the plurality of first conductive layers; and The fifth region is located between the third region and the fourth region; and The plurality of first structures are disposed in the fifth region. At least a portion of the plurality of second structures is disposed in the third region. At least a portion of the plurality of second structures is disposed in the fourth region.

2. The semiconductor memory device according to claim 1, wherein The semiconductor material is polycrystalline silicon (Si). The insulating material is silicon nitride (SiN).

3. The semiconductor memory device according to claim 1 or 2, wherein At least a portion of the plurality of second structures is in contact with the contact electrode.

4. The semiconductor memory device according to claim 1 or 2, wherein More than 30% of the plurality of first structures and the plurality of second structures in the second region are the first structures.

Images