Display substrate and display device
By setting shielded signal lines connected to a fixed potential between adjacent sub-pixel units in the display panel, the coupling capacitance problem between signal lines is solved, improving the uniformity and stability of the display.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2021-06-22
- Publication Date
- 2026-07-21
AI Technical Summary
In display panels, signal crosstalk can occur due to the coupling between signal lines, affecting the uniformity and stability of display brightness.
A shielded signal line is set between adjacent sub-pixel units. The shielded signal line is connected to a fixed potential. The shielded signal line is set between the signal lines to prevent the formation of coupling capacitance and reduce signal interference.
By using shielded signal lines, the coupling capacitance between signal lines is reduced, improving the uniformity and stability of the display.
Smart Images
Figure CN115868258B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Technology
[0002] In today's rapidly developing world of smart technology, the market's demand and expectations for smart terminal display devices are getting higher and higher. The size of mobile phones and tablets is getting larger and larger, and the more diverse application scenarios mean that while people are pursuing full-screen displays, they also hope to enjoy a higher resolution visual experience.
[0003] In a display panel, due to the coupling relationship between various signal lines, there will be more or less signal crosstalk between the signal lines, which will affect the uniformity and stability of the display brightness. Summary of the Invention
[0004] This disclosure provides a display substrate and a display device to reduce signal crosstalk.
[0005] This disclosure provides a display substrate including a plurality of sub-pixel units, the plurality of sub-pixel units including a first sub-pixel unit and a second sub-pixel unit disposed adjacently, the display substrate including: a substrate and a first metal layer, a first insulating layer and a second metal layer stacked on one side of the substrate;
[0006] The first metal layer includes a first electrode block, which is connected to a fixed potential.
[0007] The second metal layer includes signal lines and connecting lines; the signal lines include a first signal line and a second signal line; the connecting lines include a first connecting line and a second connecting line; the first signal line is connected to the driving circuit of the first sub-pixel unit, the second signal line is connected to the driving circuit of the second sub-pixel unit, the first connecting line is located within the first sub-pixel unit, and the second connecting line is located within the second sub-pixel unit;
[0008] A shielded signal line is provided between the first signal line and the second connecting line, and the shielded signal line is connected to the first electrode block.
[0009] In one alternative implementation, the shielded signal line is disposed on the same layer as the second metal layer, and the shielded signal line is connected to the first electrode block through a via disposed on the first insulating layer.
[0010] In one alternative implementation, the shielded signal line is disposed in the same layer as the first metal layer.
[0011] In one alternative implementation, the orthographic projection of the shielded signal line on the substrate does not overlap with the orthographic projection of the signal line on the substrate.
[0012] In one alternative implementation, the extension direction of the shielded signal line is parallel to or intersects the extension direction of the connecting line.
[0013] In one alternative implementation, the orthographic projection of the shielded signal line onto the substrate is a straight line or a curve.
[0014] In one optional implementation, the plurality of sub-pixel units are arranged in an array, the column arrangement direction of the plurality of sub-pixel units is a first direction, and the orthographic projection of the second connecting line on the substrate in the first direction overlaps with the orthographic projection of the shielding signal line on the substrate in the first direction.
[0015] In one alternative implementation, the orthographic projection of the second connection line on the substrate in the first direction falls within the range of the orthographic projection of the shielding signal line on the substrate in the first direction.
[0016] In one alternative implementation, along the first direction, the ratio of the length of the overlap to the length of the orthographic projection of the second connecting line onto the substrate in the first direction is greater than or equal to 0.5 and less than or equal to 0.8.
[0017] In one optional implementation, the plurality of sub-pixel units are arranged in an array, the column arrangement direction of the plurality of sub-pixel units is a first direction, and along the first direction, the length of the shielding signal line is greater than or equal to 4μm and less than or equal to 8μm.
[0018] In one alternative implementation, the second metal layer further includes a power signal line, which is connected to the first electrode block via a via disposed on the first insulating layer.
[0019] In one optional implementation, the display substrate further includes: an active layer, a second insulating layer, a gate layer and a third insulating layer stacked between the substrate and the first metal layer, wherein the first metal layer is disposed on the side of the third insulating layer facing away from the substrate;
[0020] The active layer includes a first channel region, a second channel region, and a first resistive region connecting the first channel region and the second channel region. The gate layer includes a first gate corresponding to the first channel region and a second gate corresponding to the second channel region. The first gate and the second gate are connected.
[0021] The first metal layer further includes a second electrode block, the orthographic projection of the second electrode block on the substrate overlaps with the orthographic projection of the first resistive region on the substrate, and the second electrode block is connected to the shielded signal line.
[0022] In one alternative implementation, the orthographic projection of the second electrode block onto the substrate overlaps the orthographic projection of the first resistive region onto the substrate.
[0023] In one optional implementation, the active layer further includes a second resistance region disposed on the side of the second channel region away from the first resistance region, and the second resistance region is connected to the second channel region;
[0024] The second resistance region and the second connection line are connected by vias disposed on the first insulating layer, the third insulating layer and the second insulating layer.
[0025] In one optional implementation, the active layer further includes a third channel region, a third resistor region connecting the third channel region and the first channel region, and a fourth resistor region disposed on the side of the third channel region away from the third resistor region, the fourth resistor region being connected to the third channel region.
[0026] The gate layer further includes a third gate corresponding to the third channel region, and the third gate is connected to the second connection line through vias disposed on the first insulating layer and the third insulating layer;
[0027] The second signal line is connected to the fourth resistance region through vias disposed on the first insulating layer, the third insulating layer, and the second insulating layer.
[0028] In one alternative implementation, the third gate overlaps with the orthographic projection of the first electrode block onto the substrate.
[0029] This disclosure provides a display device, which includes the display substrate described in any embodiment.
[0030] Compared with the prior art, this disclosure includes the following advantages:
[0031] This disclosure provides a display substrate and a display device. The display substrate includes: a plurality of sub-pixel units, the plurality of sub-pixel units including adjacent first sub-pixel units and second sub-pixel units; the display substrate includes: a substrate and a first metal layer, a first insulating layer and a second metal layer stacked on one side of the substrate; wherein, the first metal layer includes a first electrode block connected to a fixed potential; the second metal layer includes signal lines and connecting lines; the signal lines include a first signal line and a second signal line; the connecting lines include a first connecting line and a second connecting line; the first signal line is connected to a driving circuit of the first sub-pixel unit, the second signal line is connected to a driving circuit of the second sub-pixel unit, the first connecting line is located within the first sub-pixel unit, and the second connecting line is located within the second sub-pixel unit; a shielded signal line is provided between the first signal line and the second connecting line, and the shielded signal line is connected to the first electrode block. The technical solution disclosed herein provides a shielded signal line connected to the first electrode block, which makes the potential on the shielded signal line a fixed potential. Since the shielded signal line is located between the first signal line and the second connecting line, it can prevent the formation of a coupling capacitor between the first signal line and the second connecting line, reduce the signal interference of the first signal line to the second connecting line, and improve the uniformity and stability of the display.
[0032] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the scale in the drawings is for illustration only and does not represent the actual scale.
[0034] Figure 1 A schematic diagram of the planar structure of a display substrate in the related art is shown;
[0035] Figure 2 A schematic diagram of a planar structure of a display substrate provided in an embodiment of this disclosure is shown;
[0036] Figure 3 A cross-sectional structural diagram of a display substrate at a first position is shown according to an embodiment of the present disclosure;
[0037] Figure 4A cross-sectional structural diagram of a display substrate at a second position is shown according to an embodiment of the present disclosure;
[0038] Figure 5 This illustration shows a schematic diagram of the planar structure of the active layer of a display substrate provided in an embodiment of the present disclosure;
[0039] Figure 6 This illustration shows a planar structural diagram of the gate layer of a display substrate according to an embodiment of the present disclosure;
[0040] Figure 7 This diagram illustrates a planar structure of the first metal layer of a display substrate according to an embodiment of the present disclosure.
[0041] Figure 8 This diagram shows a planar structural schematic of the first insulating layer of a display substrate according to an embodiment of the present disclosure;
[0042] Figure 9 A schematic diagram of the planar structure of the second metal layer of a display substrate provided in an embodiment of the present disclosure is shown. Detailed Implementation
[0043] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.
[0044] In related technologies, such as Figure 1 As shown, due to the lateral coupling capacitance between the node signal line 11 of this pixel and the data signal line 12 of the adjacent pixel, signal crosstalk occurs between the data signal on the data signal line 12 and the node signal on the node signal line 11, resulting in poor consistency and stability of display brightness.
[0045] To address the aforementioned problems, one embodiment of this disclosure provides a display substrate, with reference to... Figure 2 A schematic diagram of a planar structure of a display substrate provided in an embodiment of this disclosure is shown. For example... Figure 2 As shown, the display substrate includes multiple sub-pixel units, and the multiple sub-pixel units include a first sub-pixel unit p1 and a second sub-pixel unit p2 arranged adjacent to each other.
[0046] Reference Figure 3 It shows Figure 2 A schematic diagram of the cross-sectional structure of the display substrate along CA'. (Refer to...) Figure 4 It shows Figure 2A schematic diagram of the cross-sectional structure of the display substrate along BB'.
[0047] like Figure 3 and Figure 4 As shown, the display substrate includes: a substrate 21 and a first metal layer 22, a first insulating layer 23 and a second metal layer 24 stacked on one side of the substrate 21.
[0048] The first metal layer 22 includes a first electrode block 221, which is connected to a fixed potential.
[0049] Reference Figure 2 The second metal layer 24 includes signal lines and connecting lines; the signal lines include a first signal line 241 and a second signal line 244; the connecting lines include a first connecting line 245 and a second connecting line 242; the first signal line 241 is connected to the driving circuit of the first sub-pixel unit p1, the second signal line 244 is connected to the driving circuit of the second sub-pixel unit p2, the first connecting line 245 is located in the first sub-pixel unit p1, and the second connecting line 242 is located in the second sub-pixel unit p2.
[0050] Reference Figure 2 and Figure 4 A shielded signal line 25 is provided between the first signal line 241 and the second connecting line 242, and the shielded signal line 25 is connected to the first electrode block 221.
[0051] The shielded signal line 25 is used to shield the signal coupling between the first signal line 241 and the second connecting line 242, so as to prevent the signal on the first signal line 241 from interfering with the signal on the second connecting line 242.
[0052] In this embodiment, the first metal layer 22 can be disposed close to the substrate 21, such as... Figure 3 and Figure 4 As shown; alternatively, the second metal layer 24 can be disposed close to the substrate 21, but this embodiment does not limit this.
[0053] To achieve a fixed potential connection for the first electrode block 221, one possible implementation is as follows: Figure 2 As shown, the second metal layer 24 may further include a power signal line 243, which is connected to the first electrode block 221 through a via provided on the first insulating layer 23. This allows the first electrode block 221 to be connected to a fixed power supply voltage signal such as VDD.
[0054] It should be noted that the fixed potential connected to the first electrode block 221 can also be the ground potential, etc., and this embodiment does not limit this.
[0055] In specific implementations, there can be multiple ways to connect the shielded signal line 25 to the first electrode block 221.
[0056] In one alternative implementation, the shielded signal line 25 can be disposed on the same layer as the first metal layer 22, and the shielded signal line 25 is in contact with the first electrode block 221. In this implementation, the shielded signal line 25 and the first electrode block 221 can be an integral structure.
[0057] In another alternative implementation, such as Figure 4 As shown, the shielded signal line 25 can be disposed on the same layer as the second metal layer 24, that is, the shielded signal line 25 is disposed on the same layer as the first signal line 241 and the second connecting line 242. The shielded signal line 25 is connected to the first electrode block 221 through a via disposed on the first insulating layer 23. Since the shielded signal line 25 is disposed on the same layer as the first signal line 241 and the second connecting line 242, signal crosstalk between the first signal line 241 and the second connecting line 242 can be better shielded.
[0058] In this implementation, the material of the shielded signal line 25 can be the same as that of the first signal line 241 and the second connecting line 242, so that the shielded signal line 25, the first signal line 241, and the second connecting line 242 can be formed synchronously.
[0059] The display substrate provided in this embodiment, by setting a shielded signal line 25 connected to the first electrode block 221, makes the potential on the shielded signal line 25 a fixed potential. Since the shielded signal line 25 is set between the first signal line 241 and the second connecting line 242, the shielded signal line 25 can effectively prevent the formation of coupling capacitance between the first signal line 241 and the second connecting line 242 of adjacent sub-pixel units, prevent the signal on the first signal line 241 from interfering with the signal on the second connecting line 242, and improve the uniformity and stability of the display.
[0060] In one alternative implementation, such as Figure 2 As shown, the orthographic projection of the shielded signal line 25 on the substrate 21 does not overlap with the orthographic projection of the signal lines (including the first signal line 241 and the second signal line 244) on the substrate 21. This avoids the formation of coupling capacitance between the shielded signal line 25 and the signal lines, thus preventing the shielded signal line 25 from interfering with the signals on the signal lines.
[0061] In this embodiment, the extension direction of the shielded signal line 25 can be parallel to the extension direction of the connecting lines (including the first connecting line 245 and the second connecting line 242) (e.g., Figure 2 (as shown in the figure) or intersecting, but this embodiment does not limit this.
[0062] In this embodiment, the orthogonal projection of the shielded signal line 25 onto the substrate 21 can be a straight line (e.g., Figure 2The projection of the shielding signal line 25 onto the substrate 21 can be a straight line or a curve with a certain width (the dimension perpendicular to the extension direction of the shielding signal line 25). In a specific implementation, the projection of the shielding signal line 25 onto the substrate 21 can be a straight line or a curve with a certain width (the dimension perpendicular to the extension direction of the shielding signal line 25).
[0063] like Figure 2 As shown, multiple sub-pixel units are arranged in an array, with the column arrangement direction of the multiple sub-pixel units being the first direction. The orthographic projection of the second connecting line 242 on the substrate 21 in the first direction overlaps with the orthographic projection of the shielding signal line 25 on the substrate 21 in the first direction. The ratio of the length of this overlap along the first direction to the length of the orthographic projection of the second connecting line 242 on the substrate 21 in the first direction can be greater than or equal to 0.5 and less than or equal to 0.8. This can further improve the shielding effect of the shielding signal line.
[0064] In one alternative implementation, such as Figure 2 As shown, the orthographic projection of the second connecting line 242 onto the substrate 21 in the first direction falls within the orthographic projection range of the shielding signal line 25 onto the substrate 21 in the first direction. Thus, in the first direction, the length of the shielding signal line 25 completely covers the length of the second connecting line 242, thereby completely preventing the second connecting line 242 from being interfered with by the signal of the first signal line 241 of the adjacent sub-pixel unit.
[0065] In one alternative implementation, such as Figure 2 As shown, multiple sub-pixel units are arranged in an array, and the column arrangement direction of the multiple sub-pixel units is a first direction. Along the first direction, the length of the shielding signal line 25 can be greater than or equal to 4μm and less than or equal to 8μm. In specific implementations, the length of the shielding signal line 25 can be determined based on factors such as the length of the second connecting line 242 and the design space. This embodiment does not limit its specific value.
[0066] In an alternative implementation, the display substrate may further include: an active layer 50, a second insulating layer, a gate layer 60, and a third insulating layer stacked between the substrate 21 and the first metal layer 22, wherein the first metal layer 22 is disposed on the side of the third insulating layer facing away from the substrate 21. (Refer to...) Figures 5 to 9 A schematic diagram of the planar structure of the active layer 50, gate layer 60, first metal layer 22, first insulating layer 23, and second metal layer 24 is shown. Figure 8 The via area shown is provided in the first insulating layer 23.
[0067] Reference Figure 5The active layer 50 may include a first channel region 501, a second channel region 502, and a first resistive region 503 connecting the first channel region 501 and the second channel region 502. The first resistive region 503 may be formed by conductiveing a corresponding region in the active layer 50.
[0068] Reference Figure 6 The gate layer 60 may include a first gate 601 corresponding to the first channel region 501 and a second gate 602 corresponding to the second channel region 502, wherein the first gate 601 and the second gate 602 are connected. The orthogonal projection of the first gate 601 onto the substrate 21 may cover the orthogonal projection of the first channel region 501 onto the substrate 21. Similarly, the orthogonal projection of the second gate 602 onto the substrate 21 may cover the orthogonal projection of the second channel region 502 onto the substrate 21.
[0069] Reference Figure 2 , Figure 3 and Figure 7 The first metal layer 22 may also include a second electrode block 222, the orthographic projection of the second electrode block 222 on the substrate 21 overlaps with the orthographic projection of the first resistor region 503 on the substrate 21, and the second electrode block 222 is connected to the shielded signal line 25.
[0070] In this implementation, since the orthographic projections of the second electrode block 222 and the first resistor region 503 on the substrate 21 overlap, the second electrode block 222 and the first resistor region 503 form a coupling capacitor. Furthermore, since the shielded signal line 25 is connected to both the first electrode block 221 and the second electrode block 222, and the first electrode block 221 is connected to a fixed potential, the potential on the second electrode block 222 is fixed. This means that one plate of the coupling capacitor has a fixed potential, thereby stabilizing the voltage on the other plate, i.e., the first resistor region 503.
[0071] In specific implementations, there can be multiple ways to connect the shielded signal line 25 to the second electrode block 222. In one optional implementation, the shielded signal line 25 can be disposed on the same layer as the first metal layer 22, and the shielded signal line 25 can be connected to the first electrode block 221 and the second electrode block 222 respectively.
[0072] In another alternative implementation, such as Figure 3 and Figure 4 As shown, the shielded signal line 25 can be disposed on the same layer as the second metal layer 24, that is, the shielded signal line 25 is disposed on the same layer as the first signal line 241 and the second connecting line 242. The shielded signal line 25 is connected to the first electrode block 221 and the second electrode block 222 respectively through the vias disposed on the first insulating layer 23.
[0073] In order to further improve the voltage regulation effect of the second electrode block 222 on the first resistor region 503, the orthogonal projection of the second electrode block 222 on the substrate 21 can cover the orthogonal projection of the first resistor region 503 on the substrate 21.
[0074] It should be noted that, in order to avoid the second electrode block 222 affecting the signals on the first channel region 501, the second channel region 502, the first gate 601 and the second gate 602, the orthogonal projection of the second electrode block 222 on the substrate 21 can be non-overlapping with the orthogonal projections of the first channel region 501, the second channel region 502, the first gate 601 and the second gate 602 on the substrate 21 respectively.
[0075] Reference Figure 5 The active layer 50 may further include a second resistance region 504 disposed on the side of the second channel region 502 away from the first resistance region 503, and the second resistance region 504 is connected to the second channel region 502; the second resistance region 504 and the second connecting line 242 are connected through vias disposed on the first insulating layer 23, the third insulating layer, and the second insulating layer. The second resistance region 504 may be formed by conductiveing a corresponding region in the active layer 50.
[0076] Since the second resistor region 504 is connected to the first resistor region 503 through the second channel region 502, and the second resistor region 504 is connected to the second connecting line 242 through a via, and since the voltage of the first resistor region 503 is relatively stable, this implementation can further improve the voltage stability on the second connecting line 242 and prevent the voltage on the second connecting line 242 from being interfered with by other signals.
[0077] Reference Figure 5 The active layer 50 may also include a third channel region 505; see reference. Figure 6 The gate layer 60 may also include a third gate 603 corresponding to the third channel region 505. The third gate 603 is connected to the second connection line 242 through vias disposed on the first insulating layer 23 and the third insulating layer.
[0078] The orthogonal projection of the third gate 603 onto the substrate 21 can cover the orthogonal projection of the third channel region 505 onto the substrate 21.
[0079] In this embodiment, since the third gate 603 is connected to the second connection line 242 through a via, and the voltage on the second connection line 242 is relatively stable, the voltage stability on the third gate 603 connected to the second connection line 242 is also improved accordingly. This avoids interference from other signals on the voltage on the third gate 603, making the conduction and cutoff of the third channel region 505 more accurate, and improving display uniformity and stability.
[0080] Reference Figure 5The active layer 50 may further include a third resistance region 506 connecting the third channel region 505 and the first channel region 501, and a fourth resistance region 507 disposed on the side of the third channel region 505 away from the third resistance region 506, the fourth resistance region 507 being connected to the third channel region 505.
[0081] The third resistance region 506 and the fourth resistance region 507 can be formed by conductor-forming the corresponding regions in the active layer 50.
[0082] The second signal line 244 and the fourth resistor region 507 can be connected by vias provided on the first insulating layer 23, the third insulating layer and the second insulating layer.
[0083] In this implementation, the third channel region 505, the first channel region 501, and the second channel region 502, under the control of the scanning signals in the third gate 603, the first gate 601, and the second gate 602, respectively, write the signal in the second signal line 244 into the third gate 603 through the second connection line 242.
[0084] In order to maintain a constant voltage signal on the third gate 603, refer to Figure 6 and Figure 7 The orthographic projections of the third gate 603 and the first electrode block 221 on the substrate 21 may overlap. In this way, a storage capacitor is formed between the third gate 603 and the first electrode block 221. This storage capacitor is used to maintain a constant voltage difference between the third gate 603 and the first electrode block 221. Since the first electrode block 221 is connected to a fixed potential, the voltage signal on the third gate 603 can remain unchanged.
[0085] In a specific implementation, the first signal line 241 can be connected to the first data signal input terminal, and the second signal line 244 can be connected to the second data signal input terminal. This embodiment does not limit this.
[0086] In this embodiment, the display substrate can be an OLED display substrate, but this embodiment is not limited to it.
[0087] It should be noted that the thin-film transistor structures corresponding to the first channel region 501, the second channel region 502, and the third channel region 505 mentioned above are all top-gate structures. In specific implementations, these thin-film transistors can also be bottom-gate structures. By adopting a top-gate structure, the film layer separating the third gate 603 and the first electrode block 221 is thinner, thereby increasing the storage capacitance.
[0088] Another embodiment of this disclosure also provides a display device, which may include the display substrate described in any embodiment.
[0089] It should be noted that the display device in this embodiment can be any product or component with 2D or 3D display function, such as a display panel, electronic paper, mobile phone, tablet computer, television, laptop computer, digital photo frame, or navigator.
[0090] This disclosure provides a display substrate and a display device. The display substrate includes: a plurality of sub-pixel units, the plurality of sub-pixel units including adjacent first sub-pixel units and second sub-pixel units; the display substrate includes: a substrate and a first metal layer, a first insulating layer and a second metal layer stacked on one side of the substrate; wherein, the first metal layer includes a first electrode block connected to a fixed potential; the second metal layer includes signal lines and connecting lines; the signal lines include a first signal line and a second signal line; the connecting lines include a first connecting line and a second connecting line; the first signal line is connected to a driving circuit of the first sub-pixel unit, the second signal line is connected to a driving circuit of the second sub-pixel unit, the first connecting line is located within the first sub-pixel unit, and the second connecting line is located within the second sub-pixel unit; a shielded signal line is disposed between the first signal line and the second connecting line, and the shielded signal line is connected to the first electrode block. The technical solution disclosed herein provides a shielded signal line connected to the first electrode block, which makes the potential on the shielded signal line a fixed potential. Since the shielded signal line is located between the first signal line and the second connecting line, it can effectively prevent the formation of a coupling capacitor between the first signal line and the second connecting line, reduce the signal interference of the first signal line to the second connecting line, and improve the uniformity and stability of the display.
[0091] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0092] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0093] The above provides a detailed description of a display substrate and display device provided by this disclosure. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this disclosure. Furthermore, those skilled in the art will recognize that, based on the ideas of this disclosure, there will be changes in specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this disclosure. The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a specific feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Additionally, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.
[0094] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.
[0095] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This disclosure can be implemented by means of hardware comprising a plurality of different elements and by means of a suitably programmed computer. In a unit claim enumerating a plurality of means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.
[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.
Claims
1. A display substrate, characterized in that, The display substrate includes multiple sub-pixel units, wherein the multiple sub-pixel units include adjacent first sub-pixel units and second sub-pixel units, and the display substrate includes: a substrate and a first metal layer, a first insulating layer and a second metal layer stacked on one side of the substrate; The first metal layer includes a first electrode block, which is connected to a fixed potential. The second metal layer includes signal lines and connecting lines; the signal lines include a first signal line and a second signal line; the connecting lines include a first connecting line and a second connecting line; the first signal line is connected to the driving circuit of the first sub-pixel unit, the second signal line is connected to the driving circuit of the second sub-pixel unit, the first connecting line is located within the first sub-pixel unit, and the second connecting line is located within the second sub-pixel unit; A shielded signal line is provided between the first signal line and the second connecting line, and the shielded signal line is connected to the first electrode block. The orthographic projection of the shielded signal line on the substrate is located between the orthographic projections of the first signal line and the second connecting line on the substrate; The display substrate further includes: an active layer, a second insulating layer, a gate layer and a third insulating layer stacked between the substrate and the first metal layer, wherein the first metal layer is disposed on the side of the third insulating layer opposite to the substrate; The active layer includes a first channel region, a second channel region, and a first resistive region connecting the first channel region and the second channel region. The gate layer includes a first gate corresponding to the first channel region and a second gate corresponding to the second channel region. The first gate and the second gate are connected. The first metal layer further includes a second electrode block, the orthographic projection of the second electrode block on the substrate overlaps with the orthographic projection of the first resistive region on the substrate, and the second electrode block is connected to the shielded signal line; The orthogonal projection of the second electrode block on the substrate overlaps the orthogonal projection of the first resistive region on the substrate.
2. The display substrate according to claim 1, characterized in that, The shielded signal line is disposed in the same layer as the second metal layer, and the shielded signal line is connected to the first electrode block through a via disposed in the first insulating layer.
3. The display substrate according to claim 1, characterized in that, The shielded signal line is disposed in the same layer as the first metal layer.
4. The display substrate according to claim 1, characterized in that, The orthographic projection of the shielded signal line on the substrate does not overlap with the orthographic projection of the signal line on the substrate.
5. The display substrate according to claim 1, characterized in that, The extension direction of the shielded signal line is parallel to or intersects with the extension direction of the connecting line.
6. The display substrate according to claim 1, characterized in that, The orthogonal projection of the shielded signal line onto the substrate is a straight line or a curve.
7. The display substrate according to claim 1, characterized in that, The plurality of sub-pixel units are arranged in an array, and the column arrangement direction of the plurality of sub-pixel units is a first direction. The orthographic projection of the second connecting line on the substrate in the first direction overlaps with the orthographic projection of the shielding signal line on the substrate in the first direction.
8. The display substrate according to claim 7, characterized in that, The orthographic projection of the second connecting line on the substrate in the first direction is within the range of the orthographic projection of the shielding signal line on the substrate in the first direction.
9. The display substrate according to claim 7, characterized in that, Along the first direction, the ratio of the length of the overlap to the length of the orthographic projection of the second connecting line onto the substrate in the first direction is greater than or equal to 0.5 and less than or equal to 0.
8.
10. The display substrate according to claim 1, characterized in that, The plurality of sub-pixel units are arranged in an array, and the column arrangement direction of the plurality of sub-pixel units is a first direction. Along the first direction, the length of the shielding signal line is greater than or equal to 4μm and less than or equal to 8μm.
11. The display substrate according to claim 1, characterized in that, The second metal layer also includes a power signal line, which is connected to the first electrode block through a via disposed on the first insulating layer.
12. The display substrate according to claim 1, characterized in that, The active layer further includes a second resistance region disposed on the side of the second channel region away from the first resistance region, and the second resistance region is connected to the second channel region; The second resistance region and the second connection line are connected by vias disposed on the first insulating layer, the third insulating layer and the second insulating layer.
13. The display substrate according to claim 12, characterized in that, The active layer further includes a third channel region, a third resistance region connecting the third channel region and the first channel region, and a fourth resistance region disposed on the side of the third channel region away from the third resistance region, the fourth resistance region being connected to the third channel region. The gate layer further includes a third gate corresponding to the third channel region, and the third gate is connected to the second connection line through vias disposed on the first insulating layer and the third insulating layer; The second signal line is connected to the fourth resistance region through vias disposed on the first insulating layer, the third insulating layer, and the second insulating layer.
14. The display substrate according to claim 13, characterized in that, The third gate overlaps with the orthographic projection of the first electrode block onto the substrate.
15. A display device, characterized in that, The display device includes the display substrate according to any one of claims 1 to 14.