Peak voltage detection circuit and peak voltage detection method
By working together with the clock generation module, the set start switch, the comparator module, the successive approximation logic module, and the digital-to-analog conversion module, the problem of low detection efficiency of traditional peak detection circuits at high frequencies is solved, and efficient detection and accurate output of high-speed periodic disturbance signals are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUN YAT SEN UNIV
- Filing Date
- 2022-12-15
- Publication Date
- 2026-06-02
AI Technical Summary
Traditional peak detection circuits have low detection efficiency, the input signal frequency is limited by the operational amplifier bandwidth and cannot work at high frequencies, and digital auxiliary circuits have complex structures and are not easy to integrate.
By employing the coordinated operation of a clock generation module, a set start switch, a comparator module, a successive approximation logic module, and a digital-to-analog conversion module, and by controlling the clock phase shift and adjusting the feedback signal through successive approximation logic, high-speed peak detection is achieved.
It achieves efficient detection of high-speed periodic disturbance signals, has a simple circuit structure, is easy to integrate, and has high versatility and detection accuracy.
Smart Images
Figure CN115877073B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of peak voltage detection technology, and in particular to a peak voltage detection circuit and a peak voltage detection method. Background Technology
[0002] A peak detection circuit is a circuit that can detect the peak value of an AC signal. The input to a peak detection circuit is the AC signal being detected, and ideally, the output is a stable voltage, i.e., the peak value of the AC signal. Peak detection circuits are widely used in integrated circuit front-end readout modules, such as in automatic gain control circuits, biomedical equipment, and molecular image detection. However, traditional peak detection circuits have low detection efficiency, and the input signal frequency is limited by the operational amplifier bandwidth, operating only in the range of several thousand to 1 megahertz.
[0003] Two high-speed peak detection devices assisted by digital circuits have been proposed in related technologies. One is a time-delay compensated peak detector, which uses digital calibration to enable the analog peak detector to operate at frequencies up to 20MHz, improving the voltage error after time-delay compensation from -6.85% to -0.81%. The other is a high-precision digitally assisted peak detection circuit based on 0.18µm technology, capable of peak detection of MHz-GHz periodic signals with a peak-to-peak error of only 2mV. In traditional peak detection circuits, the input signal frequency is limited by the operational amplifier bandwidth, operating only in the range of several thousand to 1 MHz. While time-delay compensated peak detectors use digital assistance to further increase the input signal frequency and reduce the detection error, they are still limited by the bandwidth of the integrator operational amplifier, preventing further increases in the input signal frequency and resulting in low versatility. Although digitally assisted peak detection devices can operate in the MHz-GHz range with relatively small peak errors, their circuit structure is complex, making them difficult to embed into other modules and limiting their versatility. Summary of the Invention
[0004] This invention provides a peak voltage detection circuit and a peak voltage detection method that can detect high-speed periodic disturbance signals and has high versatility.
[0005] In a first aspect, embodiments of the present invention provide a peak voltage detection circuit, comprising:
[0006] The clock generation module includes a clock signal output terminal and a lock signal output terminal. The clock signal output terminal is used to output an external clock signal that is phase-shifted by 1 / 2π from the clock of the input signal to be measured.
[0007] A set-start switch includes a lock signal input terminal and a set terminal connected to the lock signal output terminal;
[0008] The comparator module includes a clock signal receiving terminal, an inverting input terminal, a non-inverting input terminal connected to the set terminal, and a comparator output terminal. The clock signal receiving terminal is connected to the clock signal output terminal, and the inverting input terminal is used to input the input signal to be measured.
[0009] The successive approximation logic module includes a comparison input terminal and a switch switching signal output terminal, wherein the comparison input terminal is connected to the comparison output terminal;
[0010] The digital-to-analog converter module includes a switch switching signal input terminal and a feedback terminal. The switch switching signal input terminal is connected to the switch switching signal output terminal, and the feedback terminal is connected to the set terminal and the in-phase input terminal, respectively.
[0011] The peak voltage detection circuit provided according to the embodiments of the present invention has at least the following beneficial effects: A clock generation module includes a clock signal output terminal and a lock signal output terminal. The clock signal output terminal is used to output an external clock signal with a phase shift of 1 / 2π compared to the clock of the input signal to be measured. The lock signal output terminal is used to output a lock signal controlling the on / off state of a set-start switch. The set-start switch is used to control the on / off state of the set-start switch when the output lock signal is low. The set-start switch includes a lock signal input terminal and a set terminal connected to the lock signal output terminal. The set-start switch is used to control the setting of the digital-to-analog converter module or the start of the comparator module. The comparator module is started when the set-start switch is off, and outputs a set signal to set the feedback terminal of the digital-to-analog converter module to a common-mode level when the set-start switch is closed and conducting. The comparator module includes a clock signal receiving terminal, an inverting input terminal, a non-inverting input terminal connected to the set terminal, and a comparison output terminal. The clock signal receiving terminal is connected to the clock signal output terminal. The inverting input terminal is used to input the input signal to be measured. The comparator module is used to control the on / off state of the input signal under the control of an external clock signal. Under the control of the circuit, the peak value of the input signal to be measured is compared with the voltage value of the feedback signal, the comparison result signal is output, and the cumulative number of comparisons is obtained. The successive approximation logic module includes a comparison input terminal and a switch switching signal output terminal. The comparison input terminal is connected to the comparison output terminal. The successive approximation logic module is used to receive the comparison result signal output by the comparator module, and to perform logical judgment processing based on the comparison result signal to obtain and output a switch switching signal. This switch switching signal is used to perform voltage adjustment processing on the first feedback signal to obtain an updated second feedback signal. The digital-to-analog conversion module includes a switch switching signal input terminal and a feedback terminal. The switch switching signal input terminal is connected to the switch switching signal output terminal, and the feedback terminal is connected to the set terminal and the non-inverting input terminal respectively. The digital-to-analog conversion module is used to perform voltage adjustment processing on the first feedback signal under the control of the switch switching signal to obtain and output an updated second feedback signal. The second feedback signal is used to compare the voltage value with the input signal to be measured again. When the number of comparisons i is equal to the preset number threshold, the peak voltage detection circuit outputs the peak voltage of the input signal to be measured. The peak voltage detection circuit of this invention has a simple circuit structure, is easy to integrate into other circuits, and can detect high-speed periodic disturbance signals through the coordinated work of various modules, thus having high versatility.
[0012] In a second aspect, embodiments of the present invention provide a peak voltage detection method, applied to the peak voltage detection circuit as described in the first aspect, comprising:
[0013] When the lock signal output by the clock generation module is low, the set start switch is disconnected, causing the digital-to-analog converter module to output the first feedback signal.
[0014] Under the control of the external clock signal output by the clock generation module, which has a phase shift of 1 / 2π compared with the clock of the input signal to be measured, the voltage value of the input signal to be measured is compared with the first feedback signal by the comparator module to obtain the comparison result signal and the cumulative number of comparisons i.
[0015] The switch switching signal is obtained by performing logical judgment processing based on the comparison result signal through the successive approximation logic module.
[0016] Under the control of the switch switching signal, the first feedback signal is subjected to voltage regulation processing to obtain an updated second feedback signal;
[0017] If the number of comparisons i is less than a preset threshold, the voltage values of the second feedback signal and the input signal to be measured are compared sequentially.
[0018] When the number of comparisons i equals a preset threshold number, the peak voltage of the input signal to be measured is output.
[0019] The peak voltage detection method provided by the embodiments of the present invention has at least the following beneficial effects: In the peak voltage detection circuit, when the lock signal output by the clock generation module is low, the set start switch is disconnected, causing the digital-to-analog converter module to output a first feedback signal; then, under the control of the external clock signal output by the clock generation module, which has a phase shift of 1 / 2π compared with the clock of the input signal to be measured, the voltage value of the input signal to be measured and the first feedback signal are compared by the comparator module to obtain a comparison result signal and the accumulated comparison count i; then, the successive approximation logic module performs logical judgment processing based on the comparison result signal to obtain a switch switching signal; next, under the control of the switch switching signal, the voltage of the first feedback signal is adjusted to obtain an updated second feedback signal; then, when the comparison count i is less than a preset count threshold, the voltage value of the second feedback signal and the input signal to be measured are compared sequentially; finally, when the comparison count i is equal to the preset count threshold, the peak voltage of the input signal to be measured is output. According to the embodiment of the present invention, by controlling an external clock signal with a phase shift of 1 / 2π from the clock of the input signal to be measured, the comparator module can compare the peak value of the input signal to be measured with the voltage value of the first feedback signal and output a comparison result signal. Then, based on the comparison result signal, the first feedback signal is adjusted successively to obtain a second feedback signal, so that the second feedback signal successively approaches the peak voltage. When the number of comparisons is equal to a preset threshold, the peak voltage of the input signal to be measured is output. That is to say, the embodiment of the present invention can detect high-speed periodic disturbance signals and has high versatility.
[0020] The beneficial effects of this invention can be understood by practicing it. The objectives and other advantages of this invention can be realized and obtained through the structures particularly pointed out in the specification and drawings. Attached Figure Description
[0021] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the technical solutions of the present invention, and do not constitute a limitation on the technical solutions of the present invention.
[0022] Figure 1 This is a schematic diagram of the peak voltage detection circuit provided in one embodiment of the present invention;
[0023] Figure 2 This is a schematic diagram of the specific structure of a peak voltage detection circuit provided in another embodiment of the present invention;
[0024] Figure 3 This is a schematic diagram of the structure of a successive approximation logic module provided in one embodiment of the present invention;
[0025] Figure 4 This is a schematic diagram of the specific structure of an internal clock generation module provided in one embodiment of the present invention;
[0026] Figure 5 This is a schematic diagram of the specific structure of the judgment and setting subunit of the judgment and setting module provided in one embodiment of the present invention;
[0027] Figure 6 This is a schematic diagram of the specific structure of a digital-to-analog conversion module provided in one embodiment of the present invention;
[0028] Figure 7 This is a flowchart of a peak voltage detection method provided in one embodiment of the present invention;
[0029] Figure 8 This is a flowchart of the peak voltage detection method provided in one embodiment of the present invention. Detailed Implementation
[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0031] It should be noted that although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0032] This invention provides a peak voltage detection circuit and a peak voltage detection method. The peak voltage detection circuit includes a clock generation module, a set-start switch, a comparator module, a successive approximation logic module, and a digital-to-analog conversion module. The circuit structure is simple and easy to integrate into other circuits. Through the coordinated work of the clock generation module, the set-start switch, the comparator module, the successive approximation logic module, and the digital-to-analog conversion module, it can detect high-speed periodic disturbance signals and has high versatility.
[0033] The embodiments of the present invention will be further described below with reference to the accompanying drawings.
[0034] Firstly, such as Figure 1 As shown, Figure 1 This is a schematic diagram of the peak voltage detection circuit provided in one embodiment of the present invention. Figure 1 In the example, the peak voltage detection circuit 100 includes a clock generation module 110, a set start switch 120, a comparator module 130, a successive approximation logic module 140, and a digital-to-analog converter module 150. The system includes a clock generation module 110, which includes a clock signal output terminal and a lock signal output terminal. The clock signal output terminal is used to output an external clock signal that is 1 / 2π phase-shifted from the clock of the input signal under test. A set start switch 120 includes a lock signal input terminal and a set terminal connected to the lock signal output terminal. A comparator module 130 includes a clock signal receiving terminal, an inverting input terminal, a non-inverting input terminal connected to the set terminal, and a comparison output terminal. The clock signal receiving terminal is connected to the clock signal output terminal, and the inverting input terminal is used to input the input signal under test. A successive approximation logic module 140 includes a comparison input terminal and a switch switching signal output terminal. The comparison input terminal is connected to the comparison output terminal. A digital-to-analog conversion module 150 includes a switch switching signal input terminal and a feedback terminal. The switch switching signal input terminal is connected to the switch switching signal output terminal, and the feedback terminal is connected to the set terminal and the non-inverting input terminal, respectively.
[0035] The peak voltage detection circuit 100 provided by the present invention includes a clock generation module 110, a set start switch 120, a comparator module 130, a successive approximation logic module 140, and a digital-to-analog conversion module 150. The circuit structure is simple and easy to integrate into other circuits.
[0036] The clock generation module 110 includes a clock signal output terminal and a lock signal output terminal. The clock signal output terminal is used to output an external clock signal that is phase-shifted by 1 / 2π from the clock of the input signal to be measured. The lock signal output terminal is used to output a lock signal that controls the on / off state of the set start switch. When the output lock signal is low, the set start switch is opened; when the output lock signal is high, the set start switch is closed.
[0037] The set start switch 120 includes a lock signal input terminal and a set terminal connected to the lock signal output terminal. The set start switch 120 is used to control the setting of the digital-to-analog converter module 150 or the start of the comparator module 130. When the set start switch 120 is open, the comparator module 130 is started. When the set start switch 120 is closed and conducting, a set signal is output to set the feedback terminal of the digital-to-analog converter module 150 to the common-mode level.
[0038] The comparator module 130 includes a clock signal receiving terminal, an inverting input terminal, a non-inverting input terminal connected to the set terminal, and a comparison output terminal. The clock signal receiving terminal is connected to the clock signal output terminal, and the inverting input terminal is used to input the input signal to be measured. The comparator module 130 is used to compare the peak value of the input signal to be measured with the feedback signal under the control of an external clock signal, output the comparison result signal, and obtain the cumulative number of comparisons.
[0039] The successive approximation logic module 140 includes a comparison input terminal and a switch switching signal output terminal. The comparison input terminal is connected to the comparison output terminal. The successive approximation logic module 140 is used to receive the comparison result signal output by the comparator module 130, and perform logical judgment processing based on the comparison result signal to obtain and output the switch switching signal. The switch switching signal is used to perform voltage regulation processing on the first feedback signal to obtain an updated second feedback signal.
[0040] The digital-to-analog converter module 150 includes a switch switching signal input terminal, a set signal input terminal, and a feedback terminal. The switch switching signal input terminal is connected to the switch switching signal output terminal, and the feedback terminal is connected to the set terminal and the non-inverting input terminal, respectively. The digital-to-analog converter module 150 is used to perform voltage regulation processing on the first feedback signal under the control of the switch switching signal to obtain and output an updated second feedback signal. The second feedback signal is used to compare the voltage value with the input signal to be measured Vin again. When the number of comparisons i is equal to the preset number threshold, the feedback terminal outputs the peak voltage Vpeak of the input signal to be measured.
[0041] In this embodiment of the invention, the comparator module 130, controlled by an external clock signal with a 1 / 2π phase shift relative to the clock of the input signal under test, performs voltage value comparison processing on the peak value of the input signal under test and the first feedback signal, and outputs a comparison result signal. Therefore, the input signal under test can be a high-frequency periodic disturbance signal.
[0042] Therefore, the peak voltage detection circuit 100 provided by the present invention can detect high-speed periodic disturbance signals through the coordinated operation of various modules, and has high versatility.
[0043] In one embodiment, reference is made to Figure 2 , Figure 2 This is a schematic diagram of the specific structure of a peak voltage detection circuit provided in another embodiment of the present invention.
[0044] The clock generation module 110 can employ a DLL (Delay-locked Loop) circuit. The input terminal of the DLL circuit receives the clock signal of the input signal under test. After processing, the DLL circuit provides the comparator module 130 with an external clock signal that differs from the clock of the input signal under test by 1 / 2π, facilitating the comparator module 130 to successively approximate the peak values of the feedback signal and the input signal under test. The DLL circuit also includes a lock detection circuit, which outputs a lock signal to control the on / off state of the set-start switch. When the lock detection circuit is not locked, the lock signal output by the DLL circuit (i.e., the Begin signal in the diagram) is high, causing the set-start switch 120 to close and conduct; when the lock detection circuit is locked, the lock signal output by the DLL circuit is low, causing the set-start switch 120 to open.
[0045] The set-start switch 120 employs a gate voltage bootstrap sampling circuit (BOOTSTRAP), capable of receiving the lock signal output from the DLL circuit and closing or opening under the control of the lock signal. The set-start switch 120 is used to control the setting of the digital-to-analog converter module 150 or the start of the comparator module 130. When the set-start switch 120 is closed, the set signal Vcm is input to the digital-to-analog converter module 150, setting the upper plate voltage to the common-mode level Vcm. When the set-start switch 120 is open, the digital-to-analog converter module 150 outputs a feedback signal to the comparator module 130, which then starts comparing the voltage values of the feedback signal and the input signal to be measured. The specific structure of the BOOTSTRAP circuit is not described in detail in this embodiment of the invention.
[0046] The comparator module 130 employs a high-speed comparator. The high-speed comparator includes a non-inverting input terminal and an inverting input terminal. The non-inverting input terminal is used to input the feedback signal output by the digital-to-analog conversion module 150, and the inverting input terminal is used to input the input signal to be measured. In addition, the high-speed comparator can also receive the external clock signal output by the DLL circuit. Under the control of the external clock signal, the peak value of the input signal to be measured and the feedback signal are successively compared in terms of voltage value to generate a comparison result signal, and the comparison result signal is output to the successive approximation logic module 140. Specifically, the comparison result signal includes a Voutp signal, a Voutn signal, and a Valid signal. Among them, the Valid signal is the sum signal of the Voutp signal and the Voutn signal. When the feedback signal is greater than the peak value of the input signal to be measured, that is, V+>V-, the Voutp signal is a pulse signal, and the Voutn signal is a low-level signal; when the feedback signal is less than the peak value of the input signal to be measured, that is, V+<V-, the Voutp signal is a low-level signal, and the Voutn signal is a pulse signal. Here, the specific structure of the high-speed comparator in the embodiments of the present invention will not be elaborated.
[0047] The successive approximation logic module 140 is used to receive the comparison result signal output by the high-speed comparator and perform logical judgment processing according to the comparison result signal to obtain and output a switch switching signal. Specifically, the switch switching signal includes a first array switch switching signal (i.e., A1 to A8 shown in the figure) and a second array switch switching signal (i.e., B1 to B8 shown in the figure). The first array switch switching signal is used to indicate that the nth switching switch in the first capacitor array is grounded, so that the voltage of the upper plate rises, thereby increasing the voltage of the second feedback signal. The second array switch switching signal is used to indicate that the nth switching switch in the second capacitor array is connected to the reference voltage source, so that the voltage of the upper plate drops, thereby reducing the voltage of the second feedback signal. This switch switching signal is used to perform voltage adjustment processing on the first feedback signal to obtain an updated second feedback signal.
[0048] The digital-to-analog conversion module 150 can adopt a digital-to-analog converter (CDAC), which is used to receive the first array switch switching signal and the second array switch switching signal output by the successive approximation logic module 140, and under the control of the switch switching signal, perform voltage adjustment processing on the first feedback signal to obtain and output an updated second feedback signal, so that the second feedback signal successively approximates the peak voltage of the input signal to be measured.
[0049] In the peak voltage detection circuit of the embodiments of the present invention, the detection speed of its circuit structure is only affected by the speed of the high-speed comparator and the CDAC establishment time, and it can input a periodic disturbance signal with a frequency of up to several hundred megahertz, having strong universality.
[0050] Refer to Figure 3 , Figure 3This is a schematic diagram of the structure of a successive approximation logic module provided in one embodiment of the present invention. In some embodiments, the successive approximation logic module 140 includes an internal clock module 141 and a judgment and setting module 142. The first internal clock input terminal of the internal clock module 141 and the signal input terminal of the judgment and setting module 142 are respectively connected to the comparison output terminal, and the first internal clock output terminal of the internal clock module 141 is connected to the second internal clock input terminal of the judgment and setting module 142.
[0051] Reference Figure 4 , Figure 4 This is a schematic diagram of the internal clock generation module provided in one embodiment of the present invention. The internal clock module includes multiple level flip-flops, which are connected sequentially to form a series structure. Specifically, the internal clock module 141 is composed of n first D flip-flops 1411 connected in series. Each first D flip-flop 1411 includes a clock input pin (CLK), a signal input pin (D), a reset pin (rstn), and a non-inverting output pin (Q). Each clock input pin is connected to a comparison output terminal to receive a Valid signal. Each reset pin is used to input a reset signal. The signal input pin of the first first D flip-flop 1411 is used to input a VDD signal, and the non-inverting output pin of the nth first D flip-flop 1411 is used to output the generated internal clock signal. In the internal clock module, when the Valid signal arrives, the n first D flip-flops 1411 sequentially generate the internal clock signal, i.e., the Clk<1:n> signal.
[0052] Reference Figure 5 , Figure 5 This is a schematic diagram of the specific structure of a judgment and set subunit of a judgment and set module provided in one embodiment of the present invention. In some embodiments, the judgment and set module 142 is composed of n judgment and set subunits connected in parallel, wherein each judgment and set unit includes a second D flip-flop 1421 and a third D flip-flop 1422. The second D flip-flop 1421 and the third D flip-flop 1422 both include a clock input pin (CLK), a signal input pin (D), a reset pin (rstn), a non-inverting output pin (Q), and an inverting output pin (QN). The two clock input pins are connected to the non-inverting output pin of the nth first D flip-flop 1411 of the internal clock generation module to receive the Clk<1:n> signal; each reset pin is used to input the reset signal rstn; the signal input pin of the second D flip-flop 1421 is connected to the comparison output terminal to acquire the Voutn signal, and the inverting output pin of the second D flip-flop 1421 is used to output the first array switch switching signal (A in the figure). <n>The signal input pin of the third D flip-flop 1422 is connected to the comparator output to acquire the Voutp signal. The inverting output pin of the third D flip-flop is used to output the second array switch switching signal (B in the diagram). <n>Specifically, in practical work, when comparing from the nth position onwards, if V+ > V-, then Voutp <n>The signal is a pulse signal, Voutn <n>The signal is a low-level signal. At this time, the set module collects Voutp. <n>Signal and Voutn <n>Signal, to obtain B <n> ＝1，A <n>=1, and output to the digital-to-analog conversion module 150.
[0053] Reference Figure 6 , Figure 6 This is a schematic diagram of the specific structure of a digital-to-analog converter (CDAC) module according to an embodiment of the present invention. The CDAC module includes a first capacitor array CPA and a second capacitor array CPB, both with their upper plates connected to a set terminal. Both the first and second capacitor arrays include multiple capacitors, with the number of capacitors in both arrays being equal. Each capacitor in the first and second capacitor arrays is connected to a reference voltage source Vref or a reference ground GND via its corresponding switching switch. The switching switch is used to connect to the reference voltage source Vref under high-level control or to the reference ground GND under low-level control. Specifically, the switching switch is a single-pole double-throw switch.
[0054] In some embodiments, the first capacitor array CPA is used to control the rise of the upper plate voltage of the digital-to-analog converter module 150, and the second capacitor array CPB is used to control the fall of the upper plate voltage of the digital-to-analog converter module 150.
[0055] In one embodiment of this application, before the peak voltage detection circuit 100 starts working, all switches in the first capacitor array CPA are pre-connected to the reference voltage source Vref; all switches in the second capacitor array CPB are pre-connected to the reference ground GND. When the nth bit comparison begins, the digital-to-analog converter module 150 receives the first array switch switching signal A output by the judgment and setting module of the successive approximation logic module 140. <n>Second array switch switching signal B <n> 。A <n> 、B <n>These control the nth switching switch corresponding to the first capacitor array CPA and the second capacitor array CPB, respectively. For example, when A... <n> ＝1，B <n>If the value of i is 1, the nth switch of the first capacitor array CPA remains unchanged and is connected to the reference voltage source Vref; while the nth switch of the second capacitor array CPB switches and is connected to the reference voltage source Vref; this causes the digital-to-analog converter module to perform voltage regulation processing, re-establish a new voltage value, and output a second feedback signal with the new voltage value. If the number of comparisons i is less than a preset threshold, the second feedback signal is used to compare the voltage value with the input signal under test again; if the number of comparisons i is equal to the preset threshold, the feedback terminal of the digital-to-analog converter module 150 outputs the second feedback signal as the peak voltage Vpeak of the input signal under test.
[0056] It is understood that the range of the digital-to-analog conversion module 150 should cover the range of the detected peak values. Those skilled in the art can configure it according to specific needs, and this invention will not elaborate on this.
[0057] Secondly, referring to Figure 7 , Figure 7 This is a flowchart of a peak voltage detection method provided in one embodiment of the present invention. This peak voltage detection method can be applied to a peak voltage detection circuit as provided in the first aspect embodiment, such as... Figure 1 The peak voltage detection circuit 100 shown. The peak voltage detection method may include, but is not limited to, steps S710 to S760.
[0058] Step S710: When the lock signal output by the clock generation module is low, disconnect the set start switch to make the digital-to-analog converter output the first feedback signal.
[0059] Step S720: Under the control of the external clock signal output by the clock generation module, which has a phase shift of 1 / 2π compared with the clock of the input signal to be measured, the voltage value of the input signal to be measured is compared with the first feedback signal by the comparator module to obtain the comparison result signal and the cumulative number of comparisons i.
[0060] Step S730: The successive approximation logic module performs logical judgment processing based on the comparison result signal to obtain the switch switching signal.
[0061] Step S740: Under the control of the switch switching signal, the first feedback signal is subjected to voltage regulation processing to obtain an updated second feedback signal.
[0062] Step S750: If the number of comparisons i is less than the preset number threshold, the voltage values of the second feedback signal and the input signal to be measured are compared sequentially.
[0063] Step S760: When the number of comparisons i is equal to the preset number threshold, output the peak voltage of the input signal to be tested.
[0064] In this embodiment of the invention, a peak voltage detection method including steps S710 to S760 is employed. In the peak voltage detection circuit, when the lock signal output by the clock generation module is low, the set start switch is disconnected, causing the digital-to-analog converter module to start outputting the first feedback signal. Then, under the control of an external clock signal output by the clock generation module, which has a phase shift of 1 / 2π compared to the clock of the input signal under test, the voltage values of the input signal under test and the first feedback signal are compared by the comparator module to obtain a comparison result signal and the accumulated comparison count i. Then, the successive approximation logic module performs logical judgment processing based on the comparison result signal to obtain a switch switching signal. Next, under the control of the switch switching signal, the voltage of the first feedback signal is adjusted to obtain an updated second feedback signal. Then, when the comparison count i is less than a preset threshold, the voltage values of the second feedback signal and the input signal under test are compared sequentially. Finally, when the comparison count i is equal to the preset threshold, the peak voltage of the input signal under test is output. According to the embodiment of the present invention, by controlling an external clock signal with a phase shift of 1 / 2π from the clock of the input signal to be measured, the comparator module can compare the peak value of the input signal to be measured with the voltage value of the first feedback signal and output a comparison result signal. Then, based on the comparison result signal, the first feedback signal is adjusted successively to obtain a second feedback signal, so that the second feedback signal successively approaches the peak voltage. When the number of comparisons i is equal to a preset threshold, the peak voltage of the input signal to be measured is output. That is to say, the embodiment of the present invention can detect high-speed periodic disturbance signals and has high versatility.
[0065] It is understood that the switching signals include the first array switching signal and the second array switching signal.
[0066] In some embodiments, the preset number threshold is equal to the number N of capacitors in the first capacitor array or the second capacitor array.
[0067] In another embodiment, the step "obtaining the switch switching signal by performing logical judgment processing based on the comparison result signal through the successive approximation logic module" is further explained. This step may include, but is not limited to, the following steps:
[0068] If the voltage value of the first feedback signal is less than the peak value of the input signal to be measured, the second comparison result signal is output.
[0069] An internal clock signal is generated by the internal clock module based on the first comparison result signal;
[0070] Under the control of the internal clock signal, the first comparison result signal is judged by the judgment and setting module to generate a first array switch switching signal. This first array switch switching signal is used to indicate that the nth switch in the first capacitor array is grounded, causing the upper plate voltage to rise and thus increasing the voltage value of the second feedback signal. The voltage increase is determined by the reference voltage Vref and the comparison number i. Specifically, the voltage increase ΔV = Vref ref / 2 i+1 This is beneficial because, when the initial feedback signal is less than the peak value of the input signal to be measured, the voltage value of the feedback signal can be gradually increased to gradually approach the peak value of the input signal to be measured, thereby reducing the peak error during the detection process and improving the detection accuracy.
[0071] In one embodiment, the step "obtaining the switch switching signal by performing logical judgment processing based on the comparison result signal through the successive approximation logic module" is further described. This step may also include, but is not limited to, the following steps:
[0072] If the voltage value of the first feedback signal is greater than the peak value of the input signal to be measured, the second comparison result signal is output.
[0073] An internal clock signal is generated by the internal clock module based on the second comparison result signal;
[0074] Under the control of the internal clock signal, the second comparison result signal is judged by the judgment and setting module, and a second array switch switching signal is generated. This second array switch switching signal instructs the nth switch in the second capacitor array to connect to the reference voltage source, causing the upper plate voltage to drop and thus reducing the voltage value of the second feedback signal. The voltage reduction amount is determined by the reference voltage Vref and the comparison number i. Specifically, the voltage reduction amount ΔV = Vref ref / 2 i+1 This is beneficial because, when the initial feedback signal is greater than the peak value of the input signal to be measured, the voltage value of the feedback signal can be gradually reduced to gradually approach the peak value of the input signal to be measured, thereby reducing the peak error during the detection process and improving the detection accuracy.
[0075] For example, refer to Figure 8 , Figure 8 This is a flowchart of the peak voltage detection method provided in one embodiment of the present invention.
[0076] In the initial stage, the set start switch is off. Sampling and setting are performed to set the voltage of the upper plate in the digital-to-analog conversion module to the common-mode level Vcm. At this time, the voltage V+ at the non-inverting input terminal of the comparator module is Vcm, and the voltage V- at the inverting input terminal is Vin. The initial value of the sampling count is set to 1. All the switching switches at the lower plates of the first capacitor array CPA are connected to the reference voltage source Vref, and all the switching switches at the lower plates of the second capacitor array CPB are connected to the reference ground GND. After the DLL is established, the DLL outputs a low-level lock signal to disconnect the set start switch, enabling the comparator module to perform successive approximation comparison of the peak value. Since there is a phase shift of 1 / 2π between the external clock signal provided by the DLL and the input signal to be measured, when the external clock signal provided by the DLL arrives, the rising edge of the external clock signal exactly corresponds to the peak value V of the input signal to be measured TOP , that is, at this time, the voltage values of the feedback signal and the peak value of the input signal to be measured are compared, and the cumulative comparison count i is recorded. If V+>V-, the corresponding positions of the switching switches in the first capacitor array CPA remain unchanged, and the nth switching switch in the second capacitor array CPB is set to 1 and switched to be connected to the reference voltage source Vref, causing the voltage of the upper plate in the digital-to-analog conversion module to decrease, thereby causing V+ to decrease. The decrease amount of V+ is V ref / 2 i+1 . Similarly, when V+<V-, the nth switching switch in the first capacitor array CPA is set to 0 and switched to be connected to the reference ground GND, and the corresponding positions of the switching switches in the second capacitor array CPB remain unchanged, causing the voltage of the upper plate in the digital-to-analog conversion module to increase, thereby causing V+ to increase. The increase amount of V+ is V ref / 2 i+1 . Since the measurement range of the digital-to-analog conversion module covers the peak value range, when the comparison count i is equal to the preset count threshold N, V+≈V-, that is, the peak voltage of the input voltage to be measured is obtained.
[0077] The above has specifically described the preferred embodiment of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations or substitutions are all included within the scope defined by the present invention.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>
Claims
1. A peak voltage detection circuit, characterized in that, include: The clock generation module includes a clock signal output terminal and a lock signal output terminal. The clock signal output terminal is used to output an external clock signal that is phase-shifted by 1 / 2π from the clock of the input signal to be measured. A set-start switch includes a lock signal input terminal and a set terminal connected to the lock signal output terminal; The comparator module includes a clock signal receiving terminal, an inverting input terminal, a non-inverting input terminal connected to the set terminal, and a comparator output terminal. The clock signal receiving terminal is connected to the clock signal output terminal, and the inverting input terminal is used to input the input signal to be measured. The successive approximation logic module includes a comparison input terminal and a switch switching signal output terminal, wherein the comparison input terminal is connected to the comparison output terminal; A digital-to-analog converter module includes a switch switching signal input terminal and a feedback terminal. The switch switching signal input terminal is connected to the switch switching signal output terminal, and the feedback terminal is connected to the set terminal and the in-phase input terminal, respectively. The digital-to-analog conversion module includes a first capacitor array and a second capacitor array, and the upper plates of both the first capacitor array and the second capacitor array are connected to the set terminal. Both the first capacitor array and the second capacitor array include multiple capacitors, and the number of capacitors in the first capacitor array and the second capacitor array are equal. Each capacitor in the first capacitor array and the second capacitor array is connected to a reference voltage source or a reference ground through its corresponding switching switch. The switching switch is used to connect to the reference voltage source under high level control or to the reference ground under low level control.
2. The peak voltage detection circuit according to claim 1, characterized in that, The successive approximation logic module includes an internal clock module and a judgment and set module. The first internal clock input terminal of the internal clock module and the signal input terminal of the judgment and set module are respectively connected to the comparison output terminal. The first internal clock output terminal of the internal clock module is connected to the second internal clock input terminal of the judgment and set module.
3. The peak voltage detection circuit according to claim 2, characterized in that, The internal clock module includes multiple level triggers, which are connected in sequence to form a series structure.
4. A peak voltage detection method, characterized in that, The method, applied to the peak voltage detection circuit as described in any one of claims 1 to 3, comprises: When the lock signal output by the clock generation module is low, the set start switch is disconnected, causing the digital-to-analog converter module to output the first feedback signal. Under the control of the external clock signal output by the clock generation module, which has a phase shift of 1 / 2π compared with the clock of the input signal to be measured, the voltage value of the input signal to be measured is compared with the first feedback signal by the comparator module to obtain the comparison result signal and the cumulative number of comparisons i. The switch switching signal is obtained by performing logical judgment processing based on the comparison result signal through the successive approximation logic module. Under the control of the switch switching signal, the first feedback signal is subjected to voltage regulation processing to obtain an updated second feedback signal; If the number of comparisons i is less than a preset threshold, the voltage values of the second feedback signal and the input signal to be measured are compared sequentially. When the number of comparisons i equals a preset threshold number, the peak voltage of the input signal to be measured is output.
5. The peak voltage detection method according to claim 4, characterized in that, The preset number of times threshold is equal to the number N of capacitors in the first capacitor array or the second capacitor array.
6. The peak voltage detection method according to claim 4, characterized in that, The switch switching signal includes a first array switch switching signal. The step of obtaining the switch switching signal by performing logical judgment processing based on the comparison result signal through the successive approximation logic module includes: If the voltage value of the first feedback signal is less than the peak value of the input signal to be measured, the first comparison result signal is output. An internal clock signal is generated by the internal clock module based on the first comparison result signal; Under the control of the internal clock signal, the first comparison result signal is judged by the judgment and setting module to generate the first array switch switching signal. The first array switch switching signal is used to indicate that the nth switching switch in the first capacitor array is grounded, so that the voltage of the upper plate rises and thereby increases the voltage value of the second feedback signal.
7. The peak voltage detection method according to claim 4, characterized in that, The switch switching signal includes a second array switch switching signal. The step of obtaining the switch switching signal through logical judgment processing based on the comparison result signal by the successive approximation logic module further includes: If the voltage value of the first feedback signal is greater than the peak value of the input signal to be measured, a second comparison result signal is output. An internal clock signal is generated by the internal clock module based on the second comparison result signal; Under the control of the internal clock signal, the second comparison result signal is judged by the judgment and setting module to generate the second array switch switching signal. The second array switch switching signal is used to indicate that the nth switching switch in the second capacitor array is connected to the reference voltage source so that the voltage of the upper plate decreases and thus reduces the voltage value of the second feedback signal.