Chip aging test apparatus and method

Abstract

The application provides a chip aging test device and method, the device comprises a connection state detection module, a test control module and an aging control module, wherein the connection state detection module is electrically connected with a chip, used for detecting whether the connection state between the chip and an aging board is normal when the chip is placed on a test seat of the aging board, and a trigger signal is generated when the detection is normal; the test control module is used for generating an aging confirmation signal according to the trigger signal; and the aging control module is used for allowing the chip aging test device to perform aging test on the chip according to the aging confirmation signal. The application increases the detection of the connection state between the chip and the aging board by the chip aging test device, can effectively avoid the aging test of the aging board and the chip in the case of connection failure, optimizes the chip aging test effect, and improves the aging coverage.

Description

Technical Field

[0001] This application relates to the field of chip testing and manufacturing technology, and in particular to a chip aging test apparatus and a chip aging test method. Background Technology

[0002] To eliminate potentially prematurely failing products before chip delivery, aging tests are typically required. Aging tests are accelerated life tests performed after packaging and mainly include voltage testing, current testing, timing characteristic testing, and functional testing under high temperature and high pressure conditions. Aging tests can ensure a high aging coverage.

[0003] As chip size increases, the connection problems between the chip and the test socket of the aging board during aging testing also increase. Currently, the connectivity issues of chip aging testing are usually ignored during chip aging testing, which leads to aging testing still being carried out when the connection between the aging board and the chip fails, resulting in poor chip aging test results and affecting aging coverage. Summary of the Invention

[0004] This application provides a chip aging test apparatus and method to at least solve the problems of poor chip aging test results and reduced aging coverage caused by aging tests performed when the aging board and chip are in a state of connection failure.

[0005] According to one aspect of this application, a chip aging test apparatus is provided, comprising a connection status detection module, a test control module, and an aging control module, wherein...

[0006] The connection status detection module is electrically connected to the chip and is used to detect whether the connection status between the chip and the aging board is normal when the chip is placed on the test socket of the aging board, and generate a trigger signal when the detection is normal.

[0007] The test control module is used to generate an aging confirmation signal based on the trigger signal; and,

[0008] The aging control module is used to allow the chip aging test device to perform aging tests on the chip based on the aging confirmation signal.

[0009] In one embodiment, the connection status detection module is specifically used to obtain the decoding information of the chip based on the received test instruction sequence when the chip is placed on the test socket of the aging board, and to detect whether the connection status between the chip and the aging board is normal based on the decoding information.

[0010] In one embodiment, the connection state detection module includes a controller, a finite state machine, and a control generator, wherein the controller is electrically connected to the chip, the finite state machine, and the control generator, respectively.

[0011] The controller is used to test the instruction sequence when the chip is placed on the test socket of the aging board, and to verify whether the test instruction sequence is the same as the preset test instruction sequence used to start the aging test. When the verification result is the same, the controller obtains the decoding information of the chip, and detects whether the connection status between each pin of the chip and the aging board is normal according to the decoding information. When all connection statuses are normal, the controller generates a control signal, which is used to drive the finite state machine to work.

[0012] The control generator is used to generate a trigger signal when the finite state machine reaches a preset working state, and send the trigger signal to the test control module.

[0013] In one embodiment, the test control module includes a clock gating, an AND gate, and a flip-flop, and has a signal terminal for receiving the trigger signal and an enable signal terminal for receiving an aging signal. The signal terminal and the enable signal terminal are connected to the flip-flop via the AND gate. The enable signal terminal is also connected to the clock gating, and the clock gating is turned on when the enable signal terminal receives the aging signal. The flip-flop is used to generate an aging confirmation signal based on the trigger signal and the aging signal after the clock gating is turned on.

[0014] In one implementation, a shielding module is also included.

[0015] The shielding module is used to emit a shielding signal to shield signals other than those generated during aging tests.

[0016] According to another aspect of this application, a chip aging test method is provided, including a connection status detection module, a test control module, and an aging control module, wherein the connection status detection module is electrically connected to the chip, and the method includes:

[0017] The connection status detection module detects whether the connection status between the chip and the aging board is normal when the chip is placed on the test socket of the aging board, and generates a trigger signal when the detection is normal.

[0018] The test control module generates an aging confirmation signal based on the trigger signal; and

[0019] The aging control module generates an aging test signal based on the aging confirmation signal, and allows the chip aging test device to perform aging tests on the chip based on the aging test signal.

[0020] In one embodiment, the connection status detection module detects whether the connection status between the chip and the aging board is normal when the chip is placed on the test socket of the aging board, including:

[0021] When the chip is placed on the test socket of the aging board, the connection detection module obtains the decoding information of the chip based on the received test command sequence, and detects whether the connection status between the chip and the aging board is normal based on the decoding information.

[0022] In one embodiment, the connection status detection module includes a controller, a finite state machine, and a control generator. The controller is electrically connected to the chip, the finite state machine, and the control generator, respectively. Based on the decoded information, it detects whether the connection status between the chip and the burn-in board is normal. When the detection is normal, it generates a trigger signal, including:

[0023] The controller performs a test command sequence when the chip is placed on the test socket of the aging board, and verifies whether the test command sequence is the same as a preset test command sequence used to start the aging test. When the verification result is the same, it acquires the decoding information of the chip, and checks whether the connection status between each pin of the chip and the aging board is normal based on the decoding information. If all connections are normal, it generates a control signal, which is used to drive the finite state machine to work; and...

[0024] The control generator determines whether the finite state machine has reached a preset working state. If so, it generates a trigger signal and sends the trigger signal to the test control module.

[0025] In one embodiment, the test control module includes a clock gating, an AND gate, and a flip-flop, and has a signal terminal for receiving the trigger signal and an enable signal terminal for receiving the aging signal. The signal terminal and the enable signal terminal are connected to the flip-flop through the AND gate. The enable signal terminal is also connected to the clock gating. When the enable signal terminal receives the aging signal, the clock gating is turned on.

[0026] The test control module generates an aging confirmation signal based on the trigger signal, including: the signal terminal receiving the trigger signal;

[0027] The enable signal terminal receives the aging signal;

[0028] After the clock gate is turned on, the trigger generates an aging confirmation signal based on the trigger signal and the aging signal.

[0029] In one embodiment, a shielding module is further included, and after the connection status detection module generates a trigger signal, the method further includes:

[0030] The shielding module emits a shielding signal to shield signals other than those generated during aging tests.

[0031] The chip aging test apparatus and method provided in this application are electrically connected to the chip via a connection status detection module. When the chip is placed on the test socket of the aging board, the connection status between the chip and the aging board is detected to be normal. When the connection status is normal, a trigger signal is generated. Then, the test control module generates an aging confirmation signal based on the trigger signal. Finally, the aging control module controls the start of the aging test between the chip and the aging board based on the aging confirmation signal. This method can detect the connection status between the chip and the aging board during the chip aging test, effectively avoiding aging tests when the connection between the aging board and the chip is failed, optimizing the chip aging test effect, and improving the aging coverage. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0033] Figure 1 This is a schematic diagram illustrating a possible application scenario of a chip aging test apparatus according to an embodiment of this application;

[0034] Figure 2 This is one of the structural schematic diagrams of a chip aging test device provided in an embodiment of this application;

[0035] Figure 3 for Figure 2 A schematic diagram of the connection status detection module 131;

[0036] Figure 4 for Figure 2 A schematic diagram of the structure of the test control module 132;

[0037] Figure 5(a) is a schematic diagram of chip aging test in related technologies;

[0038] Figure 5(b) is a schematic diagram of the chip aging test in the embodiments of this application, including a test mode for detecting chip connection status and a test mode for not detecting chip connection status;

[0039] Figure 6 This is a second schematic diagram of a chip aging test device provided in an embodiment of this application;

[0040] Figure 7 This is one of the flowcharts illustrating a chip aging test method provided in an embodiment of this application;

[0041] Figure 8This is a second schematic flowchart of a chip aging test method provided in an embodiment of this application.

[0042] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0043] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0044] As chip size increases, the number of chip pins also increases, leading to more connection problems between the chip and the test socket during aging tests. These problems mainly manifest in two aspects: firstly, the large number of control pins, and secondly, the numerous frequency points outside the test cores. These characteristics can cause connection failures between the aging board and the chip. To avoid performing aging tests despite connection failures, which could result in poor aging test performance and reduced aging coverage, proper connection testing between the aging board and the chip is crucial.

[0045] In related technologies, logic flip tests and memory (RAM) flip tests are performed simultaneously or cyclically in the aging test mode to complete chip aging tests. The aging status is only observed through TDO (Test Data Output), and the shift output results of the scan chain or the MBIST test results are selected by configuring core-configure-chain. However, in the logic flip test and memory (RAM) flip test modes, the connection status between I / O ports other than the control ports and the aging board cannot be detected by scan tests; only the connection status between the I / O ports used in the aging test mode and the aging board is detected through TDO. That is, in the aging test mode, only the connection status of some I / O ports and the aging board can be detected through the observation results of TDO. In this case, it is not possible to flexibly start and pause the aging test according to the connection status between the aging board and the chip, making it difficult to achieve the technical effect of avoiding aging tests when the connection between the aging board and the chip fails.

[0046] In another related technology, although connection detection methods between the chip and the test board have been proposed for other chip testing modes, the methods for detecting the connection status between the chip and the test board on ATE (Automatic Test Equipment) usually require configuring a test protocol and having the ATE generate and output stimulus signals. This makes it difficult to implement such testing costs and stimulus application on a aging board. In other words, the connection detection methods between the chip and the test board in ordinary chip testing modes cannot be applied to aging tests.

[0047] In view of this, embodiments of this application propose adding a chip aging test device between the chip and the aging board, combined with Figure 1 As shown, Figure 1 This is a schematic diagram of a possible application scenario for a chip aging test device in an embodiment of this application. It includes an aging board 110, a chip 120, and a chip aging test device 130. The aging board 110 may include a plurality of test sockets 111. The chip 120 is electrically connected to the aging board by being placed on the test sockets 111. In this embodiment of the application, by using a chip aging test device to detect the connection status between the chip and the aging board during the aging test, and then controlling the start of the aging test between the chip and the aging board, the aging test can be effectively avoided when the connection between the aging board and the chip fails, thus optimizing the chip aging test effect and improving the aging coverage.

[0048] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0049] Please refer to Figure 2 , Figure 2 A chip aging test apparatus 130 provided in this application embodiment includes a connection status detection module 131, a test control module 132, and an aging control module 133, wherein...

[0050] The connection status detection module 131 is electrically connected to the chip and is used to detect whether the connection status between the chip and the aging board is normal when the chip is placed on the test socket of the aging board, and generate a trigger signal when the detection is normal.

[0051] In this embodiment, the chip's decoding information can be obtained and processed according to the received test instruction sequence when the chip is placed on the test socket of the aging board, and the connection status between the chip and the aging board can be detected based on the chip's decoding information.

[0052] Understandably, the chip's decoding information is the information obtained through decoding by a decoder. Based on this decoding information, the connection status information of each pin of the chip, such as voltage and current, can be detected to determine if it is normal. Considering that the chip may undergo multiple tests simultaneously in addition to aging tests, this embodiment obtains the chip's decoding information based on a received test command sequence. This test command sequence can be a sequence of information input by the tester. In one implementation, the received test command sequence is verified. If the received test command sequence is a preset test command sequence, the chip's decoding information is obtained. This preset command sequence is a system-preset functional command sequence used to initiate the aging test process. For example, in connection detection mode, the operator inputs this preset command sequence to initiate chip connection status detection. If the operator inputs a command sequence that is not the preset command sequence, the chip connection status detection is not initiated; instead, other test processes are started based on the corresponding functional command sequence. This design allows the chip to undergo multiple tests simultaneously in addition to aging tests, without interference between different tests.

[0053] It should be noted that those skilled in the art can adapt the preset instruction sequence information to suit actual applications; in addition, the chip is placed on the test socket, either directly on the test socket or connected to the test socket via a circuit.

[0054] In one implementation, such as Figure 3 As shown, the connection status detection module 131 includes a controller 1311, a finite state machine 1312, and a control generator 1313. The controller 1311 is electrically connected to the chip, the finite state machine 1312, and the control generator 1313, respectively.

[0055] It is understandable that a finite state machine, or finite state automaton (FSM), is a computational model abstracted for studying computational processes with limited memory and certain language classes. A finite state automaton has a finite number of states, each of which can transition to zero or more states. The input string determines which state transition is executed. A finite state automaton can be represented as a directed graph. The controller 1311 is used to receive a test instruction sequence when the chip is placed on the test socket of the aging board, and to verify whether the test instruction sequence is the same as a preset test instruction sequence used to start the aging test. When the verification result is the same, it acquires the decoding information of the chip, and based on the decoding information, detects whether the connection status between each pin of the chip and the aging board is normal. If all connections are normal, it generates a control signal, which drives the finite state machine 1312 to operate.

[0056] The control generator 1313 is used to generate a trigger signal when the finite state machine reaches a preset working state, and send the trigger signal to the test control module.

[0057] In this embodiment, the system verifies whether the received test instruction sequence is the same as the preset test instruction sequence used to start the aging test, thereby determining whether the user has initiated the aging test process. Based on the voltage and other information of the chip pins in the obtained decoding information, the system detects whether the state of each pin of the chip is normal. If all are normal, a control signal is generated to drive the finite state machine 1312 to work. The finite state machine 1312 and the control generator 1313 form a state analysis module. The state analysis module analyzes that when the finite state machine reaches the preset state, it generates a trigger signal and sends it to the test control module 132.

[0058] In this system, the finite state machine begins operation upon receiving a control signal. When it transitions to a preset operating state, the control generator generates a trigger signal. It is understood that those skilled in the art can adaptively set the preset operating state according to practical applications. For example, the finite state machine includes two states: the current state and the next state. When a condition is met (a control signal is received), the corresponding action is executed, transitioning from the current state to the next state, which is the preset operating state. In some examples, the finite state machine may also transition directly to the next state without executing any action after receiving a control signal.

[0059] The test control module 132 is used to generate an aging confirmation signal based on the trigger signal.

[0060] Compared to related technologies that directly perform chip aging tests via enable switches or function commands, neglecting the connection issue between the chip and the aging board, this embodiment only generates an aging confirmation signal upon receiving a trigger signal from the connection status detection module 131, thereby controlling the initiation of aging tests between the chip and the aging board. This effectively avoids aging tests being performed when the connection between the aging board and the chip fails.

[0061] In one implementation, such as Figure 4 As shown, the test control module 132 includes

[0062] The system includes a clock gate (CG), an AND gate (AND), and a flip-flop (D). It also has a signal terminal a for receiving the trigger signal and an enable signal terminal b for receiving the aging signal. The signal terminal a and the enable signal terminal b are connected to the flip-flop D via the AND gate. The enable signal terminal b is also connected to the clock gate (CG). When the enable signal terminal b receives the aging signal, the clock gate is turned on.

[0063] The trigger D is used to generate an aging confirmation signal based on the trigger signal and the aging signal after the clock-gated CG is turned on.

[0064] In this example, the test control module 132 consists of a flip-flop D with reset, a clock-gated gate CG, and an AND gate. The clock of flip-flop D is controlled by the clock-gated gate CG, and the enable terminal b of CG is directly controlled by the aging signal BURNIN_EN. In other modes, CG is disabled, the output value of flip-flop D is 0 (after reset), and the aging confirmation signal burnin_connect is 1. The aging signal BURNIN_EN and the trigger signal Trigger jointly control the output of the AND gate, and the output of the AND gate is connected to the D terminal of the flip-flop. That is, in the aging test mode, the clock of the flip-flop is valid, and the aging confirmation signal burnin_connect is determined by both the trigger signal Trigger and the aging signal BURNIN_EN.

[0065] The aging control module 133 is used to allow the chip aging test device to perform aging tests on the chip based on the aging confirmation signal.

[0066] In this embodiment, after receiving the aging confirmation signal, the aging control module 133 controls the start of the aging test between the chip and the aging board, that is, it generates a test signal to enter the scan chain / memory to start the aging (test) mode. The value of the trigger in the chip or the MBIST running result can be detected by shifting out through the scan chain, and the observation signal result is output. Correspondingly, if the connection status verification between the chip pin and the aging board fails, the chip will enter the non-aging test mode, and the aging observation result will be set to other specified states.

[0067] In a specific example, the aging test mode can be divided into a chip connection status detection test mode and a non-chip connection status detection test mode, as shown in Figures 5(a) and 5(b). Using the technology of this application, the aging mode of the circuit is jointly controlled by the trigger signal Trigger and the aging signal BURNIN_EN. When BURNIN_EN changes from 0 to 1, the chip enters the aging test mode. If the Trigger signal is 1 at this time, it enters the chip connection status detection test mode; if the Trigger signal is 0, it enters the non-chip connection status detection test mode. When the BURNIN_EN signal changes from 1 to 0, the chip exits the aging (test) mode.

[0068] Please refer to Figure 6 , Figure 6This is a second schematic diagram of a chip aging test apparatus provided in this application. Based on the above embodiments, this example also considers signal interference and other issues during the chip aging test process. By setting a shielding module, it shields signals other than those generated during the aging test, making the processed signal clearer and more accurate. Figure 6 As shown, the chip aging test device includes a connection status detection module 131, a test control module 132, an aging control module 133, a shielding module 134, and a scan chain / memory, wherein the scan chain / memory is used to perform aging tests and generate observation signals.

[0069] It should be noted that scan chain / memory is a common chip testing method in this field. It involves adding a selector before ordinary flip-flops to connect them in series into a long chain of multiple flip-flops. The selector has two inputs: one from the scan input and the other from combinational logic. The scan enable signal controls the selector to choose the data input source for the flip-flops. In aging test mode, when the scan enable is 1, the chip is in shift mode. In shift mode, after multiple clock cycles, the scan input value can be shifted into the flip-flops on the chain or the value in the flip-flops on the chain can be shifted out for observation.

[0070] In addition, the chip test design includes a variety of test modes, such as JTAG test, IOMAP test and Nand-Tree test for IO (Input / Output) electrical parameter characteristics. These test modes can be controlled using JTAG design. For each test mode, different JTAG instructions need to be configured and the data register of the corresponding instruction needs to be initialized. This embodiment will not elaborate on this further.

[0071] The shielding module 134 is used to emit a shielding signal to shield signals other than those generated during aging tests.

[0072] In one example, after generating an aging confirmation signal, the test control module synchronously transmits the aging confirmation signal to the shielding module 134. The shielding module 134 can determine whether to send a shielding signal to the aging control module 133 based on the status of the aging confirmation signal. The aging control module 133 can then send a test signal based on the signals sent by the test control module and the shielding module to control the start of the aging test process of the scan chain / memory.

[0073] Based on the same technical concept, this application also provides one of the chip aging test methods, including a connection status detection module, a test control module, and an aging control module, wherein the connection status detection module is electrically connected to the chip, such as... Figure 7 As shown, the method includes steps S701-S704.

[0074] Step S701: When the chip is placed on the test socket of the aging board, the connection status detection module detects whether the connection status between the chip and the aging board is normal. If it is normal, step S702 is executed; otherwise, the process ends. In some embodiments, the non-chip connection status detection mode is entered, which has been described in the device embodiment and will not be repeated here.

[0075] Step S702: The connection status detection module generates a trigger signal;

[0076] Step S703: The test control module generates an aging confirmation signal based on the trigger signal; and,

[0077] Step S704: The aging control module generates an aging test signal based on the aging confirmation signal, and allows the chip aging test device to perform an aging test on the chip based on the aging test signal.

[0078] In one embodiment, step S701, where the connection status detection module detects whether the connection status between the chip and the aging board is normal when the chip is placed on the test socket of the aging board, includes the following steps:

[0079] When the chip is placed on the test socket of the aging board, the connection detection module obtains the decoding information of the chip based on the received test command sequence, and detects whether the connection status between the chip and the aging board is normal based on the decoding information.

[0080] In one embodiment, the connection status detection module includes a controller, a finite state machine, and a control generator. The controller is electrically connected to the chip, the finite state machine, and the control generator, respectively. Based on the decoded information, it detects whether the connection status between the chip and the aging board is normal. When the detection is normal, it generates a trigger signal (step S701), including the following steps:

[0081] The controller receives a test command sequence when the chip is placed on the test socket of the aging board, and verifies whether the test command sequence is the same as a preset test command sequence used to start the aging test. When the verification result is the same, it acquires the decoding information of the chip, and checks whether the connection status between each pin of the chip and the aging board is normal according to the decoding information. If all connections are normal, it generates a control signal, which is used to drive the finite state machine to work; and,

[0082] The control generator determines whether the finite state machine has reached a preset working state. If so, it generates a trigger signal and sends the trigger signal to the test control module.

[0083] In one embodiment, the test control module includes

[0084] The test control module includes a clock gating, an AND gate, and a flip-flop, and has a signal terminal for receiving the trigger signal and an enable signal terminal for receiving the aging signal. The signal terminal and the enable signal terminal are connected to the flip-flop through the AND gate. The enable signal terminal is also connected to the clock gating. When the enable signal terminal receives the aging signal, the clock gating is turned on.

[0085] The test control module generates an aging confirmation signal based on the trigger signal (step S702), which includes the following steps:

[0086] The signal terminal receives the trigger signal;

[0087] The enable signal terminal receives the aging signal;

[0088] After the clock gate is turned on, the trigger generates an aging confirmation signal based on the trigger signal and the aging signal.

[0089] In one embodiment, a shielding module is further included. After the connection status detection module generates a trigger signal, the method further includes the following steps:

[0090] The shielding module emits a shielding signal to shield signals other than those generated during aging tests.

[0091] It should be noted that the principles of each step of the method provided in the embodiments of this application have been described in detail in the above device embodiments, and will not be repeated here.

[0092] Please refer to the above-described device embodiments for details. Figure 8 , Figure 8 The second flowchart illustrating the chip aging test method provided in this application embodiment first involves powering on the chip and selecting a mode. If the output signal is BURNIN_EN = 1, the aging (test) mode is selected; if the output signal is BURNIN_EN = 0, another mode is selected. In aging mode, pin status verification (i.e., connection status detection) is performed first. If the verification passes, the chip connection status detection aging mode is entered; otherwise, the non-chip connection status detection aging mode is entered. Specifically,

[0093] After the chip completes the power-on operation and enters the working mode, the BURNIN_EN signal is set to 0, and the chip will enter the non-aging mode. Operations in the non-aging mode are independent of pin status verification. Regardless of whether the user performs pin status verification or whether the verification passes, the trigger signal generated by the pin status verification module will not affect the current operation.

[0094] After the chip is powered on, if you want to enter the aging mode for detecting chip connection status, set the BURNIN_EN signal to 1 to enter the aging mode. In the aging mode, the user can verify the pin status. After the pin status verification is successful, the chip will switch to the aging mode for detecting chip connection status.

[0095] During the aging process of entering the chip connection status detection mode, the trigger signal generated by the connection status detection module is sent to the test control module. The test control module generates a corresponding aging confirmation signal, and the shielding module can further determine whether the aging output result needs to be processed. Therefore, the test output result in the chip connection status aging mode is the original result after signal shielding, while the test output result in the non-chip connection status aging mode is the result that requires processing.

[0096] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0097] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A chip aging test apparatus, characterized in that, It includes a connection status detection module, a test control module, and an aging control module. The connection status detection module includes a finite state machine, a controller, and a control generator. The controller is electrically connected to the chip, the finite state machine, and the control generator, respectively. The connection status detection module is electrically connected to the chip and is used to obtain the chip's decoding information based on the received test command sequence when the chip is placed on the test socket of the aging board, and to detect whether the connection status between the chip and the aging board is normal based on the decoding information. The controller is configured to receive a test instruction sequence when the chip is placed on the test socket of the aging board, and verify whether the test instruction sequence is the same as the preset test instruction sequence used to start the aging test. When the verification result is the same, the controller obtains the decoding information of the chip, and detects whether the connection status between each pin of the chip and the aging board is normal according to the decoding information. When all connection statuses are normal, the controller generates a control signal, which is used to drive the finite state machine to work. The control generator is used to generate a trigger signal when the finite state machine reaches a preset working state, and send the trigger signal to the test control module; The test control module is used to generate an aging confirmation signal based on the trigger signal; and, The aging control module is used to allow the chip aging test device to perform aging tests on the chip based on the aging confirmation signal.

2. The apparatus according to claim 1, characterized in that, The test control module includes a clock gating, an AND gate, and a flip-flop, and has a signal terminal for receiving a trigger signal and an enable signal terminal for receiving an aging signal. The signal terminal for receiving the trigger signal and the enable signal terminal are connected to the flip-flop through the AND gate. The enable signal terminal is also connected to the clock gating. When the enable signal terminal receives the aging signal, the clock gating is turned on. The trigger is used to generate an aging confirmation signal based on the trigger signal and the aging signal after the clock gating is turned on.

3. The apparatus according to claim 1, characterized in that, It also includes a shielding module. The shielding module is used to emit a shielding signal to shield signals other than those generated during aging tests.

4. A chip aging test method, characterized in that, The method includes a connection status detection module, a test control module, and an aging control module. The connection status detection module is electrically connected to the chip and includes a finite state machine, a controller, and a control generator. The controller is electrically connected to the chip, the finite state machine, and the control generator. The controller receives a test command sequence when the chip is placed on the test socket of the aging board, and verifies whether the test command sequence is the same as a preset test command sequence used to start the aging test. When the verification result is the same, it acquires the decoding information of the chip, and checks whether the connection status between each pin of the chip and the aging board is normal according to the decoding information. If all connections are normal, it generates a control signal, which is used to drive the finite state machine to work; and, The control generator determines whether the finite state machine has reached a preset working state. If so, it generates a trigger signal and sends the trigger signal to the test control module. The test control module generates an aging confirmation signal based on the trigger signal; and The aging control module generates an aging test signal based on the aging confirmation signal, and allows the chip aging test device to perform an aging test on the chip based on the aging test signal.

5. The method according to claim 4, characterized in that, The test control module includes a clock gating, an AND gate, and a flip-flop, and has a signal terminal for receiving a trigger signal and an enable signal terminal for receiving an aging signal. The signal terminal for receiving the trigger signal and the enable signal terminal are connected to the flip-flop through the AND gate. The enable signal terminal is also connected to the clock gating. When the enable signal terminal receives an aging signal, the clock gating is turned on. The test control module generates an aging confirmation signal based on the trigger signal, including: The signal terminal that receives the trigger signal receives the trigger signal; The enable signal terminal receives the aging signal; After the clock gate is turned on, the trigger generates an aging confirmation signal based on the trigger signal and the aging signal.

6. The method according to claim 4, characterized in that, The method also includes a shielding module, and after the connection status detection module generates a trigger signal, the method further includes: The shielding module emits a shielding signal to shield signals other than those generated during aging tests.

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