Array substrate, array substrate mother board and display device

Abstract

An array substrate includes: a substrate, at least one first trace, and at least one second trace. The substrate includes: a display area and a first peripheral area located on one side of the display area. The first peripheral area includes at least: a first trace area and a first bonding area; the first trace area is located on the side of the first bonding area near the edge of the array substrate. At least one first trace and at least one second trace are located in the first trace area. The orthographic projections of the first trace and the second trace on the substrate overlap. Each first trace includes: at least two sub-traces. The two sub-traces of each first trace are electrically connected through at least one first connection electrode. The first connection electrode is made of a transparent conductive material.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to an array substrate, an array substrate motherboard, and a display device. Background Technology

[0002] Liquid crystal display (LCD) devices have advantages such as low power consumption and no radiation. An LCD device typically includes a liquid crystal panel, which comprises an array substrate, a color filter substrate, and a liquid crystal layer sandwiched between the two. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides an array substrate, an array substrate motherboard, and a display device.

[0005] In one aspect, embodiments of this disclosure provide an array substrate, including: a substrate, at least one first trace, and at least one second trace. The substrate includes: a display area and a first peripheral area located on one side of the display area. The first peripheral area includes at least: a first trace area and a first bonding area; the first trace area is located on the side of the first bonding area near the edge of the array substrate. At least one first trace and at least one second trace are located in the first trace area. The orthographic projection of the first trace onto the substrate overlaps with the orthographic projection of the second trace onto the substrate. Each first trace includes: at least two sub-traces. The two sub-traces of each first trace are electrically connected through at least one first connection electrode. The first connection electrode is made of a transparent conductive material.

[0006] In some exemplary embodiments, the orthographic projection of the first connection electrode on the substrate does not overlap with the orthographic projection of the second trace on the substrate.

[0007] In some exemplary embodiments, the second trace is made of a metallic material, and the orthographic projection of the first connection electrode on the substrate is located on the side of the orthographic projection of the second trace on the substrate that is away from the first bonding region.

[0008] In some exemplary embodiments, the second trace is made of a transparent conductive material.

[0009] In some exemplary embodiments, the first trace includes a first sub-trace and a second sub-trace, which are electrically connected via two first connection electrodes. The first sub-trace has a first body and a first protrusion and a second protrusion protruding from the first body toward the second sub-trace. The second sub-trace has a second body and a third protrusion and a fourth protrusion protruding from the second body toward the first sub-trace. The first and third protrusions are electrically connected via one first connection electrode, and the second and fourth protrusions are electrically connected via another first connection electrode. The two first connection electrodes do not overlap in their orthographic projections onto the substrate.

[0010] In some exemplary embodiments, the first trace includes a first sub-trace, a second sub-trace, and a third sub-trace, wherein the first sub-trace and the second sub-trace are electrically connected through a first connection electrode, and the second sub-trace and the third sub-trace are electrically connected through another first connection electrode.

[0011] In some exemplary embodiments, a plurality of first connection electrodes connected to different first traces are aligned in a second direction.

[0012] In some exemplary embodiments, the first bonding area is provided with at least one third trace, and the at least one first trace and the at least one third trace are electrically connected through at least one second connection electrode; the second connection electrode is made of a transparent conductive material.

[0013] In some exemplary embodiments, the second connection electrode is located on the side of the first connection electrode away from the substrate.

[0014] In some exemplary embodiments, the first bonding area is further provided with at least one first bonding pin, and the at least one third trace is electrically connected to the driver chip through the at least one first bonding pin.

[0015] In some exemplary embodiments, the first peripheral area further includes a second bonding area located on the side of the first bonding area away from the display area, the second bonding area being provided with a plurality of third bonding pins, and the second trace extending to the third bonding area and electrically connected to at least one third bonding pin.

[0016] In some exemplary embodiments, in a direction perpendicular to the array substrate, the array substrate includes: a first conductive layer, a first insulating layer, a semiconductor layer, a first transparent conductive layer, a second conductive layer, a second insulating layer, and a second transparent conductive layer sequentially disposed on the substrate. The sub-trace is located on the second conductive layer; the first connection electrode is located on the first transparent conductive layer.

[0017] In some exemplary embodiments, the second trace is located in the first conductive layer or the second transparent conductive layer.

[0018] In some exemplary embodiments, the second insulating layer is provided with an isolation groove, the orthographic projection of the isolation groove on the substrate overlaps with the orthographic projection of the first connecting electrode on the substrate, and the orthographic projection of the isolation groove on the substrate does not overlap with the orthographic projections of the first trace and the second trace on the substrate.

[0019] On the other hand, embodiments of this disclosure provide a display device including an array substrate as described above.

[0020] On the other hand, embodiments of this disclosure provide an array substrate motherboard, including: a plurality of array regions and a plurality of test electrode regions corresponding one-to-one with the plurality of array regions. Each array region includes: a display area and a first peripheral region located on one side of the display area. The first peripheral region includes at least a first wiring area and a first bonding area, the first wiring area being located on the side of the first bonding area closer to the test electrode region. At least one test electrode is located in the test electrode region. At least one first wiring and at least one second wiring are located in the first wiring area. At least one second wiring is electrically connected to at least one test electrode in the test electrode region, and the at least one second wiring extends from the first wiring area to the first bonding area. The orthographic projection of the first wiring on the substrate overlaps with the orthographic projection of the second wiring on the substrate. Each second wiring includes: at least two sub-wirings. The two sub-wirings in each second wiring are electrically connected through at least one first connection electrode. The first connection electrode is made of a transparent conductive material.

[0021] In some exemplary embodiments, the test electrode area is provided with a plurality of test electrodes arranged in a regular manner, and the first trace area is provided with a plurality of first traces, which are electrically connected to the plurality of test electrodes one by one.

[0022] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0023] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0024] Figure 1 This is a schematic diagram of an array substrate according to at least one embodiment of the present disclosure;

[0025] Figure 2This is a partial cross-sectional schematic diagram of the display area of ​​an array substrate according to at least one embodiment of the present disclosure;

[0026] Figure 3 for Figure 1 A partial schematic diagram of the central region S1;

[0027] Figure 4 for Figure 3 A partial cross-sectional view along the P-P' direction;

[0028] Figure 5 for Figure 3 A partially enlarged schematic diagram of the first binding area is shown below;

[0029] Figure 6 for Figure 5 A partial cross-sectional view along the Q-Q' direction;

[0030] Figure 7 This is a partial schematic diagram of an array substrate motherboard according to at least one embodiment of the present disclosure;

[0031] Figure 8 for Figure 1 Another partial schematic diagram of the central region S1;

[0032] Figure 9 for Figure 8 Enlarged schematic diagram of the middle region S2;

[0033] Figure 10 for Figure 1 Another partial schematic diagram of the central region S1;

[0034] Figure 11 for Figure 10 A partial cross-sectional view along the R-R' direction;

[0035] Figure 12 for Figure 1 Another partial schematic diagram of the central region S1;

[0036] Figure 13 for Figure 12 A partial cross-sectional view along the V-V' direction;

[0037] Figure 14 for Figure 1 Another partial schematic diagram of the central region S1;

[0038] Figure 15 for Figure 14 A partial cross-sectional view along the U-U' direction;

[0039] Figure 16 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0040] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0041] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0042] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0043] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0044] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0045] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0046] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0047] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0048] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0049] In this disclosure, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "roughly the same" means that the values ​​differ by no more than 10%.

[0050] As people increasingly value improving their physical fitness through exercise, smart wearable products are gaining popularity. These products (such as smartwatches and fitness trackers) not only offer traditional timekeeping functions but also integrate features like alarms, photography, heart rate monitoring, exercise data statistics, and activity status tracking. With this growing appreciation for smart wearables, consumers are not only demanding integrated functions but also paying closer attention to their aesthetic design. For example, smartwatches have evolved from rounded corners to perfectly round designs. Furthermore, the bottom bezels of perfectly round smart wearables are extremely narrow, often less than 2.5 millimeters (mm). With the bottom bezel narrowing, the test electrodes for the display panel cannot be placed inside the display panel and must be placed outside. As a result, the test traces need to cross the cut line of the display panel, exposing the test traces at the cut line location. Since the test traces exposed by the cut line cannot be coated with adhesive, the broken ends of the test traces at the cut line location are easily corroded during reliability high temperature and humidity tests (e.g., temperature of 60°C and humidity of 90%). Moreover, moisture can enter the display panel along the test traces and corrode the internal traces of the display panel.

[0051] This disclosure provides an array substrate, including: a substrate, at least one first trace, and at least one second trace. The substrate includes a display area and a first peripheral area located on one side of the display area. The first peripheral area includes at least: a first trace area and a first bonding area. The first trace area is located on the side of the first bonding area near the edge of the array substrate. At least one first trace and at least one second trace are located in the first trace area. The orthographic projection of the first trace onto the substrate overlaps with the orthographic projection of the second trace onto the substrate. Each first trace includes at least two sub-traces. The two sub-traces of each first trace are electrically connected through at least one first connection electrode. The first connection electrode is made of a transparent conductive material.

[0052] In some examples, the first trace is configured as a test trace for transmitting test signals, and the second trace is configured as a ground connection for transmitting ground signals. However, this embodiment is not limited to this.

[0053] The array substrate provided in this embodiment uses a first connecting electrode made of transparent conductive material to jumper the first trace, forming a moisture isolation channel. This can prevent moisture from entering the interior of the array substrate from the edge of the first trace, thereby improving the trace corrosion in the reliability high temperature and high humidity test.

[0054] In some exemplary embodiments, the orthographic projection of the first connection electrode onto the substrate does not overlap with the orthographic projection of the second trace onto the substrate. This example avoids the situation where the first connection electrode burns out due to excessive trace current in the second trace when the orthographic projections of the first connection electrode and the second trace overlap.

[0055] In some exemplary embodiments, the second trace is made of a metallic material, and the orthographic projection of the first connection electrode onto the substrate is located on the side of the second trace's orthographic projection onto the substrate away from the first bonding region. For example, the second trace can be located on the side of the first trace closer to the substrate. In this example, because the second trace is made of a metallic material, by setting the first connection electrode on the side of the second trace near the edge of the array substrate to form a moisture isolation channel, corrosion of the second trace can be avoided, thereby improving the trace corrosion situation present in the reliability high temperature and high humidity test.

[0056] In some exemplary embodiments, the second trace is made of a transparent conductive material. In some examples, the material of the second trace can be indium tin oxide (ITO). Due to the low reactivity of ITO, it is less prone to corrosion during reliability high-temperature and high-humidity testing, which can improve the trace corrosion situation present in reliability high-temperature and high-humidity testing. For example, the second trace can be located on the side of the first connection electrode and the first trace away from the substrate. In this example, the orthographic projection of the first connection electrode on the substrate can be located on the side of the second trace on the substrate away from the first bonding region, or closer to the first bonding region. However, this embodiment is not limited to this.

[0057] In some exemplary embodiments, the first trace may include a first sub-trace and a second sub-trace, which are electrically connected via two first connection electrodes. The first sub-trace has a first body and a first protrusion and a second protrusion extending from the first body toward the second sub-trace. The second sub-trace has a second body and a third protrusion and a fourth protrusion extending from the second body toward the first sub-trace. The first and third protrusions are electrically connected via one first connection electrode, and the second and fourth protrusions are electrically connected via another first connection electrode. The orthographic projections of the two first connection electrodes onto the substrate do not overlap. In this example, establishing two parallel transmission channels between the first traces via the two first connection electrodes can reduce the risk of trace burn-out.

[0058] In some exemplary embodiments, the first trace may include a first sub-trace, a second sub-trace, and a third sub-trace. The first and second sub-traces are electrically connected via a first connection electrode, and the second and third sub-traces are electrically connected via another first connection electrode. In this example, two moisture isolation channels can be formed on the second trace via two first connection electrodes, which can further prevent moisture from entering the array substrate along the first trace.

[0059] In some exemplary embodiments, multiple first connection electrodes connected to different first traces are aligned in a second direction. In this example, the multiple first connection electrodes are arranged continuously in one direction, which can form a moisture barrier channel to prevent corrosion of the traces.

[0060] In some exemplary embodiments, the first bonding region is provided with at least one third trace, and at least one first trace and at least one third trace are electrically connected through at least one second connection electrode. The second connection electrode is made of a transparent conductive material. In some examples, the second connection electrode may be located on the side of the first trace and the third trace away from the substrate. In this example, using the second connection electrode to establish a jumper channel between the first trace and the third trace can further isolate moisture and prevent corrosion of the internal traces of the array substrate.

[0061] In some exemplary embodiments, the first bonding area is further provided with at least one first bonding pin, and at least one third trace is electrically connected to the driver chip through at least one first bonding pin. In some examples, when the array substrate is not bonded to the driver chip, the first trace can transmit test signals to the third trace to enable testing of the array substrate. After the array substrate is cut with the first trace and the driver chip is bonded, signals are transmitted to the third trace through the driver chip.

[0062] In some exemplary embodiments, the first peripheral region further includes a second bonding region located on the side of the first bonding region away from the display area. The second bonding region is provided with a plurality of third bonding pins, and a second trace extends into the third bonding region and is electrically connected to at least one third bonding pin. For example, the third bonding pin electrically connected to the second trace is a ground pin.

[0063] In some exemplary embodiments, in a direction perpendicular to the array substrate, the array substrate includes: a first conductive layer, a first insulating layer, a semiconductor layer, a first transparent conductive layer, a second conductive layer, a second insulating layer, and a second transparent conductive layer sequentially disposed on a substrate. Sub-traces are located on the second conductive layer; first connection electrodes are located on the first transparent conductive layer. In some examples, the second trace may be located on either the first conductive layer or the second transparent conductive layer. However, this embodiment is not limited to this.

[0064] In some exemplary embodiments, the second insulating layer is provided with an isolation trench. The orthographic projection of the isolation trench onto the substrate overlaps with the orthographic projection of the first connecting electrode onto the substrate, but the orthographic projection of the isolation trench onto the substrate does not overlap with the orthographic projections of the first trace and the second trace onto the substrate. In this example, by forming an isolation trench in the second insulating layer, moisture can be better prevented from entering the interior of the array substrate.

[0065] The following examples illustrate the solution of this embodiment.

[0066] In some exemplary embodiments, the array substrate of this embodiment can be an LCD array substrate. After assembling the array substrate and the color filter substrate, filling the space between them with a liquid crystal layer can create an LCD display panel. An electric field drives the liquid crystal molecules to twist, allowing light to selectively pass through and display images of different grayscale levels. The electric field driving the twisting of the liquid crystal molecules is formed between the pixel electrode and the common electrode. In some examples, the pixel electrode and the common electrode can both be disposed on the array substrate; for example, the pixel electrode and the common electrode can be disposed in the same layer or in different layers. However, this embodiment is not limited to this.

[0067] Figure 1 This is a schematic diagram of an array substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as Figure 1 As shown, the array substrate includes: a display area AA, a first peripheral area B1 located on one side of the display area AA, and a second peripheral area B2 located on the side of the display area AA away from the first peripheral area B1. For example, the first peripheral area B1 is located on one side of the display area AA along a second direction Y. The first peripheral area B1 and the second peripheral area B2 are connected and surround the display area AA. In some examples, the display area AA can be circular or elliptical. The first peripheral area B1 and the second peripheral area B2 can form a ring or an elliptical ring around the display area AA. However, this embodiment is not limited to this. For example, the display area AA can be rectangular or other shapes.

[0068] In some exemplary embodiments, the display area AA is provided with multiple gate lines and multiple data lines. These gate lines and data lines can intersect to define multiple sub-pixel areas. Each sub-pixel area is provided with a pixel electrode, a common electrode, and a pixel circuit connected to the pixel electrode. The pixel circuit may include at least one thin-film transistor (TFT). For example, the drain electrode of the TFT may be electrically connected to the pixel electrode, the source electrode may be electrically connected to the data line, and the gate electrode may be electrically connected to the gate line. The scanning signal transmitted through the gate line controls the switching on and off of the TFT, and the pixel voltage transmitted on the data line is output to the pixel electrode through a driving circuit. The common electrode is connected to a common voltage line. An electric field is formed between the pixel electrode and the common electrode to drive the deflection of liquid crystal molecules, thereby achieving the display of a specific grayscale level.

[0069] Figure 2 This is a partial cross-sectional schematic diagram of the display area according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 2As shown, in a direction perpendicular to the array substrate, the display area AA may include: a substrate 10, a first conductive layer, a first insulating layer 11, a semiconductor layer, a first transparent conductive layer, a second conductive layer, a second insulating layer 12, and a second transparent conductive layer sequentially disposed on the substrate 10. In some examples, the first conductive layer includes at least the gate electrode 141 of the thin-film transistor of the pixel circuit. The semiconductor layer includes at least the active layer 142 of the thin-film transistor of the pixel circuit. The second conductive layer includes at least the source electrode 143 and the drain electrode 144 of the thin-film transistor of the pixel circuit. The first transparent conductive layer includes at least the pixel electrode 16, and the second transparent conductive layer includes at least the common electrode 18. The pixel electrode 16 and the drain electrode 144 of the thin-film transistor of the pixel circuit are in direct contact. The common electrode 18 may have multiple slits.

[0070] In some exemplary embodiments, the substrate 10 can be a transparent substrate, such as a quartz substrate, a glass substrate, or an organic resin substrate. The first insulating layer 11 and the second insulating layer 12 can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or composite layers. The first insulating layer 11 is also referred to as a gate insulator (GI) layer; the second insulating layer 12 is also referred to as a passivation layer. The first conductive layer and the second conductive layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The first transparent conductive layer and the second transparent conductive layer can be made of transparent conductive materials, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The semiconductor layer can be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. In other words, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0071] In some exemplary implementations, such as Figure 1 As shown, the first peripheral region B1 of the array substrate is approximately symmetrical about the centerline O of the array substrate in the first direction X. The first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y. The following description takes the first peripheral region B1 to the left of the centerline O as an example.

[0072] Figure 3 for Figure 1 A partial schematic diagram of the central region S1. In some exemplary embodiments, such as... Figure 3 As shown, the first peripheral region B1 includes a first trace area, a first bonding area B11, and a second bonding area B12. The second bonding area B12 is located on the side of the first bonding area B11 away from the display area AA. The first trace area is located on the side of the first bonding area B11 closer to the edge E of the array substrate. The first bonding area B11 may house a driver chip, and the second bonding area B12 may be connected to a flexible printed circuit (FPC). In some examples, the driver chip may be configured to provide data signals and control signals for the gate drive circuit. The FPC may be configured to provide drive signals, power signals, etc., required for module testing of the display panel subsequently assembled from the array substrate. However, this embodiment is not limited to this.

[0073] In some exemplary implementations, such as Figure 3 As shown, the first trace area is provided with multiple first traces 21 (e.g., twelve first traces). The multiple first traces 21 can be configured to provide test data signals, test switch signals, and test signals (e.g., test clock signals, test start signals, and test power signals) to the gate drive circuit. The multiple first traces 21 extend from the edge E of the array substrate along the first direction X to the first bonding area B11, and are electrically connected to multiple third traces 25 in the first bonding area B11 via second connection electrodes 26. For example, the multiple first traces 21 and the multiple third traces 25 can be electrically connected one-to-one. The multiple third traces 25 extend from the first bonding area B11 towards the display area AA. For example, the multiple third traces 25 can extend to the second peripheral area and be electrically connected to the gate drive circuit disposed in the second peripheral area. The multiple third traces 25 can be configured to provide clock signals, start signals, and power signals to the gate drive circuit. However, this embodiment is not limited in this respect.

[0074] In some exemplary implementations, such as Figure 3 As shown, the first trace area is further provided with a second trace 23. The second trace 23 extends along the second direction Y in the first trace area. The extension direction of the second trace 23 intersects the extension directions of the plurality of first traces 21. The orthographic projection of the second trace 23 onto the substrate overlaps with the orthographic projection of the plurality of first traces 21 onto the substrate. In some examples, the plurality of first traces 21 are disposed on the same layer, and the second trace 23 is located on the side of the plurality of first traces 21 closer to the substrate.

[0075] In some exemplary implementations, such as Figure 3As shown, in the second direction Y, a third connection electrode 24 is provided on the side of the first trace area away from the bonding area B12. The third connection electrode 24 is located on the side of the first trace area closer to the display area. The third connection electrode 24 may include a first sub-connection electrode and a second sub-connection electrode, which are electrically connected. The orthographic projection of the first sub-connection electrode onto the substrate and the orthographic projection of the second sub-connection electrode onto the substrate may overlap, for example, coincide. In some examples, the first sub-connection electrode may be located in the first conductive layer, and the second connection electrode may be located in the second transparent conductive layer. A first via K1 is formed on the second insulating layer, and the first and second insulating layers within the first via K1 are removed. The second sub-connection electrode is electrically connected to the first sub-connection electrode through the first via K1. In this example, one end of the second trace 23 is connected to the first connection electrode, and the other end passes through multiple first traces 21, extends to the second bonding area B12, and is electrically connected to a third bonding pin (e.g., a ground pin) of the second bonding area B12. In some examples, the second trace 23 and the first sub-connection electrode may be an integral structure. However, this embodiment is not limited in this respect.

[0076] In some exemplary embodiments, when the array substrate and the color filter substrate are assembled together, conductive adhesive (e.g., conductive silver paste) can be applied to the third connection electrode 24 of the array substrate to facilitate electrical connection with the color filter substrate. The third connection electrode 24 and the second trace 23 can form an electrostatic discharge path, thereby achieving electrostatic elimination.

[0077] Figure 4 for Figure 3 A partial cross-sectional view along the P-P' direction. In some exemplary embodiments, a first trace 21 is used as an example for illustration. Figure 3 and Figure 4 As shown, a first trace 21 may include a first sub-trace 211 and a second sub-trace 212. The first sub-trace 211 and the second sub-trace 212 may extend generally along a first direction X. During the fabrication of the array substrate, the first sub-trace 211 is cut off at the edge E of the array substrate. In the first trace region, the first sub-trace 211 and the second sub-trace 212 of the first trace 21 are electrically connected through a first connection electrode 22.

[0078] In some exemplary implementations, such as Figure 4As shown, a first sub-trace 211 and a second sub-trace 212 of a first trace 21 can be located in the second conductive layer, and a first connecting electrode 22 can be located in the first transparent conductive layer. A second trace 23 can be located in the first conductive layer. In this example, the first connecting electrode 22 is made of a transparent conductive material (e.g., ITO), and the first sub-trace 211 and the second sub-trace 212 are made of metallic materials. Because transparent conductive materials have low activity, they are not prone to corrosion during reliability high-temperature and high-humidity tests. Therefore, a moisture isolation channel can be established through the first connecting electrode to prevent moisture from entering the array substrate through the first sub-trace 211 and corroding the second sub-trace 212. In this example, the first connecting electrode is located in the first transparent conductive layer and can directly contact the second conductive layer to achieve electrical connection with the first trace without the need for a drilling process; moreover, it can avoid short circuits with the second sub-connecting electrode located in the second transparent conductive layer during the adhesive coating process.

[0079] In some exemplary implementations, such as Figure 3 and Figure 4 As shown, the orthographic projection of the first connecting electrode 22 onto the substrate does not overlap with the orthographic projection of the second trace 23 onto the substrate. The orthographic projection of the first connecting electrode 22 onto the substrate is located on the side of the second trace 23 away from the first bonding region B11. In this example, the moisture isolation channel established by the first connecting electrode 22 can prevent corrosion of the second trace 23. Moreover, the fact that the orthographic projections of the first connecting electrode 22 and the second trace 23 onto the substrate do not overlap can prevent the first connecting electrode 22 from burning out when the current in the second trace 23 is too high.

[0080] In some exemplary implementations, such as Figure 3 As shown, each first trace 21 connects to a first connection electrode 22. Multiple first connection electrodes 22 connected by multiple first traces 21 are arranged sequentially along the second direction Y, and the multiple first connection electrodes 22 are aligned in the second direction Y. The arrangement direction of the multiple first connection electrodes 22 is approximately parallel to the second direction Y. However, this embodiment is not limited in this respect.

[0081] In some exemplary implementations, such as Figure 3As shown, the length of the first connecting electrode 22 along the first direction X can be greater than or equal to 20 micrometers and less than or equal to 200 micrometers. For example, the length of the first connecting electrode 22 can be approximately 40 μm to 80 μm, such as 40 μm or 50 μm. However, this embodiment is not limited to this. In this example, since the first connecting electrode is made of a transparent conductive material, and the resistance of a transparent conductive material is relatively high, limiting the length of the first connecting electrode 22 can avoid the situation where the first trace is burned out due to excessive resistance, thereby improving the detection accuracy of the array substrate. In some examples, the lengths of multiple first connecting electrodes 22 along the first direction X can be approximately the same, or partially the same, or different. However, this embodiment is not limited to this.

[0082] In some exemplary implementations, such as Figure 3 As shown, the orthographic projection of the first connecting electrode 22 onto the substrate can be rectangular. However, this embodiment is not limited to this. For example, the orthographic projection of the first connecting electrode onto the substrate can be wavy or other shapes.

[0083] Figure 5 for Figure 3 A partially enlarged schematic diagram of the first binding area is shown. Figure 6 for Figure 5 A partial cross-sectional view along the Q-Q' direction.

[0084] In some exemplary implementations, such as Figure 3 and Figure 5 As shown, the first bonding area B11 is provided with a plurality of first bonding pins 31 and a plurality of second bonding pins 33. The plurality of first bonding pins 31 are arranged sequentially along a first direction X, and the plurality of second bonding pins 33 are arranged sequentially along the first direction X. For example, the plurality of first bonding pins 31 are arranged in one row, and the plurality of second bonding pins 33 are arranged in one row. The plurality of second bonding pins 33 are located on the side of the first bonding pins 31 away from the display area. In some examples, the plurality of first bonding pins 31 are located in a second conductive layer, and a third trace 25 is electrically connected to at least one first bonding pin 31. For example, a third trace 25 can be electrically connected to two first bonding pins 31. The third trace 25 can be electrically connected to the driver chip through the first bonding pins 31. The plurality of second bonding pins 32 can be a double-layer structure, and at least one second bonding pin 32 can include a first sub-pin located in the first conductive layer and a second sub-pin located in the second transparent conductive layer. The second bonding pins 32 can be electrically connected to the driver chip. The driver chip can provide gate drive signals (e.g., including clock signals, power signals, start signals, etc.) through the first bonding pins 31 and the second bonding pins 32.

[0085] In some exemplary implementations, such as Figure 3 and Figure 5 As shown, the second sub-trace 212 of the first trace 21 extends to the first bonding area B11 and is electrically connected to the third trace 25 via the second connecting electrode 26. Multiple first traces 21 and multiple third traces 25 can be electrically connected in a one-to-one correspondence. For example, the first trace 21 extends along the first direction X, and the third trace 25 can extend along the second direction Y towards the display area AA.

[0086] In some exemplary implementations, such as Figure 6 As shown, the first trace 21 can be located in the second conductive layer, and the third trace 25 can be located in the first conductive layer. The second connecting electrode 26 can be located in the second transparent conductive layer. One end of the second connecting electrode 26 is electrically connected to the first trace 21 through a via formed in the second insulating layer 12, and the other end is electrically connected to the third trace 25 through vias formed in the second insulating layer 12 and the first insulating layer 11. In this example, by using the second connecting electrode located in the second transparent conductive layer to design jumpers for the first and third traces, moisture intrusion can be further prevented.

[0087] In some exemplary implementations, such as Figure 3 As shown, the second bonding region B12 is provided with a plurality of third bonding pins 33. The plurality of third bonding pins 33 are arranged sequentially along a first direction X, for example, the plurality of third bonding pins 33 are arranged in a row. The second trace 23 can extend to the second bonding region B12 and be electrically connected to one of the third bonding pins 33 (e.g., a ground pin) to achieve grounding. At least one third bonding pin 33 can be a double-layer structure; for example, at least one third bonding pin can include a third sub-pin located in the first conductive layer and a fourth sub-pin located in the second transparent conductive layer. The third sub-pin and the fourth sub-pin are electrically connected, and the orthographic projection of the third sub-pin onto the substrate overlaps with the orthographic projection of the fourth sub-pin onto the substrate. The third bonding pin 33 can be electrically connected to the FPC.

[0088] Figure 7This is a partial schematic diagram of an array substrate motherboard according to at least one embodiment of the present disclosure. In some exemplary embodiments, during the fabrication of the array substrate, an array substrate motherboard is first formed, and then multiple array substrates are obtained by cutting the array substrate motherboard. In some examples, the array substrate motherboard includes: multiple array regions and multiple test electrode regions C1 corresponding to each of the multiple array regions. The array region may include: a display area and a first peripheral region located on one side of the display area, the first peripheral region including at least a first wiring area and a first bonding area, the first wiring area being located on the side of the first bonding area B11 close to the test electrode region C1. After the fabrication of the array substrate motherboard is completed, the circuit of the array region is tested using the test electrode regions. After the test is completed, the test electrode region C1 can be cut off according to the cutting line CT to obtain the array substrate. In some examples, the test electrode regions can be used to perform electrical and optical tests on the array substrate, for example, to detect whether there is display defect in a solid color image. However, this embodiment is not limited to this.

[0089] In some exemplary implementations, such as Figure 7 As shown, the test electrode area C1 is provided with multiple test electrodes 30. These multiple test electrodes 30 can be arranged in a regular pattern. However, this embodiment does not limit this arrangement.

[0090] In some exemplary implementations, such as Figure 7 As shown, multiple test electrodes 30 are connected one-to-one with multiple first traces 21. The multiple first traces 21 can extend from the first trace area of ​​the array region to the test electrode area C1 and be electrically connected to the test electrodes 30. In some examples, the test electrodes 30 can be a double-layer structure. For example, the test electrodes 30 may include a first sub-test electrode located in the second conductive layer and a second sub-test electrode located in the second transparent conductive layer. The first sub-test electrode and the second sub-test electrode can be electrically connected through a second via K2 opened in the second insulating layer. The orthographic projections of the first sub-test electrode and the second sub-test electrode onto the substrate may overlap, for example, coincide. However, this embodiment is not limited to this.

[0091] For a description of the array area of ​​the array substrate motherboard in this embodiment, please refer to the description of the array substrate above, and therefore it will not be repeated here.

[0092] Figure 8 for Figure 1 Another partial schematic diagram of the central region S1. Figure 9 for Figure 8 A magnified schematic diagram of the central region S2. Figure 8 The first binding area is omitted.

[0093] In some exemplary implementations, such as Figure 8As shown, the first trace area of ​​the first peripheral region is provided with a second trace 23 and multiple first traces 21 (e.g., ten first traces). At least one first trace 21 may include a first sub-trace 211 and a second sub-trace 212. The first sub-trace 211 can be electrically connected to the second sub-trace 212 through two first connection electrodes. The orthographic projection of the first connection electrode on the substrate does not overlap with the orthographic projection of the second trace 23 on the substrate, and is located on the side of the second trace 23 away from the first bonding region B11, that is, on the side of the second trace 23 closer to the edge E of the array substrate.

[0094] In some exemplary implementations, such as Figure 9 As shown, the first sub-trace 211 includes a first body 211c, a first protrusion 211a and a second protrusion 211b protruding from the first body 211c toward the second sub-trace 212. The first protrusion 211a and the second protrusion 211b are not connected, that is, there is a recess between the first protrusion 211a and the second protrusion 211b. The second sub-trace 212 includes a second body 212c, a third protrusion 212a and a fourth protrusion 212b protruding from the second body 212c toward the first sub-trace 211. The third protrusion 212a and the fourth protrusion 212b are not connected, that is, there is a recess between the third protrusion 212a and the fourth protrusion 212b. A first connecting electrode 22a connects the first protrusion 211a and the third protrusion 212a, and a first connecting electrode 22b connects the second protrusion 211b and the fourth protrusion 212b. In some examples, the orthographic projection of the first connecting electrode 22a onto the substrate overlaps with the orthographic projections of the first protrusion 211a and the third protrusion 212a onto the substrate, and the orthographic projection of the first connecting electrode 22b onto the substrate overlaps with the orthographic projections of the second protrusion 211b and the fourth protrusion 212b onto the substrate. However, this embodiment is not limited to this. In this example, by using two first connecting electrodes to establish two parallel transmission channels on a first trace, the risk of burn-out of the first connecting electrodes can be reduced.

[0095] In some exemplary implementations, such as Figure 8 As shown, some of the multiple first traces (e.g., seven first traces) can be designed as dual-transmission channels, while the remaining first traces (e.g., three first traces) can be designed as single-transmission channels. For example, a dual-transmission channel design can be used for first traces transmitting high-current signals (e.g., clock signals, high-potential signals, etc.) to reduce the risk of burn-out of the first connection electrode. However, this embodiment is not limited to this.

[0096] In some exemplary implementations, such as Figure 8As shown, the first trace 21 can be located in the second conductive layer, the first connecting electrode can be located in the first transparent conductive layer, and the second trace 23 can be located in the first conductive layer. The remaining structure of the array substrate in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0097] Figure 10 for Figure 1 Another partial schematic diagram of the central region S1. Figure 11 for Figure 10 A partial cross-sectional view along the R-R' direction. Figure 10 The first binding area is omitted in the diagram.

[0098] In some exemplary implementations, such as Figure 10 and Figure 11 As shown, the second trace 23 can be located in the second transparent conductive layer. The orthographic projection of the first connection electrode 22a onto the substrate is located on the side of the second trace 23 closer to the first bonding region. In this example, the second trace 23 is located in the second transparent conductive layer, which can prevent the first trace from burning out due to excessive current when the second trace 23 transmits static electricity. Moreover, since the second transparent conductive layer is made of a transparent conductive material, the transparent conductive material has low activity and is not prone to corrosion during reliability high temperature and high humidity tests. Even if the first connection electrode is placed on the side of the second trace 23 closer to the first bonding region, moisture can still be prevented from entering the internal trace. In some other exemplary embodiments, the orthographic projection of the first connection electrode onto the substrate can be located on the side of the second trace 23 on the substrate closer to the first bonding region.

[0099] The remaining structure of the array substrate in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0100] Figure 12 for Figure 1 Another partial schematic diagram of the central region S1. Figure 13 for Figure 12 A partial cross-sectional view along the V-V' direction. Figure 12 The first binding area is omitted in the diagram.

[0101] In some exemplary implementations, such as Figure 12 and Figure 13As shown, the first trace 21 may include a first sub-trace 211, a second sub-trace 212, and a third sub-trace 213. The first sub-trace 211 and the second sub-trace 212 are electrically connected via a first connecting electrode 22a, and the second sub-trace 212 and the third sub-trace 213 are electrically connected via a first connecting electrode 22b. The orthographic projections of the first connecting electrodes 22a and 22b onto the substrate do not overlap with the orthographic projection of the second trace 23 onto the substrate, and are located on the side of the second trace 23 closest to the edge E of the array substrate. In this example, the second trace 23 may be located in the first conductive layer. The first trace 21 may be located in the second conductive layer, and the first connecting electrodes 22a and 22b may be located in the first transparent conductive layer.

[0102] In some exemplary implementations, such as Figure 12 As shown, multiple first connecting electrodes 22a are arranged sequentially along the second direction Y, and may be aligned without misalignment in the first direction X, thereby forming a first moisture barrier channel. Multiple first connecting electrodes 22b are arranged sequentially along the second direction Y, and may be aligned without misalignment in the first direction X, thereby forming a second moisture barrier channel. The second sub-trace 212 between the first and second moisture barrier channels can serve as a corrosion zone, thereby better preventing moisture from entering the internal traces.

[0103] In other examples, the second trace 23 may be located in the second transparent conductive layer, in which case the first moisture barrier channel and the second moisture barrier channel may be located on opposite sides of the second trace 23 in the first direction X, or they may be located on the side of the second trace 23 closer to the first bonding area. However, this embodiment is not limited to this.

[0104] The remaining structure of the array substrate in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0105] Figure 14 for Figure 1 Another partial schematic diagram of the central region S1. Figure 15 for Figure 14 A partial cross-sectional view along the U-U' direction. Figure 14 The first binding area is omitted in the diagram.

[0106] In some exemplary implementations, such as Figure 14 and Figure 15As shown, the second insulating layer 12 is provided with an isolation trench OP. The orthographic projection of the isolation trench OP onto the substrate overlaps with the orthographic projection of the first connecting electrode 22 onto the substrate. The isolation trench OP can expose at least a portion of the first connecting electrode 22. The orthographic projection of the isolation trench OP onto the substrate does not overlap with the orthographic projections of the second trace 23 and the first trace 21 onto the substrate. In some examples, the isolation trench OP can be formed around the edge of the array substrate. In this example, by forming the isolation trench OP at the location of the first connecting electrode 22, an isolation band can be formed using the isolation trench OP, confining the first sub-trace 211 to one side of the isolation band, thereby better preventing the entry of moisture.

[0107] In some examples, the width of the isolation trench OP may be less than the length of the first connection electrode 22 not covered by the second conductive layer along the first direction X.

[0108] The remaining structure of the array substrate in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0109] This embodiment also provides an array substrate motherboard, including: multiple array regions and multiple test electrode regions corresponding one-to-one with the multiple array regions. Each array region includes: a display area and a first peripheral region located on one side of the display area. The first peripheral region includes at least a first wiring area and a first bonding area, the first wiring area being located on the side of the first bonding area closer to the test electrode region. At least one test electrode is located in the test electrode region. At least one first wiring and at least one second wiring are located in the first wiring area. At least one first wiring is electrically connected to at least one test electrode in the test electrode region, and at least one first wiring extends from the first wiring area to the first bonding area. The orthographic projection of the first wiring onto the substrate overlaps with the orthographic projection of the second wiring onto the substrate. Each first wiring includes: at least two sub-wirings. The two sub-wirings in each first wiring are electrically connected through at least one first connection electrode. The first connection electrode is made of a transparent conductive material.

[0110] In some exemplary embodiments, the test electrode area is provided with a plurality of test electrodes arranged in a regular manner, and the first trace area is provided with a plurality of first traces, which are electrically connected to the plurality of test electrodes one by one.

[0111] The description of the array substrate motherboard in this embodiment can be found in the description of the foregoing embodiment, and therefore will not be repeated here.

[0112] This disclosure also provides a display device, including the array substrate described above.

[0113] Figure 16 This is a schematic diagram of the structure of a display device according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 16As shown, the display device may include: an array substrate 61 and a color filter substrate 62 disposed opposite to each other, and a liquid crystal layer 63 filled between the array substrate 61 and the color filter substrate 62. In some examples, the display device of this embodiment may be a Fringe Field Switching (FFS) type or an Advanced-Super Dimension Switching (AD-SDS) type LCD display panel, wherein the pixel electrodes and common electrodes are both disposed on the array substrate and are disposed in different layers. The structure of the array substrate 61 can refer to the structure of the array substrate in the above embodiment, and therefore will not be described again here. The color filter substrate 62 may include a substrate, a color filter layer disposed on the substrate, and an alignment layer disposed on the side of the color filter layer away from the substrate. The color filter layer may include a plurality of color filter units of different colors and a black matrix located between the color filter units. However, this embodiment is not limited in this respect.

[0114] In some examples, the display device can be any product or component with display functionality, such as an LCD display panel, OLED display panel, mini-LED display panel, micro-LED display panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, in-vehicle display, watch, or wristband. However, this embodiment is not limited to this.

[0115] The accompanying drawings in this disclosure only illustrate the structures relevant to this disclosure; other structures can be referenced to common designs. Unless otherwise specified, embodiments of this disclosure, i.e., features within the embodiments, can be combined with each other to obtain new embodiments.

[0116] Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions disclosed herein without departing from the spirit and scope of the technical solutions disclosed herein, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. An array substrate, characterized in that, include: The substrate includes: a display area and a first peripheral area located on one side of the display area; the first peripheral area includes at least: a first wiring area and a first bonding area; the first wiring area is located on the side of the first bonding area near the edge of the array substrate; At least one first trace and at least one second trace are located in the first trace area; the orthographic projection of the first trace on the substrate and the orthographic projection of the second trace on the substrate overlap; the first trace extends from the edge of the array substrate to the first bonding area; the first trace is configured as a test trace for transmitting test signals, and the second trace is configured as a ground connection line for transmitting ground signals. Each first trace includes at least two sub-traces; the two sub-traces in each first trace are electrically connected through at least one first connection electrode; the first connection electrode is made of a transparent conductive material; The first trace includes: a first sub-trace and a second sub-trace, and the first sub-trace and the second sub-trace are electrically connected through two first connection electrodes. The first sub-trace has a first body, and a first protrusion and a second protrusion protruding from the first body toward the second sub-trace; The second sub-trace has a second body, and a third protrusion and a fourth protrusion protruding from the second body toward the first sub-trace; The first protrusion and the third protrusion are electrically connected by a first connecting electrode, and the second protrusion and the fourth protrusion are electrically connected by another first connecting electrode. The two first connecting electrodes do not overlap in their orthographic projections onto the substrate.

2. The array substrate according to claim 1, characterized in that, The orthographic projection of the first connecting electrode on the substrate does not overlap with the orthographic projection of the second trace on the substrate.

3. The array substrate according to claim 2, characterized in that, The second trace is made of metal, and the orthographic projection of the first connecting electrode on the substrate is located on the side of the orthographic projection of the second trace on the substrate that is away from the first bonding area.

4. The array substrate according to claim 2, characterized in that, The second trace is made of a transparent conductive material.

5. The array substrate according to claim 1, characterized in that, Multiple first connection electrodes connected to different first traces are aligned and arranged in a second direction.

6. The array substrate according to claim 1, characterized in that, The first binding area is provided with at least one third trace, and the at least one first trace and the at least one third trace are electrically connected through at least one second connecting electrode; the second connecting electrode is made of a transparent conductive material.

7. The array substrate according to claim 6, characterized in that, The second connection electrode is located on the side of the first connection electrode away from the substrate.

8. The array substrate according to claim 6, characterized in that, The first bonding area is further provided with at least one first bonding pin, and the at least one third trace is electrically connected to the driver chip through the at least one first bonding pin.

9. The array substrate according to claim 1, characterized in that, The first peripheral area further includes a second bonding area located on the side of the first bonding area away from the display area, the second bonding area being provided with a plurality of third bonding pins, and the second trace extending to the second bonding area and electrically connected to at least one third bonding pin.

10. The array substrate according to any one of claims 1 to 9, characterized in that, In a direction perpendicular to the array substrate, the array substrate includes: a first conductive layer, a first insulating layer, a semiconductor layer, a first transparent conductive layer, a second conductive layer, a second insulating layer, and a second transparent conductive layer sequentially disposed on the substrate. The sub-trace is located in the second conductive layer; the first connecting electrode is located in the first transparent conductive layer.

11. The array substrate according to claim 10, characterized in that, The second trace is located in the first conductive layer or the second transparent conductive layer.

12. The array substrate according to claim 10, characterized in that, The second insulating layer is provided with an isolation groove. The orthographic projection of the isolation groove on the substrate overlaps with the orthographic projection of the first connecting electrode on the substrate. The orthographic projection of the isolation groove on the substrate does not overlap with the orthographic projections of the first trace and the second trace on the substrate.

13. A display device, characterized in that, Includes the array substrate as described in any one of claims 1 to 12.

14. An array substrate mother plate, characterized in that, include: Multiple array regions and multiple test electrode regions corresponding one-to-one with the multiple array regions; Each array region includes: a display area and a first peripheral area located on one side of the display area, the first peripheral area including at least a first trace area and a first bonding area, the first trace area being located on the side of the first bonding area closer to the test electrode area; At least one test electrode is located in the test electrode region; At least one first trace and at least one second trace are located in the first trace area; the at least one first trace is electrically connected to at least one test electrode in the test electrode area, and the at least one first trace extends from the first trace area to the first bonding area; the orthographic projection of the first trace on the substrate overlaps with the orthographic projection of the second trace on the substrate; the first trace extends from the edge of the array substrate to the first bonding area; the first trace is configured as a test trace for transmitting test signals, and the second trace is configured as a ground connection line for transmitting ground signals; Each first trace includes at least two sub-traces; the two sub-traces in each first trace are electrically connected through at least one first connection electrode; the first connection electrode is made of a transparent conductive material; The first trace includes: a first sub-trace and a second sub-trace, and the first sub-trace and the second sub-trace are electrically connected through two first connection electrodes. The first sub-trace has a first body, and a first protrusion and a second protrusion protruding from the first body toward the second sub-trace; The second sub-trace has a second body, and a third protrusion and a fourth protrusion protruding from the second body toward the first sub-trace; The first protrusion and the third protrusion are electrically connected by a first connecting electrode, and the second protrusion and the fourth protrusion are electrically connected by another first connecting electrode. The two first connecting electrodes do not overlap in their orthographic projections onto the substrate.

15. The array substrate motherboard according to claim 14, characterized in that, The test electrode area is provided with a plurality of test electrodes arranged in a regular pattern, and the first trace area is provided with a plurality of first traces, which are electrically connected to the plurality of test electrodes one by one.

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