Array substrate and electronic paper

Abstract

The application provides an array substrate and electronic paper, and relates to the technical field of display, and aims to solve the problem that when the electronic paper is applied outdoors, the channel material of the transistor in the electronic paper will generate photo-generated carriers under strong outdoor light irradiation, Ioff is increased, pixel voltage cannot be maintained, and the display effect is affected. The array substrate comprises a substrate and a plurality of pixel driving units arranged on the substrate, wherein the pixel driving unit comprises a driving transistor and a pixel electrode coupled with each other, and the driving transistor comprises a channel portion; the array substrate further comprises a light shielding layer, at least part of the light shielding layer is located between the driving transistor and the pixel electrode, and the orthographic projection of the light shielding layer on the substrate at least partially overlaps with the orthographic projection of the channel portion on the substrate. The array substrate provided by the application is used for forming electronic paper.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to an array substrate and electronic paper. Background Technology

[0002] Electronic paper (ESL) display technology is widely used in display fields such as electronic price tags, electronic signage, and e-readers in supermarkets due to its advantages such as low cost and low power consumption.

[0003] However, the current applications of electronic paper are mainly limited to indoor settings. This is primarily because the channel material of the transistors in electronic paper generates photogenerated carriers when exposed to strong outdoor light, causing an increase in Ioff (inverting current), which in turn makes it impossible to maintain the pixel voltage and affects the display effect. Summary of the Invention

[0004] The purpose of this invention is to provide an array substrate and electronic paper to solve the problem that when electronic paper is used outdoors, the channel material of the transistors in the electronic paper generates photogenerated carriers under strong outdoor light, causing Ioff to increase, the pixel voltage cannot be maintained, and the display effect is affected.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A first aspect of the present invention provides an array substrate, comprising: a substrate and a plurality of pixel driving units disposed on the substrate, wherein each pixel driving unit includes a driving transistor and a pixel electrode coupled together, and the driving transistor includes a channel portion; the array substrate further comprises:

[0007] A light-shielding layer, at least a portion of which is located between the driving transistor and the pixel electrode, wherein the orthographic projection of the light-shielding layer on the substrate at least partially overlaps with the orthographic projection of the channel portion on the substrate.

[0008] Optionally, the light-shielding layer overlaps with the pixel electrode;

[0009] The array substrate further includes:

[0010] An organic insulating layer, at least a portion of which is located between the light-shielding layer and the driving transistor.

[0011] Optionally, the array substrate further includes:

[0012] A first passivation layer is located between the organic insulating layer and the light-shielding layer, and at least two first vias are provided on the first passivation layer;

[0013] The organic insulating layer is provided with a second via, and the boundary of the orthographic projection of the second via on the substrate surrounds the orthographic projection of the at least two first vias on the substrate.

[0014] The pixel electrode is coupled to the driving transistor through the second via and the at least two first vias.

[0015] Optionally, the orthographic projection of the light-shielding layer on the substrate does not overlap with the orthographic projection of the second via on the substrate.

[0016] Optionally, the light-shielding layer includes a plurality of first electrode blocks corresponding one-to-one with the plurality of pixel driving units, and the plurality of first electrode blocks are independent of each other;

[0017] The orthographic projection of the first electrode block on the substrate has a first overlapping area with the orthographic projection of the corresponding pixel electrode on the substrate. The first overlapping area is greater than 50%*S, where S is the area of ​​the pixel electrode.

[0018] Optionally, the pixel driving unit further includes a common electrode plate, which includes a first part and a second part. The orthographic projection of the first part on the substrate is located inside the orthographic projection of the corresponding first electrode block on the substrate. The orthographic projection of the second part on the substrate does not overlap with the orthographic projection of the corresponding first electrode block on the substrate. The orthographic projection of the second part on the substrate is adjacent to the orthographic projection of the second via on the substrate.

[0019] Optionally, the array substrate further includes:

[0020] A second passivation layer and a third passivation layer are stacked together, wherein the second passivation layer is located between the light-shielding layer and the driving transistor, and the third passivation layer is located between the light-shielding layer and the pixel electrode;

[0021] A common signal line is located in the peripheral area of ​​the array substrate; the light-shielding layer is coupled to the common signal line.

[0022] Optionally, the light-shielding layer includes a plurality of second electrode blocks corresponding one-to-one with the plurality of pixel driving units, and the second electrode blocks located in the same row along the first direction are coupled to each other through a connecting portion, and the two ends of the second electrode blocks in the same row are respectively coupled to the peripheral signal lines.

[0023] The orthographic projection of the second electrode block on the substrate at least partially overlaps with the orthographic projection of the channel portion of the driving transistor in the corresponding pixel driving unit on the substrate.

[0024] Optionally, the orthographic projection of the second electrode block on the substrate has a second overlapping area with the orthographic projection of the corresponding pixel electrode on the substrate, the second overlapping area being less than 25%*S, where S is the area of ​​the pixel electrode.

[0025] Optionally, the pixel driving unit further includes a common electrode plate, the orthographic projection of which on the substrate does not overlap with the orthographic projection of the second electrode block on the substrate.

[0026] Optionally, at least one third via is provided on the second passivation layer, and at least one fourth via is provided on the third passivation layer. The third via and the fourth via are in one-to-one correspondence, and the third via is connected to the corresponding fourth via.

[0027] The pixel electrode is coupled to the driving transistor through the third via and the fourth via.

[0028] Optionally, the orthographic projection of the pixel electrode on the substrate at least partially overlaps with the orthographic projection of the channel portion on the substrate; or,

[0029] The orthographic projection of the pixel electrode on the substrate does not overlap with the orthographic projection of the channel portion on the substrate.

[0030] Based on the above-described array substrate technical solution, a second aspect of the present invention provides an electronic paper comprising the above-described array substrate, wherein the electronic paper further comprises a counter substrate and a charged particle layer; the array substrate and the counter substrate are disposed opposite to each other, and the charged particle layer is located between the array substrate and the counter substrate.

[0031] In the technical solution provided by this invention, a light-shielding layer is disposed between the driving transistor and the pixel electrode, and the orthographic projection of the light-shielding layer on the substrate at least partially overlaps with the orthographic projection of the channel portion on the substrate. Therefore, in the array substrate provided by this embodiment, the light-shielding layer can shield the channel portion included in the driving transistor, preventing strong light from irradiating the channel portion and generating photogenerated carriers, thus avoiding an excessively high Ioff. Therefore, when the array substrate provided by this embodiment is applied to electronic paper, the electronic paper can be used in outdoor environments, ensuring that the Ioff of the driving transistor remains within the allowable range, thereby maintaining the pixel voltage and ensuring the display effect of the electronic paper. Therefore, when the array substrate provided by this embodiment is applied to electronic paper, the production capacity and profitability of the electronic paper can be improved. Attached Figure Description

[0032] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0033] Figure 1 This is a first cross-sectional schematic diagram of a pixel driving unit provided in an embodiment of the present invention;

[0034] Figure 2 This is a first layout schematic diagram of the pixel driving unit provided in an embodiment of the present invention;

[0035] Figure 3 for Figure 2 Schematic diagram of the common electrode plate;

[0036] Figure 4 This is a second cross-sectional schematic diagram of the pixel driving unit provided in an embodiment of the present invention;

[0037] Figure 5 This is a schematic diagram of the second layout of the pixel driving unit provided in an embodiment of the present invention;

[0038] Figure 6 This is a schematic diagram of electronic paper provided in an embodiment of the present invention. Detailed Implementation

[0039] To further illustrate the array substrate and electronic paper provided in the embodiments of the present invention, a detailed description is provided below with reference to the accompanying drawings.

[0040] Based on the problems existing in the background technology, the following verification is performed:

[0041] 1. Do not block the channel portion of the driving transistor included in the array substrate of the electronic paper. Test the characteristics of the driving transistor and find that the Ion of the driving transistor is 4.49μA in a dark environment and the Ioff of the driving transistor is 346.37pA in a photo environment (i.e., under light).

[0042] 2. The channel portion of the driving transistors included in the array substrate of the electronic paper was shielded. The characteristics of the driving transistors were tested, and it was found that the Ion of the driving transistors was 4.51μA in the dark environment and the Ioff of the driving transistors was 1.92pA in the photo environment.

[0043] The conclusion is that the Ion level is comparable in the Dark environment with and without channel shading. In the Photo environment with no shading, Ioff increases significantly, mainly due to photogenerated carriers generated by strong light irradiating the channel.

[0044] Please see Figures 1 to 5This invention provides an array substrate, including: a substrate 10 and a plurality of pixel driving units disposed on the substrate 10. Each pixel driving unit includes a driving transistor DTFT coupled to a pixel electrode 11, and the driving transistor DTFT includes a channel portion 12. The array substrate further includes:

[0045] A light-shielding layer 15, at least a portion of which is located between the driving transistor DTFT and the pixel electrode 11, wherein the orthographic projection of the light-shielding layer 15 on the substrate 10 at least partially overlaps with the orthographic projection of the channel portion 12 on the substrate 10.

[0046] For example, the array substrate includes a plurality of pixel driving units disposed on the substrate 10, each pixel driving unit including a driving transistor DTFT and a pixel electrode 11 coupled together. The plurality of driving transistors DTFT included in the plurality of pixel driving units are arranged in an array. The plurality of pixel electrodes 11 included in the plurality of pixel driving units are arranged in an array.

[0047] For example, the array substrate further includes multiple gate lines 18 and multiple data lines 19, which intersect. The gate 30 of the driving transistor DTFT is coupled to the corresponding gate line 18, the first electrode 13 of the driving transistor DTFT is coupled to the corresponding data line 19, and the second electrode 14 of the driving transistor DTFT is coupled to the pixel electrode 11 belonging to the same pixel driving unit. The gate line 18 is used to control whether the driving transistor DTFT is turned on. When the driving transistor DTFT is turned on, the data signal transmitted by the coupled data line 19 can be written to the corresponding pixel electrode 11.

[0048] For example, the driving transistor DTFT includes an active layer, and the channel portion 12 of the active layer is a-Si.

[0049] For example, the light-shielding layer 15 is made of an opaque metallic material, such as Al, Mo, etc., but not limited to this.

[0050] For example, at least a portion of the light-shielding layer 15 is located between the source and drain electrodes (including the source electrode and the drain electrode) of the driving transistor DTFT and the pixel electrode 11.

[0051] For example, the orthographic projection of the light-shielding layer 15 onto the substrate 10 covers the orthographic projection of the channel portion 12 onto the substrate 10.

[0052] As can be seen from the specific structure of the array substrate described above, in the array substrate provided in this embodiment of the invention, a light-shielding layer 15 is disposed between the driving transistor DTFT and the pixel electrode 11, and the orthographic projection of the light-shielding layer 15 on the substrate 10 at least partially overlaps with the orthographic projection of the channel portion 12 on the substrate 10. Therefore, in the array substrate provided in this embodiment of the invention, the light-shielding layer 15 can shield the channel portion 12 included in the driving transistor DTFT, preventing strong light from irradiating the channel portion 12 and generating photogenerated carriers, thus avoiding an excessively large Ioff.

[0053] Therefore, when the array substrate provided in this embodiment of the invention is applied to electronic paper, the electronic paper can be used in outdoor environments, ensuring that the Ioff of the driving transistor DTFT is within the allowable range, thereby maintaining the pixel voltage and ensuring the display effect of the electronic paper. Thus, when the array substrate provided in this embodiment of the invention is applied to electronic paper, the production capacity and profitability of the electronic paper can be improved.

[0054] Further verification is as follows:

[0055] 1. Pixel electrode 11 completely covers the driving transistor DTFT. Testing the characteristics of the driving transistor DTFT revealed that, in a dark environment, the Ion of the driving transistor DTFT was 353.55 μA, and the Ioff was 398 pA.

[0056] 2. Pixel electrode 11 does not cover the driving transistor DTFT. Testing the characteristics of the driving transistor DTFT revealed that, in a dark environment, the Ion of the driving transistor DTFT was 322.17 μA and the Ioff was 41.40 pA.

[0057] The above verification uses the existing pixel electrode 11 as the light-shielding layer 15, which is equivalent to verifying the Ion and Ioff of the driving transistor DTFT in the Dark environment when the light-shielding layer 15 completely covers the driving transistor DTFT and does not cover the driving transistor DTFT.

[0058] Verification results show that, in the Dark environment, the Ion level is comparable whether the light-shielding layer 15 completely covers the driving transistor DTFT or not. However, when the light-shielding layer 15 completely covers the driving transistor DTFT, the Ioff increases by one order of magnitude in the Dark environment. This is because the light-shielding layer 15, the channel portion 12, and the passivation layer between them together form a top-gate transistor. This transistor, along with the driving transistor DTFT (bottom-gate transistor), simultaneously affects the channel portion 12, resulting in a larger Ioff.

[0059] The above verification revealed the following issues:

[0060] If the light-shielding layer 15 adopts a passive design (i.e., floating), the voltage difference between the light-shielding layer 15 and the pixel electrode 11 will cause uneven display of the electronic paper formed on the array substrate. If the light-shielding layer 15 adopts an active design, that is, there is voltage on the light-shielding layer 15, then the influence of the top-gate structure transistor formed by the light-shielding layer 15 on the characteristics of the driving transistor DTFT needs to be considered.

[0061] like Figures 1 to 3 As shown, in some embodiments, the light-shielding layer 15 overlaps with the pixel electrode 11; the array substrate further includes:

[0062] An organic insulating layer 16, at least a portion of which is located between the light-shielding layer 15 and the driving transistor DTFT.

[0063] For example, there is no other insulating layer between the pixel electrode 11 and the light-shielding layer 15, that is, the light-shielding layer 15 is directly connected to the pixel electrode 11, so that the light-shielding layer 15 has the same potential as the pixel electrode 11, which is equivalent to a part of the pixel electrode 11.

[0064] For example, the thickness of the organic insulating layer 16 is in about.

[0065] For example, the organic insulating layer 16 has a relatively thick thickness, which not only insulates the light-shielding layer 15 from the driving transistor DTFT, but also makes the light-shielding layer 15 far away from the channel portion 12 of the driving transistor DTFT, so that a transistor with a top gate structure is not formed.

[0066] The above-mentioned arrangement of the light-shielding layer 15 overlapping with the pixel electrode 11 not only avoids the light-shielding layer 15 from floating, but also ensures that there is no pressure difference between the light-shielding layer 15 and the pixel electrode 11, thereby ensuring the stability of the array substrate and the display uniformity of the electronic paper formed by the array substrate.

[0067] The organic insulating layer 16 is provided between the light-shielding layer 15 and the driving transistor DTFT to prevent the light-shielding layer 15 from forming a top-gate structure transistor with the channel portion 12, thereby avoiding any impact on the characteristics of the driving transistor DTFT, preventing the Ioff of the driving transistor DTFT from being too large, and ensuring the working performance of the driving transistor DTFT.

[0068] like Figures 1 to 3 As shown, in some embodiments, the array substrate further includes:

[0069] A first passivation layer PVX1 is located between the organic insulating layer 16 and the light-shielding layer 15, and at least two first vias Via1 are provided on the first passivation layer PVX1.

[0070] The organic insulating layer 16 is provided with a second via Via2, and the boundary of the orthographic projection of the second via Via2 on the substrate 10 surrounds the orthographic projection of the at least two first via Via1 on the substrate 10.

[0071] The pixel electrode 11 is coupled to the driving transistor DTFT through the second via Via2 and the at least two first vias Via1.

[0072] For example, the first passivation layer PVX1 is provided with four first vias Via1 arranged in an array.

[0073] For example, the driving transistor DTFT includes a first electrode 13 and a second electrode 14. The first electrode 13 serves as an input electrode, and the second electrode 14 serves as an output electrode. The first electrode 13 is coupled to a corresponding data line 19, and the second electrode 14 is coupled to the pixel electrode 11. One of the first electrode 13 and the second electrode 14 serves as a source electrode, and the other serves as a drain electrode. The first electrode 13 and the second electrode 14 are fabricated using source and drain metal layers.

[0074] For example, the orthographic projection of the first via Via1 on the substrate 10 is located inside the orthographic projection of the second electrode 14 on the substrate 10, and the orthographic projection of the second via Via2 on the substrate 10 is located inside the orthographic projection of the second electrode 14 on the substrate 10. After forming the first via Via1 and the second via Via2, the second electrode 14 can be exposed so that the pixel electrode 11 formed subsequently can be coupled to the second electrode 14 of the driving transistor DTFT through the second via Via2 and the at least two first via Via1.

[0075] The array substrate described above also includes a first passivation layer PVX1, which can better insulate the light-shielding layer 15 from the source / drain metal layer in the array substrate, and prevent short circuits between the light-shielding layer 15 and other conductive structures made of the source / drain metal layer.

[0076] The array substrate described above also includes a first passivation layer PVX1, which further increases the distance between the light-shielding layer 15 and the channel portion 12, thereby better preventing the light-shielding layer 15 from affecting the characteristics of the driving transistor DTFT.

[0077] like Figures 1 to 3As shown, in some embodiments, the orthographic projection of the light-shielding layer 15 on the substrate 10 does not overlap with the orthographic projection of the second via Via2 on the substrate 10.

[0078] The above configuration avoids the light-shielding layer 15 remaining in the second via Via2, and better ensures that the pixel electrode 11 is coupled to the driving transistor DTFT through the first via Via1 and the second via Via2.

[0079] like Figures 1 to 3 As shown, in some embodiments, the light-shielding layer 15 includes a plurality of first electrode blocks 151 corresponding one-to-one with the plurality of pixel driving units, and the plurality of first electrode blocks 151 are independent of each other.

[0080] The orthographic projection of the first electrode block 151 on the substrate 10 has a first overlapping area with the orthographic projection of the corresponding pixel electrode 11 on the substrate 10. The first overlapping area is greater than 50%*S, where S is the area of ​​the pixel electrode 11.

[0081] For example, the orthographic projection of the first electrode block 151 on the substrate 10 covers the orthographic projection of the channel portion 12 of the driving transistor DTFT on the substrate 10.

[0082] For example, the plurality of first electrode blocks 151 in the array substrate correspond one-to-one with the plurality of pixel electrodes 11, and each first electrode block 151 is connected to the corresponding pixel electrode 11.

[0083] For example, the plurality of first electrode blocks 151 are arranged in an array.

[0084] Because the first electrode block 151 has a certain slope angle at its edge, a large slope angle may cause the pixel electrode 11 that climbs the slope angle to break, resulting in the part of the pixel electrode 11 that overlaps with the first electrode block 151 and the part of the pixel electrode 11 that does not overlap with the first electrode block 151 being completely disconnected, or in a state of partial disconnection. The part of the pixel electrode 11 that does not overlap with the first electrode block 151 is coupled to the driving transistor DTFT and can receive driving signals. If the above-mentioned disconnection or partial disconnection occurs, the part of the pixel electrode 11 that overlaps with the light-shielding layer 15 will not be able to receive driving signals normally, thereby affecting the yield of the array substrate.

[0085] The above-mentioned configuration has a first overlapping area between the orthographic projection of the first electrode block 151 on the substrate 10 and the orthographic projection of the corresponding pixel electrode 11 on the substrate 10. The first overlapping area is greater than 50%*S, which makes the first electrode block 151 and the pixel electrode 11 form a large overlapping area. The portion of the pixel electrode 11 that climbs the slope angle of the first electrode block 151 also has a large area. In this way, even if the pixel electrode 11 breaks in some slope angle areas, the normal climbing of the pixel electrode 11 can still be guaranteed in other slope angle areas, thereby effectively improving the yield of the array substrate.

[0086] like Figures 1 to 3 As shown, in some embodiments, the pixel driving unit further includes a common electrode plate 17, which includes a first portion 171 and a second portion 172. The orthographic projection of the first portion 171 on the substrate 10 is located inside the orthographic projection of the corresponding first electrode block 151 on the substrate 10. The orthographic projection of the second portion 172 on the substrate 10 does not overlap with the orthographic projection of the corresponding first electrode block 151 on the substrate 10. The orthographic projection of the second portion 172 on the substrate 10 is adjacent to the orthographic projection of the second via Via2 on the substrate 10.

[0087] For example, along the extension direction of the gate line 18, common plates 17 located in the same row are coupled sequentially, and the two ends of a row of common plates 17 are respectively coupled to common signal lines in the array substrate to receive common signals transmitted by the common signal lines.

[0088] For example, the first portion 171 and the second portion 172 are formed as a single structure.

[0089] For example, the steps of fabricating the light-shielding layer 15 include: forming a light-shielding metal layer using a light-shielding metal material, the light-shielding metal layer covering the second via Via2, and patterning the light-shielding metal layer to form the light-shielding layer 15. The orthographic projection of the light-shielding layer 15 on the substrate 10 needs to not overlap with the orthographic projection of the second via Via2 on the substrate 10.

[0090] For example, the first electrode block 151 is formed in an L-shaped structure.

[0091] For example, within a pixel driving unit, the orthographic projection of the second portion 172 on the substrate 10, the orthographic projection of the second via Via2 on the substrate 10, and the orthographic projection of the channel portion 12 on the substrate 10 are arranged sequentially along the extension direction of the gate line 18.

[0092] Since the second via Via2 is relatively deep, if the photoresist formed on the light-shielding metal layer in the second via Via2 is not sufficiently exposed when patterning the light-shielding metal layer, some light-shielding metal material will remain in the second via Via2 during the subsequent etching process.

[0093] The above-described limitation ensures that the orthographic projection of the second portion 172 on the substrate 10 does not overlap with the orthographic projection of the corresponding first electrode block 151 on the substrate 10; the orthographic projection of the second portion 172 on the substrate 10 is adjacent to the orthographic projection of the second via Via2 on the substrate 10; thus, the first electrode block 151 is not located in at least a portion of the region adjacent to the second via Via2. In this way, during the patterning of the light-shielding metal layer, the exposure of the photoresist on the light-shielding metal layer near the second via Via2 is increased, thereby improving the sufficiency of photoresist exposure within the second via Via2 and reducing the risk of residual light-shielding metal material inside the second via Via2.

[0094] The array substrate provided in the above embodiments includes, in sequence along the direction away from the substrate 10: a first gate metal layer, a gate insulating layer GI, an active layer, a source / drain metal layer, a buffer layer, an organic insulating layer 16, a first passivation layer PVX1, a light-shielding layer 15, and a pixel electrode 11 layer.

[0095] The first gate metal layer includes: a gate line 18, a gate 30 of a driving transistor DTFT, and a common electrode 17. Exemplarily, the common signal line may also be fabricated using the first gate metal layer, but is not limited thereto.

[0096] The active layer includes the channel portion 12 of the driving transistor DTFT.

[0097] The source and drain metal layers include the source electrode and drain electrode of the driving transistor DTFT, and data line 19.

[0098] The light-shielding layer 15 includes a plurality of first electrode blocks 151.

[0099] The pixel electrode 11 layer includes a plurality of pixel electrodes 11.

[0100] The array substrate with the above structure undergoes a 6-mask process, and the main process flow is as follows:

[0101] The first gate metal layer is formed using a 1mask process.

[0102] The active layer and the source / drain metal layer are formed using a 2-mask process. The active layer and the source / drain metal layer are formed simultaneously using a Half-Tone Mask process. More specifically, an active material layer is deposited, a source / drain metal material layer is formed on the active material layer, and photoresist is formed on the source / drain metal material layer. The photoresist is exposed and developed using a halftone mask to form a photoresist fully retained region, a photoresist partially retained region, and a photoresist completely removed region. The photoresist fully retained region corresponds to the source electrode, drain electrode, and data line 19 of the driving transistor DTFT. The photoresist partially retained region corresponds to the channel portion 12. The photoresist completely removed region corresponds to the portion other than the source electrode, drain electrode, data line 19, and channel portion 12. The active layer and the source / drain metal layer located in the photoresist completely removed region are etched to remove both the active layer and the source / drain metal layer located in the photoresist completely removed region. Remove the photoresist located in the partially retained photoresist region, remove the source and drain metal material layers located in the partially retained photoresist region, and etch a portion of the active layer located in the partially retained photoresist region to form the channel portion 12. Remove the photoresist in the fully retained photoresist region to form the active layer, source electrode, drain electrode, and data line 19 of the driving transistor DTFT.

[0103] The 3mask process forms the organic insulating layer 16 and the second via Via2 on the organic insulating layer 16.

[0104] The 4mask process forms a light-shielding layer 15.

[0105] The 5mask process forms the first passivation layer PVX1 and the first via Via1 on the first passivation layer PVX1.

[0106] The pixel electrode 11 is formed using a 6-mask process.

[0107] The array substrate is manufactured using a 6-mask process. Although the overall solution is a completely new design, each layer has mature process conditions, making it less difficult and ensuring a high yield.

[0108] When the array substrate provided in the above embodiment adopts the above structure, the characteristics of the driving transistor DTFT are tested in a dark environment, and the average Ion value is 3.28μA, which is 4.1% higher than the reference value (Spec) of 3.08μA. The average Ioff value is 0.25pA, which is less than the reference value of 2pA.

[0109] like Figure 4 and Figure 5 As shown, in some embodiments, the array substrate further includes:

[0110] A second passivation layer PVX2 and a third passivation layer PVX3 are stacked together. The second passivation layer PVX2 is located between the light-shielding layer 15 and the driving transistor DTFT, and the third passivation layer PVX3 is located between the light-shielding layer 15 and the pixel electrode 11.

[0111] A common signal line is located in the peripheral area of ​​the array substrate; the light-shielding layer 15 is coupled to the common signal line.

[0112] For example, the array substrate includes a display area and a peripheral area surrounding the display area, and the common signal line is located in the peripheral area, surrounding the display area. The common signal line is used to transmit a common signal.

[0113] For example, the voltage of the signal is between 12V and 0V, and may include endpoint values.

[0114] For example, the third passivation layer PVX3 is located between the light-shielding layer 15 and the pixel electrode 11, thereby insulating the light-shielding layer 15 from the pixel electrode 11. The second passivation layer PVX2 is located between the light-shielding layer 15 and the driving transistor DTFT, thereby insulating the light-shielding layer 15 from the driving transistor DTFT.

[0115] It is worth noting that if the light-shielding layer 15 is in a floating state, it is easily coupled by the voltage on the pixel electrode 11, generating a pixel voltage. Furthermore, since there is no organic insulating layer 16 between the light-shielding layer 15 and the driving transistor DTFT in this design, the light-shielding layer 15, the second passivation layer PVX2, and the channel portion 12 are prone to forming a top-gate structure transistor, affecting the characteristics of the driving transistor DTFT.

[0116] In the array substrate provided in the above embodiments, the light-shielding layer 15 is coupled to the common signal line, so that the common signal is loaded on the light-shielding layer 15, preventing the light-shielding layer 15 from being in a floating state. This avoids the light-shielding layer 15 being affected by the pixel electrode 11, reducing the impact on the characteristics of the driving transistor DTFT.

[0117] like Figure 4 and Figure 5 As shown, in some embodiments, the light-shielding layer 15 includes a plurality of second electrode blocks 152 corresponding one-to-one with the plurality of pixel driving units. The second electrode blocks 152 located in the same row along the first direction are coupled to each other through a connecting portion 153. The two ends of the second electrode blocks 152 in the same row are respectively coupled to the peripheral signal lines.

[0118] The orthographic projection of the second electrode block 152 on the substrate 10 at least partially overlaps with the orthographic projection of the channel portion 12 of the driving transistor DTFT in the corresponding pixel driving unit on the substrate 10.

[0119] For example, the first direction includes the extension direction of the gate line 18.

[0120] For example, the connecting portion 153 and the second electrode block 152 form an integral structure.

[0121] For example, the orthographic projection of the second electrode block 152 on the substrate 10 covers the orthographic projection of the channel portion 12 of the driving transistor DTFT in the corresponding pixel driving unit on the substrate 10.

[0122] For example, the plurality of second electrode blocks 152 in the array substrate correspond one-to-one with the plurality of pixel electrodes 11. The plurality of second electrode blocks 152 are arranged in an array.

[0123] For example, the orthographic projection of the connecting portion 153 on the substrate 10 at least partially overlaps with the orthographic projection of the common electrode plate 17 on the substrate 10.

[0124] For example, the orthographic projection of the connecting portion 153 on the substrate 10 does not overlap with the orthographic projection of the second via Via2 on the substrate 10.

[0125] For example, the orthographic projection of the second electrode block 152 on the substrate 10 does not overlap with the orthographic projection of the second via Via2 on the substrate 10.

[0126] For example, the orthographic projection of the second electrode block 152 on the substrate 10 is located inside the orthographic projection of the pixel electrode 11 on the substrate 10.

[0127] For example, the array substrate includes multiple rows of second electrode blocks 152, and the two ends of each row of second electrode blocks 152 are respectively coupled to the peripheral signal lines.

[0128] like Figure 4 and Figure 5 As shown, in some embodiments, the orthographic projection of the second electrode block 152 on the substrate 10 has a second overlapping area with the orthographic projection of the corresponding pixel electrode 11 on the substrate 10, the second overlapping area being less than 25%*S, where S is the area of ​​the pixel electrode 11.

[0129] It is worth noting that the second electrode block 152, the third passivation layer PVX3, and the pixel electrode 11 form a storage capacitor. If the area of ​​the second electrode block 152 is too large, the capacitance of the formed storage capacitor will be large. Because of the principle that capacitance cannot change abruptly, the voltage of the second electrode block 152 will continuously pull the voltage of the pixel electrode 11, resulting in a slowdown in charging and discharging speed and an increase in product power consumption.

[0130] The above setting reduces the voltage pull of the second electrode block 152 on the pixel electrode 11 by less than 25%*S, thereby reducing the power consumption of the product.

[0131] like Figure 4 and Figure 5 As shown, in some embodiments, the pixel driving unit further includes a common electrode plate 17, the orthographic projection of the common electrode plate 17 on the substrate 10 not overlapping with the orthographic projection of the second electrode block 152 on the substrate 10.

[0132] For example, the common electrode 17 serves as one electrode of the storage capacitor and can stabilize the voltage signals on the second electrode block 152 and the pixel electrode 11.

[0133] In some embodiments, at least one third via Via3 is provided on the second passivation layer PVX2, and at least one fourth via Via4 is provided on the third passivation layer PVX3. The third via Via3 and the fourth via Via4 correspond one-to-one and are connected. The pixel electrode 11 is coupled to the driving transistor DTFT through the third via Via3 and the fourth via Via4.

[0134] For example, four third vias Via3 are provided on the second passivation layer PVX2, and four fourth vias Via4 are provided on the third passivation layer PVX3. The third vias Via3 and the fourth vias Via4 are formed in the same patterning process.

[0135] In some embodiments, the orthographic projection of the pixel electrode 11 on the substrate 10 at least partially overlaps with the orthographic projection of the channel portion 12 on the substrate 10; or, the orthographic projection of the pixel electrode 11 on the substrate 10 does not overlap with the orthographic projection of the channel portion 12 on the substrate 10.

[0136] The array substrate provided in the above embodiments includes, in sequence along the direction away from the substrate 10: a first gate metal layer, a gate insulating layer GI, an active layer, a source / drain metal layer, a second passivation layer PVX2, a light-shielding layer 15, a third passivation layer PVX3, and a pixel electrode 11 layer.

[0137] The first gate metal layer includes: a gate line 18, a gate 30 of a driving transistor DTFT, and a common electrode 17. Exemplarily, the common signal line may also be fabricated using the first gate metal layer, but is not limited thereto.

[0138] The active layer includes the channel portion 12 of the driving transistor DTFT.

[0139] The source and drain metal layers include the source electrode and drain electrode of the driving transistor DTFT, and data line 19.

[0140] The light-shielding layer 15 includes a plurality of second electrode blocks 152 and a connecting portion 153.

[0141] The pixel electrode 11 layer includes a plurality of pixel electrodes 11.

[0142] The array substrate with the above structure undergoes a 5-mask process, and the main process flow is as follows:

[0143] The first gate metal layer is formed using a 1mask process.

[0144] The active layer and the source / drain metal layer are formed using a 2-mask process. The active layer and the source / drain metal layer are formed simultaneously using a Half-Tone Mask process. More specifically, an active material layer is deposited, a source / drain metal material layer is formed on the active material layer, and photoresist is formed on the source / drain metal material layer. The photoresist is exposed and developed using a halftone mask to form a photoresist fully retained region, a photoresist partially retained region, and a photoresist completely removed region. The photoresist fully retained region corresponds to the source electrode, drain electrode, and data line 19 of the driving transistor DTFT. The photoresist partially retained region corresponds to the channel portion 12. The photoresist completely removed region corresponds to the portion other than the source electrode, drain electrode, data line 19, and channel portion 12. The active layer and the source / drain metal layer located in the photoresist completely removed region are etched to remove both the active layer and the source / drain metal layer located in the photoresist completely removed region. Remove the photoresist located in the partially retained photoresist region, remove the source and drain metal material layers located in the partially retained photoresist region, and etch a portion of the active layer located in the partially retained photoresist region to form the channel portion 12. Remove the photoresist in the fully retained photoresist region to form the active layer, source electrode, drain electrode, and data line 19 of the driving transistor DTFT.

[0145] The 3mask process forms a light-shielding layer 15.

[0146] The second passivation layer PVX2 and the third passivation layer PVX3 are formed using a 4-mask process, which forms the third via Via3 and the fourth via Via4. It should be noted that the second passivation layer PVX2 and the third passivation layer PVX3 are formed through two deposition processes and one etching process.

[0147] The pixel electrode 11 is formed using a 5-mask process.

[0148] The array substrate is manufactured using a 5-mask process. Although the overall solution is a completely new design, each layer has mature process conditions, making it less difficult and ensuring a high yield.

[0149] When the array substrate provided in the above embodiment adopts the above structure, the characteristics of the driving transistor DTFT are tested in a dark environment, and the average Ion value is 2.61μA, which is 23.6% lower than the reference value of Ion. However, the simulated charging rate at the average value is 90.02%, which meets the customer requirements (>90%). The average Ioff value is 0.39pA, which meets the requirement of being less than the reference value of Ioff by 2pA.

[0150] like Figure 6 As shown, this embodiment of the invention also provides an electronic paper, comprising: the array substrate provided in the above embodiment, the electronic paper further comprising a counter substrate and a charged particle layer; the array substrate and the counter substrate are disposed opposite to each other, and the charged particle layer is located between the array substrate and the counter substrate.

[0151] The opposing substrate includes a substrate 20, on which a common electrode 21 and a protective film 22 are disposed. The common electrode 21 is located between the charged particle layer and the substrate 20, and the protective film 22 is located on the side of the substrate 20 opposite to the charged particle layer.

[0152] The charged particle layer includes charged microspheres 23, each containing a first charged particle and a second charged particle. The first and second charged particles have opposite charges and different colors. For example, the first charged particles include black, positively charged particles. The second charged particles include white, negatively charged particles. The charged microspheres 23 also contain a transparent electrophoretic solution 233. The charged particle layer also includes an adhesive 24.

[0153] In the array substrate provided in the above embodiments, a light-shielding layer 15 is disposed between the driving transistor DTFT and the pixel electrode 11, and the orthographic projection of the light-shielding layer 15 on the substrate 10 at least partially overlaps with the orthographic projection of the channel portion 12 on the substrate 10. Therefore, in the array substrate provided in the above embodiments, the light-shielding layer 15 can shield the channel portion 12 included in the driving transistor DTFT, preventing strong light from irradiating the channel portion 12 and generating photogenerated carriers, thus avoiding an excessively large Ioff.

[0154] Therefore, when the electronic paper provided in this embodiment includes the array substrate provided in the above embodiment, the electronic paper can be used in outdoor environments, ensuring that the Ioff of the driving transistor DTFT is within the allowable range, thereby maintaining the pixel voltage and ensuring the display effect of the electronic paper. Therefore, when the electronic paper provided in this embodiment includes the array substrate provided in the above embodiment, it can improve the production capacity and profitability of the electronic paper.

[0155] It should be noted that, in the embodiments of the present invention, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0156] In the various method embodiments of the present invention, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps without creative effort are also within the scope of protection of the present invention.

[0157] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0158] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0159] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0160] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0161] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An electronic paper, characterized in that, It includes an array substrate, a counter substrate, and a charged particle layer; The array substrate and the opposing substrate are disposed opposite to each other, and the charged particle layer is located between the array substrate and the opposing substrate; The array substrate includes: a substrate and a plurality of pixel driving units disposed on the substrate, each pixel driving unit including a driving transistor and a pixel electrode coupled together, the driving transistor including a channel portion; the array substrate further includes: A light-shielding layer, at least a portion of which is located between the driving transistor and the pixel electrode, wherein the orthographic projection of the light-shielding layer on the substrate at least partially overlaps with the orthographic projection of the channel portion on the substrate; the light-shielding layer is made of an opaque metallic material. The light-shielding layer overlaps with the pixel electrode; The array substrate further includes: An organic insulating layer, at least a portion of which is located between the light-shielding layer and the driving transistor; The light-shielding layer includes a plurality of first electrode blocks that correspond one-to-one with the plurality of pixel driving units, and the plurality of first electrode blocks are independent of each other; The orthographic projection of the first electrode block on the substrate has a first overlapping area with the orthographic projection of the corresponding pixel electrode on the substrate. The first overlapping area is greater than 50% × S, where S is the area of ​​the pixel electrode.

2. The electronic paper according to claim 1, characterized in that, The array substrate further includes: A first passivation layer is located between the organic insulating layer and the light-shielding layer, and at least two first vias are provided on the first passivation layer; The organic insulating layer is provided with a second via, and the boundary of the orthographic projection of the second via on the substrate surrounds the orthographic projection of the at least two first vias on the substrate. The pixel electrode is coupled to the driving transistor through the second via and the at least two first vias.

3. The electronic paper according to claim 2, characterized in that, The orthographic projection of the light-shielding layer on the substrate does not overlap with the orthographic projection of the second via on the substrate.

4. The electronic paper according to claim 2, characterized in that, The pixel driving unit further includes a common electrode plate, which includes a first part and a second part, wherein the orthographic projection of the first part on the substrate is located inside the orthographic projection of the corresponding first electrode block on the substrate; The orthographic projection of the second part on the substrate does not overlap with the orthographic projection of the corresponding first electrode block on the substrate; The orthographic projection of the second portion on the substrate is adjacent to the orthographic projection of the second via on the substrate.

5. The electronic paper according to any one of claims 1 to 4, characterized in that, The orthographic projection of the pixel electrode on the substrate at least partially overlaps with the orthographic projection of the channel portion on the substrate; or, The orthographic projection of the pixel electrode on the substrate does not overlap with the orthographic projection of the channel portion on the substrate.

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