Method for configuring operating frequency of chip during operation

Abstract

The application discloses a configuration method of working frequency in chip operation process, comprising the following steps: S1, chip working frequency A, chip software switches work to crystal frequency; S2, chip software resets PLL; S3, configuration PLL frequency parameter; S4, release PLL reset, execute frequency locking process; S5, software reads PLL Loc state; S6, after PLL locking, output required output frequency B; S7, chip software configures non-glitch frequency switching circuit, and working frequency switching is carried out. Advantage, chip working frequency can realize dynamic switching according to application scene and real-time state; software configurable chip frequency, chip frequency configuration pin is omitted, thereby reducing chip manufacturing cost; software configurable chip frequency, chip application board frequency dial switch is omitted, device material is reduced, PCB board area is reduced, and application board cost is reduced.

Description

Technical Field

[0001] This invention relates to a method for configuring the operating frequency of a chip during operation. Background Technology

[0002] The traditional method for switching the main frequency during chip operation is to adjust the frequency DIP switch on the circuit board after the chip is powered off and then power it back on to complete the switching of the operating frequency.

[0003] The configurable operating frequency of a chip during operation is achieved through a specific software configuration process, enabling dynamic switching of the chip's operating frequency during operation.

[0004] The disadvantages of traditional methods are: (1) The chip needs to have frequency configuration pins, which increases the number of PADs and increases manufacturing costs; (2) The application circuit board needs to have a frequency DIP switch, which affects the PCB layout, increases the PCB area, increases the difficulty of PCB design and manufacturing cost.

[0005] (3) After power-on, the chip's operating frequency cannot be switched dynamically in real time.

[0006] The drawbacks of traditional methods are due to the following reasons: (1) The chip PLL frequency module needs to have frequency configuration information. If PAD selection is used, the number of chip package pins needs to be increased. At the same time, if the chip has multiple PLLs, the number of chip frequency configuration pins will increase exponentially. The increase in chip pins will increase the area of ​​the bare die in the case of PAD Limit, thereby increasing the manufacturing cost of the bare die silicon wafer. When packaging the bare die, the increased PADs will also increase the packaging manufacturing cost.

[0007] (2) On the application circuit board, the chip operating frequency is selected via a DIP switch. Adding a DIP switch increases the difficulty of PCB layout and routing, increases the PCB area, and thus increases PCB manufacturing costs. The selected DIP switch also increases the cost of PCB components. Summary of the Invention

[0008] In response to the above technical problems, the invention proposes a method for configuring the operating frequency of a chip during operation. The purpose is to (1) reduce the number of chip pins, thereby reducing chip cost; (2) reduce the number of components on the application board, reduce PCB wiring difficulty, and reduce PCB manufacturing cost; and (3) realize dynamic adjustment of the chip main frequency, increasing application flexibility.

[0009] The technical solution adopted is as follows: A method for configuring the operating frequency of a chip during operation. When the chip is operating normally, its main operating frequency is frequency A. The operating frequency A can be switched to frequency B according to real-time application requirements, achieving dynamic switching of the operating frequency. The specific operating frequency configuration method includes the following steps: S1, chip operating frequency A, chip software configuration of glitch-free frequency switching circuit, switching from the PLL output clock to the board-level crystal oscillator clock, the entire chip operates at the board-level crystal oscillator clock frequency; S2. The chip software resets the phase-locked loop (PLL) settings, putting it into a reset and initialization configuration state. S3. According to the required operating frequency B, the chip configures the PLL frequency parameters. At this time, the PLL reset is always effective and the PLL is in the reset state. S4. After completing the PLL frequency parameter configuration word, the chip software releases the PLL reset, and the PLL starts to execute the frequency locking process according to the frequency configuration word. S5. After the PLL frequency is locked, the PLL outputs the Lock state. If the PLL Lock state is locked when the PLL is locked, the software proceeds to the next step. If it is not locked, the software program reads the PLL Lock state again. S6. After the phase-locked loop (PLL) is locked, the PLL outputs the required output frequency B. S7. The chip software is configured with a glitch-free frequency switching circuit to switch the operating frequency.

[0010] In a preferred embodiment of the present invention, the PLL locking in S5 requires a certain amount of time. The chip software determines whether the PLL locking is complete by cyclically reading the PLL Lock status. This solution combines dedicated frequency configuration circuit logic with frequency configuration software to enable the chip to switch from the current operating frequency A to the desired operating frequency B during operation without power-on restart. Simultaneously, the chip continues to operate normally without any abnormal states during the switching process. This technology significantly reduces the number of components on the chip application board, optimizes the application board design, and lowers PCB manufacturing costs.

[0011] In a preferred embodiment of the present invention, the chip software is configured with a glitch-free frequency switching circuit to switch from the board-level crystal oscillator clock to the PLL output clock, thereby completing the power-on configuration of the chip's operating frequency. The glitch-free frequency switching circuit is a glitch-free clock switch. The glitch-free clock switch circuit uses basic D-Reg flip-flops, AND gate units, and OR gate units stacked to achieve dual clock switching function. This clock circuit receives two clock inputs with different frequencies and phases, generates a clock with the same phase and frequency as the selected input clock, and does not generate glitches during the clock switching process.

[0012] The glitch-free clock switch mentioned in the technical solution of this invention is a known technology, which is known to those skilled in the art, and achieves glitch-free clock frequency switching.

[0013] Compared with the prior art, the beneficial effects of this invention are: 1. The chip operating frequency of the method of the present invention can be dynamically switched according to the application scenario and real-time status.

[0014] 2. The method of the present invention allows the software to configure the chip frequency, eliminating the need for chip frequency configuration pins, thereby reducing chip manufacturing costs.

[0015] 3. The method of the present invention allows the software to configure the chip frequency, eliminating the need for the frequency DIP switch on the chip application board, reducing component materials, reducing PCB board area, and thus reducing application board cost. Attached Figure Description

[0016] Figure 1 This is a flowchart of the method of the present invention.

[0017] Figure 2 This is a circuit diagram of the Glitch Free Clock Switch in this embodiment. Detailed Implementation

[0018] The technical solution of the present invention will be described in detail below, but the scope of protection of the present invention is not limited to the embodiments described.

[0019] To make the content of this invention clearer and easier to understand, the following description is in conjunction with the appendix. Figure 1 -Appendix Figure 2 The specific implementation methods will be further described below.

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0021] like Figure 1 As shown, a method for configuring the operating frequency of a chip during operation is described. When the chip is operating normally, its main operating frequency is frequency A. The operating frequency A can be switched to frequency B according to real-time application requirements, achieving dynamic switching of the operating frequency. The specific operating frequency configuration method includes the following steps: S1, chip operating frequency A, chip software configuration of glitch-free frequency switching circuit, switching from the PLL output clock to the board-level crystal oscillator clock, the entire chip operates at the board-level crystal oscillator clock frequency; S2. The chip software resets the phase-locked loop (PLL) settings, putting it into a reset and initialization configuration state. S3. According to the required operating frequency B, the chip configures the PLL frequency parameters. At this time, the PLL reset is always effective and the PLL is in the reset state. S4. After completing the PLL frequency parameter configuration word, the chip software releases the PLL reset, and the PLL starts to execute the frequency locking process according to the frequency configuration word. S5. After the PLL frequency is locked, the PLL outputs a Lock state. In S5, the PLL locking process takes a certain amount of time. The chip software reads the PLL Lock state repeatedly to determine whether the PLL is locked. If the PLL Lock state is locked, the software proceeds to the next step. If it is not locked, the software program reads the PLL Lock state again. S6. After the phase-locked loop (PLL) is locked, the PLL outputs the required output frequency B. S7. The chip software is configured with a glitch-free frequency switching circuit to switch the operating frequency.

[0022] like Figure 2 As shown, the chip software configures a glitch-free frequency switching circuit to switch from the board-level crystal oscillator clock to the PLL output clock, completing the power-on configuration of the chip's operating frequency. The glitch-free frequency switching circuit is a glitch-free clock switch. The glitch-free clock switch circuit uses basic D-Reg flip-flops, AND gate units, and OR gate units stacked to realize the dual clock switching function. This clock circuit receives two clock inputs with different frequencies and phases, generates a clock with the same phase and frequency as the selected input clock, and does not generate glitches during the clock switching process.

[0023] like Figure 2 As shown, it should be noted that both input clocks need to be in a stable state when switching clocks; otherwise, clock switching cannot be completed correctly and the circuit will have no clock output.

[0024] Application Examples Jiangsu Huachuang Microsystems Co., Ltd., in collaboration with the 14th Research Institute of China Electronics Technology Group Corporation, has developed the HC3020 series high-performance general-purpose DSP chips, HC3080 series high-performance general-purpose DSP chips, KWDSP high-performance general-purpose DSP chips, and MCU embedded chips, all of which utilize this technology to achieve dynamic switching of the chip's operating frequency. This technology reduces the number of components required on the chip application board, lowers PCB routing complexity, reduces design and manufacturing costs, and enables dynamic frequency switching during chip operation.

[0025] All parts not covered in this invention are the same as or can be implemented using existing technologies.

[0026] As described above, although the invention has been shown and described with reference to specific preferred embodiments, it should not be construed as limiting the invention itself. Various changes in form and detail may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for configuring the operating frequency of a chip during operation, characterized in that: When the chip is working normally, its main operating frequency is operating frequency A. The operating frequency can be switched from A to B according to real-time application requirements, achieving dynamic frequency switching. The specific operating frequency configuration method includes the following steps: S1, chip operating frequency A, chip software configuration of glitch-free frequency switching circuit, switching from the PLL output clock to the board-level crystal oscillator clock, the entire chip operates at the board-level crystal oscillator clock frequency; S2. The chip software resets the phase-locked loop (PLL) settings, putting it into a reset and initialization configuration state. S3. According to the required operating frequency B, the chip configures the PLL frequency parameters. At this time, the PLL reset is always effective and the PLL is in the reset state. S4. After completing the PLL frequency parameter configuration word, the chip software releases the PLL reset, and the PLL starts to execute the frequency locking process according to the frequency configuration word. S5. After the PLL frequency is locked, the PLL outputs a Lock state. If the PLL Lock state is locked, the software proceeds to the next step. If not locked, the software program will read the PLLLock status of the PLL lock again; S6. After the phase-locked loop (PLL) is locked, the PLL outputs the required output frequency B. S7. The chip software configures a glitch-free frequency switching circuit to switch the operating frequency. The chip software configures a glitch-free frequency switching circuit to switch from the board-level crystal oscillator clock to the PLL output clock, completing the power-on configuration of the chip's operating frequency. Among them, the glitch-free frequency switching circuit is a glitch-free clock switch circuit. The glitch-free clock switch circuit is configured to perform clock switching only when both the board-level crystal oscillator clock and the PLL output clock are in a stable state. The glitch-free clock switch circuit uses D-Reg flip-flops, AND gate units, and OR gate units stacked to realize the dual clock switching function, which is used to receive two clock inputs with different frequencies and phases and generate a clock with the same phase and frequency as the selected input clock.

2. The method for configuring the operating frequency of a chip during operation according to claim 1, characterized in that: In S5, the PLL lock-up requires a certain amount of time. The chip software determines whether the PLL lock-up is complete by cyclically reading the PLL Lock status.

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