Methods for writing HDD metadata into NAND flash memory

Abstract

The data storage device includes a hard disk drive coupled to a printed circuit board (PCB), a volatile memory device coupled to the PCB, a non-volatile memory device coupled to the PCB, and a controller coupled to the PCB, such that the controller communicates with the hard disk drive, the volatile memory device, and the non-volatile memory device. The controller is configured to recognize the pattern and / or structure of the metadata of the hard disk drive, perform one or more of the following operations on the metadata to adjust the metadata: data shaping, content-aware decoding, adaptive data trimming, and / or adaptive block resizing, and write the adjusted metadata to the non-volatile memory device. The metadata is at least one of repeatable yaw metadata, location error signal metadata, adjacent track interference metadata, and / or emergency power failure metadata.

Description

Background Technology Technical Field

[0002] The embodiments of this disclosure generally relate to data storage devices, such as hard disk drives (HDDs), and more specifically, to efficiently programming HDD metadata into the non-volatile memory of the HDD.

[0003] Description of related fields

[0004] To reduce HDD costs, the track density of each generation of HDDs has increased, requiring more sophisticated algorithms to achieve reliable storage and data retrieval. These algorithms use various types of metadata and calibration data to overcome problems such as head positioning errors, poor track alignment, interference between adjacent tracks, head wobble, airflow and spindle vibration, disk warping, electronic noise, and thermal noise. For a 20+ TB HDD, the metadata can be approximately 40 GB in size.

[0005] Hybrid drives, such as solid-state hybrid drives (SSHDs), can leverage both HDD and SSD components to improve performance and storage capacity in ways that neither HDD nor SSD can achieve alone. For example, a hybrid drive may include disks with read / write heads, non-volatile memory (NVM) such as NAND flash memory, and volatile memory such as static random access memory (SRAM) and dynamic random access memory (DRAM). Metadata for a hybrid drive can be stored in DRAM. However, the amount of DRAM required increases due to the size of the metadata, leading to increased cost and power consumption.

[0006] Therefore, there is a need in the art for an improved metadata storage in HDDs that include NVM. Summary of the Invention

[0007] This disclosure generally relates to data storage devices, such as hard disk drives (HDDs), and more specifically, to efficiently programming HDD metadata into the non-volatile memory of the HDD. The data storage device includes a hard disk drive coupled to a printed circuit board (PCB), a volatile memory device coupled to the PCB, a non-volatile memory device coupled to the PCB, and a controller coupled to the PCB, such that the controller communicates with the hard disk drive, the volatile memory device, and the non-volatile memory device. The controller is configured to recognize the pattern and / or structure of the hard disk drive's metadata, perform one or more of the following operations on the metadata to adjust the metadata: data shaping, content-aware decoding, adaptive data trimming, and / or adaptive block resizing, and write the adjusted metadata to the non-volatile memory device. The metadata is at least one of repeatable yaw metadata, location error signal metadata, adjacent track interference metadata, and / or emergency power failure metadata.

[0008] In one embodiment, the data storage device includes a hard disk drive coupled to a printed circuit board, a volatile memory device coupled to a printed circuit board, a non-volatile memory device coupled to a printed circuit board, and a controller coupled to the printed circuit board, such that the controller communicates with the hard disk drive, the volatile memory device, and the non-volatile memory device. The controller is configured to recognize the pattern and / or structure of metadata of the hard disk drive, perform one or more of the following operations on the metadata to adjust the metadata: data shaping, content-aware decoding, adaptive data trimming, and / or adaptive block size resizing, and write the adjusted metadata to the non-volatile memory device. The pattern and / or structure of the metadata includes non-uniformly distributed data, data write speed requirements, and data durability requirements.

[0009] In another embodiment, the data storage device includes a printed circuit board, one or more rotatable disks coupled to the printed circuit board, a volatile memory device coupled to the printed circuit board, a non-volatile memory device coupled to the printed circuit board, and a controller coupled to the printed circuit board, such that the controller communicates with the one or more rotatable disks, the volatile memory device, and the non-volatile memory device. The controller is configured to recognize the pattern and / or structure of the positioning error signal (PES) metadata or adjacent track interference (ATI) metadata of the hard disk drive, adjust the PES metadata or ATI metadata using data configuration, and write the adjusted PES metadata or ATI metadata to the single-level cell (SLC) memory of the non-volatile memory device.

[0010] In another embodiment, the data storage device includes a printed circuit board, one or more rotatable disks coupled to the printed circuit board, a volatile memory device coupled to the printed circuit board, a non-volatile memory device coupled to the printed circuit board, and a controller coupled to the printed circuit board, such that the controller communicates with the one or more rotatable disks, the volatile memory device, and the non-volatile memory device. The controller is configured to recognize the pattern and / or structure of repeatable sway (RRO) metadata of the hard disk drive, adjust the RRO metadata using content-aware decoding, and write the adjusted RRO metadata to the three-level cell (TLC) memory of the non-volatile memory device. Attached Figure Description

[0011] Therefore, a detailed understanding of the foregoing features of this disclosure, a more specific description of this disclosure, and the foregoing brief overview can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of this disclosure and should therefore not be considered as limiting its scope, as this disclosure allows for other equally effective embodiments.

[0012] Figure 1 This is a schematic diagram of a magnetic media driver including a magnetic read head according to certain implementation schemes.

[0013] Figure 2A This is a schematic diagram of the cavity view of an HDD according to certain implementation schemes.

[0014] Figure 2B It is based on certain implementation plans. Figure 2A A schematic diagram of the abdominal view of an HDD.

[0015] Figure 3 It is a graph showing the distribution of repeatable sway (RRO) metadata values ​​according to certain implementation schemes.

[0016] Figure 4 This is a flowchart illustrating a method for programming metadata into the non-volatile memory of an HDD according to certain implementations.

[0017] For ease of understanding, the same reference numerals are used where possible to denote the same elements common in the accompanying drawings. It is conceivable that elements disclosed in one embodiment may be advantageously used in other embodiments without specific description. Detailed Implementation

[0018] In the following text, reference is made to embodiments of this disclosure. However, it should be understood that this disclosure is not limited to the specifically described embodiments. Rather, consider any combination of the following features and elements (whether or not related to different embodiments) to achieve and practice this disclosure. Furthermore, while embodiments of this disclosure may achieve advantages over other possible solutions and / or over the prior art, whether a particular advantage is achieved by a given embodiment is not a limitation of this disclosure. Therefore, the following aspects, features, embodiments, and advantages are illustrative only and should not be considered as elements or limitations of the appended claims unless expressly stated in the claims. Similarly, reference to “this disclosure” should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered as elements or limitations of the appended claims unless expressly stated in the claims.

[0019] This disclosure generally relates to data storage devices, such as hard disk drives (HDDs), and more specifically, to efficiently programming HDD metadata into the non-volatile memory of the HDD. The data storage device includes a hard disk drive coupled to a printed circuit board (PCB), a volatile memory device coupled to the PCB, a non-volatile memory device coupled to the PCB, and a controller coupled to the PCB, such that the controller communicates with the hard disk drive, the volatile memory device, and the non-volatile memory device. The controller is configured to recognize the pattern and / or structure of the hard disk drive's metadata, perform one or more of the following operations on the metadata to adjust the metadata: data shaping, content-aware decoding, adaptive data trimming, and / or adaptive block resizing, and write the adjusted metadata to the non-volatile memory device. The metadata is at least one of repeatable yaw metadata, location error signal metadata, adjacent track interference metadata, and / or emergency power failure metadata.

[0020] Figure 1 This is a schematic diagram of a magnetic media drive 100 including a magnetic write head and a magnetic read head according to certain embodiments. The magnetic media drive 100 may be a single drive / device or include multiple drives / devices. The magnetic media drive 100 includes a magnetic recording medium, such as one or more rotatable disks 112 supported on a spindle 114 and rotated by a drive motor 118. For ease of illustration, a single disk drive is shown according to one embodiment. Magnetic recording on each disk 112 is in the form of any suitable pattern of data tracks, such as a toroidal pattern of concentric data tracks (not shown) on the disk 112.

[0021] At least one slider 113 is positioned near the disk 112. Each slider 113 supports a head assembly 121, which includes one or more read / write heads, such as write heads and read heads including TMR devices. As the disk 112 rotates, the slider 113 moves radially in and out above the disk surface 122, allowing the head assembly 121 to access different tracks of the disk 112 for writing or reading desired data. Each slider 113 is attached to an actuator arm 119 via a suspension 115. The suspension 115 provides a slight spring force that biases the slider 113 toward the disk surface 122. Each actuator arm 119 is attached to an actuator 127. Figure 1 The actuator 127 shown may be a voice coil motor (VCM). The VCM includes a coil capable of moving within a fixed magnetic field, the direction and speed of which the coil moves are controlled by a motor current signal supplied by the control unit 129.

[0022] During operation of the magnetic media drive 100, the rotation of the disk 112 generates air or an air bearing between the slider 113 and the disk surface 122, which exerts an upward force or lift on the slider 113. Thus, during normal operation, the air or air bearing counteracts the slight spring force of the suspension 115 and holds the slider 113 away from and slightly above the disk surface 122 by a small, substantially constant distance.

[0023] Various components of the magnetic media drive 100 are controlled during operation by control signals such as access control signals and internal clock signals generated by the control unit 129. Typically, the control unit 129 includes logic control circuitry, storage devices, and a microprocessor. The control unit 129 generates control signals that control various system operations, such as drive motor control signals on line 123 and head position and seek control signals on line 128. The control signals on line 128 provide a desired current distribution to optimally move and position the slider 113 onto the desired data track on the disk 112. Write and read signals are transmitted to and from the head assembly 121 via the recording channel 125. Figure 1 Some implementations of the magnetic media actuator may also include multiple media or disks, multiple actuators and / or multiple sliders.

[0024] Figure 2A This is a schematic diagram of the cavity view of HDD 202 according to certain implementation schemes. Figure 2B It is based on certain implementation plans. Figure 2A This is a schematic diagram of the abdominal view of HDD 202. For simplicity, Figure 2A and Figure 2B Described collectively in this document, HDD 202 may include... Figure 1 The magnetic media drive 100 may include components similar to the magnetic media drive 100. In some examples, for clarity, the HDD 202 may include... Figure 2A and Figure 2B Additional components are not shown. In some examples, the physical dimensions and connector configuration of the HDD 202 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, 3.5" data storage devices, 2.5" data storage devices, 1.8" data storage devices, Peripheral Component Interconnect (PCI), PCI Expansion (PCI-X), and PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini Card, MiniPCI, etc.). In some examples, the HDD 202 may be directly coupled (e.g., directly soldered or inserted into a connector) to the motherboard of a host device.

[0025] HDD 202 includes an actuator arm 204 coupled to a read / write head 206, a plurality of rotatable disks 208, a spindle 210, a VCM 212, a printed circuit board (PCB) cable 214, a bottom housing 252, and a PCB 254 mounted to the bottom housing 252. The actuator arm 204 may be a series of actuator arms, each having a read / write head configured to interact with a specific rotatable disk among the plurality of rotatable disks 208. The plurality of rotatable disks 208 may be... Figure 1 The disk 112. Read / write heads 206 are configured to program data onto and read data from a plurality of rotatable disks 208, wherein the plurality of rotatable disks rotate about a spindle 210. The VCM 212 includes a coil capable of moving within a fixed magnetic field, wherein the direction and speed of the coil's movement are controlled by a VCM control unit such as... Figure 1 The control unit 129 controls the operation. The PCB cable 214 is a connection between components of the hard disk drive assembly, including but not limited to read / write heads 206, multiple rotatable disks 208, and PCB 254, enabling data transfer between the multiple rotatable disks 208 and PCB 254.

[0026] PCB 254 includes controller 256, PCB cable connector 258, non-volatile memory (NVM) 262, volatile memory 260, and connector 264. In some examples, for clarity, PCB 254 may include... Figure 2B Additional components, not shown, include conductive traces that electrically interconnect components of PCB 254 to other components of HDD 202. PCB cable connector 258 is coupled to PCB cable 214, enabling data transfer between PCB 254 and multiple swivel disks 208. PCB cable connector 258 is coupled to controller 256.

[0027] Controller 256 manages one or more operations of HDD 202. For example, controller 256 manages data reading from NVM 262 and / or data writing to NVM 262 and the multiple spinnerets 208. In some implementations, when HDD 202 receives a write command from a host device, controller 256 may initiate a data storage command to store data to NVM 262 or the multiple spinnerets 208 and monitor the progress of the data storage command. Controller 256 includes an error correction engine 266, which is configured to generate error correction codes and perform data configuration for data and metadata.

[0028] Connector 264 may be an interface for connection between the host device and HDD 202. Connector 264 may include one or both of a data bus for exchanging data with the host device and a control bus for exchanging commands with the host device. Connector 264 may operate according to any suitable protocol. For example, connector 264 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. Connector 264 (e.g., data bus, control bus, or both) is electrically connected to controller 256, thereby providing an electrical connection between the host device and controller 256, allowing data exchange between the host device and controller 256. In some examples, the electrical connection of connector 264 also allows HDD 202 to receive power from the host device.

[0029] NVM 262 may include multiple memory devices or storage units. NVM 262 may be configured to store and / or retrieve data. For example, a storage unit of NVM 262 may receive data and a message from controller 108 instructing the storage unit to store the data. Similarly, a storage unit may receive a message from controller 256 instructing the storage unit to retrieve data. In some examples, each storage unit in the storage unit may be referred to as a die. In some examples, NVM 262 may include multiple dies (e.g., multiple storage units). In some examples, each storage unit may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

[0030] In some examples, each memory cell may include any type of non-volatile memory device, such as flash memory device, phase-change memory (PCM) device, resistive random access memory (ReRAM) device, magnetoresistive random access memory (MRAM) device, ferroelectric random access memory (F-RAM), holographic memory device, and any other type of non-volatile memory device.

[0031] The NVM 262 may include multiple flash memory devices or memory cells. The NVM flash memory device may include NAND- or NOR-based flash memory devices and may store data based on the charge in the floating gate of the transistor contained in each flash memory cell. In the NVM flash memory device, the flash memory device may be divided into multiple dies, each of which includes multiple physical or logical blocks, which may be further divided into multiple pages. Each of the multiple blocks within a particular memory device may include multiple NVM cells. Rows of NVM cells may be electrically connected using word lines to define pages within the multiple pages. A corresponding cell in each page of the multiple pages may be electrically connected to a corresponding bit line. Furthermore, the NVM flash memory device may be a 2D or 3D device and may be a single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), or four-level cell (QLC). The controller 108 may write data to and read data from the NVM flash memory device at the page level and erase data from the NVM flash memory device at the block level.

[0032] Volatile memory 260 may be used by controller 256 to store information. Volatile memory 260 may include one or more volatile memory devices. In some examples, controller 256 may use volatile memory 260 as a cache. For example, controller 256 may store cached information in volatile memory 260 until the cached information is written to NVM 262. Examples of volatile memory 260 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)).

[0033] Metadata may be stored in one or more of the following storage elements: NVM 262, volatile memory 260, multiple swivel disks 208, or a combination of the previously listed storage elements. Metadata may be categorized based on data type and / or data characteristics such as non-uniformly distributed data, write speed requirements, and durability requirements. Non-uniformly distributed data can be manipulated using data profiling and content-aware decoding. For example, centralized data is a type of non-uniformly distributed data. Write speed requirements may include determining which trimmings and / or partitions of SLC memory, MLC memory, TLC memory, QLC memory, etc., are programmed into the data based on the programming speed associated with the data being programmed. For example, Repeatable Oscillation (RRO) metadata, Position Error Signal (PES) metadata, Adjacent Track Interference (ATI) metadata, and Emergency Power Outage (EPO) metadata may be data types with write speed requirements. Durability requirements may differ between metadata types. For example, RRO metadata may not require high-endurance memory because it is written only once and therefore can be written to TLC memory. In another example, PES metadata and ATI metadata may require high-endurance memory.

[0034] It should be understood that other types of metadata not described herein may be applicable to the implementations described herein. For example, metadata with offsets is envisioned, where those offsets are centered around one or more values. During the production of the memory device, RRO metadata is measured and recorded, such as during initial testing of multiple swivel disks 208, NVM 262, and volatile memory 260. In some examples, RRO metadata is measured and recorded once. PES metadata is measured and recorded during each sector write of the multiple swivel disks 208. ATI metadata includes information on the count of adjacent track writes during HDD 202 operation. EPO metadata is refreshed during abnormal shutdown events to allow for rapid recovery when power is restored.

[0035] Typically, metadata is stored in volatile memory 260, such as DRAM. However, because stored metadata can be aggregated into a larger size, it can instead be stored in NVM 262. NVM 262 can have a larger capacity than volatile memory 260 and includes different memory partitions, such as SLC memory, MLC memory, TLC memory, QLC memory, PLC memory, etc., for storing different metadata types. For example, since RRO metadata is generated and recorded once, it can be programmed into TLC memory. Similarly, due to durability and speed issues, PES metadata, ATI metadata, and EPO metadata can be programmed into SLC memory. PES and ATI metadata can be stored in a first SLC memory trimming, and EPO metadata can be stored in a second SLC memory trimming. SLC memory trimming can refer to the speed and durability of the SLC memory. For example, the second SLC memory trimming may be faster in operation than the first SLC memory trimming. However, the first SLC memory trimming may have greater durability than the first SLC memory trimming.

[0036] Additionally, metadata types can be stored in metadata blocks of various sizes within the NVM 262's associated memory. For example, EPO metadata can utilize large metadata blocks, and EPO metadata can be programmed into these large metadata blocks using dual-plane writes. In another example, PES metadata and ATI metadata can utilize metadata blocks smaller than the aforementioned large metadata blocks, where the smaller metadata blocks can be based on a single plane.

[0037] Furthermore, one or more types of adjustments may be adopted or performed by the controller 256 or, in other examples, by the iterative content-aware decoder before the metadata is programmed into the NVM 262. In a non-limiting example, one or more types include at least data configuration and content-aware decoding. Data configuration utilizes low data entropy to configure the metadata (or, in other examples, data) in a manner that may result in less wear in each programming / erasing cycle. For example, data configuration may include transforming the metadata such that the number (e.g., probability) of 1 bits included in the bit distribution of the metadata when programmed into the NVM 262 is greater than 0 bits. In one example, the input sequence has a first number of 1 bits and a second number of 0 bits, and the output sequence has a second number of 1 bits and a second number of 0 bits. The first number of 1 bits is less than the first number of 0 bits, and the second number of 1 bits is greater than the second number of 0 bits. The input and output sequences have the same size. In one example, data configuration may reduce the amount of programmed SLC storage cells by approximately 4 times. Furthermore, data configuration can be performed transparently without firmware involvement because data configuration maps 4KB of raw data to 4KB of configured data. Therefore, there is no need to manage the mapping from logic to variable physical size.

[0038] Content-aware decoding leverages low data entropy and data characteristics to enhance error-correcting code (ECC) capabilities. While ECC data is illustrated, other data reliability data, such as XOR parity data, can also be applied. Controller 256 can analyze metadata and predict one or more characteristics of the metadata. The metadata may have at least one of the following: sparse regions with zero-padding, regions with counter behavior, regions with byte repetition, and regions with non-uniformly distributed random data.

[0039] Zero-padding refers to a segment completely filled with zeros, which can be indicated to the decoder to improve error correction capability because the probability of knowing a 0 bit is greater than the probability of knowing a 1 bit. Counter behavior can refer to a segment filled with counter data. For example, when compared with the previous byte or two bytes (e.g., 0x00, 0x01, 0x02, 0x03, 0x04, etc.), each pair of bytes increments by 1. For counter data, the decoder of controller 256, such as a content-aware decoder or an iterative content-aware decoder, can take advantage of the fact that many bits change slowly. For example, in a byte pattern including 0x00, 0x01, 0x02, 0x03, and 0x04, the most significant byte in each pair of bytes remains 0 for a long period. In this example, the content-aware decoder can increase the probability of decoding the most significant byte in each pair of bytes as a 0 bit.

[0040] Byte repetition can refer to the periodic repetition of a constant byte value, or the repetition of a number of bytes at regular intervals. Content-aware decoders can track highly repetitive bytes and increase the probability of decoding such byte values. Random data with a non-uniform distribution refers to random data with one or more byte values ​​that are more common than others. Content-aware decoders can improve decoding capabilities by understanding that one or more byte values ​​are more common than others.

[0041] By determining one or more characteristics of the metadata, a decoder such as error correction engine 266 (or a decoder separate from controller 256) can predict one or more bit combinations before receiving relevant metadata such as RRO metadata. The prediction of one or more bit combinations can be used by error correction engine 266 to improve decoding latency and decoding accuracy.

[0042] Furthermore, the controller 256 can be combined or integrated with data configurations to utilize or perform content-aware decoding. When the metadata has low entropy, the metadata can be configured such that the number of 1-bits included in the metadata is greater than 0 bits. Additionally, an estimate of the number of 1-bits can be provided to the decoder, thereby improving correction capabilities and decoding latency. The log-likelihood ratio (LLR) per bit can be adjusted using the following formula:

[0043]

[0044] Where y indicates the received bit array, Pr{y / bit i Let y = 0 be the probability of receiving y when the original value of the i-th bit of the codeword is 0, and p be the probability that a bit in the codeword or metadata has a bit value of 1. For example, p can be estimated by counting the number of 1 bits in the representation of the codeword or metadata. In the final equation, It can be determined from the LLR table stored in the relevant memory device of HDD202. Furthermore, It is a correction term determined by the probability of 1 bit in the codeword or metadata.

[0045] In one example, PES metadata can be adjusted by performing data shaping, adaptive data trimming, or adaptive block size adjustment. In another example, EPO metadata can be adjusted by performing adaptive data trimming or adaptive block size adjustment. In yet another example, RRO metadata can be adjusted by performing data shaping or content-aware decoding.

[0046] In one example, adjusting PES metadata or ATI metadata includes performing at least two of data configuration, adaptive data trimming, and / or adaptive block size adjustment. In another example, adjusting EPO metadata includes performing adaptive data trimming and adaptive block size adjustment. In yet another implementation, adjusting RRO metadata includes performing data configuration and content-aware decoding.

[0047] Figure 3 This is a graph 300 illustrating the distribution of Repeatable Oscillation (RRO) metadata values ​​according to certain implementation schemes. The RRO metadata value distribution is predominantly zero and near-zero values. This skewed distribution towards zero and near-zero values ​​allows for efficient compression techniques, such as data shaping and content-aware decoding, to be used on RRO metadata. RRO data includes information used for compressing head components such as... Figure 1 The head position of the head assembly 121 is aligned with the actual track center by a correction value (or offset). Therefore, when a histogram of the RRO values ​​is created, a distribution near zero with zero values ​​and near-zero values ​​is generated. The X-axis of chart 300 corresponds to the correction value, and the Y-axis of chart 300 corresponds to the total value of each value (as shown in the histogram).

[0048] Figure 4 This is a flowchart illustrating a method 400 for programming metadata into a non-volatile memory, such as according to certain embodiments. Figure 2B NVM 262, such as Figure 2A and Figure 2B HDD 202. Figure 2A and Figure 2BVarious aspects may be used for illustrative purposes in the description herein. For example, method 400 may be adopted or performed by controller 256.

[0049] At box 402, controller 256 receives a write command from the host device for writing data to HDD 202. Based on the write command, write command data can be programmed to NVM 262 or one or more of the multiple swivel disks 208. At box 404, controller 256 generates metadata for the write command data. The metadata can be RRO metadata, PES metadata, ATI metadata, EPO metadata, or a combination of previously listed metadata. At box 406, controller 256 identifies the metadata type.

[0050] At box 408, controller 256 applies data manipulation and / or encoding schemes to the identified metadata type. Data manipulation and / or encoding schemes may be performed by error correction engine 266. For example, PES metadata and ATI metadata can be tuned by performing data shaping on the metadata. In another example, RRO metadata can be tuned by performing data shaping, content-aware decoding, or both.

[0051] At block 410, controller 256 programs the modified metadata to the relevant memory location of NVM 262. For example, controller 256 can program PES metadata and ATI metadata to a first SLC memory trimming and EPO metadata to a second SLC memory trimming, wherein the first SLC memory trimming has greater durability but lower speed than the second SLC memory trimming. PES metadata and ATI metadata can be programmed into a single-plane metablock, while EPO metadata can be programmed into a larger metablock using dual-plane writes compared to the metablocks associated with PES metadata and ATI metadata. Similarly, controller 256 can program RRO metadata to TLC memory.

[0052] By identifying, adapting, and programming different types of metadata, including NVM HDDs, more efficient programming, reduced NVM costs, reduced volatile memory costs, improved lifetime, and reduced power consumption can be achieved.

[0053] In one embodiment, the data storage device includes a hard disk drive coupled to a printed circuit board, a volatile memory device coupled to a printed circuit board, a non-volatile memory device coupled to a printed circuit board, and a controller coupled to the printed circuit board, such that the controller communicates with the hard disk drive, the volatile memory device, and the non-volatile memory device. The controller is configured to recognize the pattern and / or structure of metadata of the hard disk drive, perform one or more of the following operations on the metadata to adjust the metadata: data shaping, content-aware decoding, adaptive data trimming, and / or adaptive block size resizing, and write the adjusted metadata to the non-volatile memory device. The pattern and / or structure of the metadata includes non-uniformly distributed data, data write speed requirements, and data durability requirements.

[0054] Metadata is at least one of the following: Repeatable Oscillation (RRO) metadata, Position Error Signal (PES) metadata, Adjacent Track Interference (ATI) metadata, Emergency Power Outage (EPO) metadata, and / or metadata centered on one or more values. The non-volatile memory device includes single-level cell (SLC) or three-level cell (TLC) modules. The SLC includes a first SLC trimming and a second SLC trimming. EPO metadata is stored in the first SLC trimming. PES and ATI metadata are stored in the second SLC trimming. RRO metadata is stored in the TLC. Trimming includes adjusting the EPO metadata using a first single-level cell (SLC) trimming with a first speed. Trimming includes adjusting the PES or ATI metadata using a second SLC trimming with a second speed slower than the first speed. The second SLC trimming has higher durability than the first SLC trimming. Writing the adjusted EPO metadata includes writing to a dual-plane module. Writing the adjusted PES or ATI metadata includes writing to a single plane module. Adjustments include performing at least two of the following on PES or ATI metadata: data shaping, adaptive data trimming, and / or adaptive chunk size adjustment. Adjustments include performing adaptive data trimming and adaptive chunk size adjustment on EPO metadata. Adjustments include performing data shaping and content-aware decoding on RRO metadata.

[0055] In another embodiment, the data storage device includes a printed circuit board, one or more rotatable disks coupled to the printed circuit board, a volatile memory device coupled to the printed circuit board, a non-volatile memory device coupled to the printed circuit board, and a controller coupled to the printed circuit board, such that the controller communicates with the one or more rotatable disks, the volatile memory device, and the non-volatile memory device. The controller is configured to recognize the pattern and / or structure of the positioning error signal (PES) metadata or adjacent track interference (ATI) metadata of the hard disk drive, adjust the PES metadata or ATI metadata using data configuration, and write the adjusted PES metadata or ATI metadata to the single-level cell (SLC) memory of the non-volatile memory device.

[0056] The controller includes an error correction engine, which is configured to execute a data configuration. Adjustment involves converting an input sequence with a number of programming bits greater than the number of erase bits into an output sequence with a second number of programming bits less than the second number of erase bits. The input and output sequences have equal data sizes.

[0057] In another embodiment, the data storage device includes a printed circuit board, one or more rotatable disks coupled to the printed circuit board, a volatile memory device coupled to the printed circuit board, a non-volatile memory device coupled to the printed circuit board, and a controller coupled to the printed circuit board, such that the controller communicates with the one or more rotatable disks, the volatile memory device, and the non-volatile memory device. The controller is configured to recognize the pattern and / or structure of repeatable sway (RRO) metadata of the hard disk drive, adjust the RRO metadata using content-aware decoding, and write the adjusted RRO metadata to the three-level cell (TLC) memory of the non-volatile memory device.

[0058] The identified patterns and / or structures include at least one of the following: sparse regions with zero padding, regions with counter behavior, regions with byte repetition, and regions with non-uniformly distributed random data. The controller includes a decoder. The decoder is configured to receive the identified patterns and / or structures and, prior to decoding the RRO metadata, predict one or more bit combinations based on the received identified patterns and / or structures.

[0059] While the foregoing describes embodiments of this disclosure, other and additional embodiments of this disclosure may be contemplated without departing from the basic scope of this disclosure, the scope of which is defined by the appended claims.

Claims

1. A data storage device, the data storage device comprising: A hard disk drive, which is coupled to a printed circuit board; A volatile memory device coupled to the printed circuit board; A non-volatile memory device coupled to the printed circuit board; A controller, coupled to the printed circuit board, wherein the controller communicates with the hard disk drive, the volatile memory device, and the non-volatile memory device, wherein the controller is configured to: Identify the pattern and / or structure of the metadata of the hard disk drive, wherein the pattern and / or structure of the metadata includes non-uniformly distributed data, data write speed requirements, and data durability requirements; Based on the identified pattern and / or structure, one or more of the following are performed on the metadata to adjust the metadata: data configuration, content-aware decoding, adaptive data trimming, and / or adaptive meta-block size adjustment; as well as Write the adjusted metadata to the non-volatile memory device; and The metadata is at least one of the following: repeatable yaw metadata, location error signal metadata, adjacent track interference metadata, emergency power failure metadata, and / or metadata centered on one or more values.

2. The data storage device according to claim 1, wherein the non-volatile memory device comprises a single-level cell or a three-level cell, and wherein the single-level cell comprises a first single-level cell trimming and a second single-level cell trimming.

3. The data storage device according to claim 2, wherein the emergency power failure metadata is stored in the first single-level unit trimming.

4. The data storage device according to claim 3, wherein the positioning error signal metadata and the adjacent track interference metadata are stored in the second single-stage unit trimming.

5. The data storage device according to claim 1, wherein the repeatable sway metadata is stored in a three-level unit.

6. The data storage device of claim 1, wherein the adjustment includes adjusting emergency power failure metadata using a first single-stage cell trimming having a first speed.

7. The data storage device of claim 6, wherein the adjustment includes adjusting the positioning error signal metadata or adjacent track interference metadata using a second single-stage unit trimming having a second speed slower than the first speed.

8. The data storage device according to claim 7, wherein the second single-level cell trimming has higher durability than the first single-level cell trimming.

9. The data storage device of claim 1, wherein writing the adjusted emergency power failure metadata includes writing to a dual-plane system.

10. The data storage device of claim 1, wherein writing the adjusted positioning error signal metadata or adjacent track interference metadata comprises writing to a single plane.

11. The data storage device of claim 1, wherein the adjustment includes performing at least two of the following on the positioning error signal metadata or the adjacent track interference metadata: data shaping, adaptive data trimming, and / or adaptive block size adjustment.

12. The data storage device of claim 1, wherein the adjustment includes performing adaptive data trimming and adaptive block size adjustment on the emergency power failure metadata.

13. The data storage device of claim 1, wherein the adjustment includes performing data shaping and content-aware decoding on the repeatable skew metadata.

14. A data storage device, the data storage device comprising: Printed circuit boards; One or more rotatable disks, said one or more rotatable disks being coupled to the printed circuit board; A volatile memory device coupled to the printed circuit board; A non-volatile memory device coupled to the printed circuit board; and A controller, coupled to the printed circuit board, is configured to communicate with the one or more rotatable disks, the volatile memory device, and the non-volatile memory device, wherein the controller is configured to: Identify the pattern and / or structure of hard drive positioning error signal metadata or adjacent track interference metadata; Based on the identified patterns and / or structures, data configuration is used to adjust the positioning error signal metadata or the adjacent track interference metadata; as well as The adjusted positioning error signal metadata or adjacent track interference metadata is written to the single-level cell memory of the non-volatile memory device.

15. The data storage device of claim 14, wherein the controller includes an error correction engine, and wherein the error correction engine is configured to perform the data configuration.

16. The data storage device of claim 14, wherein the adjustment comprises converting an input sequence having a number of programming bits greater than the number of erase bits into an output sequence having a second number of programming bits less than a second number of erase bits, and wherein the data sizes of the input sequence and the output sequence are equal.

17. A data storage device, the data storage device comprising: Printed circuit boards; One or more rotatable disks, said one or more rotatable disks being coupled to the printed circuit board; A volatile memory device coupled to the printed circuit board; A non-volatile memory device coupled to the printed circuit board; and A controller, coupled to the printed circuit board, is configured to communicate with the one or more rotatable disks, the volatile memory device, and the non-volatile memory device, wherein the controller is configured to: Identify the patterns and / or structure of repeatable yaw metadata of hard drives; Based on the identified patterns and / or structures, content-aware decoding is used to adjust the repeatable skew metadata; as well as The adjusted repeatable yaw metadata is written to the level 3 cell memory of the non-volatile memory device.

18. The data storage device of claim 17, wherein the identified pattern and / or structure includes at least one of the following: Sparse regions with zero fill; Regions exhibiting counter behavior; Regions with repeated bytes; as well as A region with non-uniformly distributed random data.

19. The data storage device of claim 18, wherein the controller includes a decoder, wherein the decoder is configured to: Receive the identified pattern and / or structure; and Before decoding the repeatable yaw metadata, one or more bit combinations are predicted based on the received and identified patterns and / or structures.

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