Methods, storage media, and devices for moving multiple data items based on a single instruction.

Abstract

This disclosure relates to a method, storage medium, computing device, integrated circuit device, and board for moving N data items within a processor core based on a single instruction. The computing device of this disclosure is embodied in a computing processing unit within a combined processing unit, which may further include a general interconnect interface and other processing units. The computing processing unit interacts with other processing units to jointly complete user-specified computational operations. The combined processing unit may also include a storage device connected to both the computing processing unit and other processing units for storing data from those units. The solution of this disclosure enables fast and efficient data loading.

Description

Technical Field

[0001] This disclosure generally relates to the field of artificial intelligence technology. More specifically, this disclosure relates to a method, storage medium, computing device, integrated circuit device, and circuit board for moving N data items in a processor core based on a single instruction. Background Technology

[0002] Neural networks are powerful algorithms that have been widely used in various fields such as image recognition and language processing in recent years. The emergence of intelligent processors has further enabled neural networks to have hardware support and perform calculations more efficiently.

[0003] Intelligent processors typically require specific instruction sets, which contain multiple execution instructions. In certain scenarios (such as sparse matrix multiplication and radar algorithms), preceding instructions use vector computation instructions to calculate the parameters (such as address and size) needed by subsequent instructions. When subsequent instructions require these parameters, they read data from memory and store it in registers for use by later instructions. In these scenarios, memory is accessed frequently, and how to quickly and efficiently load multiple data items from memory into registers is one of the pressing problems that needs to be solved. Summary of the Invention

[0004] In view of the technical problems mentioned in the background section, this disclosure provides a scheme for moving N data items within a processor core based on a single instruction. This scheme allows for the movement of multiple data items based on a single instruction, thereby enabling fast and efficient data loading.

[0005] In one aspect, this disclosure provides a method for moving N data items in a processor core based on a single instruction. The instruction comprises N instruction groups, each instruction group controlling the movement of one data item and including an enable domain and a control domain. The control domain includes an address domain and a coordinate domain. The processor core includes a neuron storage unit and an instruction decoding unit. The method includes: determining whether each of the N instruction groups is enabled from its enable domain; if so, performing the following steps: obtaining read address information from the address domain of the control domain of the same instruction group; obtaining write coordinate information from the coordinate domain of the control domain of the same instruction group; reading target data from the neuron storage unit according to the read address information, wherein the target data is one of the N data items; and writing the target data into a temporary register group of the instruction decoding unit according to the write coordinate information; wherein N is a positive integer greater than 1.

[0006] In another aspect, this disclosure provides a computer-readable storage medium having stored thereon computer program code that moves N data items in a processor core based on an instruction, wherein the aforementioned method is executed when the computer program code is run by a processing device.

[0007] In another aspect, this disclosure provides a computing device for moving N data items within a processor core based on a single instruction. The instruction comprises N instruction sets, each instruction set controlling the movement of one data item and including an enable domain and a control domain. The control domain includes an address domain and a coordinate domain. The computing device includes multiple clusters, each cluster including multiple processor cores. Each processor core includes a storage module and a control module.

[0008] The storage module includes a neuron storage unit for storing the N data items, wherein the N data items are one of the feature maps and intermediate results calculated by the processor core, and N is a positive integer greater than 1. The control module includes an instruction decoding unit, which is used to: determine whether each of the N instruction groups is enabled from its enable field; if so, obtain read address information from the address field in the control field of the same instruction group; obtain write coordinate information from the coordinate field in the control field of the same instruction group; read target data from the neuron storage unit according to the read address information, wherein the target data is one of the N data items; and write the target data into the temporary register group of the instruction decoding unit according to the write coordinate information.

[0009] In another aspect, this disclosure provides an integrated circuit device including the aforementioned computing device, and also provides a board including the aforementioned integrated circuit device.

[0010] According to the solutions provided in the above-mentioned aspects of this disclosure, a technical means can be realized to move multiple data based on a single instruction, thereby achieving the technical effect of fast and efficient data loading. Attached Figure Description

[0011] The above and other objects, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the present disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0012] Figure 1 This is a structural diagram of a board according to an embodiment of the present disclosure;

[0013] Figure 2 This is a structural diagram illustrating an integrated circuit device according to an embodiment of the present disclosure;

[0014] Figure 3 This is a schematic diagram showing the internal structure of a single-core computing device according to an embodiment of the present disclosure;

[0015] Figure 4 This is a schematic diagram showing the internal structure of a multi-core computing device according to an embodiment of the present disclosure;

[0016] Figure 5 This is a schematic diagram illustrating the internal structure of a processor core according to an embodiment of the present disclosure;

[0017] Figure 6 This is a schematic diagram showing the internal structure of the instruction decoding unit according to an embodiment of the present disclosure;

[0018] Figure 7 This is a schematic diagram illustrating GLD instructions applicable to embodiments of this disclosure;

[0019] Figure 8 This is a schematic diagram illustrating the structure of a register group according to an embodiment of the present disclosure;

[0020] Figure 9 This is a flowchart illustrating a method for moving multiple data based on GLD instructions according to another embodiment of this disclosure; and

[0021] Figure 10 This is a flowchart illustrating a method for moving N data points based on GLD instructions according to yet another embodiment of this disclosure. Detailed Implementation

[0022] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure, and the multiple described embodiments can be appropriately combined according to different scenarios to achieve different applications. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0023] It should be understood that the terms "first," "second," and "third," etc., that may be used in the claims, specification, and drawings of this disclosure are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "including" as used in the specification and claims of this disclosure indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0024] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0025] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0026] The specific embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0027] Figure 1 This diagram illustrates the structure of a board 10 according to an embodiment of the present disclosure. The board 10 includes a chip 101, which is a system-on-chip (SoC). In one implementation scenario, it integrates one or more combined processing devices. These combined processing devices are artificial intelligence computing units used to support various deep learning and machine learning algorithms, meeting the intelligent processing needs of complex scenarios in fields such as computer vision, speech, natural language processing, and data mining. Deep learning technology is particularly prevalent in cloud-based intelligent applications. A significant characteristic of cloud-based intelligent applications is the large volume of input data, placing high demands on the platform's storage and computing capabilities. The board 10 of this embodiment is suitable for cloud-based intelligent applications, possessing massive off-chip storage, on-chip storage, and powerful computing capabilities.

[0028] As further shown in the figure, chip 101 is connected to external device 103 via external interface device 102. Depending on the application scenario, external device 103 may be, for example, a server, computer, camera, monitor, mouse, keyboard, network card, or Wi-Fi interface. Data to be processed is transmitted from external device 103 to chip 101 via external interface device 102. The calculation results from chip 101 are transmitted back to external device 103 via external interface device 102. Depending on the application scenario, external interface device 102 may have different interface types, such as a PCIe interface.

[0029] The board 10 also includes a storage device 104 for storing data, which includes one or more memory cells 105. The storage device 104 is connected to and transmits data with the controller 106 and the chip 101 via a bus. The controller 106 in the board 10 can be configured to regulate the state of the chip 101. For this purpose, in one application scenario, the controller 106 may include a microcontroller (MCU).

[0030] Figure 2 This is a structural diagram illustrating the combined processing apparatus in chip 101 according to the above embodiment. Figure 2 As shown, the combined processing device 20 includes a computing device 201, an interface device 202, a processing device 203, and off-chip memory 204 of dynamic random access memory (DRAM).

[0031] The computing device 201 is configured to perform user-specified operations, primarily implemented as a single-core or multi-core intelligent processor. In some operations, it performs deep learning or machine learning calculations and also interacts with the processing device 203 via the interface device 202 to jointly complete the user-specified operations.

[0032] Interface device 202 is used to transmit data and control commands between computing device 201 and processing device 203. For example, computing device 201 obtains input data from processing device 203 via interface device 202 and writes it to on-chip storage device of computing device 201. Further, computing device 201 obtains control commands from processing device 203 via interface device 202 and writes them to on-chip control cache of computing device 201. Alternatively or optionally, interface device 202 may also read data from storage device of computing device 201 and transmit it to processing device 203.

[0033] The processing device 203, as a general-purpose processing device, performs basic controls including but not limited to data transfer and starting and / or stopping the computing device 201. Depending on the implementation, the processing device 203 may be one or more types of processors, including but not limited to digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, the computing device 201 of this disclosure can be considered to have a single-core structure or a homogeneous multi-core structure. However, when the computing device 201 and the processing device 203 are considered together, they are considered to form a heterogeneous multi-core structure.

[0034] The off-chip memory 204 is used to store data to be processed. It is DDR memory, typically 16G or larger, and is used to store data of computing device 201 and / or processing device 203.

[0035] Figure 3 The diagram shows the internal structure of the single-core computing device 201. The single-core computing device 301 is used to process input data such as computer vision, speech, natural language, and data mining. The single-core computing device 301 includes three main modules: a control module 31, a processing module 32, and a storage module 33.

[0036] The control module 31 coordinates and controls the operation of the computation module 32 and the storage module 33 to complete the deep learning task. It includes an instruction fetch unit (IFU) 311 and an instruction decode unit (IDU) 312. The instruction fetch unit 311 fetches instructions from the processing device 203, and the instruction decode unit 312 decodes the fetched instructions and sends the decoding result as control information to the computation module 32 and the storage module 33.

[0037] The computation module 32 includes a vector operation unit 321 and a matrix operation unit 322. The vector operation unit 321 is used to perform vector operations and can support complex operations such as vector multiplication, addition, and nonlinear transformations; the matrix operation unit 322 is responsible for the core computations of deep learning algorithms, namely matrix multiplication and convolution.

[0038] Storage module 33 is used to store or move relevant data, including neuron RAM (NRAM) 331, weight RAM (WRAM) 332, and direct memory access (DMA) module 333. NRAM 331 is used to store input neurons, output neurons, and intermediate results after computation; WRAM 332 is used to store the convolution kernels of the deep learning network, i.e., the weights; DMA 333 is connected to external memory 204 through bus 34 and is responsible for data transfer between the single-core computing device 301 and external memory 204.

[0039] Figure 4 The diagram illustrates the internal structure of the computing device 201 in the combined processing device 20 as a multi-core unit. The multi-core computing device 41 can employ a hierarchical design, functioning as a system-on-a-chip (SoC) comprising at least one cluster, with each cluster containing multiple processor cores. In other words, the multi-core computing device 41 is structured in a hierarchical manner of SoC-cluster-processor core. From the perspective of the SoC hierarchy, as... Figure 4 As shown, the multi-core computing device 41 includes an external storage controller 401, a peripheral communication module 402, an on-chip interconnect module 403, a synchronization module 404, and multiple clusters 405.

[0040] There can be multiple external storage controllers 401 (two are shown as an example in the figure), which are used to respond to access requests issued by the processor core to access external storage devices, i.e., off-chip memory 204, thereby reading data from or writing data to the off-chip memory. The peripheral communication module 402 is used to receive control signals from the processing device 203 through the interface device 202 and to start the computing device 201 to execute tasks. The on-chip interconnect module 403 connects the external storage controllers 401, the peripheral communication module 402, and multiple clusters 405 to transmit data and control signals between the modules. The synchronization module 404 is a Global Barrier Controller (GBC) used to coordinate the working progress of each cluster and ensure information synchronization. In this embodiment, the multiple clusters 405 are the computing cores of the multi-core computing device 41. Although in Figure 4The example shows four clusters; however, with the development of hardware, the multi-core computing device 41 of this embodiment may also include eight, sixteen, sixty-four, or even more clusters 405. In one application scenario, cluster 405 can be used to efficiently execute deep learning algorithms.

[0041] From the perspective of cluster hierarchy, such as Figure 4 As shown, each cluster 405 may include multiple processor cores (IPU cores) 406 and one memory core (MEM core) 407.

[0042] The processor core 406 is exemplarily shown as four in the figure. This disclosure does not limit the number of processor cores 406, and its internal architecture is as follows. Figure 5 As shown. Each processor core 406 is similar to Figure 3 The single-core computing device 301 can also include three modules: a control module 51, an arithmetic module 52, and a storage module 53. The functions and structures of the control module 51, arithmetic module 52, and storage module 53 are largely the same as those of the control module 31, arithmetic module 32, and storage module 33, and will not be repeated here. The following description will focus on the operation of the multi-core computing device 201. Unless otherwise specified, the technical description of the multi-core computing device 201 can be extended to... Figure 3 The single-core computing device 301.

[0043] It should be noted that the storage module 53 may include an Input / Output Direct Memory Access (IODMA) module 533 and a Move Direct Memory Access (MVDMA) module 534. The IODMA 533 controls the memory access of NRAM 531 / WRAM 532 and off-chip memory 204 through the broadcast bus 409; the MVDMA 534 is used to control the memory access of NRAM 531 / WRAM 532 and SRAM 408.

[0044] Back Figure 4 The storage core 407 is primarily used for storage and communication, namely storing shared data or intermediate results among processor cores 406, and for communication between the execution cluster 405 and off-chip memory 204, communication between clusters 405, and communication between processor cores 406. In other embodiments, the storage core 407 may have scalar operation capabilities to perform scalar operations.

[0045] Storage core 407 includes shared random-access memory (SRAM) 408, a broadcast bus 409, a cluster direct memory access (CDMA) module 410, and a global direct memory access (GDMA) module 411. In one implementation scenario, SRAM 408 can act as a high-performance data relay station. Therefore, data multiplexed between different processor cores 406 within the same cluster 405 does not need to be obtained from off-chip memory 204 by each processor core 406, but is instead relayed between processor cores 406 via SRAM 408. Furthermore, storage core 407 only needs to quickly distribute multiplexed data from SRAM 408 to multiple processor cores 406, thereby improving inter-core communication efficiency and significantly reducing on-chip and off-chip I / O access.

[0046] Broadcast bus 409, CDMA 410, and GDMA 411 are used to perform communication between processor cores 406, communication between clusters 405, and data transfer between cluster 405 and off-chip memory 204, respectively. These will be explained below.

[0047] The broadcast bus 409 is used to complete high-speed communication between the processor cores 406 within the cluster 405. In this embodiment, the broadcast bus 409 supports inter-core communication methods including unicast, multicast, and broadcast. Unicast refers to point-to-point (e.g., data transmission from one processor core to another) data transmission. Multicast is a communication method that transmits a piece of data from SRAM 408 to several specific processor cores 406. Broadcast is a communication method that transmits a piece of data from SRAM 408 to all processor cores 406, and is a special case of multicast.

[0048] CDMA 410 is used to control memory access to SRAM 408 between different clusters 405 within the same computing device 201. GDMA 411 works in conjunction with the external memory controller 401 to control memory access from SRAM 408 of cluster 405 to off-chip memory 204, or to read data from off-chip memory 204 into SRAM 408. As described above, communication between off-chip memory 204 and NRAM 531 or WRAM 532 can be achieved in two ways. The first way is to communicate directly with off-chip memory 204 and NRAM 531 or WRAM 532 via IODAM 433; the second way is to first transfer data between off-chip memory 204 and SRAM 408 via GDMA 411, and then transfer data between SRAM 408 and NRAM 531 or WRAM 532 via MVDMA 534. Although the second approach may require more components and has a longer data flow, in some embodiments, the bandwidth of the second approach is significantly greater than that of the first approach. Therefore, performing communication between off-chip memory 204 and NRAM 531 or WRAM 532 using the second approach may be more efficient. It is understood that the data transmission methods described herein are merely exemplary, and those skilled in the art can flexibly select and apply various data transmission methods according to the specific hardware arrangement based on the teachings of this disclosure.

[0049] In other embodiments, the functions of GDMA 411 and IODMA 533 can be integrated into the same component. Although this embodiment treats GDMA 411 and IODMA 533 as different components for ease of description, those skilled in the art will recognize that any implementation with similar functionality and technical effects falls within the scope of this disclosure. Furthermore, the functions of GDMA 411, IODMA 533, CDMA 410, and MVDMA 534 can also be implemented by the same component.

[0050] Figure 6 A partial internal structure diagram of the instruction decoding unit 512 according to this embodiment is shown. Figure 6 The structure is used to process GLD instructions. A GLD instruction is a control instruction that retrieves data from storage module 53, temporarily stores it in control module 51, and then uses the arithmetic module 52 for further processing or sends it to SRAM 408. For example... Figure 6As shown, the instruction decoding unit 512 includes a non-scalar temporary register 601, a load temporary register 602, a register group 603, and a synchronization table entry 604. The load temporary register 602 includes a demultiplexer 605, a first-in-first-out (FIFO) memory for order-preserving instructions 606, a FIFO memory for non-order-preserving instructions 607, and an output control module 608. The output control module 608 includes a multiplexer 609, an instruction decoder 610, an order-preserving commit queue 611, and a non-order-preserving commit queue 612.

[0051] The non-scalar register 601 is a first-in-first-out register used to receive GLD instructions from the instruction fetch unit 511 and remove the temporary space dependencies of other operations other than the write-after-write dependency of multiple vector load operations on the same temporary space, and send the de-dependency instructions to the load register 602.

[0052] The demultiplexer 605 in the load register 602 is used to select whether to send the instruction to the order-preserving instruction FIFO memory 606 or the non-order-preserving instruction FIFO memory 607, depending on whether the input instruction needs to be preserved in order. If order preservation is required, the instruction is sent to the order-preserving instruction FIFO memory 606. For example, instructions that need to be preserved in order include load instructions and store instructions. If order preservation is not required, the instruction is sent to the non-order-preserving instruction FIFO memory 607. It should be noted that "order preservation" and "non-order preservation" here only indicate whether the instructions are sequentially dependent.

[0053] The output control module 608 is used to select an executable instruction from either the ordered instruction FIFO memory 606 or the non-ordered instruction FIFO memory 607 and decode it into a read / write request. Specifically, in this embodiment, the output control module 608 is based on Round-Robin Scheduling. One thread will continue to execute until the ordered instruction FIFO memory 606 or the non-ordered instruction FIFO memory 607 voluntarily relinquishes control, is preempted by a higher-priority thread, or its time slice expires. Only then will the multiplexer 609 switch to the other of the ordered instruction FIFO memory 606 or the non-ordered instruction FIFO memory 607 to continue reading instructions. The instruction selected by the multiplexer 609 is sent to the instruction decoder 610.

[0054] The instruction decoder 610 decodes the instruction into read / write micro-instructions and sends them to the data path register 613 in the NRAM 531. The data path register 613 handles read / write requests for the data stream and coordinates the data path for read / write requests from I / O ports. Based on the address of the read / write micro-instruction, the data path register 613 writes the data to the register group 603 and deletes the record of the instruction from the corresponding pre-order commit queue 611 or non-pre-order commit queue 612. The commit queue is a mechanism for monitoring the completion of instruction execution. When an instruction is sent to the input control module 608, if the instruction is fetched from the pre-order instruction FIFO memory 606, it will be recorded in the pre-order commit queue 611; if the instruction is fetched from the non-pre-order instruction FIFO memory 607, it will be recorded in the non-pre-order commit queue 612. Once the data corresponding to the instruction is written to the register group 603, the corresponding record in the order-keeping commit queue 611 or the non-order-keeping commit queue 612 will be deleted, indicating that the instruction has been executed. At the same time, the data path register 613 will also modify the information in the synchronization table entry 604 to update the processing of the synchronization instruction.

[0055] The GLD instruction in this embodiment includes N instruction groups, each of which controls the loading of one piece of data. Therefore, the GLD instruction in this embodiment can control the loading of N pieces of data simultaneously. Figure 7 A schematic diagram of GLD instructions applicable to this embodiment is shown, illustrating the example of GLD instructions comprising four instruction groups. Figure 7 As shown, the GLD instruction 700 includes a first instruction group 701, a second instruction group 702, a third instruction group 703, and a fourth instruction group 704, each with the same structure. Taking the first instruction group 701 as an example, the first instruction group 701 includes an enable field 705 and a control field 706. The enable field 705 is used to indicate whether the first instruction group 701 is enabled or void, where a value of 1 indicates that the first instruction group 701 carries valid information, and a value of 0 indicates that the first instruction group 701 is idle. Figure 7 The enable field of the first instruction group 701 has a value of 1, therefore the first instruction group 701 contains valid information. The control field 706 includes the address field 707, the type field 708, the operation field 709, and the coordinate field 710.

[0056] Address field 707 represents the address information for reading neuron data in NRAM 531, and includes base address field 711 and offset field 712. In this embodiment, NRAM 531 is composed of multiple memory blocks arranged sequentially. Base address field 711 represents the starting address of the target memory block in NRAM 531, and offset field 712 represents the offset from the aforementioned starting address. Assuming that each memory block in NRAM 531 has 256 memory spaces, the base address of the first memory block is 0000, the base address of the second memory block is 0255, the base address of the third memory block is 0511, and so on. In the figure, the value "0255" in base address field 711 indicates that the neuron data to be read is stored in the second memory block, while the value "100" in offset field 712 indicates that the neuron data is stored in the memory space at an offset of 100 in the second memory block, that is, the 101st memory space in the second memory block.

[0057] Type field 708 is used to represent the data type of the neuron data to be read. The data type refers to the length of the neuron data; in this embodiment, the data type is one of 48 bits, 32 bits, 16 bits, or 8 bits. Type field 708 uses the values ​​"00", "01", "10", and "11" to represent 48-bit, 32-bit, 16-bit, and 8-bit data types, respectively. Figure 7 The value of type field 708 in the data is "00", therefore the data type of the neuron data to be read is 48 bits.

[0058] Operation field 709 is used to indicate the type of operation of the neuron data to be read, to record whether the data is used for computation or for output / input operations. For example, the values ​​"1" and "0" in operation field 709 indicate that the neuron data to be read is used for "computation" and "output / input", respectively. Figure 7 The value of operation field 708 in the data is "1", so it can be identified that the neuron data is used for computation.

[0059] The coordinate field 710 is used to represent the write coordinate information of the temporary register group 603, and it includes an identification code field 713 and an encoding field 714. In this embodiment, the temporary register group 603 forms a storage array, including multiple temporary storage units, each of which is located by an identification code and an encoding. Figure 8 A schematic diagram of an example of the temporary register group 603 according to this embodiment is shown. Figure 8As shown, the register group 603 includes 16 register units, from register 0 to register 15, arranged in a 4x4 array structure. Identification codes 0, 1, 2, and 3 represent the row information of the register unit (row 1, row 2, row 3, row 4), respectively, while codes 0, 1, 2, and 3 represent the column information of the register unit (column 1, column 2, column 3, column 4), respectively. Each register unit in register group 603 can be located using the identification code and the code. For example, Figure 8 If the value of the identification code field is "00" and the value of the encoding field is "11", it means that the neuron data should be stored in temporary storage unit 3.

[0060] To address the write-after-write dependency issue, nonscalar register 601 temporarily stores all other instructions corresponding to the identifier of the target temporary storage unit. Specifically, it stores all instructions whose identifier field 713 matches the identifier field 713 of the first instruction group 701. After the instruction decoding unit 512 writes the target data to the target temporary storage unit, the loading register 602 receives these instructions and accesses any temporary storage unit corresponding to the identifier of the target temporary storage unit. In other words, all instructions whose identifier matches the identifier of the first instruction group 701 will not be executed until the first instruction group 701 has finished executing, thus meeting the requirement of execution order dependency.

[0061] Figure 7 The structures of the second instruction group 702, the third instruction group 703, and the fourth instruction group 704 are the same as those of the first instruction group 701, and will not be described again.

[0062] The GLD instructions in this embodiment include four instruction groups, each controlling the transfer of data for one neuron. The data for a single neuron controlled by each instruction group is a feature map or an intermediate result calculated by the processor core 406. Since each GLD instruction includes four instruction groups, a single GLD instruction can be used to control the transfer of data for four neurons. It should be noted that although the GLD instructions shown in the above embodiments of this disclosure include four instruction groups, the embodiments of this disclosure are not limited to this and may include more or fewer instruction groups, such as eight, sixteen, two, etc.

[0063] The instruction fetch unit 511 fetches the GLD instruction, the instruction decoding unit 512 decodes the GLD instruction, and uses the decoding result as control information to read specific neuron data from the NRAM 531 and write it into the temporary register group 603 of the instruction decoding unit 512 for later use.

[0064] The instruction decoding unit 512 first determines whether the first instruction group 701 is enabled or disabled from the enable field 705 of the first instruction group 701. If the first instruction group 701 is enabled, the starting address, offset, data type, operation type, identification code, and encoding are obtained from the base address field 711, offset field 712, type field 708, operation field 709, identification code field 713, and encoding field 714 of the control field 706 of the first instruction group 701, respectively. If the first instruction group 701 is disabled, the instruction decoding unit 512 skips the control field 706 of the first instruction group 701 and then determines whether the second instruction group 702 is enabled or disabled from the enable field of the second instruction group 702.

[0065] When the first instruction group 701 is enabled, the instruction decoding unit 512 specifically obtains the starting address from the base address field 711 and the offset from the offset field 712. The instruction decoding unit 512 can determine the address information of the neuron data to be read in the NRAM 531 (i.e., the aforementioned target storage unit) through the starting address and the offset.

[0066] Next, the instruction decoding unit 512 obtains the data type of the neuron data from the type field 708, the operation type of the neuron data from the operation field 709, the identification code of the temporary storage unit to be written to the temporary storage group 603 from the identification code field 713, and the encoding of the temporary storage unit to be written to the temporary storage group 603 from the encoding field 714.

[0067] Subsequently, the instruction decoding unit 512 retrieves the neuron data from the target storage unit in NRAM 531 according to the starting address, offset, and data type. Specifically, the instruction decoding unit 512 selects the target storage block according to the starting address, selects the target storage unit of the target storage block according to the offset, and determines the length of the neuron data according to the data type, so as to completely retrieve the neuron data of the data type size from the target storage unit.

[0068] Next, the instruction decoding unit 512 identifies the temporary storage unit (i.e., the aforementioned target temporary storage unit) in the temporary storage group 603 according to the identification code and encoding, and writes the read neuron data into the target temporary storage unit. This completes the operation of retrieving and temporarily storing neuron data.

[0069] Finally, the instruction decoding unit 512 sends the neuron data from the target temporary storage unit to the arithmetic module 52 or SRAM 408 according to the operation type. More specifically, if the operation type is for computation, the instruction decoding unit 512 sends the neuron data from the temporary storage unit in the temporary storage group 603 to the arithmetic module 52; if the operation type is for output / input, the instruction decoding unit 512 sends the neuron data from the temporary storage unit in the temporary storage group 603 to SRAM 408. This completes all operations of the first instruction group 701.

[0070] The operation of the computing device 201 on the second instruction group 702, the third instruction group 703, and the fourth instruction group 704 is the same as that on the first instruction group 701, and will not be described again here.

[0071] This disclosure does not limit the representation of the enable field, address field, type field, operation field, and coordinate field of the first instruction group 701, the second instruction group 702, the third instruction group 703, and the fourth instruction group 704, nor does it limit the order of the enable field, address field, type field, operation field, and coordinate field in each instruction group.

[0072] The GLD instructions in this embodiment can control the transfer of multiple data at once, thereby quickly and efficiently loading data from artificial intelligence chips.

[0073] Another embodiment of this disclosure is a method for moving N data items in a processing core based on GLD instructions, where the GLD instructions are... Figure 7 The GLD instruction 700 can be used, and the processor core can be the processor core 406 in the aforementioned embodiment. For ease of explanation, this embodiment also uses N=4 as an example. Figure 9 This embodiment illustrates a flowchart of how the first instruction set based on GLD instructions moves data within the processing core.

[0074] In step 901, it is determined whether the enable field 705 in the first instruction group 701 is enabled. More specifically, if the value of the enable field 705 in the first instruction group 701 is "1", then the first instruction group 701 is in an enabled state; if the value of the enable field 705 in the first instruction group 701 is "0", then the first instruction group 701 is in a disabled state.

[0075] If the first instruction group 701 is enabled, then step 902 is executed. In step 902, control information is obtained from each field of the control domain 706 of the first instruction group 701. More specifically, the starting address, offset, data type, operation type, identification code, and encoding are obtained from the base address field 711, offset field 712, type field 708, operation field 709, identification code field 713, and encoding field 714 of the control domain 706 of the first instruction group 701, respectively.

[0076] In step 903, target data is read from the neuron storage unit according to control information. This control information includes the starting address, offset, and data type. The target storage block is selected from multiple storage blocks of the NRAM 531 based on the starting address, and then the target storage unit of the target storage block is selected based on the offset. The length of the neuron data is then determined based on the data type, so that neuron data of the data type size, i.e., the target data, can be completely retrieved from the target storage unit.

[0077] In step 904, the target data is written into the temporary register group 603 of the instruction decoding unit 512 according to the control information. The control information in this step includes the operation type, identification code, and encoding. The temporary register group 603 includes multiple temporary register units, each located by the identification code and encoding. The target temporary register unit in the temporary register group 603 is determined based on the identification code and encoding in the control information, and the read target data is written into that target temporary register unit. This completes all operations of the first instruction group 701.

[0078] If it is determined in step 901 that the first instruction group 701 is in a useless state, or after step 904 is executed, this embodiment then executes the second instruction group 702, the third instruction group 703, and the fourth instruction group 704 in sequence. Since the operations of the second instruction group 702, the third instruction group 703, and the fourth instruction group 704 are the same as those of the first instruction group 701, they will not be described in detail. After all operations of the GLD instruction 700 are executed sequentially, the movement of four data items in the processor core 406 based on a single GLD instruction 700 is completed.

[0079] The target data temporarily stored in the target temporary storage unit will be sent from the temporary storage unit to the arithmetic module 52 or SRAM 408 at an appropriate time by the storage module 53 according to another instruction sent by the instruction decoding unit 512. This control information sends the target data from the target temporary storage unit to the arithmetic module 52 or SRAM 408 according to the operation type. More specifically, if the operation type is for calculation, the target data is sent from the target temporary storage unit to the arithmetic module 52; if the operation type is for input / output, the target data is sent from the target temporary storage unit to SRAM 408.

[0080] In another scenario, when the hardware configuration is sufficiently high, the operations of the aforementioned first instruction group 701, second instruction group 702, third instruction group 703, and fourth instruction group 704 can be processed in parallel to improve the computing speed.

[0081] Another embodiment of this disclosure is also a method for moving N data items in the processing core based on GLD instructions, where the GLD instructions are... Figure 7The GLD instruction 700 can be used, and the processor core can be the processor core 406 in the aforementioned embodiment. For ease of explanation, this embodiment also uses N=4 as an example. Figure 10 This embodiment illustrates a flowchart of how the first instruction group based on GLD instructions moves data from the processing core to the target temporary storage unit.

[0082] In step 1001, it is determined whether the enable field in the first instruction group is enabled. If the value of the enable field in the first instruction group is "1", then the first instruction group is in an enabled state; if the value of the enable field in the first instruction group is "0", then the first instruction group is in a disabled state.

[0083] If the enable field of the first instruction group is enabled, then step 1002 is executed to obtain the read address information from the address field in the control field of the first instruction group. The neuron storage unit in this embodiment includes multiple storage blocks arranged in sequence. The address field of the GLD instruction includes a base address field and a bias field, wherein the base address field records the starting address of the target storage block among the multiple storage blocks, and the bias field records the offset from the starting address. This step further obtains the starting address from the base address field of the first instruction group and the offset from the bias field of the first instruction group.

[0084] In step 1003, the write coordinate information is obtained from the coordinate field of the control field of the first instruction group. In this embodiment, the register group includes multiple temporary storage units, each located by an identification code and an encoding. The coordinate field includes an identification code field and an encoding field, wherein the identification code field records the identification code of the target temporary storage unit among the multiple temporary storage units, and the encoding field records the encoding of the target temporary storage unit. This step further obtains the identification code of the target temporary storage unit from the identification code field of the first instruction group and the encoding of the target temporary storage unit from the encoding field of the first instruction group.

[0085] In step 1004, access to all temporary storage units corresponding to the identifier of the target temporary storage unit is suspended by other instructions. Before continuing the operation of the first instruction group, access to all temporary storage units corresponding to the identifier (i.e., all temporary storage units in the same row) by other instructions is suspended to avoid write-after-write dependency issues.

[0086] In step 1005, the data type of the target data is obtained from the type field in the control domain of the first instruction group. The data type includes at least one of 48 bits, 32 bits, 16 bits, and 8 bits.

[0087] In step 1006, target data is read from the neuron's storage unit according to the read address information. More specifically, this step first selects the target storage block based on the starting address, then selects the target storage unit of the target storage block based on the offset, and finally retrieves the target data from the target storage unit.

[0088] In step 1007, the target data is written into the temporary register group of the instruction decoding unit according to the written coordinate information. More specifically, this step involves writing the target data into the target temporary register unit based on the identification code and encoding of the target temporary register unit.

[0089] In step 1008, operation type information is obtained from the operation field in the control field of the first instruction group.

[0090] In step 1009, based on the operation type information, the target data is sent from the temporary storage group to the computation module or the neuron storage unit. More specifically, if the operation type is for computation, the target data is sent from the target temporary storage unit to the computation module; if the operation type is for output / input, the target data is sent from the target temporary storage unit to the neuron storage unit. This completes all operations of the first instruction group.

[0091] In step 1010, other instructions are initiated to access any temporary storage unit corresponding to the identifier of the target temporary storage unit. After step 1009 is executed, the write-after-write dependency issue no longer exists, and this step initiates other instructions to access any temporary storage unit corresponding to the identifier of the target temporary storage unit.

[0092] If it is determined in step 1001 that the first instruction group is in a useless state, or after step 1010 has been executed, this embodiment then executes the second, third, and fourth instruction groups sequentially. Since the operations of the second, third, and fourth instruction groups are the same as those of the first instruction group, they are executed in the same manner. Figure 10 The process is detailed here, so it will not be elaborated upon. After all operations of the GLD instruction are executed sequentially, the transfer of four data items within the processor core based on a single GLD instruction is complete.

[0093] In another scenario, when the hardware configuration is sufficiently high, steps 1001 to 1007 of the aforementioned first, second, third, and fourth instruction groups can be executed in parallel to improve the computational speed.

[0094] Another embodiment of this disclosure is a computer-readable storage medium storing computer program code that moves N data items within a processor core based on a single instruction. When the computer program code is executed by the processor, it performs the methods described in the foregoing embodiments, for example... Figure 9 or Figure 10 The process.

[0095] This disclosure enables a technical means to move multiple data based on a single instruction, thereby achieving the technical effect of fast and efficient data loading.

[0096] Depending on the application scenario, the electronic devices or apparatus disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, dashcams, navigators, sensors, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, autonomous driving terminals, vehicles, home appliances, and / or medical devices. The vehicles include airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound scanners, and / or electrocardiographs. The electronic devices or apparatus disclosed herein can also be applied in fields such as the Internet, IoT, data centers, energy, transportation, public management, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and healthcare. Furthermore, the electronic devices or apparatus disclosed herein can also be used in cloud, edge, and terminal applications related to artificial intelligence, big data, and / or cloud computing. In one or more embodiments, the high-computing-power electronic devices or apparatuses according to the present disclosure can be applied to cloud devices (e.g., cloud servers), while the low-power electronic devices or apparatuses can be applied to terminal devices and / or edge devices (e.g., smartphones or cameras). In one or more embodiments, the hardware information of the cloud devices and the hardware information of the terminal devices and / or edge devices are compatible with each other, so that suitable hardware resources can be matched from the hardware resources of the cloud devices to simulate the hardware resources of the terminal devices and / or edge devices based on the hardware information of the terminal devices and / or edge devices, so as to complete the unified management, scheduling and collaborative work of the end-to-cloud or cloud-edge-end integration.

[0097] It should be noted that, for the sake of brevity, this disclosure describes some methods and their embodiments as a series of actions and combinations thereof. However, those skilled in the art will understand that the solutions of this disclosure are not limited by the order of the described actions. Therefore, based on the disclosure or teachings of this disclosure, those skilled in the art will understand that some steps can be performed in a different order or simultaneously. Furthermore, those skilled in the art will understand that the embodiments described in this disclosure can be considered as optional embodiments, that is, the actions or modules involved are not necessarily essential for the implementation of one or more solutions of this disclosure. In addition, depending on the solution, the description of some embodiments in this disclosure also has different emphases. In view of this, those skilled in the art will understand that parts not described in detail in a certain embodiment of this disclosure can also be referred to the relevant descriptions of other embodiments.

[0098] In terms of specific implementation, based on the disclosure and teachings of this disclosure, those skilled in the art will understand that the several embodiments disclosed herein can also be implemented in other ways not disclosed herein. For example, regarding the various units in the electronic device or apparatus embodiments described above, this document divides them based on logical functions, but in actual implementation, there may be other division methods. As another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. Regarding the connection relationship between different units or components, the connection discussed above in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection utilizing an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

[0099] In this disclosure, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network units. Furthermore, depending on actual needs, some or all of the units can be selected to achieve the purpose of the solution described in the embodiments of this disclosure. Additionally, in some scenarios, multiple units in the embodiments of this disclosure may be integrated into one unit or each unit may exist physically independently.

[0100] In some implementation scenarios, the integrated unit described above can be implemented as a software program module. If implemented as a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable storage device (CMSDD). Therefore, when the solution of this disclosure is embodied in the form of a software product (e.g., a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to cause a computer device (e.g., a personal computer, server, or network device) to execute some or all of the steps of the method described in the embodiments of this disclosure. The aforementioned memory may include, but is not limited to, various media capable of storing program code, such as USB flash drives, flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0101] In other implementation scenarios, the integrated units described above can also be implemented in hardware, i.e., as specific hardware circuits, which may include digital circuits and / or analog circuits. The physical implementation of the circuit's hardware structure may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors. Therefore, the various devices described herein (e.g., computing devices or other processing devices) can be implemented using appropriate hardware processors, such as CPUs, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage units or storage devices can be any suitable storage medium (including magnetic storage media or magneto-optical storage media), such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), ROM, and RAM.

[0102] While numerous embodiments of this disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and intent of this disclosure. It should be understood that various alternatives to the embodiments of this disclosure described herein may be employed in the practice of this disclosure. The appended claims are intended to define the scope of this disclosure and therefore cover equivalents or alternatives within the scope of those claims.

[0103] Clause A1. A method for moving N data items in a processor core based on an instruction, wherein the instruction comprises N instruction groups, each instruction group controlling the movement of one data item and including an enable domain and a control domain, the control domain including an address domain and a coordinate domain, the processor core including a neuron storage unit and an instruction decoding unit, the method comprising:

[0104] Determine whether each of the N instruction groups is enabled by examining its enable field;

[0105] If so, proceed with the following steps:

[0106] Retrieve address information from the address field within the control domain of the same instruction group;

[0107] Retrieve and write coordinate information from the coordinate field within the control domain of the same instruction group;

[0108] Based on the read address information, target data is read from the neuron storage unit, wherein the target data is one of the N data items; and

[0109] Based on the written coordinate information, the target data is written into the temporary register group of the instruction decoding unit;

[0110] Where N is a positive integer greater than 1.

[0111] Clause A2. The method according to Clause A1, wherein in the determination step, if the value of the enable field is 1, then it is enabled.

[0112] Clause A3. The method according to Clause A1, wherein the neuron storage unit comprises a plurality of storage blocks arranged in sequence, and the address field further comprises:

[0113] The base address field is used to record the starting address of the target storage block, wherein the target storage block is one of the plurality of storage blocks; and

[0114] The offset field is used to record the offset from the starting address;

[0115] The step of obtaining the read address information includes:

[0116] The starting address is obtained from the base address field; and

[0117] The offset is obtained from the offset field.

[0118] Clause A4. The method according to Clause A3, wherein the step of reading the target data includes:

[0119] The target storage block is selected based on the starting address;

[0120] The target storage unit of the target storage block is selected based on the offset; and

[0121] Retrieve the target data from the target storage unit.

[0122] Clause A5. The method according to Clause A1, wherein the control domain further includes a type domain, and the method further includes:

[0123] The data type of the target data is obtained from the type field in the control domain of the same instruction group.

[0124] Clause A6. The method according to Clause A5, wherein the data type includes at least one of 48 bits, 32 bits, 16 bits, and 8 bits.

[0125] Clause A7. The method according to Clause A1, wherein the processor core further includes an arithmetic module, the control domain further includes an operation domain, and the method further includes:

[0126] The target data is identified from the operation domain within the control domain of the same instruction group for calculation or output input;

[0127] If used for calculation, the target data is sent from the temporary storage group to the computing module; and

[0128] If used for input / output, the target data is sent from the register group to the outside of the processor core.

[0129] Clause A8. The method according to Clause A1, wherein the register group comprises a plurality of register units, each register unit being located by an identification code and an encoding, and the coordinate field further comprises:

[0130] An identification code field is used to record the identification code of the target temporary storage unit, wherein the target temporary storage unit is one of the plurality of temporary storage units; and

[0131] The encoding field is used to record the encoding of the target temporary storage unit;

[0132] The step of obtaining and writing coordinate information includes:

[0133] The identification code of the target temporary storage unit is obtained from the identification code field; and

[0134] The encoding of the target temporary storage unit is obtained from the encoding field.

[0135] Clause A9. The method according to Clause A8, wherein the step of writing the target data into the register group of the instruction decoding unit includes:

[0136] The target data is written into the target temporary storage unit according to the identification code and encoding of the target temporary storage unit.

[0137] Clause A10. The method according to Clause A9, wherein the method further comprises:

[0138] Suspend all accesses by other commands to all temporary storage units corresponding to the identifier of the target temporary storage unit; and

[0139] After the step of writing the target data into the target temporary storage unit is executed, the other instructions are initiated to access any temporary storage unit corresponding to the identification code of the target temporary storage unit.

[0140] Clause A11. The method described in Clause A1, wherein N is 4.

[0141] Clause A12. A computer-readable storage medium having stored thereon computer program code that moves N data items in a processor core based on an instruction, wherein when the computer program code is run by a processing device, it performs the method described in any one of Clauses A1 to A11.

[0142] Clause A13. A computing device for moving N data items based on a single instruction, the instruction comprising N instruction groups, each instruction group controlling the movement of one data item and including an enable domain and a control domain, the control domain including an address domain and a coordinate domain, the computing device comprising multiple clusters, each cluster comprising multiple processor cores, each processor core comprising:

[0143] The storage module includes a neuron storage unit for storing the N data points, wherein the N data points are one of the feature maps and intermediate results calculated by the processor core, and N is a positive integer greater than 1.

[0144] The control module includes an instruction decoding unit, which is used to:

[0145] Determine whether each of the N instruction groups is enabled by examining its enable field;

[0146] If so, then:

[0147] Retrieve address information from the address field within the control domain of the same instruction group;

[0148] Retrieve and write coordinate information from the coordinate field within the control domain of the same instruction group;

[0149] Based on the read address information, target data is read from the neuron storage unit, wherein the target data is one of the N data items; and

[0150] Based on the written coordinate information, the target data is written into the temporary register group of the instruction decoding unit.

[0151] Clause A14. The computing device according to Clause A13, wherein the neuron storage unit comprises a plurality of storage blocks arranged in sequence, and the address field further comprises:

[0152] The base address field is used to record the starting address of the target storage block, wherein the target storage block is one of the plurality of storage blocks; and

[0153] The offset field is used to record the offset from the starting address;

[0154] The instruction decoding unit obtains the starting address from the base address field and the offset from the offset field.

[0155] Clause A15. The computing apparatus according to Clause A14, wherein the instruction decoding unit is further configured to:

[0156] The target storage block is selected based on the starting address;

[0157] The target storage unit of the target storage block is selected based on the offset; and

[0158] Retrieve the target data from the target storage unit.

[0159] Clause A16. The computing apparatus according to Clause A13, wherein the control domain further includes a type domain, and the instruction decoding unit obtains the data type of the target data from the type domain in the control domain of the same instruction group.

[0160] Clause A17. The computing device according to Clause A16, wherein the data type includes at least one of 48 bits, 32 bits, 16 bits, and 8 bits.

[0161] Clause A18. The computing device according to Clause A13, wherein the cluster further includes a shared memory unit, the processor core further includes an arithmetic module, the control domain further includes an operation domain, and the instruction decoding unit identifies the target data from the operation domain in the control domain of the same instruction set for computation or output / input; if for computation, the instruction decoding unit sends the target data from the register set to the arithmetic module; if for output / input, the instruction decoding unit sends the target data from the register set to the shared memory unit.

[0162] Clause A19. The computing device according to Clause A13, wherein the register group comprises a plurality of temporary storage units, each temporary storage unit being located by an identification code and an encoding, and the coordinate field further comprises:

[0163] An identification code field is used to record the identification code of the target temporary storage unit, wherein the target temporary storage unit is one of the plurality of temporary storage units; and

[0164] The encoding field is used to record the encoding of the target temporary storage unit;

[0165] The instruction decoding unit obtains the identification code of the target temporary storage unit from the identification code field and obtains the encoding of the target temporary storage unit from the encoding field.

[0166] Clause A20. The computing device according to Clause A19, wherein the instruction decoding unit writes the target data into the target temporary storage unit according to the identification code and encoding of the target temporary storage unit.

[0167] Clause A21. The computing device according to Clause A20, wherein the instruction decoding unit comprises:

[0168] A non-scalar temporary register is used to temporarily store other instructions that access all temporary registers corresponding to the identifier of the target temporary register; and

[0169] A loading register is used to receive other instructions after the instruction decoding unit writes the target data into the target temporary storage unit, so as to access any temporary storage unit corresponding to the identification code of the target temporary storage unit.

[0170] Clause A22. The computing device according to Clause A21, wherein the neuron storage unit further includes a data path register for processing the data stream of the neuron storage unit, the loading register includes a first-in-first-out memory, the instruction decoding unit retrieves the instruction from the first-in-first-out memory and sends it to the data path register, and the target data is moved from the data path register to the target storage unit.

[0171] Clause A23. The computing device according to Clause A22, wherein the load register further includes a submission queue, wherein the load register removes the instruction from the submission queue as the target data is moved from the data path register to the target storage unit.

[0172] Clause A24. An integrated circuit device comprising a computing device according to any one of Clauses A13 to A23.

[0173] Clause A25. A board including an integrated circuit device as described in Clause A24.

Claims

1. A method for moving N data items in a processor core based on a single instruction, wherein the instruction comprises N instruction groups, each instruction group controlling the movement of one data item and including an enable domain and a control domain, the control domain including an address domain and a coordinate domain, the processor core including a neuron storage unit and an instruction decoding unit, the method comprising: Determine whether each of the N instruction groups is enabled by examining its enable field; If so, proceed with the following steps: Retrieve address information from the address field within the control domain of the same instruction group; Retrieve and write coordinate information from the coordinate field within the control domain of the same instruction group; According to the read address information, target data is read from the neuron storage unit, wherein the target data is one of the N data; as well as Based on the written coordinate information, the target data is written into the temporary register group of the instruction decoding unit; Where N is a positive integer greater than 1; The step of writing the target data into the temporary register group of the instruction decoding unit includes: The target data is written into the target temporary storage unit according to the identification code and encoding of the target temporary storage unit; Suspend all accesses by other commands to all temporary storage units corresponding to the identifier of the target temporary storage unit; and After the step of writing the target data into the target temporary storage unit is executed, the other instructions are initiated to access any temporary storage unit corresponding to the identification code of the target temporary storage unit.

2. The method according to claim 1, wherein in the determination step, if the value of the enable field is 1, then it is enabled.

3. The method according to claim 1, wherein the neuron storage unit comprises a plurality of storage blocks arranged in sequence, and the address field further comprises: The base address field is used to record the starting address of the target storage block, wherein the target storage block is one of the plurality of storage blocks; as well as The offset field is used to record the offset from the starting address; The step of obtaining the read address information includes: The starting address is obtained from the base address field; as well as The offset is obtained from the offset field.

4. The method according to claim 3, wherein the step of reading the target data includes: The target storage block is selected based on the starting address; The target storage unit of the target storage block is selected based on the offset. as well as Retrieve the target data from the target storage unit.

5. The method according to claim 1, wherein the control domain further includes a type domain, and the method further includes: The data type of the target data is obtained from the type field in the control domain of the same instruction group.

6. The method according to claim 5, wherein the data type includes at least one of 48 bits, 32 bits, 16 bits, and 8 bits.

7. The method according to claim 1, wherein the processor core further includes a computation module, the control domain further includes an operation domain, and the method further includes: The target data is identified from the operation domain within the control domain of the same instruction group for calculation or output input; If used for calculation, the target data is sent from the temporary storage group to the computing module; as well as If used for input / output, the target data is sent from the register group to the outside of the processor core.

8. The method according to claim 1, wherein the temporary storage group comprises a plurality of temporary storage units, each temporary storage unit being located by an identification code and an encoding, and the coordinate domain further comprises: The identification code field is used to record the identification code of the target temporary storage unit, wherein the target temporary storage unit is one of the plurality of temporary storage units; as well as The encoding field is used to record the encoding of the target temporary storage unit; The step of obtaining and writing coordinate information includes: The identification code of the target temporary storage unit is obtained from the identification code field; as well as The encoding of the target temporary storage unit is obtained from the encoding field.

9. The method of claim 1, wherein N is 4.

10. A computer-readable storage medium having stored thereon computer program code that moves N data items in a processor core based on an instruction, wherein when the computer program code is run by a processing device, it performs the method according to any one of claims 1 to 9.

11. A computing device for moving N data items based on a single instruction, wherein the instruction comprises N instruction groups, each instruction group controls the movement of one data item and includes an enable domain and a control domain, the control domain including an address domain and a coordinate domain, the computing device comprising multiple clusters, each cluster comprising multiple processor cores, each processor core comprising: The storage module includes a neuron storage unit for storing the N data points, wherein the N data points are one of the feature maps and intermediate results calculated by the processor core, and N is a positive integer greater than 1. The control module includes an instruction decoding unit, which is used to: Determine whether each of the N instruction groups is enabled by examining its enable field; If so, then: Retrieve address information from the address field within the control domain of the same instruction group; Retrieve and write coordinate information from the coordinate field within the control domain of the same instruction group; According to the read address information, target data is read from the neuron storage unit, wherein the target data is one of the N data; as well as Based on the written coordinate information, the target data is written into the temporary register group of the instruction decoding unit; Among them, the instruction decoding unit The target data is written into the target temporary storage unit according to the identification code and encoding of the target temporary storage unit; Suspend all accesses by other commands to all temporary storage units corresponding to the identifier of the target temporary storage unit; and After the target data is written into the target temporary storage unit, the other instructions are initiated to access any temporary storage unit corresponding to the identification code of the target temporary storage unit.

12. The computing device of claim 11, wherein the neuron storage unit comprises a plurality of storage blocks arranged in sequence, and the address field further comprises: The base address field is used to record the starting address of the target storage block, wherein the target storage block is one of the plurality of storage blocks; as well as The offset field is used to record the offset from the starting address; The instruction decoding unit obtains the starting address from the base address field and the offset from the offset field.

13. The computing device according to claim 12, wherein the instruction decoding unit is further configured to... The target storage block is selected based on the starting address; The target storage unit of the target storage block is selected based on the offset; and Retrieve the target data from the target storage unit.

14. The computing device of claim 11, wherein the control domain further includes a type domain, and the instruction decoding unit obtains the data type of the target data from the type domain in the control domain of the same instruction group.

15. The computing device of claim 14, wherein the data type includes at least one of 48 bits, 32 bits, 16 bits, and 8 bits.

16. The computing device of claim 11, wherein the cluster further includes a shared storage unit, the processor core further includes an arithmetic module, the control domain further includes an operation domain, and the instruction decoding unit identifies the target data from the operation domain in the control domain of the same instruction group for computation or output / input; if for computation, the instruction decoding unit sends the target data from the register group to the arithmetic module; if for output / input, the instruction decoding unit sends the target data from the register group to the shared storage unit.

17. The computing device of claim 11, wherein the register group comprises a plurality of temporary storage units, each temporary storage unit being located by an identification code and an encoding, and the coordinate domain further comprises: The identification code field is used to record the identification code of the target temporary storage unit, wherein the target temporary storage unit is one of the plurality of temporary storage units; as well as The encoding field is used to record the encoding of the target temporary storage unit; The instruction decoding unit obtains the identification code of the target temporary storage unit from the identification code field and obtains the encoding of the target temporary storage unit from the encoding field.

18. The computing device of claim 11, wherein the instruction decoding unit comprises: A non-scalar register is used to temporarily store other instructions for all temporary registers corresponding to the identifier of the target temporary register. as well as A loading register is used to receive other instructions after the instruction decoding unit writes the target data into the target temporary storage unit, so as to access any temporary storage unit corresponding to the identification code of the target temporary storage unit.

19. The computing device of claim 18, wherein the neuron storage unit further includes a data path register for processing the data stream of the neuron storage unit, the loading register includes a first-in-first-out memory, the instruction decoding unit retrieves the instruction from the first-in-first-out memory and sends it to the data path register, and the target data is moved from the data path register to the target storage unit.

20. The computing device of claim 19, wherein the load register further includes a submission queue, wherein the load register removes the instruction from the submission queue as the target data is moved from the data path register to the target storage unit.

21. An integrated circuit device comprising a computing device according to any one of claims 11 to 20.

22. A board comprising the integrated circuit device according to claim 21.

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