Serial debug system and method

Abstract

The embodiment of the application provides a serial port debugging system and method, relates to the technical field of integrated circuits, and the system comprises a CPU, a signal conversion component and a serial port debugging component, the CPU is used for transmitting sending signals of each UART interface to the signal conversion component, and based on receiving debugging signals transmitted by the signal conversion component, the signal conversion component is used for realizing signal conversion processing between the CPU and the serial port debugging component, each serial port debugging device is used for receiving sending signals transmitted by the signal conversion component, and according to a set rule, one target serial port debugging device is determined from two or more serial port debugging devices, and debugging signals of the target serial port debugging device are sent to the signal conversion component, so that the convenience of serial port debugging is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a serial port debugging system and method. Background Technology

[0002] Servers typically include a CPU (Central Processing Unit), a BIOS (Basic Input Output System), and a BMC (Baseboard Management Controller), among other components. These components work together to implement various functions of the server system. For example, serial port debugging functionality can be implemented on a server based on the BMC; however, the ease of serial port debugging currently needs improvement. Summary of the Invention

[0003] One of the objectives of this invention includes, for example, providing a serial port debugging system and method to at least partially improve the convenience of serial port debugging.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, the present invention provides a serial port debugging system, comprising: a CPU, a signal conversion component, and a serial port debugging component, wherein the CPU and the serial port debugging component are connected through the signal conversion component;

[0006] The CPU has multiple UART interfaces, and the CPU is used to transmit the transmit signals of each UART interface to the signal conversion component, and to receive the debug signals transmitted by the signal conversion component based on each UART interface;

[0007] The signal conversion component is used to convert and process each of the transmitted signals from the CPU, send the converted and processed transmitted signals to the serial port debugging component, and convert and process the debugging signals transmitted from the serial port debugging component, and send the converted and processed debugging signals to the CPU.

[0008] The serial port debugging component includes two or more serial port debugging devices. Each serial port debugging device is used to receive the transmission signal transmitted from the signal conversion component, and determine a target serial port debugging device from the two or more serial port debugging devices according to the set rules, and send the debugging signal of the target serial port debugging device to the signal conversion component.

[0009] In an optional implementation, the two or more serial port debugging devices include a BMC, a USB Type-C connector, and an onboard header connector; the signal conversion component includes level conversion and signal decomposition circuitry.

[0010] The level conversion and signal decomposition circuit is used to receive each of the transmitted signals from the CPU, perform level conversion on each of the transmitted signals, and convert each transmitted signal after level conversion into multiple output signals. A portion of the multiple output signals are sent to the onboard header connector, and the remaining output signals are sent to the BMC and USB Type-C connector respectively.

[0011] In an optional implementation, the level conversion and signal decomposition circuit includes an MB CPLD and a DC-SCMCPLD. The DC-SCMCPLD has a built-in buffer. The first port of the MB CPLD is connected to the CPU, the second port is connected to the onboard header connector, and the third port is connected to the first port of the DC-SCMCPLLD. The second port of the DC-SCMCPLLD is connected to the BMC and the USB Type-C connector, respectively.

[0012] The MB CPLD is used to receive each of the transmission signals transmitted from the CPU based on the first port, perform level conversion on each of the transmission signals, and convert each of the level-converted transmission signals into two output signals. One of the two output signals is sent to the onboard header connector through the second port, and the other of the two output signals is sent to the first port of the DC-SCM CPLD through the third port.

[0013] The DC-SCM CPLD is used to buffer each of the received output signals based on the buffer, and send the two output signals obtained from the buffering process to the BMC and the USB Type-C connector respectively through the second port.

[0014] In an optional implementation, the two or more serial port debugging devices include a BMC, a USB Type-C connector, and an onboard header connector; the signal conversion component includes level conversion and signal selection circuitry.

[0015] The level conversion and signal selection circuit is used to receive each of the transmitted signals from the CPU, perform level conversion on each of the transmitted signals, and convert each transmitted signal after level conversion into multiple output signals. A portion of the multiple output signals are sent to the onboard header connector, and one of the UART interfaces of the CPU is connected based on the control instructions of the BMC. The remaining output signals of the multiple output signals and the output signals corresponding to the connected UART interface are sent to the BMC and the USB Type-C connector respectively.

[0016] In an optional implementation, the level conversion and signal selection circuit includes an MB CPLD and a DC-SCMCPLD. The MB CPLD integrates a signal selection module and a controlled module. The DC-SCMCPLLD has a built-in buffer. The first port of the MB CPLD is connected to the CPU, the second port is connected to the onboard header connector, and the third port is connected to the first port of the DC-SCMCPLLD through the signal selection module. The second port of the DC-SCMCPLLD is connected to the BMC and the USB Type-C connector respectively. The controlled module is connected between the BMC and the signal selection module.

[0017] The MB CPLD is used to receive each of the transmitted signals from the CPU via the first port, perform level conversion on each of the transmitted signals, and convert each of the level-converted transmitted signals into two output signals. One of the two output signals is sent to the onboard header connector through the second port. Based on the control command sent by the BMC to the signal selection module through the controlled module, one of the UART interfaces of the CPU is connected, and the output signal corresponding to the connected UART interface is sent to the first port of the DC-SCM CPLD through the third port.

[0018] The DC-SCM CPLD is used to buffer the received output signal based on the buffer, and send the two output signals obtained from the buffering process to the BMC and the USB Type-C connector respectively through the second port.

[0019] In an optional implementation, the target serial port debugging device is determined in the following way:

[0020] Based on the preset priority relationship between the BMC, USB Type-C connector and onboard header connector, one of the BMC, USB Type-C connector and onboard header connector is determined as the target serial port debugging device.

[0021] In an optional implementation, the priority relationship between the preset BMC, USB Type-C connector and onboard header connector includes: for debug signals transmitted to the CPU, the onboard header connector has a higher priority than the USB Type-C connector, and the USB Type-C connector has a higher priority than the BMC.

[0022] The target serial port debugging device is determined in the following way:

[0023] The MB CPLD is used to determine whether to place the signal selection module in a first working state or a second working state based on the high and low level states of the detection signal; wherein, the detection signal is used to detect whether there is a UART terminal in place on the onboard header connector; if it is in place, the signal selection module is placed in the first working state; if it is not in place, the signal selection module is placed in the second working state.

[0024] In the first working state, the onboard header connector is identified as the target serial port debugger, so that the debug signal of the onboard header connector is sent to the CPU.

[0025] In the second operating state, the DC-SCM CPLD is used to determine whether a cable is inserted into the USB Type-C connector based on the high or low level of the insertion detection signal. If yes, the USB Type-C connector is identified as the target serial port debugger, and the debug signal of the USB Type-C connector is sent to the CPU. If no, the BMC is identified as the target serial port debugger, and the debug signal of the BMC is sent to the CPU.

[0026] Secondly, embodiments of the present invention provide a serial port debugging method applied to a serial port debugging system. The serial port debugging system includes: a CPU, a signal conversion component, and a serial port debugging component. The CPU and the serial port debugging component are connected through the signal conversion component. The CPU has multiple UART interfaces, and the serial port debugging component includes two or more serial port debugging devices. The method includes:

[0027] The CPU transmits the transmit signals of each of the UART interfaces to the signal conversion component;

[0028] The signal conversion component converts each of the transmitted signals from the CPU and sends the converted transmitted signals to the serial port debugging component.

[0029] Each of the serial port debugging devices receives the transmission signal from the signal conversion component, and determines a target serial port debugging device from two or more serial port debugging devices according to a set rule, and sends the debugging signal of the target serial port debugging device to the signal conversion component;

[0030] The signal conversion component converts the debugging signal transmitted from the serial port debugging component and sends the converted debugging signal to the CPU.

[0031] The CPU receives debugging signals transmitted by the signal conversion components based on each of the UART interfaces and performs debugging processing.

[0032] In an optional implementation, the two or more of the serial port debugging devices include a BMC, a USB Type-C connector, and an onboard header connector; the signal conversion component includes level conversion and signal decomposition circuitry.

[0033] The step of the signal conversion component converting the transmitted signals from the CPU and sending the converted signals to the serial port debugging component includes:

[0034] The level conversion and signal decomposition circuit receives each of the transmitted signals from the CPU and performs level conversion on each of the transmitted signals;

[0035] Each transmitted signal, after level conversion, is converted into multiple output signals;

[0036] A portion of the multiple output signals are sent to the onboard header connector, and the remaining output signals are sent to the BMC and USB Type-C connector respectively.

[0037] In an optional implementation, the two or more of the serial port debugging devices include a BMC, a USB Type-C connector, and an onboard header connector; the signal conversion component includes level conversion and signal selection circuitry.

[0038] The step of the signal conversion component converting the transmitted signals from the CPU and sending the converted signals to the serial port debugging component includes:

[0039] The level conversion and signal selection circuit receives each of the transmitted signals from the CPU and performs level conversion on each of the transmitted signals;

[0040] Each transmitted signal, after level conversion, is converted into multiple output signals;

[0041] Send a portion of the output signals from the plurality of output signals to the onboard header connector;

[0042] Based on the control instructions of the BMC, one of the UART interfaces of the CPU is connected, and the output signal corresponding to the connected UART interface is sent to the BMC and the USB Type-C connector respectively.

[0043] The beneficial effects of the embodiments of the present invention include, for example, the ingenious integration and design of the CPU, signal conversion components and serial port debugging components, which allows for the flexible selection of a target serial port debugging device from two or more serial port debugging devices to achieve debugging functions, thereby improving the flexibility and convenience of serial port debugging. Attached Figure Description

[0044] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 A schematic diagram of a server structure is shown.

[0046] Figure 2 This is a schematic diagram of one of the structures of a serial port debugging system provided by an embodiment of the present invention.

[0047] Figure 3 The second schematic diagram shows the structure of a serial port debugging system provided in an embodiment of the present invention.

[0048] Figure 4 The third schematic diagram shows the structure of a serial port debugging system provided in an embodiment of the present invention.

[0049] Figure 5 The fourth schematic diagram shows the structure of a serial port debugging system provided in an embodiment of the present invention.

[0050] Figure 6 The fifth schematic diagram shows the structure of a serial port debugging system provided in an embodiment of the present invention.

[0051] Figure 7 The diagram shows a flowchart of a serial port debugging method provided by an embodiment of the present invention. Detailed Implementation

[0052] Traditional x86 architecture-based CPUs (Central Processing Units) typically have an eSPI (Enhanced Serial Peripheral Interface) or an LPC (Low Pin Count Bus). The CPU interacts with the BMC (Baseboard Management Controller) via the eSPI or LPC bus.

[0053] like Figure 1 As shown, the BMC usually has a built-in Super IO (also known as an I / O chip). The BMC uses Super IO to convert the serial port, which can be used to implement functions such as log printing during the system boot process, and to enable server system debugging.

[0054] Research has revealed the following potential problems with the above implementation scheme:

[0055] Some CPUs, such as ARM (Advanced RISC Machines) CPUs, may not have eSPI or LPC bus interfaces. UART (Universal Asynchronous Receiver / Transmitter) is usually directly output by the CPU and there are many of them. For example, a server usually has two CPUs, each CPU has multiple UARTs. The BMC needs to receive the CPU's UART information to realize functions such as remote debugging, but the existing solutions cannot achieve this.

[0056] Server debugging requires the use of UART and can switch between local standalone debugging and remote debugging using BMC. Current UART technology generally only enables point-to-point communication between two devices, and cannot enable one device to send and multiple devices to receive, which is inconvenient for server development and debugging.

[0057] Based on the above research, this invention provides a server serial port debugging solution. Through clever server design, the CPU can be debugged via serial port in multiple ways, improving the convenience and applicability of serial port debugging.

[0058] The shortcomings of the above solutions are the result of the inventors' practical experience and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the embodiments of the present invention in the following text should be considered as contributions made by the inventors during the invention process.

[0059] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0060] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0061] It should be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0062] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0063] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0064] Please refer to the following: Figure 2 This is a schematic diagram of a serial port debugging system provided in an embodiment of the present invention. The serial port debugging system can be integrated into a server.

[0065] like Figure 2 As shown, the serial port debugging system includes a CPU, a signal conversion component, and a serial port debugging component, wherein the CPU and the serial port debugging component are connected through the signal conversion component.

[0066] The CPU has multiple UART interfaces, and the CPU is used to transmit the transmit signals of each of the UART interfaces to the signal conversion component, and to receive the debug signals transmitted by the signal conversion component based on each of the UART interfaces.

[0067] The signal conversion component is used to convert and process the transmitted signals from the CPU, send the converted transmitted signals to the serial port debugging component, and convert and process the debugging signals from the serial port debugging component, and send the converted debugging signals to the CPU.

[0068] The serial port debugging component includes two or more serial port debugging devices. Each serial port debugging device is used to receive the transmission signal transmitted from the signal conversion component, and determine a target serial port debugging device from the two or more serial port debugging devices according to the set rules, and send the debugging signal of the target serial port debugging device to the signal conversion component.

[0069] By adopting the above scheme, a target serial port debugging device can be flexibly selected from two or more serial port debugging devices to realize the debugging function, thereby improving the flexibility and convenience of serial port debugging.

[0070] In this embodiment, the serial port debugging component can be flexibly selected. For example, it can be a combination of at least two of the following: BMC, USB Type-C connector, onboard header connector, etc.

[0071] The signal conversion component can be flexibly selected, as long as it can realize the signal interaction between the CPU and the serial port debugging component.

[0072] In one implementation, please refer to [the relevant documentation / reference]. Figure 3 Taking a serial port debugging device including a BMC, a USB Type-C connector, and an onboard header connector, and a signal conversion component including a level conversion and signal decomposition circuit as an example, the implementation principle is illustrated.

[0073] The level conversion and signal decomposition circuit is used to receive each of the transmitted signals from the CPU, perform level conversion on each of the transmitted signals, and convert each transmitted signal after level conversion into multiple output signals. A portion of the multiple output signals are sent to the onboard header connector, and the remaining output signals are sent to the BMC and USB Type-C connector respectively.

[0074] For example, please refer to Figure 4The level conversion and signal decomposition circuit may include an MB CPLD (Mainboard Complex Programmable Logic Device) and a DC-SCMCPLD. The DC-SCMCPLD has a built-in buffer. The first port of the MB CPLD is connected to the CPU, the second port is connected to the onboard header connector, and the third port is connected to the first port of the DC-SCMCPLLD. The second port of the DC-SCMCPLLD is connected to the BMC and the USB Type-C connector, respectively.

[0075] The MB CPLD is used to receive each of the transmission signals transmitted from the CPU based on the first port, perform level conversion on each of the transmission signals, and convert each of the level-converted transmission signals into two output signals. One of the two output signals is sent to the onboard header connector through the second port, and the other of the two output signals is sent to the first port of the DC-SCM CPLD through the third port.

[0076] The DC-SCM CPLD is used to buffer each of the received output signals based on the buffer, and send the two output signals obtained from the buffering process to the BMC and the USB Type-C connector respectively through the second port.

[0077] Based on this implementation principle, the signal conversion component can transmit signals from each UART interface of the CPU to each serial port debugging device.

[0078] In this embodiment, the level conversion and signal decomposition circuit can also be implemented in other ways, as long as it can achieve level conversion and signal decomposition. For example, it can also be implemented using an FPGA (Field Programmable Gate Array). Alternatively, it can be implemented using separate level conversion and signal decomposition circuits.

[0079] In another implementation, please refer to [the relevant documentation]. Figure 5 In this embodiment, the implementation principle is illustrated by taking a serial port debugging device including a BMC, a USB Type-C connector, and an onboard header connector, and a signal conversion component including a level conversion and signal selection circuit.

[0080] The level conversion and signal selection circuit is used to receive each of the transmitted signals from the CPU, perform level conversion on each of the transmitted signals, convert each transmitted signal after level conversion into multiple output signals, send a portion of the multiple output signals to the onboard header connector, connect to one of the UART interfaces of the CPU based on the control instructions of the BMC, and send the remaining output signals of the multiple output signals and the output signals corresponding to the connected UART interface to the BMC and the USB Type-C connector respectively.

[0081] For example, please continue reading Figure 4 The level conversion and signal selection circuit may include an MB CPLD and a DC-SCMCPLD. The MB CPLD integrates a signal selection module and a controlled module. The DC-SCMCPLLD has a built-in buffer. The first port of the MB CPLD is connected to the CPU, the second port is connected to the onboard header connector, and the third port is connected to the first port of the DC-SCMCPLLD through the signal selection module. The second port of the DC-SCMCPLLD is connected to the BMC and the USB Type-C connector respectively. The controlled module is connected between the BMC and the signal selection module.

[0082] The MB CPLD is used to receive each of the transmitted signals from the CPU via the first port, perform level conversion on each of the transmitted signals, and convert each of the level-converted transmitted signals into two output signals. One of the two output signals is sent to the onboard header connector through the second port. Based on the control command sent by the BMC to the signal selection module through the controlled module, one of the UART interfaces of the CPU is connected, and the output signal corresponding to the connected UART interface is sent to the first port of the DC-SCM CPLD through the third port.

[0083] The DC-SCM CPLD is used to buffer the received output signal based on the buffer, and send the two output signals obtained from the buffering process to the BMC and the USB Type-C connector respectively through the second port.

[0084] Based on this implementation principle, the level conversion and signal selection circuit can transmit signals from each UART interface of the CPU to the onboard header connector, and according to the control instructions of the BMC, transmit the signal of one of the UART interfaces to the BMC and the USB Type-C connector.

[0085] In this embodiment, the level conversion and signal selection circuit can also be implemented in other ways, as long as it can achieve level conversion and signal selection. For example, it can also be implemented using an FPGA. Alternatively, it can be implemented using a separate level conversion circuit and a signal selection circuit such as a MUX device.

[0086] The two signal conversion components provided in this embodiment can be flexibly selected. For example, when the number of UART interfaces on the CPU is less than or equal to the number of UART interfaces that can be connected to the BMC and USB Type-C connector, a level conversion and signal decomposition circuit can be used. As another example, when the number of UART interfaces on the CPU is greater than the number of UART interfaces that can be connected to the BMC and USB Type-C connector, a level conversion and signal selection circuit can be used. Furthermore, both a level conversion and signal decomposition circuit and a level conversion and signal selection circuit can be used simultaneously. Please refer to [link to relevant documentation]. Figure 4 The diagram illustrates the simultaneous use of level conversion and signal decomposition circuits, as well as level conversion and signal selection circuits.

[0087] In this embodiment, the rules for determining the target serial port debugging device from two or more serial port debugging devices can be flexibly selected. For example, it can be selected based on user-defined operations. Another example is selection by a preset order. Yet another example is selection based on a set priority.

[0088] For example, the target serial port debugging device can be determined by selecting one of the BMC, USB Type-C connector and onboard header connector as the target serial port debugging device based on the preset priority relationship between the BMC, USB Type-C connector and onboard header connector.

[0089] In one implementation, the priority relationship between the preset BMC, USB Type-C connector, and onboard header connector includes: for debug signals transmitted to the CPU, the onboard header connector has a higher priority than the USB Type-C connector, and the USB Type-C connector has a higher priority than the BMC.

[0090] Accordingly, please refer to the following: Figure 6 The target serial port debugging device can be determined in the following ways:

[0091] The MB CPLD is used to determine whether to place the signal selection module in a first working state or a second working state based on the high or low level state of the detection signal; wherein, the detection signal is used to detect whether there is a UART terminal in place on the onboard header connector; if it is in place, the signal selection module is placed in the first working state; if it is not in place, the signal selection module is placed in the second working state.

[0092] In the first operating state, the onboard header connector is identified as the target serial port debugger, so that the debug signal of the onboard header connector is sent to the CPU.

[0093] In the second operating state, the DC-SCM CPLD is used to determine whether a cable is inserted into the USB Type-C connector based on the high or low level of the insertion detection signal. If yes, the USB Type-C connector is identified as the target serial port debugger, and the debug signal of the USB Type-C connector is sent to the CPU. If no, the BMC is identified as the target serial port debugger, and the debug signal of the BMC is sent to the CPU.

[0094] Based on the above, this embodiment also provides an implementation method for serial port debugging. Please refer to [link / reference]. Figure 7 , Figure 7 This is a flowchart illustrating a serial port debugging method provided in an embodiment of the present invention. The serial port debugging method can be... Figure 2 The serial port debugging system shown is implemented. The serial port debugging system includes a CPU, a signal conversion component, and a serial port debugging component. The CPU and the serial port debugging component are connected through the signal conversion component. The CPU has multiple UART interfaces, and the serial port debugging component includes two or more serial port debugging devices. It should be noted that the method provided in this embodiment has the same basic principle and technical effects as the system embodiment described above. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the system embodiment described above. This serial port debugging method includes steps S110 to S150.

[0095] S110, the CPU transmits the transmit signals of each of the UART interfaces to the signal conversion component.

[0096] S120, the signal conversion component converts each of the transmitted signals from the CPU and sends the converted transmitted signals to the serial port debugging component.

[0097] S130, each of the serial port debugging devices receives the transmission signal transmitted from the signal conversion component, and determines a target serial port debugging device from two or more serial port debugging devices according to the set rules, and sends the debugging signal of the target serial port debugging device to the signal conversion component.

[0098] S140, the signal conversion component converts the debugging signal transmitted from the serial port debugging component and sends the converted debugging signal to the CPU.

[0099] S150, the CPU receives the debugging signals transmitted by the signal conversion components based on each of the UART interfaces and performs debugging processing.

[0100] In one implementation, the two or more serial port debugging devices include a BMC, a USB Type-C connector, and an onboard header connector; the signal conversion component includes level conversion and signal decomposition circuitry.

[0101] The step of the signal conversion component converting the transmitted signals from the CPU and sending the converted transmitted signals to the serial port debugging component includes: the level conversion and signal decomposition circuit receiving the transmitted signals from the CPU and performing level conversion on each transmitted signal; converting each transmitted signal after level conversion into multiple output signals; sending a portion of the multiple output signals to the onboard header connector, and sending the remaining output signals to the BMC and USB Type-C connector respectively.

[0102] In another implementation, the two or more serial port debugging devices include a BMC, a USB Type-C connector, and an onboard header connector; the signal conversion component includes level conversion and signal selection circuitry.

[0103] The step of the signal conversion component converting the transmitted signals from the CPU and sending the converted transmitted signals to the serial port debugging component includes: the level conversion and signal selection circuit receiving the transmitted signals from the CPU and performing level conversion on each transmitted signal; converting each level-converted transmitted signal into multiple output signals; sending a portion of the multiple output signals to the onboard header connector; connecting one of the CPU's UART interfaces based on the control instructions of the BMC, and sending the output signals corresponding to the connected UART interface to the BMC and the USB Type-C connector respectively.

[0104] To more clearly illustrate the technical solution of this embodiment, the implementation principle of this embodiment will be explained using the following scenario as an example.

[0105] like Figure 4 , 6 As shown, the server includes CPU0, CPU1, I2C bus (Inter-Integrated Circuit), MBCPLD, DC-SCM CPLD, BMC, DC-SCM, USB to UART chip CH348, USB Type-C connector, and header connector.

[0106] Among them, the CPU (CPU0, CPU1) has multiple UART interfaces, based on Figure 4 , 6 In the architecture shown, during the boot process, the CPU prints log information through the UART interface. Developers can choose to receive the log information printed by the CPU through the BMC, USB Type-C connector, or onboard header connector, and can also send debug commands to the CPU through the BMC, USB Type-C connector, or onboard header connector.

[0107] The BMC, USB Type-C connector, and onboard header connector can simultaneously receive log information output from the CPU's UART interface. However, only one of the three—the BMC, USB Type-C connector, and onboard header connector—can send commands to the CPU at any given time.

[0108] Please see Figure 4 This is a block diagram illustrating the implementation principle of receiving log information printed by the CPU via the BMC, USB Type-C connector, or onboard header connector.

[0109] Given that the UART TX signal level may be 1.2V, 1.8V, etc., while the BMC and CH348 require a level of 3.3V, the CPU's signal level does not match the signal level required by the BMC and CH348. To achieve signal transmission, the UART TX signal (transmit signal) from the CPU is first connected to the MB CPLD. The MB CPLD performs level conversion, converting the CPU's 1.2V, 1.8V, etc., signal level to the 3.3V signal level required by the BMC and CH348. The LS marked in the diagram stands for level shift, indicating the level conversion.

[0110] Because the CPU has multiple UART interfaces, but the BMC and CH348 only have a maximum of eight UART interfaces, when the CPU has more than eight UART interfaces, the BMC and CH348 cannot directly receive all of the CPU's UART signals simultaneously. Therefore, in this embodiment, the level signals from some of the CPU's UART interfaces are processed and output to the header connector on the MB, while the level signals from the remaining UART interfaces are processed and output to the BMC and CH348. Figure 4 As shown, the signals output from the six UART interfaces—UART0, UART2, UART3, and UART4 of CPU0, and UART3 and UART4 of CPU1—are converted from one input to two outputs after level conversion by the MB(LS). One output is sent to the header connector on the MB, and the other is sent to the DC-SCM CPLD. The DC-SCM CPLD has a built-in buffer, and after buffering, the signals are simultaneously sent to the BMC and CH348, enabling the BMC, CH348, and MB header connector to simultaneously receive UART log information.

[0111] The remaining UART TX signals of the CPU, such as Figure 4 As shown, the signals output from the six UART interfaces—UART1, UART5 of CPU0, and UART0, UART1, UART2, and UART5 of CPU1—are connected to the MB CPLD. The MB CPLD performs level conversion and MUX (multiplexer, also known as a data selector) functions. The UARTTX signal, after level conversion by the LS in the MB CPLD, is sent to the header connector on the MB. These signals enable the reception of UART log information from the CPU via the header. The I2C slave MUX control module inside the MB CPLD can receive commands from the BMC. The BMC can issue commands to the I2C slave MUX control module via I2C to switch between different UARTs. The BMC switches to the appropriate UART via I2C to receive log information from the desired UART. The UART signals output from the MUX in the MB CPLD are sent to the DC-SCM CPLD. The DC-SCM CPLD buffers the signals before simultaneously sending them to the BMC and CH348, enabling both the BMC and CH348 to receive CPU UART log information simultaneously.

[0112] Based on the above architecture, the BMC, USB Type-C connector, or onboard header connector can receive log information printed by each UART in the CPU.

[0113] Please see Figure 6 This is a block diagram illustrating the implementation principle of sending commands to the CPU via the BMC, USB Type-C connector, or onboard header connector.

[0114] Due to the electrical characteristics of UART, only one device can send instructions to the CPU at a time using the same UART. Therefore, this embodiment sets a priority. Taking the UART RX input priority as: header > CH348 > BMC as an example, the implementation principle is as follows.

[0115] UARTx_SERVER_PRENT_N is the UART terminal presence detection signal on the header, used to detect whether there is a UART terminal present on the header. The UARTx_SERVER_PRENT_N signal is sent to the MB CPLD, and the MB CPLD switches the internal 2-to-1 MUX to the header channel or the 6-to-1 MUX channel according to the high or low level of this signal.

[0116] The TypeC_Present_N signal is a detection signal for whether a cable is inserted into the USB TypeC connector. This signal is input to the DC-SCM CPLD. The DC-SCM CPLD determines whether a cable is inserted into the USB TypeC connector based on the high or low level of this signal. When the DC-SCM CPLD determines that a cable is inserted into the USB TypeC connector, it controls its internal 2-to-1 MUX to switch the UART signal to the CH348 channel, thereby realizing the start-up switching function, that is, UART RX input priority Header > CH348 > BMC.

[0117] By employing the above-described scheme in this embodiment of the invention, it is possible to realize the function of remotely debugging the CPU via serial port based on BMC, the function of locally debugging the CPU via serial port based on USB Type-C cable, or directly debugging the CPU using the onboard header. Furthermore, all three can simultaneously receive log information printed by the CPU UART without conflicting with each other. At the same time, it is also possible to realize the CPU UART RX input priority as Header>CH348>BMC, thus achieving the function of remote debugging via BMC, local debugging using USB Type-C cable, and direct debugging using header without causing UART conflicts.

[0118] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0119] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0120] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0121] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A serial port debugging system, characterized in that, include: The system comprises a CPU, a signal conversion component, and a serial port debugging component, wherein the CPU and the serial port debugging component are connected through the signal conversion component. The CPU has multiple UART interfaces, and the CPU is used to transmit the transmit signals of each UART interface to the signal conversion component, and to receive the debug signals transmitted by the signal conversion component based on each UART interface; The signal conversion component is used to convert and process each of the transmitted signals from the CPU, send the converted and processed transmitted signals to the serial port debugging component, and convert and process the debugging signals transmitted from the serial port debugging component, and send the converted and processed debugging signals to the CPU. The serial port debugging component includes two or more serial port debugging devices. Each serial port debugging device is used to receive the transmission signal transmitted from the signal conversion component, and determine a target serial port debugging device from the two or more serial port debugging devices according to the set rules, and send the debugging signal of the target serial port debugging device to the signal conversion component. The two or more serial port debugging devices include a BMC, a USB Type-C connector, and an onboard header connector; the signal conversion component includes level conversion and signal decomposition circuitry. The level conversion and signal decomposition circuit is used to receive each of the transmitted signals from the CPU, perform level conversion on each of the transmitted signals, and convert each level-converted transmitted signal into multiple output signals. A portion of the multiple output signals is sent to the onboard header connector, and the remaining output signals are sent to the BMC and the USB Type-C connector, respectively; or... The two or more serial port debugging devices include a BMC, a USB Type-C connector, and an onboard header connector; the signal conversion component includes level conversion and signal selection circuitry. The level conversion and signal selection circuit is used to receive each of the transmitted signals from the CPU, perform level conversion on each of the transmitted signals, convert each transmitted signal after level conversion into multiple output signals, send a portion of the multiple output signals to the onboard header connector, connect to one of the UART interfaces of the CPU based on the control instructions of the BMC, and send the output signals corresponding to the connected UART interfaces of the remaining multiple output signals to the BMC and the USB Type-C connector respectively.

2. The serial port debugging system according to claim 1, characterized in that, The level conversion and signal decomposition circuit includes an MB CPLD and a DC-SCM CPLD. The DC-SCM CPLD has a built-in buffer. The first port of the MB CPLD is connected to the CPU, the second port is connected to the onboard header connector, and the third port is connected to the first port of the DC-SCM CPLD. The second port of the DC-SCM CPLD is connected to the BMC and the USB Type-C connector, respectively. The MB CPLD is used to receive each of the transmission signals transmitted from the CPU based on the first port, perform level conversion on each of the transmission signals, and convert each of the level-converted transmission signals into two output signals. One of the two output signals is sent to the onboard header connector through the second port, and the other of the two output signals is sent to the first port of the DC-SCM CPLD through the third port. The DC-SCM CPLD is used to buffer each of the received output signals based on the buffer, and send the two output signals obtained from the buffering process to the BMC and the USB Type-C connector respectively through the second port.

3. The serial port debugging system according to claim 1, characterized in that, The level conversion and signal selection circuit includes an MB CPLD and a DC-SCM CPLD. The MB CPLD integrates a signal selection module and a controlled module. The DC-SCM CPLD has a built-in buffer. The first port of the MB CPLD is connected to the CPU, the second port is connected to the onboard header connector, and the third port is connected to the first port of the DC-SCM CPLD through the signal selection module. The second port of the DC-SCM CPLD is connected to the BMC and the USB Type-C connector respectively. The controlled module is connected between the BMC and the signal selection module. The MB CPLD is used to receive each of the transmitted signals from the CPU via the first port, perform level conversion on each of the transmitted signals, and convert each of the level-converted transmitted signals into two output signals. One of the two output signals is sent to the onboard header connector through the second port. Based on the control command sent by the BMC to the signal selection module through the controlled module, one of the UART interfaces of the CPU is connected, and the output signal corresponding to the connected UART interface is sent to the first port of the DC-SCM CPLD through the third port. The DC-SCM CPLD is used to buffer the received output signal based on the buffer, and send the two output signals obtained from the buffering process to the BMC and the USB Type-C connector respectively through the second port.

4. The serial port debugging system according to claim 3, characterized in that, The target serial port debugging device is determined in the following way: Based on the preset priority relationship between the BMC, USB Type-C connector and onboard header connector, one of the BMC, USB Type-C connector and onboard header connector is determined as the target serial port debugging device.

5. The serial port debugging system according to claim 4, characterized in that, The priority relationship between the preset BMC, USB Type-C connector and onboard header connector includes: for debug signals transmitted to the CPU, the onboard header connector has a higher priority than the USB Type-C connector, and the USB Type-C connector has a higher priority than the BMC. The target serial port debugging device is determined in the following way: The MB CPLD is used to determine whether to place the signal selection module in a first working state or a second working state based on the high and low level states of the detection signal; wherein, the detection signal is used to detect whether there is a UART terminal in place on the onboard header connector; if it is in place, the signal selection module is placed in the first working state; if it is not in place, the signal selection module is placed in the second working state. In the first working state, the onboard header connector is identified as the target serial port debugging device, so that the debugging signal of the onboard header connector is sent to the CPU. In the second operating state, the DC-SCM CPLD is used to determine whether a cable is inserted into the USB Type-C connector based on the high or low level of the insertion detection signal. If yes, the USB Type-C connector is identified as the target serial port debugging device, and the debugging signal of the USB Type-C connector is sent to the CPU. If no, the BMC is identified as the target serial port debugging device, and the debugging signal of the BMC is sent to the CPU.

6. A serial port debugging method, characterized in that, The method is applicable to the serial port debugging system according to any one of claims 1 to 5, wherein the serial port debugging system comprises: a CPU, a signal conversion component, and a serial port debugging component, wherein the CPU and the serial port debugging component are connected through the signal conversion component, the CPU has multiple UART interfaces, and the serial port debugging component comprises two or more serial port debugging devices; the method comprises: The CPU transmits the transmit signals of each of the UART interfaces to the signal conversion component; The signal conversion component converts each of the transmitted signals from the CPU and sends the converted transmitted signals to the serial port debugging component. Each of the serial port debugging devices receives the transmission signal from the signal conversion component, and determines a target serial port debugging device from two or more serial port debugging devices according to a set rule, and sends the debugging signal of the target serial port debugging device to the signal conversion component; The signal conversion component converts the debugging signal transmitted from the serial port debugging component and sends the converted debugging signal to the CPU. The CPU receives debugging signals transmitted by the signal conversion components based on each of the UART interfaces and performs debugging processing.

7. The serial port debugging method according to claim 6, characterized in that, The two or more serial port debugging devices include a BMC, a USB Type-C connector, and an onboard header connector; the signal conversion component includes level conversion and signal decomposition circuitry. The step of the signal conversion component converting the transmitted signals from the CPU and sending the converted signals to the serial port debugging component includes: The level conversion and signal decomposition circuit receives each of the transmitted signals from the CPU and performs level conversion on each of the transmitted signals; Each transmitted signal, after level conversion, is converted into multiple output signals; A portion of the multiple output signals are sent to the onboard header connector, and the remaining output signals are sent to the BMC and USB Type-C connector respectively.

8. The serial port debugging method according to claim 6, characterized in that, The two or more serial port debugging devices include a BMC, a USB Type-C connector, and an onboard header connector; the signal conversion component includes level conversion and signal selection circuitry. The step of the signal conversion component converting the transmitted signals from the CPU and sending the converted signals to the serial port debugging component includes: The level conversion and signal selection circuit receives each of the transmitted signals from the CPU and performs level conversion on each of the transmitted signals; Each transmitted signal, after level conversion, is converted into multiple output signals; Send a portion of the output signals from the plurality of output signals to the onboard header connector; Based on the control instructions of the BMC, one of the UART interfaces of the CPU is connected, and the output signal corresponding to the connected UART interface is sent to the BMC and the USB Type-C connector respectively.

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