A frequency-sweep processing system for power spectrum data

Abstract

The present application relates to a kind of sweep processing system of power spectrum data, belong to radar processing field field.The system of the present application includes: bit width conversion module, mean calculation module, maximum value calculation module, the 1st true dual-port RAM, the 2nd true dual-port RAM and control module.The present application is optimized to structure, packing and calculation are combined, and multi-level control module is integrated, the present application is optimized by the design and multiplexing of true dual-port RAM, and the read-write control optimization of RAM.The present application is optimized to existing structure, packing and calculation are combined, and multi-level control module is integrated, and the cumbersome control of intermediate step is reduced.Then, in the maximum value, mean packing process, by multiplexing to RAM, not only reduce the consumption of resources, while improving processing efficiency.Finally, overall framework data stream is controlled by host computer, and data packet header, packet tail are controlled, while packet data supports real-time value, maximum value, mean arbitrary combination output.

Description

Technical Field

[0001] This invention belongs to the field of radar processing, specifically relating to a frequency sweep processing system for power spectrum data. Background Technology

[0002] The radar signal is acquired and frequency swept using an FPGA (FPGA-based programmable gate array), and its block diagram is as follows: Figure 1 As shown.

[0003] Frequency sweeping is widely used in radar processing. For high-bandwidth signals, ADCs cannot directly acquire the full bandwidth; a frequency converter is needed to switch frequencies, dividing the high-bandwidth signal into several smaller bandwidth signals. Spectrum stitching technology is then used to stitch together each acquired segment to complete the acquisition of the entire frequency band. Power spectrum calculation is now mature, its purpose being to convert time-domain signals into frequency-domain signals for easier analysis by the host computer. Power spectrum data processing in FPGAs mainly involves calculating real-time values, maximum values, and average values ​​to capture instantaneous signals. The real-time value is the signal acquired at the current frequency; the maximum value is the signal value maintained over several time periods at the current frequency, used to identify hidden or sudden signals; the average value is calculated by smoothing the signal acquired over several time periods at the current frequency to reduce signal glitches or spurious signals; and data encapsulation ensures the correctness of data transmission.

[0004] Current frequency sweep processing methods include:

[0005] The State Intellectual Property Office published application number "202110240465.4" entitled "A Method for FFT Spectrum Data Processing Based on High-Speed ​​Acquisition," which discloses a method for afterglow processing of spectrum data to solve the problem of calculating real-time, maximum, and average values ​​of power spectrum data at a fixed frequency. The steps are as follows:

[0006] Fixed-frequency processing: The input data frequency is fixed, and the number of frames to be processed is set.

[0007] Calculate the maximum value, average value, and real-time value;

[0008] After a set number of iterations are reached, the power spectrum calculation is paused via a feedback mechanism.

[0009] Pack the real-time values, maximum values, and average values;

[0010] Wait for the packaging to finish, then manually switch frequencies, and repeat the cycle to achieve the frequency sweeping purpose.

[0011] like Figure 2As shown, the horizontal axis represents the time spent by each module, and the vertical axis represents the parallel processing between modules. Frequency switching is controlled by the inverter through a feedback mechanism. Power spectrum calculation is obtained by summing the squares of the FFT data and then performing a logarithmic operation, with an output bit width of 16 bits. Here, the maximum value and average count are taken as 3. The frequency point represents the signal frequency after inverter conversion, 'Framen' represents the input power spectral density, its length is 8-65536 points, the number n represents the count of the power spectral density input packets, 'Average' represents the average value calculation result, 'Max' represents the maximum value holding result, H represents the packet head, and E represents the packet tail.

[0012] To address the inefficiency of fixed-frequency processing, RAM is added before packaging to ensure pipelined input of power spectrum data and prevent data overwriting during calculation. The steps are as follows:

[0013] Set the initial frequency point and stream input the power spectrum data;

[0014] The host computer sets the number of frames to be processed, and then calculates the maximum value, average value, and real-time value;

[0015] After reaching the set number of times, the frequency point is switched, and the calculated data is stored in RAM (random access memory).

[0016] The RAM is controlled to perform read operations on the maximum value, average value, and real-time value in a round-robin fashion and then package them.

[0017] like Figure 3 As shown, the horizontal axis represents the time spent by each module, and the vertical axis represents the parallel processing between modules.

[0018] Depend on Figure 2 It is evident that for fixed-frequency processing, switching the frequency point of the inverter via feedback control after packaging is inefficient, and the signal acquisition is discontinuous, potentially losing useful information during frequency sweeping. Figure 3 As can be seen, the acquired signals are input in a continuous flow, and the frequency switching of the inverter is controlled by counting the number of FFT operations to achieve continuous data acquisition. However, during the calculation of the mean and maximum value hold, due to the continuous data input, the calculated mean, maximum value hold, and real-time value need to be stored in RAM during the data packaging process to prevent the input data from overwriting the RAM memory. However, FPGA memory resources are limited. The FFT processes 8-65536 data points. For input data with a bit width of 16 bits, at least five 16*64K memory blocks need to be reserved, which is not conducive to the internal resource consumption of the FPGA. At the same time, control signals need to be added to control RAM read and write operations, making the system operation cumbersome. Summary of the Invention

[0019] (a) Technical problems to be solved

[0020] The technical problem to be solved by this invention is how to provide a power spectrum data sweeping processing system to solve the problems of low processing efficiency of fixed frequency processing and the unfriendly consumption of FPGA internal resources by the pipelined input of the acquired signal.

[0021] (II) Technical Solution

[0022] To solve the above-mentioned technical problems, the present invention proposes a power spectrum data sweep processing system, which includes: a bit width conversion module, a mean calculation module, a maximum value calculation module, a first true dual-port RAM, a second true dual-port RAM, and a control module;

[0023] The system's input includes 16-bit data frame_din, 1-bit data validity indicator frame_din_vld, 1-bit data frame start flag frame_din_first, and 1-bit data frame end flag frame_din_last. The bit width conversion module converts the input 16-bit data into 64-bit data and outputs it to the mean calculation module and the maximum value calculation module.

[0024] The mean calculation module performs summation and division operations, outputs the 14-bit address addra and the 98-bit summed data dina to the first true dual-port RAM, and outputs the 66-bit mean_dout to the control module.

[0025] The first true dual-port RAM stores the summed data dina, outputs 98 bits of douta to the mean calculation module and the maximum value calculation module, and outputs 98 bits of doutb to the dinb port of the second true dual-port RAM, while also outputting it as real_dout to the control module.

[0026] The maximum value calculation module completes the maximum value calculation and outputs the 14-bit address and the 66-bit comparison data to the addra port and dina port of the second true dual-port RAM.

[0027] The second true dual-port RAM stores the calculated maximum value and outputs douta to the maximum value calculation module, and outputs doutb as the max_out input to the control module;

[0028] The control module controls the reading and writing of RAM and packages data. In addition to real_dout, max_out, and mean_dout, the inputs of the control module also include clk, mean_max_time, and FFT_num. The output signals are wea and addrb of the first true dual-port RAM, and dinb and web of the first true dual-port RAM are grounded; the output signals are wea, web, and addrb of the second true dual-port RAM; the outputs include the packet validity indicator package_dout_vld, the 64-bit data packet output package_dout, the packet start flag package_first, and the packet end flag package_last.

[0029] Furthermore, the 16-bit data input to the system is power spectral density data.

[0030] Furthermore, the system packages the real-time spectrum data, maximum value data, and average value data. The real-time value is the current power spectral density data, which is directly output. When calculating the maximum or average value for multiple frames, one frame is selected as the real-time value for output. The average value calculation is to add each point of the data from multiple frames and then divide by the number of frames. The maximum value calculation compares the size of each point in multiple data frames to obtain the maximum value.

[0031] Furthermore, the system's processing procedure is divided into two cases: processing one frame and processing more than one frame.

[0032] Furthermore, when calculating the mean and maximum value of a frame of data, the calculation data is the same as the input frame. When storing data in RAM, the maximum value and the mean value are stored in the same RAM. The maximum value and the mean value are obtained by reading the data twice.

[0033] Furthermore, when processing one frame of data, the real-time data, maximum value, and average value are packaged within the time of one frame.

[0034] Furthermore, when processing one frame of data, the system's processing procedure is as follows:

[0035] S11. The host computer sends packet header information, and the FPGA performs power spectrum calculation to obtain 16-bit data.

[0036] S12, 16-bit data is converted to 64-bit;

[0037] S13, the 64-bit data input average calculation module, generates the address addra based on the valid din_vld, pulls up the wea signal, and outputs data to the dina port of the first true dual-port RAM;

[0038] S14. After waiting for a period of time, the control module outputs address addrb to read the data of the first true dual-port RAM.

[0039] S15. Store the data output from the first true dual-port RAM into the second true dual-port RAM, and at the same time output the data from the first true dual-port RAM to the control module as real-time value data.

[0040] S16. The control module detects the last flag of the real-time value to control the address addrb of the second true dual-port RAM. It reads the second true dual-port RAM through two counts to obtain the maximum value and average value results.

[0041] S17. Input the real-time value, average value, and maximum value into the control module, and then perform packaging processing;

[0042] S18. For the next frame processing, return to S11 for loop operation.

[0043] Furthermore, in step S14, when reading the first true dual-port RAM, it is necessary to wait for the input data to reach 3 / 4*L before reading the data from the first true dual-port RAM, where L represents the number of FFT points.

[0044] Furthermore, when processing data larger than one frame, the system's processing procedure is as follows:

[0045] S21. The host computer sends packet header information, and the FPGA performs power spectrum calculation to obtain 16-bit data.

[0046] S22, 16-bit data is converted to 64-bit;

[0047] S23. The data input mean calculation module of the first frame generates the address addra based on the valid din_vld, and pulls up the wea signal and outputs the data to the dina pin of the first true dual-port RAM;

[0048] S24. After waiting for a period of time, the address addrb is output through the control module, and the real_data signal is output as the real-time value from the first true dual-port RAM.

[0049] S25. In the mean calculation module, based on the valid din_vld generated address addra and the high wea signal, the data of the first true dual-port RAM is read. The input data of the second frame is added to the output of the dota terminal of the first true dual-port RAM. The result of the addition is input into the first true dual-port RAM through port dina. At the same time, in the maximum value calculation module, based on the valid din_vld generated address addra and the high wea signal, the data of the second true dual-port RAM is read. The output of the dota terminal of the first true dual-port RAM is compared with the value of each point of the input data of the second frame. The maximum value is stored in the second true dual-port RAM.

[0050] S26. Add the data of the 3rd frame to the output of the first true dual-port RAM dota terminal, and input the result of the addition into the first true dual-port RAM through port a; at the same time, compare the output of the second true dual-port RAM dota terminal with each point of the data of the 3rd frame, and store the maximum value into the second true dual-port RAM;

[0051] S27. Repeat step S26. After reaching the design requirement number of times, read the output of the first true dual-port RAM douta terminal, sum it with the last frame, and then perform a division operation to obtain the average value, which is then output to the control module. At the same time, read the output of the second true dual-port RAM douta terminal and compare it with the size of the last frame. Store the maximum value into the second true dual-port RAM through the douta terminal. Wait for the average value to be calculated, and then read it from the doutb port of the second true dual-port RAM, which is the maximum value, and output it to the control module.

[0052] S28. Input the real-time value, average value, and maximum value into the control module, and then perform packaging processing;

[0053] S29, return to S21 for loop processing.

[0054] Furthermore, in step S24, when reading the first true dual-port RAM, it is necessary to wait for the input data to reach 3 / 4*L before reading the data from the first true dual-port RAM, where L represents the number of FFT points.

[0055] (III) Beneficial Effects

[0056] This invention proposes a frequency sweep processing system for power spectrum data. The system optimizes the structure by merging packetization and computation, and integrating multi-level control modules. It utilizes a true dual-port RAM design and reuse, along with optimized RAM read / write control. The advantages of this invention are: firstly, by optimizing the existing structure, merging packetization and computation, and integrating multi-level control modules, cumbersome intermediate control steps are reduced; resource comparisons are shown in Table 1. Secondly, during the packetization of maximum and average values, RAM reuse not only reduces resource consumption but also improves processing efficiency. Finally, the overall framework data flow is controlled by a host computer, which controls the data packet header and trailer, and the packetized data supports arbitrary combinations of real-time values, maximum values, and average values ​​for output. Attached Figure Description

[0057] Figure 1 This is a block diagram of the overall frequency sweep processing.

[0058] Figure 2 For fixed-frequency processing, the next frequency scan will be performed after the packaging is completed;

[0059] Figure 3 To achieve pipelined processing by increasing RAM;

[0060] Figure 4 This is a schematic diagram of the power spectrum data sweep processing system of the present invention;

[0061] Figure 5 This is a schematic diagram illustrating the processing of one frame of data according to the present invention;

[0062] Figure 6 This is a timing diagram for the bit width conversion of the present invention;

[0063] Figure 7 This is a schematic diagram illustrating the processing of more than one frame in this invention (taking 3 as an example). Detailed Implementation

[0064] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0065] The purpose of this invention is to provide a power spectrum data sweep processing system that packages the collected data and continuously uploads it to a host computer. By reusing RAM, the system improves data processing efficiency and reduces the consumption of FPGA RAM logic resources.

[0066] The real-time value is the current power spectral density data directly output. When calculating the maximum or average value for multiple frames, one frame is selected as the real-time value for output. The average value is calculated by adding the values ​​of each point across multiple frames and then dividing by the number of frames. The maximum value is calculated by comparing the values ​​of each point across multiple data frames to obtain the maximum value.

[0067] This invention requires the packaging of real-time spectrum data, maximum value data, and average value data. Each data packet includes a header, data, and a trailer. The header and trailer parameters are sent from a host computer. By reusing the average and maximum value data in RAM, RAM usage is reduced, and cumbersome operations between modules are minimized.

[0068] The system of the present invention is as follows Figure 4 As shown, the system includes: a bit width conversion module, an average value calculation module, a maximum value calculation module, a first true dual-port RAM, a second true dual-port RAM, and a control module;

[0069] Figure 4 The input is the power spectral density data calculated by the upper-layer module. It is input in frame format, including 16-bit data frame_din, 1-bit data validity indicator frame_din_vld, 1-bit data frame start flag frame_din_first, and 1-bit data frame end flag frame_din_last. The bit width conversion module converts the input 16-bit data into 64-bit data and outputs it to the mean calculation module and the maximum value calculation module.

[0070] The mean calculation module performs summation and division operations, outputs the 14-bit address addra and the 98-bit summed data dina to the first true dual-port RAM, and outputs the 66-bit mean_dout to the control module.

[0071] The first true dual-port RAM stores the summed data dina, outputs 98 bits of douta to the mean calculation module and the maximum value calculation module, and outputs 98 bits of doutb to the dinb port of the second true dual-port RAM, while also outputting it as real_dout to the control module.

[0072] The maximum value calculation module completes the maximum value calculation and outputs the 14-bit address and the 66-bit comparison data to the addra port and dina port of the second true dual-port RAM.

[0073] The second true dual-port RAM stores the calculated maximum value and outputs douta to the maximum value calculation module, and outputs doutb as the max_out input to the control module;

[0074] The control module controls the reading and writing of RAM and packages data. In addition to real_dout, max_out, and mean_dout, the inputs of the control module also include clk, mean_max_time, and FFT_num. The output signals are wea and addrb of the first true dual-port RAM, and dinb and web of the first true dual-port RAM are grounded; the output signals are wea, web, and addrb of the second true dual-port RAM; the outputs include the packet validity indicator package_dout_vld, the 64-bit data packet output package_dout, the packet start flag package_first, and the packet end flag package_last.

[0075] To ensure backward and forward compatibility and facilitate design, this invention divides data processing into two cases: processing one frame and processing more than one frame. The design concept is largely the same, only the output control signal constraints of the control module are modified. When calculating the mean and maximum value of one frame of data, the calculated data is the same as the input frame. To prevent data in RAM from being overwritten, the maximum and mean values ​​are stored in the same RAM, and read twice to obtain the maximum and mean values. The processing procedure is as follows:

[0076] Depend on Figure 5 As can be seen, the horizontal axis represents the time spent by each module, and the vertical axis represents the parallel processing between modules. Frame (F) represents the input power spectral density, with a data bit width of 16 bits and a length (L) of 8-65536 points, which can be configured via the host computer. Average (A) represents the average value calculation result, Max (M) represents the maximum value retention result, H represents the packet header, and E represents the packet tail. To process one frame of data (with the same real-time value, maximum value, and average value), to meet pipeline processing requirements, the real-time data, maximum value, and average value must be packaged within one frame. The processing steps are as follows:

[0077] S11. The host computer sends packet header information, and the FPGA performs power spectrum calculation to obtain 16-bit data.

[0078] S12 and 16-bit data are converted to 64-bit. To meet the requirements of subsequent RAM speed-up processing, the timing diagram for the continuous input bit width conversion is as follows: Figure 6 As shown;

[0079] S13, the 64-bit data input average calculation module, generates the address addra based on the valid din_vld, pulls up the wea signal, and outputs data to the dina port of the first true dual-port RAM;

[0080] S14. After waiting for a period of time, the control module outputs address addrb to read the data of the first true dual-port RAM.

[0081] S15. Store the data output from the first true dual-port RAM into the second true dual-port RAM, and at the same time output the data from the first true dual-port RAM to the control module as real-time value data.

[0082] S16. The control module detects the last flag of the real-time value to control the address addrb of the second true dual-port RAM. It reads the second true dual-port RAM through two counts to obtain the maximum value and average value results.

[0083] S17. Input the real-time value, average value, and maximum value into the control module, and then perform packaging processing;

[0084] S18. For the next frame processing, return to S11 for loop operation.

[0085] Note: In step S14, wait for a period of time to write the data of the first true dual-port RAM into the second true dual-port RAM. Since the data is converted from 16-bit to 64-bit for processing, in order to save time by reducing area, when reading the data of the first true dual-port RAM, it is necessary to wait for the input data to reach 3 / 4*L (L represents the number of FFT points) before reading the data of the first true dual-port RAM to prevent the read from being empty.

[0086] From the above Figure 7 It can be seen that the maximum value and mean value are calculated for data exceeding one frame. The processing steps are as follows:

[0087] S21. The host computer sends packet header information, and the FPGA performs power spectrum calculation to obtain 16-bit data.

[0088] S22, 16-bit data is converted to 64-bit to meet the requirements of subsequent RAM speed-up processing. The timing diagram for continuous input bit width conversion is shown above. Figure 6 ;

[0089] S23. The data input mean calculation module of the first frame generates the address addra based on the valid din_vld, and pulls up the wea signal and outputs the data to the dina pin of the first true dual-port RAM;

[0090] S24. After waiting for a period of time, the address addrb is output through the control module, and the real_data signal is output as the real-time value from the first true dual-port RAM.

[0091] S25. In the mean calculation module, based on the valid din_vld generated address addra and the high wea signal, the data of the first true dual-port RAM is read. The input data of the second frame is added to the output of the dota terminal of the first true dual-port RAM. The result of the addition is input into the first true dual-port RAM through port dina. At the same time, in the maximum value calculation module, based on the valid din_vld generated address addra and the high wea signal, the data of the second true dual-port RAM is read. The output of the dota terminal of the first true dual-port RAM is compared with the value of each point of the input data of the second frame. The maximum value is stored in the second true dual-port RAM.

[0092] S26. Add the data of the 3rd frame to the output of the first true dual-port RAM dota terminal, and input the result of the addition into the first true dual-port RAM through port a; at the same time, compare the output of the second true dual-port RAM dota terminal with each point of the data of the 3rd frame, and store the maximum value into the second true dual-port RAM;

[0093] S27. Repeat step S26. After reaching the design requirement number of times, read the output of the first true dual-port RAM douta terminal, sum it with the last frame, and then perform a division operation to obtain the average value, which is then output to the control module. At the same time, read the output of the second true dual-port RAM douta terminal and compare it with the size of the last frame. Store the maximum value into the second true dual-port RAM through the douta terminal. Wait for the average value to be calculated, and then read it from the doutb port of the second true dual-port RAM, which is the maximum value, and output it to the control module.

[0094] S28. Input the real-time value, average value, and maximum value into the control module, and then perform packaging processing;

[0095] S29, return to S21 for loop processing.

[0096] Table 1 shows the resource priority display of the present invention:

[0097] Table 1 Resource Comparison

[0098]

[0099] This invention optimizes the structure by merging packetization and computation, and integrating multi-level control modules. It achieves this through the design and reuse of true dual-port RAM, as well as optimized RAM read / write control. The advantages of this invention are: firstly, by optimizing the existing structure, merging packetization and computation, and integrating multi-level control modules, cumbersome intermediate control steps are reduced; resource comparisons are shown in Table 1. Secondly, during the packetization of maximum and average values, RAM reuse not only reduces resource consumption but also improves processing efficiency. Finally, the overall framework data flow is controlled by a host computer, which controls the data packet header and footer, and the packetized data supports arbitrary combinations of real-time values, maximum values, and average values ​​for output.

[0100] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A power spectrum data sweep processing system, characterized in that, The system includes: a bit width conversion module, an average value calculation module, a maximum value calculation module, a first true dual-port RAM, a second true dual-port RAM, and a control module; The system's input includes 16-bit data frame_din, 1-bit data validity indicator frame_din_vld, 1-bit data frame start flag frame_din_first, and 1-bit data frame end flag frame_din_last. The bit width conversion module converts the input 16-bit data into 64-bit data and outputs it to the mean calculation module and the maximum value calculation module. The mean calculation module performs summation and division operations, outputs the 14-bit address addra and the 98-bit summed data dina to the first true dual-port RAM, and outputs the 66-bit mean_dout to the control module. The first true dual-port RAM stores the summed data dina, outputs 98 bits of douta to the mean calculation module and the maximum value calculation module, and outputs 98 bits of doutb to the dinb port of the second true dual-port RAM, while also outputting it as real_dout to the control module. The maximum value calculation module completes the maximum value calculation and outputs the 14-bit address and the 66-bit comparison data to the addra port and dina port of the second true dual-port RAM; The second true dual-port RAM stores the calculated maximum value and outputs douta to the maximum value calculation module, and outputs doutb as the max_out input to the control module; The control module controls the reading and writing of RAM and packages data. In addition to real_dout, max_out, and mean_dout, the inputs of the control module also include clk, mean_max_time, and FFT_num. The output signals are wea and addrb of the first true dual-port RAM, and dinb and web of the first true dual-port RAM are grounded; the output signals are wea, web, and addrb of the second true dual-port RAM; the outputs include the packet validity indicator package_dout_vld, the 64-bit data packet output package_dout, the packet start flag package_first, and the packet end flag package_last.

2. The power spectrum data sweep processing system as described in claim 1, characterized in that, The system inputs 16-bit data, which is power spectral density data.

3. The power spectrum data sweep processing system as described in claim 2, characterized in that, The system packages real-time spectrum data, maximum value data, and average value data. The real-time value is the current power spectral density data, which is directly output. When calculating the maximum or average value for multiple frames, one frame is selected as the real-time value for output. The average value is calculated by adding each point of data from multiple frames and then dividing by the number of frames. The maximum value is calculated by comparing the values ​​of each point in multiple data frames to obtain the maximum value.

4. The power spectrum data sweep processing system according to any one of claims 1-3, characterized in that, The system's processing procedure is divided into two cases: processing one frame and processing more than one frame.

5. The power spectrum data sweep processing system as described in claim 4, characterized in that, When calculating the mean and maximum value of a frame of data, the calculation data is the same as the input frame. When storing in RAM, the maximum value and the mean value are stored in the same RAM. The maximum value and the mean value are obtained by reading twice.

6. The power spectrum data sweep processing system as described in claim 4, characterized in that, When processing one frame of data, the real-time data, maximum value, and average value are packaged within one frame's time.

7. The power spectrum data sweep processing system as described in claim 4, characterized in that, When processing one frame of data, the system processes it as follows: S11. The host computer sends packet header information, and the FPGA performs power spectrum calculation to obtain 16-bit data. S12, 16-bit data is converted to 64-bit; S13, the 64-bit data input average calculation module, generates the address addra based on the valid din_vld, pulls up the wea signal, and outputs data to the dina port of the first true dual-port RAM; S14. After waiting for a period of time, the control module outputs address addrb to read the data of the first true dual-port RAM. S15. Store the data output from the first true dual-port RAM into the second true dual-port RAM, and at the same time output the data from the first true dual-port RAM to the control module as real-time value data. S16. The control module detects the last flag of the real-time value to control the address addrb of the second true dual-port RAM. It reads the second true dual-port RAM through two counts to obtain the maximum value and average value results. S17. Input the real-time value, average value, and maximum value into the control module, and then perform packaging processing; S18. For the next frame processing, return to S11 for loop operation.

8. The power spectrum data sweep processing system as described in claim 7, characterized in that, In step S14, when reading the first true dual-port RAM, it is necessary to wait for the input data to reach 3 / 4*L before reading the data from the first true dual-port RAM, where L represents the number of FFT points.

9. The power spectrum data sweep processing system as described in claim 4, characterized in that, When processing more than one frame of data, the system processes it as follows: S21. The host computer sends packet header information, and the FPGA performs power spectrum calculation to obtain 16-bit data. S22, 16-bit data is converted to 64-bit; S23. The data input mean calculation module of the first frame generates the address addra based on the valid din_vld, and pulls up the wea signal and outputs the data to the dina pin of the first true dual-port RAM; S24. After waiting for a period of time, the address addrb is output through the control module, and the real_data signal is output as the real-time value from the first true dual-port RAM. S25. In the mean calculation module, based on the valid address addra generated by din_vld and the high wea signal, the data of the first true dual-port RAM is read, the input data of the second frame is added to the output of the dota terminal of the first true dual-port RAM, and the result after addition is input into the first true dual-port RAM through port dina. Meanwhile, in the maximum value calculation module, based on the valid address addra generated by din_vld and the high wea signal, the data of the second true dual-port RAM is read, the output of the dota terminal of the first true dual-port RAM is compared with the size of each point of the second frame input data, and the maximum value is stored in the second true dual-port RAM. S26. Add the data of the 3rd frame to the output of the first true dual-port RAM doubleta terminal, and input the result of the addition into the first true dual-port RAM through port a; at the same time, compare the output of the second true dual-port RAM doubleta terminal with each point of the data of the 3rd frame, and store the maximum value into the second true dual-port RAM; S27. Repeat step S26. After reaching the design requirement number of times, read the output of the first true dual-port RAM douta terminal, sum it with the last frame, and then perform a division operation to obtain the average value, which is then output to the control module. At the same time, read the output of the second true dual-port RAM douta terminal and compare it with the size of the last frame. Store the maximum value into the second true dual-port RAM through the douta terminal. Wait for the average value to be calculated, and then read it from the doutb port of the second true dual-port RAM, which is the maximum value, and output it to the control module. S28. Input the real-time value, average value, and maximum value into the control module, and then perform packaging processing; S29, return to S21 for loop processing.

10. The power spectrum data sweep processing system as described in claim 9, characterized in that, In step S24, when reading the first true dual-port RAM, it is necessary to wait for the input data to reach 3 / 4*L before reading the data from the first true dual-port RAM, where L represents the number of FFT points.

Images