Watchdog circuits and control methods

Abstract

This invention provides a watchdog circuit and control method, comprising: an external module, and a watchdog module, a current regulator, and an oscillator interconnected with each other; one end of the external module is connected to the current regulator, and the other end of the external module is grounded; the current regulator is used to generate an effective enable signal and a first bias current to the oscillator and to generate a normal control signal to the watchdog module when the external module is in a preset normal state; the oscillator is used to generate a normal clock signal to the watchdog module when it receives the effective enable signal and the first bias current; the watchdog module is used to output a watchdog time window with a duration related to the external module when it receives the normal control signal and the normal clock signal. In this method, the duration of the watchdog time window of the watchdog module is controlled by the external module and the current regulator, thereby making the watchdog applicable to more application scenarios and saving circuit costs.

Description

Technical Field

[0001] This invention relates to the field of watchdog circuit technology, and in particular to a watchdog circuit and control method. Background Technology

[0002] In automotive microcontroller or microprocessor power applications, watchdog timers are used to monitor the microcontroller's operating status to prevent software malfunctions. In a reliable system, the watchdog timer needs to be independent of the microcontroller. Existing watchdog circuits control the duration of the watchdog window by the input clock frequency, but the clock frequency input to the watchdog circuit is a fixed value, and the duration of the watchdog window cannot be changed, making it unsuitable for microcontrollers that require different clock frequencies. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a watchdog circuit and control method, thereby changing the duration of the watchdog window according to the change of the resistance of the external module, and thus making the watchdog applicable to more application scenarios.

[0004] In a first aspect, embodiments of the present invention provide a watchdog circuit, comprising: an external module, and a watchdog module, a current regulator, and an oscillator interconnected with each other; one end of the external module is connected to the current regulator, and the other end of the external module is grounded; the current regulator is configured to generate an effective enable signal and a first bias current to the oscillator and generate a normal control signal to the watchdog module when the external module is in a preset normal state; and to generate an invalid enable signal and a second bias current to the oscillator and generate an abnormal control signal to the watchdog module when the external module is in a preset abnormal state; the oscillator is configured to generate a normal clock signal to the watchdog module when it receives an effective enable signal and a first bias current; and to generate an abnormal clock signal to the watchdog module when it receives an invalid enable signal and a second bias current; the watchdog module is configured to, when it receives a normal control signal and a normal clock signal, output an abnormal alert related to the duration of the watchdog window output; and when it receives an abnormal control signal and an abnormal clock signal.

[0005] Furthermore, the bias current generation unit includes a second MOSFET; wherein, the bias current generation unit is connected to the external module and the oscillator respectively; the first current comparison unit, the second current comparison unit, the enable signal generation unit, the oscillator, and the watchdog module are respectively connected to the digital logic unit; the bias current generation unit is used to generate a bias current to the oscillator according to the external module, and mirror the current of the second MOSFET to the first current comparison unit, the second current comparison unit, and the enable signal generation unit; the first current comparison unit is used to generate a first comparison current according to the ratio of the second MOSFET current and the first current; when the external module is in a preset normal state, it outputs a high level to the digital logic unit; when the external module is in a preset abnormal state and the first comparison current is greater than or equal to the second current source current provided by the second current source, it outputs a high level to the digital logic unit; when the external module is in a preset abnormal state and the first comparison current is less than the second current source current, it outputs a low level to the digital logic unit; the second current comparison unit is used to generate a second comparison current according to the ratio of the second MOSFET current and the second current; when the external module... Under the preset normal condition, a low level is output to the digital logic unit; when the external module is under the preset abnormal condition and the second comparison current is greater than or equal to the current provided by the third current source, a high level is output to the digital logic unit; when the external module is under the preset abnormal condition and the second comparison current is less than the current provided by the third current source, a low level is output to the digital logic unit; an enable signal generation unit is used to output a high level to the digital logic unit when the current of the second MOSFET is within the preset current range; and to output a low level to the digital logic unit when the current of the second MOSFET is not within the preset current range; the digital logic unit is used to generate a normal control signal to the watchdog module when it receives a high level output from the first current comparison unit and a low level output from the second current comparison unit; to generate an abnormal control signal to the watchdog module when both the first current comparison unit and the second current comparison unit output a high level or a low level; to generate a valid enable signal to the oscillator when it receives a high level output from the enable signal generation unit; and to generate an invalid enable signal to the oscillator when it receives a low level output from the enable signal generation unit.

[0006] Furthermore, the bias current generation unit includes a connected current mirror circuit and a first bias current generation circuit; the first bias current generation circuit includes an operational amplifier and a first MOSFET; the current mirror circuit includes a second MOSFET and a third MOSFET; the positive input terminal of the operational amplifier is a reference voltage input terminal; the negative input terminal of the operational amplifier and the source of the first MOSFET are connected to one end of the external module; the output terminal of the operational amplifier is connected to the gate of the first MOSFET; the gate of the second MOSFET is connected to the gate of the third MOSFET; the source of the second MOSFET is connected to the source of the third MOSFET; the drain of the second MOSFET is connected to the gate of the third MOSFET and the drain of the first MOSFET respectively; the drain of the third MOSFET is connected to the oscillator; the width-to-length ratio of the second MOSFET and the width-to-length ratio of the third MOSFET are set according to a first preset ratio; the first bias current generation circuit is used to form a loop with the second MOSFET when the external module is in a preset normal state, generating a normal second MOSFET current related to the external module; the current mirror circuit is used to generate a first bias current of the second MOSFET through the third MOSFET and send the first bias current to the oscillator.

[0007] Furthermore, the bias current generation unit also includes a second bias current generation circuit, which is connected to a current mirror circuit. The second bias current generation circuit includes a fourth MOSFET, a fifth MOSFET, a first resistor, and a first current source. The source of the fourth MOSFET is connected to the source of the second MOSFET. The gate of the fourth MOSFET is connected to the source of the fifth MOSFET and the drain of the second MOSFET. The drain of the fourth MOSFET and the gate of the fifth MOSFET are connected to the input terminal of the first current source. The width-to-length ratio of the second MOSFET and the width-to-length ratio of the fourth MOSFET are set according to a second preset ratio. The drain of the fifth MOSFET is connected to one end of the first resistor. The other end of the first resistor and the output terminal of the first current source are grounded. The second bias current generation circuit is used to form a loop with the second MOSFET when the external module is in a preset abnormal condition, and generate an abnormal second MOSFET current according to the first current source. The current mirror circuit is used to generate a second bias current of the second MOSFET through a third MOSFET and send the second bias current to the oscillator.

[0008] Furthermore, the first current comparison unit also includes a sixth MOSFET; wherein the gate and drain of the sixth MOSFET are connected to the input terminal of the second current source and the digital logic unit; the output terminal of the second current source is grounded; the sixth MOSFET is used to output a high level to the digital logic unit when the external module is in a preset normal state; to generate a first comparison current according to the ratio of the second MOSFET current and the first current, to obtain the second current source current and compare it with the first comparison current; when the external module is in a preset abnormal state and the first comparison current is greater than or equal to the second current source current, to output a high level to the digital logic unit; when the external module is in a preset abnormal state and the first comparison current is less than the second current source current, to output a low level to the digital logic unit.

[0009] Furthermore, the second current comparison unit also includes a seventh MOS transistor; wherein the gate and drain of the seventh MOS transistor are connected to the input terminal of the third current source and the digital logic unit; the output terminal of the third current source is grounded; the seventh MOS transistor is used to output a low level to the digital logic unit when the external module is in a preset normal state; to generate a second comparison current according to the ratio of the second MOS transistor current and the second current, to obtain the current of the third current source and compare it with the second comparison current; when the external module is in a preset abnormal state and the second comparison current is greater than or equal to the current of the third current source, to output a high level to the digital logic unit; when the external module is in a preset abnormal state and the second comparison current is less than the current of the third current source, to output a low level to the digital logic unit.

[0010] Furthermore, the enable signal generation unit includes an eighth MOS transistor and a first capacitor; wherein, the drain of the eighth MOS transistor is connected to one end of the first capacitor and the digital logic unit; the other end of the first capacitor is grounded; the eighth MOS transistor is used to obtain the current of the second MOS transistor to charge the first capacitor, and when the current of the second MOS transistor is within a preset current range, it outputs a high level to the digital logic unit; when the current of the second MOS transistor is not within the preset current range, it outputs a low level to the digital logic unit.

[0011] Furthermore, the enable signal generation unit includes an eighth MOS transistor and a first capacitor; wherein, the drain of the eighth MOS transistor is connected to one end of the first capacitor and the digital logic unit respectively; the other end of the first capacitor is grounded; the eighth MOS transistor is used to obtain the current of the second MOS transistor to charge the first capacitor, and when the current of the second MOS transistor is within a preset current range, it outputs a high level to the digital logic unit; when the current of the second MOS transistor is not within the preset current range, it outputs a low level to the digital logic unit.

[0012] Furthermore, the default normal condition is that the external resistor of the external module is within the preset resistance range.

[0013] Secondly, embodiments of the present invention provide a control method for a watchdog circuit, used to control the watchdog circuit of any of the above-mentioned claims. The method includes: when the external module is in a preset normal state, generating an effective enable signal and a first bias current to an oscillator through a current regulator, and generating a normal control signal to the watchdog module; generating a normal clock signal to the watchdog module through the oscillator; the output duration of the watchdog window of the watchdog module is related to the external module; when the external module is in a preset abnormal state, generating an invalid enable signal and a second bias current to an oscillator through a current regulator, and generating an abnormal control signal to the watchdog module; generating an abnormal clock signal to the watchdog module through the oscillator; and outputting an abnormal alert through the watchdog module.

[0014] This invention provides a watchdog circuit and control method, including: an external module, and a watchdog module, a current regulator, and an oscillator interconnected with each other; one end of the external module is connected to the current regulator, and the other end of the external module is grounded; the current regulator is used to generate an effective enable signal and a first bias current to the oscillator and generate a normal control signal to the watchdog module when the external module is in a preset normal state; when the external module is in a preset abnormal state, it generates an invalid enable signal and a second bias current to the oscillator and generates an abnormal control signal to the watchdog module; the oscillator is used to generate a normal clock signal to the watchdog module when it receives the effective enable signal and the first bias current; and generate an abnormal clock signal to the watchdog module when it receives the invalid enable signal and the second bias current; the watchdog module is used to output an abnormal warning when it receives the normal control signal and the normal clock signal, with the duration of the watchdog window output related to the external module; and output an abnormal warning when it receives the abnormal control signal and the abnormal clock signal. In this approach, the watchdog time window duration of the watchdog module is controlled by an external module and a current regulator, thereby making the watchdog suitable for more application scenarios and saving circuit costs.

[0015] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a watchdog circuit provided in Embodiment 1 of the present invention;

[0019] Figure 2 This is a schematic diagram of a current regulator circuit provided in Embodiment 1 of the present invention;

[0020] Figure 3 This is a schematic diagram of the bias current generation unit provided in Embodiment 1 of the present invention;

[0021] Figure 4 This is a flowchart of the control method for the watchdog circuit provided in Embodiment 2 of the present invention.

[0022] Icons: 1-Watchdog module; 2-Current regulator; 3-Oscillator; 4-External module; 21-Digital logic unit; 22-Bias current generation unit; 23-First current comparison unit; 24-Second current comparison unit; 25-Enable signal generation unit. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] To accommodate different microcontroller frequencies, this invention proposes a circuit structure where the watchdog window duration is user-adjustable. This circuit utilizes an external resistor R in an external module connected between the current regulator's ROSC pin and ground. ROSC Changing the magnitude of the current induces different currents through a current regulator, which in turn controls the oscillator frequency, ultimately resulting in different watchdog window durations. The clock frequency changes linearly with variations in the external resistor. This design is suitable for a wider range of scenarios and is more cost-effective.

[0025] To facilitate understanding of this embodiment, the embodiments of the present invention will be described in detail below.

[0026] Example 1:

[0027] Figure 1This is a schematic diagram of a watchdog circuit provided in Embodiment 1 of the present invention.

[0028] Reference Figure 1 The watchdog circuit includes: an external module 4, and a watchdog module 1, a current regulator 2, and an oscillator 3 that are interconnected with each other; one end of the external module 4 is connected to the current regulator 2, and the other end of the external module 4 is grounded.

[0029] Here, the current regulator 2 is connected to the external module via the ROSC pin.

[0030] Current regulator 2 is used to generate an effective enable signal ICurrent_OK = 1 and a first bias current I when the external module 4 is in a preset normal state. I_OSC1 The signal is sent to the oscillator, and a normal state control signal ROSC_MON_FAULT = 0 is generated and sent to the watchdog module; when the external module is in a preset abnormal state, an invalid enable signal ICurrent_OK = 0 and a second bias current I are generated. I_OSC2 The signal is sent to the oscillator, and an abnormal state control signal ROSC_MON_FAULT=1 is generated and sent to the watchdog module 1.

[0031] Here, the bias current I I_OSC Including the first bias current I I_OSC1 Second bias current I I_OSC2 .

[0032] The default normal setting is the external resistor R of external module 4. ROSC Within the preset resistance range, where R ROSC The preset resistance range is 20kΩ to 200kΩ.

[0033] The default abnormal condition is the external resistor R of external module 4. ROSC If the resistance is not within the preset range, or includes one or more of the following situations: the external module is unconnected, the external module is shorted to the power supply, the external module is shorted to ground, or the external module consists of a connected resistor and a large-capacity capacitor.

[0034] Oscillator 3 is used to generate a normal clock signal CLK_OSC1 to the watchdog module when it receives a valid enable signal ICurrent_OK=1 and a first bias current I_OSC1; and to generate an abnormal clock signal CLK_OSC2 to the watchdog module when it receives an invalid enable signal ICurrent_OK=0 and a second bias current I_OSC2.

[0035] Here, the clock signal CLK_OSC includes the normal clock signal CLK_OSC1 and the abnormal clock signal CLK_OSC2.

[0036] When the current regulator 2 controls the oscillator 3 to generate a bias current I at the clock frequency I_OSC When unstable, current regulator 2 disables oscillator 3 from generating the clock signal CLK_OSC. Bias current I I_OSC After stabilization, oscillator 3 generates a clock signal CLK_OSC. Regardless of whether the external module is in a preset normal or preset abnormal state, oscillator 3 can output the clock signal CLK_OSC to watchdog module 1.

[0037] Specifically, referring to formula (1), the clock period t of the clock signal CLK_OSC osc With bias current I I_OSC The relationship between them is:

[0038]

[0039] Among them, t osc k is the clock period of the clock signal CLK_OSC. osc k is the oscillation coefficient related to the internal reference voltage and capacitance of the oscillator. osc =2×10 -12 I I_OSC This is the bias current.

[0040] Watchdog module 1 is used to control the duration of the watchdog window when normal control signals and normal clock signals are received, with the resistance value of the external resistor in external module 4 corresponding to the duration of the watchdog window; and to output an abnormal alert when abnormal control signals and abnormal clock signals are received.

[0041] Here, the duration of the watchdog time window can be determined by the user through an external resistor R. ROSC It is customizable to adapt to the clock frequencies of different microcontrollers, making it widely applicable. When the watchdog module receives abnormal control signals or abnormal clock signals, there is still a corresponding watchdog time window duration, but the watchdog module will also output an abnormal alert to indicate the system malfunction.

[0042] The duration of the watchdog time window is given by formula (2):

[0043] t WD =k WD ×t osc (2)

[0044] Among them, t WD For the duration of the watchdog, k WD The time coefficient for the watchdog timer is related to the counting module within the watchdog timer module, k. WD =5000.

[0045] Figure 2This is a schematic diagram of a current regulator circuit provided in Embodiment 1 of the present invention.

[0046] Reference Figure 2 The current regulator 2 includes a digital logic unit 21 and a bias current generation unit 22, a first current comparison unit 23, a second current comparison unit 24 and an enable signal generation unit 25 connected in sequence; wherein, the first current comparison unit 23 includes a second current source I_bias2; and the second current comparison unit 24 includes a third current source I_bias3.

[0047] Here, the second current source I_bias2 and the third current source I_bias3 are unequal internal reference currents.

[0048] The bias current generation unit 22 includes a second MOS transistor M2; wherein, the bias current generation unit 22 is connected to the external module 4 and the oscillator 3 respectively; the first current comparison unit 23, the second current comparison unit 24, the enable signal generation unit 25, the oscillator 3 and the watchdog module 1 are connected to the digital logic unit 21 respectively.

[0049] The bias current generation unit 22 is used to generate a bias current to the oscillator 3 according to the external module 4, and to mirror the current of the second MOS transistor M2 to the first current comparison unit 23, the second current comparison unit 24 and the enable signal generation unit 25 according to a preset ratio.

[0050] Figure 3 This is a schematic diagram of the bias current generation unit provided in Embodiment 1 of the present invention.

[0051] In one embodiment, reference is made to Figure 3 The bias current generation unit 22 includes a connected current mirror circuit and a first bias current generation circuit; the first bias current generation circuit includes an operational amplifier AMP and a first MOSFET M1; the current mirror circuit includes a second MOSFET M2 and a third MOSFET M3.

[0052] The positive input terminal of the operational amplifier is the reference voltage V. REF Input terminal; the negative input terminal of the operational amplifier and the source of the first MOS transistor M1 are connected to one end of the external module 4; the output terminal of the operational amplifier AMP is connected to the gate of the first MOS transistor M1.

[0053] Here, the reference voltage V REF This is the internal reference voltage.

[0054] The gate of the second MOSFET M2 is connected to the gate of the third MOSFET M3; the source of the second MOSFET M2 is connected to the source of the third MOSFET M3; and the drain of the second MOSFET M2 is connected to the gate of the third MOSFET M3 and the drain of the first MOSFET M1, respectively.

[0055] The drain of the third MOSFET M3 is connected to the oscillator 3.

[0056] The width-to-length ratio of the second MOSFET M2 and the width-to-length ratio of the third MOSFET M3 are set according to a first preset ratio.

[0057] Here, the first preset ratio is M2:M3 = 50:1.

[0058] The first bias current generation circuit is used to form a loop with the second MOSFET M2 when the external module 4 is in a preset normal state, and generate the normal second MOSFET current I related to the external module 4. M21 .

[0059] Here, when the external module is in the preset normal state, the external module is an external resistor R within the preset resistance range. ROSC Normal second MOSFET current I M21 With external resistor R ROSC The current flowing through them is equal, as shown in the following formula (3):

[0060]

[0061] Among them, I M21 For the normal second MOSFET M2 current, I ROSC R is the current through the external resistor. ROSC The value of the external resistor is 1, where 1 represents the voltage 1V. REF =V ROSC =1V, V REF V is the reference voltage. ROSC This is the voltage across the external resistor.

[0062] The current mirror circuit is used to obtain the first bias current I_OSC1 of the second MOSFET M2 by mirroring the third MOSFET M3, and send the first bias current I_OSC1 to the oscillator 3.

[0063] Here, the magnitude of the first bias current is as shown in formula (4):

[0064]

[0065] Among them, I I_OSC1 This is the first bias current. The first preset ratio is the width-to-length ratio of the third MOSFET M3 to the width-to-length ratio of the second MOSFET M2.

[0066] Combining formulas (1), (2), and (4), it can be seen that when the external module is in the preset normal state, that is, the external resistor R is within the preset resistance range. ROSCThe duration of the watchdog window is as shown in formula (5):

[0067] t WD =R ROSC ×k WD ×k OSC ×50=R ROSC ×0.5×10 -6 (5)

[0068] In one embodiment, reference is made to Figure 3 The bias current generation unit 22 also includes a second bias current generation circuit, which is connected to the current mirror circuit. The second bias current generation circuit includes a fourth MOS transistor M4, a fifth MOS transistor M5, a first resistor R1, and a first current source I_bias1.

[0069] Here, the first current source I_bias1 is an internal reference current that is not equal to the second current source I_bias2 and the third current source I_bias3.

[0070] The source of the fourth MOSFET M4 is connected to the source of the second MOSFET M2; the gate of the fourth MOSFET M4 is connected to the source of the fifth MOSFET M5 and the drain of the second MOSFET M2; the drain of the fourth MOSFET M4 and the gate of the fifth MOSFET M5 are connected to the input terminal of the first current source; wherein, the width-to-length ratio of the second MOSFET M2 and the width-to-length ratio of the fourth MOSFET M4 are set according to a second preset ratio.

[0071] Here, the second preset ratio is: M2:M4 = 30:1.

[0072] The drain of the fifth MOSFET M5 is connected to one end of the first resistor R1; the other end of the first resistor R1 and the output terminal of the first current source I_bias1 are grounded.

[0073] The second bias current generation circuit is used to form a loop with the second MOSFET M2 when the external module 4 is in a preset abnormal condition, and to generate an abnormal second MOSFET current I based on the first current source I_bias1. M22 .

[0074] Here, when the external module is in a preset abnormal condition, I I_OSC2 This is determined by the internal circuitry. Specifically, when the external module is shorted to ground, I... I_OSC2 Determined by the internal circuitry, I at this time I_OSC2 =30uA. When the external module is unconnected or shorted to the power supply, I I_OSC2 Determined by the internal circuitry, I at this time I_OSC2 =10nA.

[0075] When external module 4 is an external resistor outside the preset resistance range, or external module is empty, or external module is shorted to power supply, or external module is shorted to ground, the second MOSFET M2, the fourth MOSFET M4, the fifth MOSFET M5, the first resistor R1 and the first current source I_bias1 form a circuit.

[0076] When external module 4 consists of a connected resistor and a large-capacity capacitor, V ROSC Voltage build-up is slow; current regulator 2 is enabled up to V. ROSC Before setup, ROSC_MON_FAULT = 1, watchdog module 1 outputs an exception report, and oscillator 3 outputs an exception clock signal CLK_OSC2; V ROSC After the voltage is established, ROSC_MON_FAULT = 0, the watchdog timer works normally, and the output of oscillator 3 is connected to R. ROSC Related clocks.

[0077] The current mirror circuit is used to generate the second bias current I_OSC2 of the second MOSFET M2 through the third MOSFET M3, and send the second bias current I_OSC2 to the oscillator 3.

[0078] The first current comparison unit 23 is used to compare the second MOS transistor current I. M2 The first comparison current I1 is generated by the ratio of the first current; when the external module 4 is in a preset normal state, the high level ISNS_LCALMP=1 is output to the digital logic unit 21; when the external module 4 is in a preset abnormal state and the first comparison current I1 is greater than or equal to the second current source current I provided by the second current source I_bias2, the comparison current I1 is generated by the ratio of the first current to the second current source I_bias2. I_bias2 When the first comparison current I1 is less than the second current source current I, the output level ISNS_LCALMP = 1 is sent to digital logic unit 21; when the first comparison current I1 is less than the second current source current I I_bias2 When the output is low, ISNS_LCALMP = 0 is output to digital logic unit 21.

[0079] In one embodiment, reference is made to Figure 2 The first current comparison unit 23 includes a sixth MOS transistor M6 and a second current source I_bias2; wherein the gate and drain of the sixth MOS transistor M6 are connected to the input terminal of the second current source I_bias2 and the digital logic unit 21; the output terminal of the second current source I_bias2 is grounded.

[0080] The sixth MOSFET M6 is used to output a high level ISNS_LCALMP=1 to the digital logic unit 21 when the external module 4 is in the preset normal state.

[0081] According to the second MOSFET current I M2The first comparison current I1 is generated by proportionalizing the first current, and the second current source current I is obtained. I_bias2 And compare it with the first comparison current I1. When the external module 4 is in a preset abnormal state and the first comparison current I1 is greater than or equal to the second current source current I... I_bias2 When the external module 4 is in a preset abnormal state and the first comparison current I1 is less than the second current source current I, the output level ISNS_LCALMP = 1 is sent to the digital logic unit; when the external module 4 is in a preset abnormal state and the first comparison current I1 is less than the second current source current I, the output level ISNS_LCALMP = 1 is sent to the digital logic unit. I_bias2 When the output is low, ISNS_LCALMP = 0 is output to digital logic unit 21.

[0082] Here, the first current ratio is a preset current ratio between the sixth MOSFET M6 and the second MOSFET M2, and the first comparison current I1 is the current generated by the sixth MOSFET M6 according to the first current ratio and flowing through the sixth MOSFET M6.

[0083] When external module 4 is in the preset abnormal state, i.e., R ROSC When the resistance value is too high, the external module is unconnected, or the external module is shorted to the power supply, I1 becomes less than I. I_bias2 When the external module is in a preset abnormal state, the output level ISNS_LCALMP = 0; when the external module is in a preset abnormal state, i.e., R ROSC If the resistance value is too low or the external module is shorted to ground, I1 will be greater than or equal to I. I_bias2 When this occurs, the output level ISNS_LCALMP = 1 is high.

[0084] The second current comparison unit 24 is used to compare the second MOS transistor current I. M2 The second comparison current is generated by the ratio of the second current; when the external module 4 is in a preset normal state, the low level ISNS_HCALMP=0 is output to the digital logic unit 21; when the external module is in a preset abnormal state and the second comparison current I2 is greater than or equal to the third current source current I_bias3 provided by the third current source I, the second comparison current I2 is generated by the ratio of the second current to the second current. I_bias3 When the external module is in a preset abnormal state and the second comparison current I2 is less than the third current source current I, the output level ISNS_HCALMP = 1 is sent to the digital logic unit 21; when the external module is in a preset abnormal state and the second comparison current I2 is less than the third current source current I, the output level ISNS_HCALMP = 1 is sent to the digital logic unit 21. I_bias3 When the output is low, ISNS_HCALMP = 0 is sent to digital logic unit 21.

[0085] In one embodiment, reference is made to Figure 2 The second current comparison unit 24 also includes a seventh MOS transistor M7; wherein the gate and drain of the seventh MOS transistor M7 are connected to the input terminal of the third current source I_bias3 and the digital logic unit 21; the output terminal of the third current source I_bias3 is grounded.

[0086] The seventh MOSFET M7 is used to output a low level ISNS_HCALMP=0 to the digital logic unit 21 when the external module 4 is in the preset normal state.

[0087] According to the second MOSFET current I M2 The second comparison current I2 is generated by the ratio of the second current; the third current source current I is obtained. I_bias3 And compare it with the second comparison current I2. When the external module 4 is in a preset abnormal state and the second comparison current I2 is greater than or equal to the third current source current I... I_bias3 When the external module is in a preset abnormal state and the second comparison current I2 is less than the third current source current I, the output level ISNS_HCALMP = 1 is sent to the digital logic unit 21; when the external module is in a preset abnormal state and the second comparison current I2 is less than the third current source current I, the output level ISNS_HCALMP = 1 is sent to the digital logic unit 21. I_bias3 When the output is low, ISNS_HCALMP = 0 is sent to digital logic unit 21.

[0088] Here, the second current ratio is a preset current ratio between the seventh MOSFET M7 and the second MOSFET M2, and the second comparison current I2 is the current generated by the seventh MOSFET M7 according to the second current ratio and flowing through the seventh MOSFET M7.

[0089] When the external module is in a preset abnormal state, i.e., R ROSC When the resistance value is too high, the external module is unconnected, or the external module is shorted to the power supply, I2 becomes less than I. I_bias3 When the external module is in a preset abnormal state, the output is low (ISNS_HCALMP = 0); when the external module is in a preset abnormal state, i.e., R... ROSC If the resistance value is too low or the external module is shorted to ground, I2 will be greater than or equal to I. I_bias3 When this occurs, the output level ISNS_HCALMP = 1.

[0090] Enable signal generation unit 25 is used to generate an enable signal when the second MOS transistor current I... M2 Within the preset current range, the output level IC_OK = 1 is high to the digital logic unit 21; when the second MOSFET current I... M2 When the current is outside the preset range, output a low level IC_OK=0 to digital logic unit 21.

[0091] In one embodiment, reference is made to Figure 2 The enable signal generation unit includes an eighth MOS transistor M8 and a first capacitor C1; wherein, the drain of the eighth MOS transistor M8 is connected to one end of the first capacitor C1 and the digital logic unit 21; the other end of the first capacitor C1 is grounded.

[0092] The eighth MOSFET, M8, is used to obtain the current I of the second MOSFET. M2 When the first capacitor C1 is charged, the second MOSFET current I M2Within the preset current range, the output level IC_OK = 1 is high to the digital logic unit 21; when the second MOSFET current I... M2 When the current is outside the preset range, output a low level IC_OK=1 to digital logic unit 21.

[0093] Here, the preset current range is set according to the actual situation.

[0094] Digital logic unit 21 is used to generate a normal control signal ROSC_MON_FAULT = 0 to the watchdog module when it receives a high level output from the first current comparison unit 23 and a low level output from the second current comparison unit 24; when both the first current comparison unit 23 and the second current comparison unit 24 output a high level or a low level, it generates an abnormal control signal ROSC_MON_FAULT = 1 to the watchdog module; when it receives a high level output from the enable signal generation unit 25, it generates a valid enable signal ICurrent_OK = 1 to the oscillator; when it receives a low level output from the enable signal generation unit 25, it generates an invalid enable signal ICurrent_OK = 0 to the oscillator.

[0095] Here, the digital logic unit 21 is a logic chip used to convert the logic control signals generated inside the current comparator into logic signals and output them to the watchdog module 1 and the oscillator 3.

[0096] When the external module is in the preset normal state, the digital logic unit 21 generates ROSC_MON_FAULT=0 to the watchdog module based on the high level ISNS_LCALMP=1 received from the first current comparison unit 23 and the low level ISNS_HCALMP=0 received from the second current comparison unit 24; and generates a valid enable signal ICurrent_OK=1 to the oscillator based on the high level IC_OK=1 received from the enable signal generation unit 25.

[0097] When the external module is in a preset abnormal condition, i.e., R ROSC When the resistance value is too high, the external module is empty, or the external module is shorted to the power supply, the digital logic unit 21 generates ROSC_MON_FAULT=1 to the watchdog module based on the low level ISNS_LCALMP=0 received from the first current comparison unit 23 and the low level ISNS_HCALMP=0 received from the second current comparison unit 24; and generates an invalid enable signal ICurrent_OK=0 to the oscillator based on the low level IC_OK=0 received from the enable signal generation unit 25.

[0098] When the external module is in a preset abnormal condition, i.e., R ROSCWhen the resistance value is too low or the external module is shorted to ground, the digital logic unit 21 generates ROSC_MON_FAULT=1 to the watchdog module based on the high level ISNS_LCALMP=1 received from the first current comparison unit 23 and the high level ISNS_HCALMP=1 received from the second current comparison unit 24; and generates an invalid enable signal ICurrent_OK=0 to the oscillator based on the low level IC_OK=0 received from the enable signal generation unit 25.

[0099] This invention provides a watchdog circuit, including: an external module, and a watchdog module, a current regulator, and an oscillator interconnected with each other; one end of the external module is connected to the current regulator, and the other end of the external module is grounded; the current regulator is used to generate an effective enable signal and a first bias current to the oscillator and generate a normal control signal to the watchdog module when the external module is in a preset normal state; when the external module is in a preset abnormal state, it generates an invalid enable signal and a second bias current to the oscillator and generates an abnormal control signal to the watchdog module; the oscillator is used to generate a normal clock signal to the watchdog module when it receives the effective enable signal and the first bias current; and generate an abnormal clock signal to the watchdog module when it receives the invalid enable signal and the second bias current; the watchdog module is used to output an abnormal warning when it receives the normal control signal and the normal clock signal, with the output duration of the watchdog window related to the external module; and output an abnormal warning when it receives the abnormal control signal and the abnormal clock signal. In this approach, the watchdog time window duration of the watchdog module is controlled by an external module and a current regulator, thereby making the watchdog suitable for more application scenarios and saving circuit costs.

[0100] Example 2:

[0101] Figure 4 This is a flowchart of the control method for the watchdog circuit provided in Embodiment 2 of the present invention.

[0102] Reference Figure 4 The watchdog circuit control method is used to control the aforementioned watchdog circuit, and the method includes:

[0103] Step S101: When the external module is in a preset normal state, an effective enable signal and a first bias current are generated to the oscillator through the current regulator, and a normal control signal is generated to the watchdog module; a normal clock signal is generated to the watchdog module through the oscillator; the output duration of the watchdog window of the watchdog module is related to the external module.

[0104] Step S102: When the external module is in a preset abnormal condition, an invalid enable signal and a second bias current are generated by the current regulator to the oscillator, and an abnormal control signal is generated to the watchdog module; an abnormal clock signal is generated by the oscillator to the watchdog module; and an abnormal alert is output by the watchdog module.

[0105] This invention provides a control method for controlling a watchdog circuit. The watchdog circuit includes: an external module, and a watchdog module, a current regulator, and an oscillator interconnected with each other; one end of the external module is connected to the current regulator, and the other end is grounded; the current regulator generates an effective enable signal and a first bias current to the oscillator and a normal control signal to the watchdog module when the external module is in a preset normal state; when the external module is in a preset abnormal state, it generates an invalid enable signal and a second bias current to the oscillator and an abnormal control signal to the watchdog module; the oscillator generates a normal clock signal to the watchdog module when it receives the effective enable signal and the first bias current; and generates an abnormal clock signal to the watchdog module when it receives the invalid enable signal and the second bias current; the watchdog module outputs a watchdog window with the duration related to the external module when it receives the normal control signal and the normal clock signal; and outputs an abnormal alert when it receives the abnormal control signal and the abnormal clock signal. In this approach, the watchdog time window duration of the watchdog module is controlled by an external module and a current regulator, thereby making the watchdog suitable for more application scenarios and saving circuit costs.

[0106] The computer program product provided in this embodiment of the invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the preceding method embodiments. For specific implementation details, please refer to the method embodiments, which will not be repeated here.

[0107] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system and apparatus described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0108] Furthermore, in the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0109] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0110] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0111] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A watchdog circuit, characterized in that, include: External modules, as well as watchdog modules, current regulators and oscillators that are interconnected; One end of the external module is connected to the current regulator, and the other end of the external module is grounded; The current regulator is used to generate an effective enable signal and a first bias current to the oscillator when the external module is in a preset normal state, and to generate a normal control signal to the watchdog module. When the external module is in a preset abnormal condition, an invalid enable signal and a second bias current are generated to the oscillator, and an abnormal control signal is generated to the watchdog module. The oscillator is used to generate a normal clock signal to the watchdog module when it receives the valid enable signal and the first bias current. When the invalid enable signal and the second bias current are received, an abnormal clock signal is generated to the watchdog module; The watchdog module is configured such that when it receives the normal control signal and the normal clock signal, the output duration of the watchdog window is related to the external module; when it receives the abnormal control signal and the abnormal clock signal, there is still a corresponding watchdog time window duration, but an abnormal alert is output at the same time. The preset normal condition is that the external resistance of the external module is within a preset resistance range; the preset abnormal condition is that the external resistance of the external module is not within the preset resistance range, or includes one or more of the following: the external module is unconnected, the external module is shorted to the power supply, the external module is shorted to ground, and the external module is a resistor and a large-capacity capacitor connected together. The current regulator includes a digital logic unit and a bias current generation unit, a first current comparison unit, a second current comparison unit, and an enable signal generation unit connected in sequence; wherein, the first current comparison unit includes a second current source; and the second current comparison unit includes a third current source. The bias current generation unit includes a second MOS transistor; wherein, the bias current generation unit is connected to the external module and the oscillator respectively; the first current comparison unit, the second current comparison unit, the enable signal generation unit, the oscillator and the watchdog module are respectively connected to the digital logic unit; The bias current generation unit is used to generate a bias current to the oscillator according to the external module, and to mirror the second MOS transistor current to the first current comparison unit, the second current comparison unit and the enable signal generation unit; The first current comparison unit is used to generate a first comparison current based on the ratio of the second MOSFET current to the first current; when the external module is in the preset normal state, it outputs a high level to the digital logic unit; when the external module is in the preset abnormal state and the first comparison current is greater than or equal to the second current source current provided by the second current source, it outputs a high level to the digital logic unit; when the external module is in the preset abnormal state and the first comparison current is less than the second current source current, it outputs a low level to the digital logic unit. The second current comparison unit is used to generate a second comparison current based on the ratio of the second MOSFET current and the second current; when the external module is in the preset normal state, it outputs a low level to the digital logic unit; when the external module is in the preset abnormal state and the second comparison current is greater than or equal to the third current source current provided by the third current source, it outputs a high level to the digital logic unit; when the external module is in the preset abnormal state and the second comparison current is less than the third current source current, it outputs a low level to the digital logic unit. The enable signal generation unit is used to output a high level to the digital logic unit when the current of the second MOS transistor is within a preset current range; and to output a low level to the digital logic unit when the current of the second MOS transistor is not within the preset current range. The digital logic unit is configured to generate a normal control signal to the watchdog module when it receives a high level output from the first current comparison unit and a low level output from the second current comparison unit; generate an abnormal control signal to the watchdog module when both the first current comparison unit and the second current comparison unit output a high level or a low level; generate a valid enable signal to the oscillator when it receives a high level output from the enable signal generation unit; and generate an invalid enable signal to the oscillator when it receives a low level output from the enable signal generation unit. The bias current generation unit includes a current mirror circuit; the current mirror circuit includes a second MOSFET and a third MOSFET; The bias current generation unit further includes a second bias current generation circuit, which is connected to the current mirror circuit; the second bias current generation circuit includes a fourth MOS transistor, a fifth MOS transistor, a first resistor, and a first current source. The source of the fourth MOS transistor is connected to the source of the second MOS transistor; the gate of the fourth MOS transistor is connected to the source of the fifth MOS transistor and the drain of the second MOS transistor; the drain of the fourth MOS transistor and the gate of the fifth MOS transistor are connected to the input terminal of the first current source; wherein, the width-to-length ratio of the second MOS transistor and the width-to-length ratio of the fourth MOS transistor are set according to a second preset ratio. The drain of the fifth MOS transistor is connected to one end of the first resistor; the other end of the first resistor and the output terminal of the first current source are grounded. The second bias current generation circuit is used to form a loop with the second MOS transistor when the external module is in the preset abnormal condition, and generate an abnormal second MOS transistor current according to the first current source; The current mirror circuit is used to generate a second bias current for the second MOS transistor through the third MOS transistor, and send the second bias current to the oscillator.

2. The watchdog circuit according to claim 1, characterized in that, The bias current generation unit includes the current mirror circuit and the first bias current generation circuit connected together; the first bias current generation circuit includes an operational amplifier and a first MOS transistor. The gate of the second MOS transistor is connected to the gate of the third MOS transistor; the source of the second MOS transistor is connected to the source of the third MOS transistor; the drain of the second MOS transistor is connected to the gate of the third MOS transistor and the drain of the first MOS transistor, respectively. The drain of the third MOS transistor is connected to the oscillator; The width-to-length ratio of the second MOS transistor and the width-to-length ratio of the third MOS transistor are set according to a first preset ratio.

3. The watchdog circuit according to claim 2, characterized in that, The first current comparison unit further includes a sixth MOS transistor; wherein the gate and drain of the sixth MOS transistor are connected to the input terminal of the second current source and the digital logic unit; the output terminal of the second current source is grounded; The sixth MOSFET is configured to output a high level to the digital logic unit when the external module is in the preset normal state; generate a first comparison current based on the ratio of the second MOSFET current and the first current; obtain the second current source current and compare it with the first comparison current; output a high level to the digital logic unit when the external module is in the preset abnormal state and the first comparison current is greater than or equal to the second current source current; and output a low level to the digital logic unit when the external module is in the preset abnormal state and the first comparison current is less than the second current source current.

4. The watchdog circuit according to claim 3, characterized in that, The second current comparison unit further includes a seventh MOS transistor; wherein the gate and drain of the seventh MOS transistor are connected to the input terminal of the third current source and the digital logic unit; the output terminal of the third current source is grounded; The seventh MOSFET is configured to output a low level to the digital logic unit when the external module is in the preset normal state; generate a second comparison current based on the ratio of the second MOSFET current and the second current, obtain the third current source current and compare it with the second comparison current; output a high level to the digital logic unit when the external module is in the preset abnormal state and the second comparison current is greater than or equal to the third current source current; and output a low level to the digital logic unit when the external module is in the preset abnormal state and the second comparison current is less than the third current source current.

5. The watchdog circuit according to claim 4, characterized in that, The enable signal generation unit includes an eighth MOS transistor and a first capacitor; wherein, the drain of the eighth MOS transistor is connected to one end of the first capacitor and the digital logic unit; the other end of the first capacitor is grounded; The eighth MOSFET is used to obtain the current of the second MOSFET to charge the first capacitor. When the current of the second MOSFET is within a preset current range, it outputs a high level to the digital logic unit; when the current of the second MOSFET is not within the preset current range, it outputs a low level to the digital logic unit.

6. A control method for a watchdog circuit, characterized in that, The method for controlling the watchdog circuit according to any one of claims 1-5, the method comprising: When the external module is in a preset normal state, an effective enable signal and a first bias current are generated to the oscillator through the current regulator, and a normal control signal is generated to the watchdog module; a normal clock signal is generated to the watchdog module through the oscillator; the output duration of the watchdog window of the watchdog module is related to the external module. When the external module is in a preset abnormal condition, an invalid enable signal and a second bias current are generated to the oscillator through the current regulator, and an abnormal control signal is generated to the watchdog module; an abnormal clock signal is generated to the watchdog module through the oscillator; and an abnormal alert is output through the watchdog module. When the external module is in a preset normal state, the first bias current generation circuit and the second MOS transistor form a loop to generate a normal second MOS transistor current related to the external module; the current mirror circuit generates the first bias current of the second MOS transistor through the third MOS transistor and sends the first bias current to the oscillator.

Images