Chip package strip, chip set and chip packaging method

Abstract

This disclosure provides a chip packaging strip, a chipset, and a chip packaging method, belonging to the field of semiconductor technology. The chip packaging strip includes a packaging strip structure disposed around at least one first chip stack; wherein the packaging strip structure includes multiple stacked metal rings, at least some of which are discontinuous metal rings composed of multiple broken arc segments, and at least one broken arc segment is respectively connected to at least one interface unit of the first chip and at least one second chip in the chipset other than the first chip, thereby establishing a logical connection between the interface unit and the second chip. Embodiments of this disclosure can reduce chip footprint, lower packaging costs, and improve packaging reliability.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a chip packaging strip, chipset, and chip packaging method. Background Technology

[0002] A seal ring (also known as a sealing ring, protective ring, etc.) is a protective ring located between the core area of ​​a chip and the scribe line. Summary of the Invention

[0003] This disclosure provides a chip packaging strip, a chipset, and a chip packaging method.

[0004] In a first aspect, this disclosure provides a chip packaging strip applied to a chipset composed of multiple stacked chips. The chip packaging strip includes a packaging strip structure disposed around at least one first chip stack. The packaging strip structure includes multiple stacked metal rings, at least some of which are discontinuous metal rings composed of multiple broken arc segments. At least one of the broken arc segments is connected to at least one interface unit of the first chip and at least one second chip in the chipset other than the first chip, thereby establishing a logical connection between the interface unit and the second chip.

[0005] In a second aspect, this disclosure provides a chipset comprising: a substrate; a plurality of chips stacked on the substrate; and a chip packaging strip disposed around at least one of the chips; wherein the chip packaging strip is a chip packaging strip as described in any one of the embodiments of this disclosure.

[0006] Thirdly, this disclosure provides a chip packaging method, which includes: providing a substrate and a plurality of chips to be packaged; selecting at least one target chip from the plurality of chips to be packaged, and setting a chip packaging strip as described in any one of the embodiments of this disclosure around the target chip; stacking the target chip and the remaining plurality of chips to be packaged on the substrate to obtain a packaged chip assembly.

[0007] The embodiments provided in this disclosure reuse the area occupied by the chip package strip when at least one chip in a chipset is provided with the chip package strip. Based on the chip package strip in the breakpoint manner, the logical connection between the interface unit in the chip and at least one other chip in the chipset is realized without having to occupy additional area outside the chip, thereby improving the chip area utilization rate. At the same time, the chip package strip can replace through-silicon vias to realize the logical connection between chips in the chipset, thereby shortening the hole depth. On the one hand, it reduces the packaging process cost, and on the other hand, it improves the packaging reliability.

[0008] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0009] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 A schematic diagram of a flip-chip packaging structure provided for related technologies;

[0011] Figure 2 A schematic diagram illustrating the working process of wafer-level packaging for related technologies;

[0012] Figure 3 A schematic diagram of a 2.5D-based chip packaging structure provided for related technologies;

[0013] Figure 4 A schematic diagram of a 3D-based chip packaging structure provided for related technologies;

[0014] Figure 5 A schematic diagram of a chip packaging strip provided in an embodiment of this disclosure;

[0015] Figure 6 A schematic diagram of a chipset provided in an embodiment of this disclosure;

[0016] Figure 7 A schematic diagram of a chip packaging strip provided in an embodiment of this disclosure;

[0017] Figure 8 A schematic diagram of a chip packaging strip provided in an embodiment of this disclosure;

[0018] Figure 9 A schematic diagram of a chip packaging strip provided in an embodiment of this disclosure;

[0019] Figure 10 A schematic diagram of a chip packaging strip provided in an embodiment of this disclosure;

[0020] Figure 11 A schematic diagram of a chip packaging strip provided in an embodiment of this disclosure;

[0021] Figure 12 This is a schematic diagram of a chip packaging strip provided in an embodiment of this disclosure.

[0022] Figure 13 A schematic diagram of a chipset provided in an embodiment of this disclosure;

[0023] Figure 14 A flowchart of a chip packaging method provided in this disclosure embodiment;

[0024] Figure 15 A block diagram of an electronic device provided in an embodiment of this disclosure;

[0025] Figure 16 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0026] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0027] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0028] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0030] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0031] As chip manufacturing processes become increasingly sophisticated, the physical dimensions of chips have reached near limits, but the demands on chip performance have not decreased. In response, chip packaging technologies have evolved, giving rise to flip chip, wafer-level packaging (WLP), two-dimensional (2D) packaging, 2.5D packaging, and three-dimensional (3D) packaging. 2.5D packaging includes methods based on interposers and redistribution layers (RDLs), while 3D packaging includes methods based on through-silicon vias (TSVs).

[0032] Figure 1 A schematic diagram of a flip-chip packaging structure provided for related technologies. (Refer to...) Figure 1 The package structure includes a stud chip 101, solder bumps 102, a substrate 103, an underfill 104, a structural adhesive 105, thermal paste 106, and an integrated cavity cover 107.

[0033] like Figure 1 As shown, unlike traditional packaging methods (where the active area of ​​the chip is typically facing upwards, away from the substrate, and then bonded), the active area of ​​the flip chip 101 faces the substrate 103, and the interconnection between the flip chip 101 and the substrate 103 is achieved through an array of solder bumps 102. The solder bumps, which enable electrical interconnection between the chip and the substrate, typically have a small spherical structure and are fabricated from conductive materials using a bumping process.

[0034] Figure 2 This is a schematic diagram illustrating the working process of wafer-level packaging for related technologies. (Refer to...) Figure 2 For a complete wafer, circuit connections are first established using the bumping process, and then the dies in the wafer are diced to obtain multiple chips. The wafer surface is usually coated with a protective layer.

[0035] Figure 3 A schematic diagram of a 2.5D-based chip packaging structure is provided for related technologies. (Refer to...) Figure 3 The chip packaging structure mainly includes a logic unit 310, a high bandwidth memory (HBM) unit 320, an interposer 330, and a substrate 340. The HBM unit 320 is composed of multiple chips 321 stacked together, and the interposer is essentially a conductive layer located between the solder balls and the die.

[0036] like Figure 3 As shown, the interposer layer 330 is located between the substrate 340 and the functional unit. Connecting through the interposer layer 330 can effectively expand the connection surface. Specifically, the logic unit 310 is connected to the substrate 340 through the interposer layer 330, the HBM unit 320 is connected to the substrate 340 through the interposer layer 330, and the logic unit 310 and the HBM unit 320 are also connected through the interposer layer 330.

[0037] It should be noted that in some optional implementations, an RDL layer can also be used to implement 2.5D packaging. The RDL layer allows the input and output connections between chips to be rerouted on the RDL layer, thereby enabling more direct and denser connections.

[0038] Figure 4 A schematic diagram of a 3D-based chip packaging structure is provided for related technologies. (Refer to...) Figure 4 The chip packaging structure mainly includes a substrate 401, a first functional layer 402 located on the back of the substrate, and a second functional layer 403 located on the front of the substrate. The first functional layer 402 contains a first metal structure 404 based on an RDL (Representational Depth Array), and the second functional layer 403 contains a second metal structure 405 based on an RDL. A through-silicon via (TSV) 406 is provided between the first and second metal structures to connect the first metal structure 404 and the second metal structure 405, thereby achieving a vertical connection between the chips.

[0039] In summary, from the perspectives of integration and performance, 3D packaging is superior to 2.5D packaging, and 2.5D packaging is superior to wafer-level packaging. However, 3D packaging typically requires TSVs (Through-Shipment Vias) to penetrate the chip, necessitating vias in non-functional areas. This usually occupies scribe lines or additional areas (e.g., during chip design, scribe lines need to be reserved inside the chip for pad-out). Furthermore, scribe lines incur area loss during slicing. Therefore, both occupying scribe lines and additional areas reduce the usable chip area. Consequently, given limited chip area, meeting these requirements reduces the area available for circuit modules, decreasing chip utilization and potentially impacting chip performance and reliability.

[0040] Furthermore, if copper (Cu) needs to be electroplated inside the via after the TSV passes through the chip, the copper growth process is from bottom to top, and the growth promoter and inhibitor required are consumed unevenly (usually the inhibitor is consumed first at the bottom, so the promoter plays a major role at the bottom). Moreover, because the organic inhibitor has a high concentration of Cl (chlorine), N (nitrogen), and O (oxygen) impurities distributed in large quantities on the grain boundaries, a pinning effect occurs, which inhibits the free growth of the grains. This results in smaller copper grains at the top, eventually forming internal stress inside the via, which may cause defects such as cracks and bulging. This leads to problems such as reduced chip reliability and increased chip packaging process costs.

[0041] A package strip is a protective ring situated between the chip's circuitry functional area and the dicing groove. It typically consists of a diff layer, contact vias, through-holes, and metal layers stacked according to specific rules. Its primary function is to prevent mechanical damage to the chip during dicing. Additionally, the package strip prevents moisture and free ions from entering the chip through the side cut and affecting its functionality. Furthermore, by grounding the package strip, it can shield against external interference. Thus, the package strip acts like a Great Wall around the chip, mitigating the impact of dicing on the internal circuitry and preventing external moisture and dust from entering the chip.

[0042] In this embodiment, when at least one chip in a stacked array of chips has a chip packaging strip, the area occupied by the chip packaging strip is reused. Based on the breakpoint chip packaging strip, a vertical logical connection between the current chip and at least one other chip in the chip group is achieved without having to occupy additional area outside the chip, thereby improving the chip area utilization rate. At the same time, the chip packaging strip can shorten the hole depth, reduce the packaging process cost, and improve the packaging reliability. In addition, the chip packaging strip also takes into account the protective function of the packaging strip structure for the chip.

[0043] The first aspect of this disclosure provides a chip packaging strip.

[0044] Figure 5 This is a schematic diagram of a chip packaging strip provided in an embodiment of the present disclosure. This chip packaging strip can be applied to a chipset composed of multiple stacked chips. (Refer to...) Figure 5The chip packaging strip includes a packaging strip structure 110 stacked around at least one first chip 100; wherein the packaging strip structure 110 includes a plurality of stacked metal rings 1110, at least some of the metal rings 1110 are discontinuous metal rings composed of a plurality of broken arc segments 11110, and at least one broken arc segment 11110 is respectively connected to at least one interface unit of the first chip 100 and at least one second chip (e.g., chip 200 and / or chip 300) in the chipset other than the first chip 100, so that a logical connection is established between the interface unit and the second chip.

[0045] Figure 6 This is a schematic diagram of a chipset provided in an embodiment of this disclosure. (Refer to...) Figure 6 The chipset 10 is formed by stacking n chips, namely chips 11, 12, ..., 1n (n is an integer greater than or equal to 2). Moreover, at least one metal connection structure (e.g., a through hole made of conductive metal material) 20 is provided between two adjacent chips to establish a connection between adjacent chips based on the metal connection structure 20.

[0046] In some alternative implementations, the connection between the current chip and the adjacent chip can be established by making metal slots on the front and / or back of the wafer corresponding to the chip, and using a conductive material to connect the metal slots of the current chip with the metal slots of the adjacent chip.

[0047] Depend on Figure 6 As can be seen, since multiple chips are stacked and each chip is on a different horizontal plane, in related technologies, to establish a logical connection between adjacent chips, it is necessary to use methods such as silicon vias to create a through-line in the vertical direction, and then establish a vertical logical connection between the chips based on the through-line.

[0048] In this embodiment of the disclosure, when multiple chips are stacked to form a chip group, in order to realize the vertical logical connection between the chips, at least one chip (i.e., the first chip) can be selected, and a package strip structure with breakpoints can be set around the chip to reuse the package strip structure to establish the aforementioned vertical logical connection. This eliminates the need to occupy additional area outside the chip to set through silicon vias, thereby improving the chip area utilization rate.

[0049] For example, targeting Figure 6 The chipset shown can arbitrarily select one or more chips from chips 11 to chips 1n, set a packaging strip structure around the selected chip, and establish a vertical logical connection between the current chip and other chips based on the packaging strip structure, so that the chip no longer needs to be processed by through silicon via.

[0050] In some alternative implementations, the encapsulation strip structure is composed of multiple stacked metal rings, and at least some of the metal rings are broken off, forming a discontinuous metal ring composed of multiple broken arc segments. Corresponding to... Figure 5 In the middle, the metal ring 1110 has multiple breaks, and these breaks cut it into multiple broken arc segments, which are spliced ​​together to form the metal ring 1110. Moreover, behind the packaging strip structure 110, the circuit module of the chip is provided, and the circuit module includes a variety of functional units.

[0051] In some alternative implementations, vias are provided between some adjacent metal rings, through which connections can be established between adjacent metal rings. For example, a partial break in the arc segment can be connected to a corresponding break in an adjacent metal ring through a via.

[0052] Furthermore, due to Figure 5 This view shows the chip package strip from the front, thus clearly illustrating the stacked structure of the chipset and the chip package strip. However, it cannot clearly show the distribution of the broken arc segments of the metal rings within the package strip structure, nor the circuit modules within the package strip structure. Therefore, in Figure 7 The chip package strip of this disclosure is shown in a top view for further explanation.

[0053] Figure 7 This is a schematic diagram of a chip packaging strip provided in an embodiment of this disclosure. (Refer to...) Figure 7 It shows a top view of the chip package strip 110.

[0054] like Figure 7 As shown, the chip 100 includes a central region 120 and a packaging strip structure 110 disposed along the periphery of the chip. The central region 120 contains at least one circuit module, which includes various functional units. The packaging strip structure is formed by stacking multiple metal rings 1110, with a strip-shaped through-hole 1120 disposed between at least two metal rings 1110. At least one metal ring 1110 has multiple breaks 130, dividing the metal ring 1110 into multiple broken arc segments 11110. Correspondingly, at the positions corresponding to the breaks 130, the through-holes 1120 are also broken, forming multiple strip-shaped through-holes. Figure 7 As can be seen, in the embodiments of this disclosure, the metal ring of the encapsulation strip structure includes multiple breaks, thereby making the encapsulation strip structure a type of encapsulation strip structure with breaks.

[0055] In some optional implementations, at least one disconnected arc segment is connected to at least one interface unit of the first chip and at least one second chip in the chipset other than the first chip, thereby establishing a logical connection between the interface unit and the second chip. Here, the first chip refers to the chip containing the package strip structure, and the second chip refers to at least one chip in the chipset other than the first chip.

[0056] In some alternative implementations, the second chip includes: an upper chip adjacent to the first chip, and / or a lower chip adjacent to the first chip; wherein, when the second chip includes the upper chip, the topmost metal ring of the packaging strip structure of the first chip is connected to the bottommost metal connection layer of the upper chip, and when the second chip includes the lower chip, the bottommost metal ring of the packaging strip structure of the first chip is connected to the topmost metal connection layer of the lower chip.

[0057] by Figure 5 For example, when any disconnected arc segment 11110 in the encapsulation strip structure 110 is connected to the interface unit in the chip 100, and the disconnected arc segment 11110 is also connected to the chip 200, it is equivalent to establishing a logical connection between the interface unit of the chip 100 and the chip 200 through the disconnected arc segment 11110, thereby enabling the chip 100 to transmit various types of data and various types of signals with the chip 200.

[0058] In other words, by disconnecting the arc segment, which serves as a bridge connecting the interface unit of the first chip and the second chip, a logical connection is established between the two chips. Furthermore, this logical connection enables the transmission of data, electrical signals, frequency signals, and other information between the first and second chips.

[0059] It should be noted that some metal rings in the package strip structure are discontinuous and broken, with at least some broken arc segments connecting to the corresponding interface units and the second chip. This design makes the package strip structure a breakpoint structure, including multiple relatively independent data transmission functional modules (each breakpoint corresponds to one data transmission functional module). If a section of the package strip structure or its corresponding interface unit fails, it will not affect other parts of the package strip structure and interface units. In this case, data transmission can still be carried out through the undamaged part of the package strip structure and its connected interface units. In summary, the package strip structure based on the breakpoint structure can not only establish vertical logical connections between chips while saving chip area, but also improve the fault tolerance of logical connections, thereby improving the stability and reliability of data transmission.

[0060] In some optional implementations, the interface unit includes an input / output (I / O) interface. The input / output interface can be a pad, a metal strip, a metal block, etc., and this disclosure does not impose any limitations on this.

[0061] In some optional implementations, the location and number of disconnections of the metal ring are determined based on the distribution and / or attribute information of the interface units in the first chip. The distribution of interface units includes at least one of the following: the number of interface units and their location; the attribute information includes at least one of the following: interface function and performance parameters. Determining the location and number of disconnections of the metal ring based on the distribution and / or attribute information of the interface units can minimize the complexity of wiring and routing operations required to establish the logical connection while meeting the logical connection requirements.

[0062] In some alternative implementations, the interface unit connected to the disconnected arc segment is selected from multiple interface units based on the distance between the disconnected arc segment and each interface unit in the first chip. For example, the distance between each interface unit in the first chip and the disconnected arc segment is determined, and the interface unit with the closest distance is selected and connected to the disconnected arc segment.

[0063] It should be noted that since distance and impedance are usually positively correlated, when the interface unit closest to the disconnected arc is connected, the impedance is relatively small, the data or signal transmission speed is faster, and the data processing efficiency is correspondingly higher.

[0064] In some alternative implementations, the interface unit connected to the disconnected arc segment can be selected according to the chip's wiring layout to minimize wiring difficulty and mitigate signal interference.

[0065] It should be noted that the above methods for establishing a connection between the disconnected arc segment and the interface unit are merely illustrative examples, and the embodiments disclosed herein do not impose any limitations on them.

[0066] Figure 8 This is a schematic diagram of a chip packaging strip provided in an embodiment of the present disclosure, showing the connection between the packaging strip structure and the interface unit from a cross-sectional perspective. (Refer to...) Figure 8 The chip 100 is provided with interface unit 1131 and interface unit 1132. Interface unit 1131 is connected to the disconnected arc segment 11111 in the packaging strip structure 110, and interface unit 1132 is connected to the disconnected arc segment 11112 in the packaging strip structure 110.

[0067] like Figure 8As shown, there is a connection between the disconnect segment 11111 and the chip 300. Therefore, it is equivalent to establishing a logical connection between the chip 100 and the chip 300 through the disconnect segment 11111. For example, when the interface unit 1131 is an output interface, the chip 100 can further transmit the first data transmitted from the chip 300 through the disconnect segment 11111 through this output interface, or perform some calculations on the first data to obtain a first calculation result and transmit the first calculation result through the output interface. When the interface unit 1131 is an input interface, the chip 100 can directly transmit the second data received based on the input interface to the chip 300 through the disconnect segment 11111, or perform some calculations on the second data and transmit the obtained second calculation result to the chip 300 through the disconnect segment 11111.

[0068] Similarly, since there is a connection between the disconnected arc segment 11112 and chip 200, it is equivalent to establishing a logical connection between chip 100 and chip 200 through the disconnected arc segment 11112. The data transfer process between chip 100 and chip 200 is similar to that between chip 100 and chip 300, and will not be described in detail here.

[0069] Figure 9 This is a schematic diagram of a chip packaging strip provided in an embodiment of this disclosure. (Refer to...) Figure 9 Multiple interface units 140 are provided on the outer side of the central region 120 of the chip 100 and on the inner side of the packaging strip structure 110.

[0070] like Figure 9 As shown, each interface unit is connected to a nearby disconnected arc segment, forming a relatively independent data transmission module ("independent" here because two adjacent disconnected arc segments in the same metal ring are not connected). Based on this discontinuous encapsulation strip structure, even if a segment of the encapsulation strip structure or an interface unit fails, data transmission can still be achieved using other segments of the encapsulation strip structure and their corresponding interface units due to their relative independence. This improves the stability of data transmission and its fault tolerance.

[0071] It should be noted that since the chip package strip may include multiple metal layers in its layered structure, and the chip itself may also have a multi-layered structure, there may be signal line interference issues when reusing the chip package strip as a connecting line for 3D packaging.

[0072] To mitigate or resolve signal line interference and ensure chip stability, some optional implementations may involve grounding a portion of the metal layers in the package structure, and / or decoupling some adjacent metal layers (i.e., placing them in a non-conductive state). Specifically, grounding the disconnected segments can provide some signal shielding, thus mitigating interference between signal lines; placing adjacent disconnected segments in a non-conductive state increases the distance between signal lines, similarly reducing interference.

[0073] In some alternative implementations, multiple adjacent metal rings have the same break position and break data, allowing multiple encapsulation strip structures to be formed based on each break arc segment and its corresponding break arc segment in the adjacent metal ring. In other words, among multiple metal rings with the same break position and number of breaks, each break arc segment and its corresponding break arc segment in the adjacent metal ring constitutes multiple encapsulation strip structures. Corresponding to... Figure 8 In the middle, the three stacked broken arc segments on the left form a packaging strip structure, and the three stacked broken arc segments on the right form a second packaging strip structure.

[0074] In some alternative implementations, at least one broken segment of at least one encapsulation strip structure is grounded, and / or at least two adjacent broken segments of at least one encapsulation strip structure are set to a non-conductive state, wherein the non-conductive state can be achieved by not providing vias or by setting the vias to an invalid connection state.

[0075] For example, when the upper and lower logic of the encapsulated strip structure is connected, multiple disconnected arc segments can be selected at intervals from the encapsulated strip structure for grounding; wherein, the upper and lower logic connection can be achieved by setting through holes between adjacent disconnected arc segments.

[0076] Figure 10 This is a schematic diagram of a chip package strip provided in an embodiment of the present disclosure, showing a grounded disconnected arc segment in the package strip substructure with upper and lower logic conductions. Wherein, Figure 10 (a) shows the case where grounding is performed on the same broken arc segment at the same location for each packaged strip structure. Figure 10 (b) shows the grounding treatment of different disconnected arc segments for each package strip structure.

[0077] like Figure 10As shown in (a), the encapsulation strip structure 110 includes multiple encapsulation strip substructures 111 / 112 / ... / 11k (k>1). In each encapsulation strip structure, multiple disconnected arc segments are selected with an interval of 1 layer and connected to a grounding unit (GND) 1140, so that these grounded disconnected arc segments can shield the signal line from interference. Among them, the grounded disconnected arc segments in each encapsulation strip structure have the same relative position (for example, the disconnected arc segments of the 2nd layer and the 4th layer are selected for grounding).

[0078] like Figure 10 As shown in (b), the encapsulation strip structure 110 includes multiple encapsulation strip substructures 111 / 112 / ... / 11k (k>1). For each encapsulation strip substructure, multiple disconnected arc segments are selected with an interval of 1 layer and connected to the grounding unit 1140, so that these grounded disconnected arc segments can shield the interference of the signal line. The number and relative positions of the grounded disconnected arc segments can differ in different encapsulation strip structures. For example, in encapsulation strip structures 111 and 112, disconnected arc segments from the 2nd and 4th layers are selected for grounding; in encapsulation strip structure 11k, disconnected arc segments from the 1st and 3rd layers are selected for grounding.

[0079] In some alternative implementations, the grounding unit 1140 may be a functional unit located inside the chip 100 or a peripheral functional unit. For a single chip, multiple grounding units may be provided, and this disclosure does not limit this.

[0080] It should be noted that the above examples of grounding disconnection arcs are merely illustrative. In other implementations, other intervals can be used to select grounding disconnection arcs, uneven intervals can be used to ground the disconnection arcs, or grounding can be performed only on a portion of the encapsulation strip structure. This disclosure does not limit these methods.

[0081] In some optional implementations, when the upper and lower logic of the encapsulation strip structure is connected, multiple encapsulation strip structures can be selected at intervals for grounding. The grounded encapsulation strip structure can then shield the encapsulation strip structures on the adjacent sides.

[0082] by Figure 10 Let's take an example to illustrate. Figure 10In the process, the encapsulation strip structure 110 includes encapsulation strip substructures 111 / 112 / ... / 11k with top and bottom logic interconnection. Multiple encapsulation strip substructures can be selected at intervals from the above k encapsulation strip substructures for grounding. For example, encapsulation strip structures 111, 113, 115, etc., can be selected evenly for grounding at intervals of 1 (i.e., one encapsulation strip structure); or encapsulation strip structures 111, 115, 117, etc., can be selected randomly at intervals for grounding.

[0083] It should be noted that the size of the interval (i.e., the number of encapsulation strip structures between adjacent grounded encapsulation strip structures) can be set according to the distribution of signal lines, the degree of interference between signal lines, and empirical and statistical data, etc., and this disclosure does not limit it.

[0084] In some alternative implementations, multiple disconnected arc segments can be selected at intervals from the encapsulation strip structure, and the selected disconnected arc segment can be set to a non-conductive state with at least one adjacent disconnected arc segment.

[0085] For example, when designing or manufacturing the packaging strip structure, through holes may not be provided between some of the metal rings, so that these metal rings are not connected vertically, thereby increasing the distance between the signal lines and alleviating or solving the interference problem between the signal lines.

[0086] For example, the aforementioned non-conductive state can also be achieved by changing the size, position, etc. of the metal ring and / or the through hole so that the metal ring and the through hole cannot be effectively connected.

[0087] Figure 11 This is a schematic diagram of a chip packaging strip provided in an embodiment of this disclosure. Wherein, Figure 11 (a) shows a case where no through holes are provided between some of the metal rings. Figure 11 (b) shows a case where a portion of the metal ring achieves a non-conductive state by changing its size.

[0088] like Figure 11 As shown in (a), the encapsulation strip structure 110 includes multiple encapsulation strip substructures 111 / 112 / ... / 11k. Furthermore, in each encapsulation strip substructure, no through-hole is provided between the second and third layer break segments, nor between the fourth and fifth layer break segments. This arrangement increases the distance between signal lines, thereby reducing the interference level of the signal lines.

[0089] like Figure 11As shown in (b), the package strip structure 110 includes multiple package strip substructures 111 / 112 / … / 11k. For each package strip substructure, the metal portion corresponding to the via in the second layer's disconnected arc segment is removed, and the metal portion corresponding to the via in the fourth layer's disconnected arc segment is also removed. This prevents the second layer's disconnected arc segment from conducting with the disconnected arc segments in the first and third layers, and also prevents the third layer's disconnected arc segment from conducting with the disconnected arc segments in the second and fourth layers. Based on this method, the distance between signal lines can also be increased, thereby reducing signal line interference.

[0090] It should be noted that the above implementation of the disconnected state is only an example, and the embodiments disclosed herein are not limited thereto.

[0091] In some alternative implementations, multiple disconnected arc segments can be selected at intervals from the encapsulation strip structure for grounding, or one or more of the remaining disconnected arc segments can be selected and set to a non-conductive state with the adjacent disconnected arc segments.

[0092] It should be noted that in different encapsulation strip structures, the number and position of the grounded and / or non-conductive disconnected arc segments can be the same or different, and the embodiments disclosed herein do not impose any restrictions on this.

[0093] In some alternative implementations, a silicon (Si) layer may exist between the first chip and the second chip in the chipset. In this case, the silicon layer needs to be broken through to establish the connection between the first chip and the second chip.

[0094] In some alternative implementations, where at least one silicon layer exists between the first chip and the second chip, at least one blind via is provided in the silicon layer; wherein the blind via connects the packaging strip structure of the first chip and the second chip respectively.

[0095] In this embodiment, a blind via is a via that connects the surface layer and the inner layer without penetrating the entire board. In this disclosure, the packaging strip structure of the first chip is exposed through this blind via, and then connected to the second chip. Figure 8 For example, one end of the blind hole is connected to the broken arc segment 11112 in the packaging strip structure, and the other end is connected to the chip 200. Since the broken arc segment 11112 is connected to the interface unit 1132, a connection is also established between the chip 200 and the interface unit 1132.

[0096] Since blind vias are typically located on the top or bottom surface of a printed circuit board and are used to connect surface circuits to underlying inner circuits, although they have a certain depth, this depth usually does not exceed a certain ratio (the ratio is determined based on the aperture). Therefore, compared to TSVs, the depth of blind vias can be effectively reduced, thereby reducing chip packaging costs and improving chip stability.

[0097] In some alternative implementations, the process of fabricating blind vias includes: First, after the logic units are fabricated, the wafer is flipped and thinned on the back side (at this point, the first chip has not yet been cut); second, holes are made in the thinned wafer and metal is poured in to expose the packaging strip structure; a protective layer is applied to the wafer to protect the chip from damage caused by oxidation or other reactions; then, the first chip to be packaged is blind-holed in the protective layer using through-hole technology until the metal is visible; finally, metal is poured in at the location where the protective layer is opened, and the first chip is stacked and connected to other chips (at least including the second chip) according to input / output relationships.

[0098] Figure 12 This is a schematic diagram of a chip packaging strip provided in an embodiment of this disclosure. (Refer to...) Figure 12 Chips 100 and 300 are stacked. Chip 100 is surrounded by a package strip structure 110 (both chip package strips 110 and 300, as seen in cross-sectional view, consist of two parts, 110a and 110b), a circuit module 150, and a silicon layer 160. Chip 300 is surrounded by a package strip structure 310 (both chip package strips 310 and 310b, as seen in cross-sectional view, consist of two parts, 310a and 310b), a circuit module 350, and a silicon layer 360.

[0099] like Figure 12 As shown, the silicon layer 160 is thinned on the back and made with openings to expose the packaging strip structure 110. Metal is then injected and connected to the packaging strip structure of the chip 300 to generate blind vias 170.

[0100] according to Figure 12 As can be seen, in this embodiment of the present disclosure, chip packaging strips and blind vias replace the TSV through-holes in 3D packaging, thereby realizing the vertical logic connection between chips.

[0101] In summary, in the embodiments of this disclosure, the chip area occupied by the chip packaging strip is reused to establish vertical logical connections between chips, thereby improving the chip area utilization rate. Moreover, when establishing vertical logical connections with the chip packaging strip, the hole depth is effectively reduced compared to through-silicon vias, thereby reducing the cost of chip packaging and improving the reliability of packaging. In addition, the use of a breakpoint-type chip packaging strip can improve the fault tolerance of the logical connection, thereby improving the stability of data transmission.

[0102] The following section, in conjunction with Table 1, compares the 3D packaging methods in related technologies with the packaging methods of the embodiments of this disclosure from multiple comparative dimensions.

[0103] Table 1 Comparison of 3D packaging method and packaging method of embodiments of this disclosure

[0104]

[0105]

[0106] A second aspect of this disclosure provides a chipset.

[0107] Figure 13 This is a schematic diagram of a chipset provided in an embodiment of this disclosure. (Refer to...) Figure 13 The chipset includes: a substrate 1310; a plurality of chips 1320 (including 1321 / 1322 / 1323 / ... / 132i) stacked on the substrate; and a chip package strip 1330 disposed around at least one chip (since the chipset is shown in a cross-sectional view, the chip package strip disposed around the chip appears on both the left and right sides of the chip, but both are essentially a single chip package strip).

[0108] Where i is an integer greater than 1, and the chip packaging strip adopts any of the chip packaging strips described in the embodiments of this disclosure.

[0109] like Figure 13 As shown, a chip packaging strip is disposed around the periphery of chips 1322 and 1323 respectively. This packaging strip structure includes multiple stacked metal rings, and at least some of the metal rings are discontinuous metal rings composed of multiple broken arc segments. For chip 1322, at least one broken arc segment of the chip packaging strip 1330 is connected to at least one interface unit of chip 1322 and chip 1323 respectively, enabling data transmission between the interface unit and chip 1323. When a silicon layer exists between chips 1322 and 1323, the above-mentioned logical connection can be established by drilling blind vias in the silicon layer. For the method of fabricating blind vias, please refer to the relevant content of the embodiments of this disclosure, which will not be repeated here.

[0110] In this embodiment, a chip packaging strip is provided for at least one chip in the chipset, thereby reusing the area occupied by the chip packaging strip. Based on the chip packaging strip in the breakpoint manner, the logical connection between the interface unit in the chip and at least one other chip in the chipset is realized without having to occupy additional area outside the chip, thereby improving the chip area utilization rate. At the same time, the chip packaging strip can replace through-silicon vias to realize the logical connection between chips in the chipset, thereby shortening the hole depth. On the one hand, it reduces the packaging process cost, and on the other hand, it improves the packaging reliability.

[0111] The third aspect of this disclosure provides a chip packaging method.

[0112] Figure 14 A flowchart illustrating a chip packaging method provided in this disclosure. (Refer to...) Figure 14 The chip packaging method includes:

[0113] Step S141: Provide a substrate and multiple chips to be packaged.

[0114] Among the plurality of chips to be packaged, at least one target chip is included, and the target chip is surrounded by a chip packaging strip as described in any one of the embodiments of this disclosure.

[0115] Step S142: Stack the target chip and the remaining multiple chips to be packaged on the substrate to obtain the packaged chipset.

[0116] In this embodiment of the disclosure, a chip packaging strip is provided for at least one chip in the chipset, and the logical connection between the interface unit in the chip and at least one other chip in the chipset is realized based on the chip packaging strip, without having to occupy additional area outside the chip, thereby improving the area utilization of the chip; at the same time, the chip packaging strip can replace through silicon vias to realize the logical connection between chips in the chipset, thereby shortening the hole depth, which reduces the packaging process cost on the one hand, and improves the packaging reliability on the other hand.

[0117] It should be noted that the chipset obtained by packaging according to the embodiments of this disclosure can be used to further manufacture electronic devices such as terminal devices and servers. The terminal device can be a user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc.; the server can be an independent physical server, a server cluster consisting of multiple servers, or a cloud server capable of cloud computing.

[0118] It is understood that the various embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step and the setting of functional modules should be determined by their functions and possible internal logic.

[0119] In addition, this disclosure also provides electronic devices and computer-readable storage media.

[0120] Figure 15 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0121] Reference Figure 15 This disclosure provides an electronic device, which includes: at least one processor 1501; at least one memory 1502; and one or more I / O interfaces 1503 connected between the processor 1501 and the memory 1502; wherein the memory 1502 stores one or more computer programs that can be executed by the at least one processor 1501, and the one or more computer programs are executed by the at least one processor 1501 to enable the at least one processor 1501 to perform various pending tasks.

[0122] Figure 16 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0123] Reference Figure 16 This disclosure provides an electronic device that includes multiple processing cores 1601 and an on-chip network 1602. The multiple processing cores 1601 are all connected to the on-chip network 1602, and the on-chip network 1602 is used to exchange data between the multiple processing cores and external data.

[0124] One or more processing cores 1601 store one or more instructions, and the one or more instructions are executed by one or more processing cores 1601 to enable one or more processing cores 1601 to perform various tasks to be processed.

[0125] In some embodiments, the electronic device may be a neuromorphic chip. Since neuromorphic chips can employ vectorized computation and require external memory, such as Double Data Rate (DDR) synchronous dynamic random access memory, to load parameters such as weights of the neural network model, the batch processing method used in this embodiment offers higher computational efficiency.

[0126] This disclosure also provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor / processing core, performs various tasks to be processed. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0127] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs various tasks to be processed.

[0128] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0129] As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable program instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable program instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0130] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0131] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0132] The computer program product described herein can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0133] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0134] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0135] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0136] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0137] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A chip package strip, characterized by Applied to a chipset consisting of multiple stacked chips, including: a package strip structure disposed around at least one first chip stack; The encapsulation strip structure includes multiple stacked metal rings, at least some of which are discontinuous metal rings composed of multiple broken arc segments. At least one of the broken arc segments is connected to at least one interface unit of the first chip and at least one second chip in the chipset other than the first chip, thereby establishing a logical connection between the interface unit and the second chip.

2. The chip package strip of claim 1, wherein, include: The location and number of metal rings that are disconnected are determined based on the distribution and / or attribute information of the interface units in the first chip. The interface unit includes at least an input / output interface.

3. The chip package strip of claim 1, wherein, include: The interface unit connected to the disconnected arc segment is selected from multiple interface units based on the distance between the disconnected arc segment and each interface unit in the first chip.

4. The chip package strip of claim 1, wherein, include: In multiple metal rings with the same break position and number of breaks, each break arc segment and the corresponding break arc segment in the adjacent metal ring form multiple encapsulation strip structures; Wherein, at least one broken arc segment of at least one of the encapsulation strip structures is grounded; And / or, at least two adjacent disconnected arc segments of at least one encapsulation strip structure are in a non-conductive state, said non-conductive state being achieved by not providing a through hole or by placing the through hole in an invalid connection state.

5. The chip package strip of claim 4, wherein, include: When the upper and lower logic of the encapsulation strip structure are connected, multiple disconnected arc segments are selected at intervals from the encapsulation strip structure for grounding. The upper and lower logic conduction is achieved by setting through holes between adjacent disconnected arc segments.

6. The chip package strip of claim 4, wherein, include: Multiple disconnected arc segments are selected at intervals from the encapsulation strip structure, and the selected disconnected arc segment is set to a non-conductive state with at least one adjacent disconnected arc segment.

7. The chip package strip of claim 4, wherein, include: When the upper and lower logic of the encapsulation strip structure is connected, multiple encapsulation strip structures are selected at intervals for grounding.

8. The chip package strip of claim 1, wherein, The second chip includes: an upper chip adjacent to the first chip, and / or a lower chip adjacent to the first chip; Wherein, if the second chip includes the upper chip, the top metal ring of the packaging strip structure of the first chip is connected to the bottom metal connection layer of the upper chip; and if the second chip includes the lower chip, the bottom metal ring of the packaging strip structure of the first chip is connected to the top metal connection layer of the lower chip.

9. The chip package strip of claim 1, wherein, include: In the case where at least one silicon layer exists between the first chip and the second chip, at least one blind via is provided in the silicon layer; The blind vias are respectively connected to the packaging strip structure of the first chip and the second chip.

10. A chipset, characterized by include: Substrate; Multiple chips stacked on the substrate; as well as A chip package strip disposed around at least one of the said chips; The chip packaging strip is the chip packaging strip as described in any one of claims 1-9.

11. A chip packaging method, characterized by, include: Provides a substrate and multiple chips to be packaged; The plurality of chips to be packaged includes at least one target chip, and the target chip is peripherally provided with the chip packaging strip as claimed in any one of claims 1-9. The target chip and the remaining plurality of chips to be packaged are stacked and arranged on the substrate to obtain a packaged chip group.

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