一种电容器及芯片
By optimizing the capacitor and isolation structures, the problem of MIM capacitors affecting chip reliability was solved, improving chip reliability and noise immunity, and reducing production costs.
CN115881701BActive Publication Date: 2026-07-17SHANGHAI ANALOGY SEMICON TECH LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI ANALOGY SEMICON TECH LTD
- Filing Date
- 2022-09-08
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
When MIM capacitors are used in chips, they affect the reliability of the chips.
Method used
Design a capacitor comprising a substrate, a well region, an active region, polysilicon, and a capacitor body. Improve the density of the active region and polysilicon and reduce parasitic capacitance by optimizing the capacitor's structure and isolation structure.
Benefits of technology
This increases the density of the active area and polysilicon in the capacitor region of the chip, enhancing the chip's reliability and noise immunity, and reducing production costs.
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Figure CN115881701B_ABST
Abstract
本申请实施例提供了一种电容器及芯片，涉及芯片设计领域。其中，电容器包括：衬底、阱区、第一有源区、第二有源区、多晶硅以及电容器本体。衬底掺杂有第一类型的离子，阱区形成于衬底的表面，并从衬底的表面延伸至衬底的内部。阱区掺杂有第二类型的离子，第一类型的离子与第二类型的离子的极性相反。第一有源区和第二有源区注入于阱区部分区域，多晶硅淀积于相邻两个第二有源区之间。电容器本体设置于第一有源区的上方区域。将此电容器应用于芯片，可以提高芯片中设置电容器区域的有源区和多晶硅的密度，进而提高芯片的可靠性。
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