Packaging structure and packaging method

Abstract

The application discloses a packaging structure and a packaging method. The packaging method comprises the following steps: providing a first packaging body, the first packaging body comprising a conductive column, a bridge chip and a first packaging layer covering the conductive column and the bridge chip, and the functional layer of the conductive column and the bridge chip being exposed from the first surface of the first packaging layer; forming a transfer layer on the first surface; arranging a plurality of chips on the side of the transfer layer away from the first surface; forming a second packaging layer covering the chips and the transfer layer; thinning the second surface of the first packaging layer to expose the conductive column; and arranging a plurality of solder balls on the thinned second surface. The packaging method of the application can simplify the process by first packaging the conductive column and the bridge chip to form the first packaging body, then arranging the transfer layer and the chips on the first packaging body, and can avoid the problems of difficult control due to the lack of a blocking layer when a hole is opened later and the invalid connection caused by incomplete etching.

Description

Technical Field

[0001] This application belongs to the field of chip packaging technology, specifically relating to a packaging structure and packaging method. Background Technology

[0002] In the field of chip packaging,

[0003] With the development of integrated circuits, chip manufacturing has approached its physical limits, giving rise to the concept of improving chip performance through advanced packaging.

[0004] To optimize the electrical performance between chips, the integration requirements for chips within a package are becoming increasingly stringent. Unlike traditional methods where all chips need to be electrically connected through a substrate, existing 2.5D / 3D stacking uses through-hole technology, employing a dielectric layer with through-holes or silicon vias (TSV, TGV) on the chip itself for stacking. The silicon substrate, acting as an intermediary layer, is connected to the substrate via a bump. However, only the stacked surfaces are connected to the substrate. While this method can effectively meet the modular requirements of multi-chip packaging, it is difficult to integrate multiple chips with non-single interconnections into a highly integrated package.

[0005] In related technologies, 3D packaging technology is often used to achieve small-size and highly integrated multi-chip packaging, enabling vertical stacking, reducing package size, and improving transmission speed. However, traditional 3D packaging technology uses through-silicon via (TSV) technology, which is complex and costly. Summary of the Invention

[0006] This application aims to solve at least one of the technical problems existing in the prior art by providing a packaging structure and packaging method.

[0007] According to a first aspect of the embodiments of this application, an encapsulation method is provided, comprising:

[0008] A first package is provided, the first package including conductive pillars, bridging chips, and a first encapsulation layer covering the conductive pillars and bridging chips, the first encapsulation layer having opposing first and second surfaces, the conductive pillars and the functional layers of the bridging chips being exposed from the first surface.

[0009] An adapter layer is formed on the first surface of the first encapsulation layer;

[0010] A plurality of chips are disposed on the side of the adapter layer away from the first surface, wherein at least some of the chips are connected to the conductive pillar circuit through the adapter layer, and at least some of the adjacent chips are interconnected through the adapter layer and the bridging chip.

[0011] A second encapsulation layer is formed, which encapsulates the chip and the adapter layer;

[0012] The second surface of the first encapsulation layer is thinned to expose the conductive pillars;

[0013] A plurality of solder balls are disposed on the thinned second surface, wherein at least some of the solder balls are electrically connected to the conductive pillar.

[0014] Optionally, the provision of the first package includes:

[0015] Provide a first glass plate and a second glass plate;

[0016] Conductive pillars are formed on the first glass sheet;

[0017] A bridging chip is disposed on the first glass sheet, with the functional surface of the bridging chip facing away from the first glass sheet;

[0018] A first molding layer is formed, which encapsulates the conductive pillar and the bridging chip.

[0019] Separate the first glass sheet and bond the side of the first molding layer away from the first glass sheet to the second glass sheet;

[0020] A second molding layer is formed, which covers the first molding layer and the bridge chip. The second molding layer and the first molding layer constitute the first encapsulation layer.

[0021] The second glass sheet is separated, and the side of the first molding layer opposite to the second molding layer is thinned to expose the conductive pillars and the functional surface of the bridging chip.

[0022] Optionally, the first glass sheet and / or the second glass sheet can be separated by removing the release layer.

[0023] Optionally, forming conductive pillars on the first glass sheet includes:

[0024] A seed layer is formed on the first glass slide;

[0025] A dielectric layer is formed on the side of the seed layer opposite to the first glass sheet;

[0026] The dielectric layer is patterned to form deep holes;

[0027] A conductive pillar is deposited within the deep hole;

[0028] Remove the dielectric layer.

[0029] Optionally, the seed layer is covered by the first encapsulation layer, and the seed layer is removed when the second surface of the first encapsulation layer is thinned.

[0030] Optionally, the first encapsulation layer and the second encapsulation layer are formed using a compression molding process.

[0031] Optionally, before forming the second encapsulation layer, the method further includes:

[0032] An underfill is filled between the chip and the adapter layer.

[0033] Optionally, after forming the second encapsulation layer, the method further includes:

[0034] A heat dissipation layer is provided on the side of the second encapsulation layer opposite to the first encapsulation layer.

[0035] Optionally, before providing a heat dissipation layer on the side of the second encapsulation layer opposite to the first encapsulation layer, the method further includes:

[0036] The side of the second encapsulation layer opposite to the first encapsulation layer is thinned to expose the non-functional surface of the chip.

[0037] According to a second aspect of the embodiments of this application, a packaging structure is provided, the packaging structure being formed by the packaging method described above.

[0038] The above-mentioned technical solution of this application has the following beneficial technical effects:

[0039] The packaging method of this application embodiment first encapsulates conductive pillars and bridging chips to form a first package, and then sets an adapter layer and a package chip on the first package. Compared with the existing method of opening holes in the package structure and making conductive pillars, the process is simpler. In addition, it can avoid the problem of difficulty in control due to lack of a barrier layer when opening holes later, as well as the situation of invalid connection due to incomplete etching. Attached Figure Description

[0040] Figure 1 This is a flowchart of an encapsulation method in an exemplary embodiment of this application;

[0041] Figures 2 to 18 This is a process for a packaging structure in an exemplary embodiment of this application;

[0042] In the figure, 101 is the first glass sheet; 102 is the second glass sheet; 103 is the first molding layer; 104 is the second molding layer; 110 is the conductive pillar; 120 is the bridging chip; 121 is the conductive bump; 130 is the first encapsulation layer; 140 is the first release layer; 150 is the second release layer; 160 is the seed layer; 170 is the adapter layer; 181 is the first chip; 182 is the second chip; 183 is the third chip; 184 is the solder pad; 190 is the underfill; 200 is the second encapsulation layer; 210 is the solder ball; and 220 is the heat dissipation layer. Detailed Implementation

[0043] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0044] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0045] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0046] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0047] like Figure 1 As shown, this application embodiment provides a packaging method, including:

[0048] S110. A first package is provided, the first package including a conductive post 110, a bridging chip 120 and a first encapsulation layer 130 covering the conductive post 110 and the bridging chip 120, the first encapsulation layer 130 having a first surface and a second surface opposite to each other, and the functional layers of the conductive post 110 and the bridging chip 120 being exposed from the first surface.

[0049] In this embodiment, the conductive post 110 is used to connect the chip to be packaged to the outside world.

[0050] like Figure 10As shown, there are two sets of conductive pillars 110, with two conductive pillars 110 in each set. The conductive pillars 110 are arranged in a direction perpendicular to the first surface. One end of the conductive pillar 110 is exposed from the first surface of the first encapsulation layer 130, and the other end of the conductive pillar 110 is covered by the first encapsulation layer 130.

[0051] In this embodiment, the bridging chip 120 is used to interconnect multiple chips to be packaged.

[0052] like Figure 10 As shown, there are two bridging chips 120, which are located between two sets of conductive pillars 110. The functional surface of the bridging chip 120 is parallel to the first surface and is exposed from the first surface of the first encapsulation layer 130. The non-functional surface of the bridging chip 120 is covered by the first encapsulation layer 130.

[0053] like Figure 10 As shown, conductive bumps 121 are provided on the functional surface of the bridging chip 120 at intervals. The conductive bumps 121 are used to electrically connect the bridging chip 120 to other components.

[0054] The conductive bump 121 can be manufactured by electroplating.

[0055] It is understandable that, since the conductive bumps 121 can electrically connect the bridging chip 120 to other components, even if the functional surface of the bridging chip 120 is not exposed from the first encapsulation layer 130, the bridging chip 120 can still be electrically connected to other components through the conductive bumps 121, provided that the conductive bumps 121 on its functional surface are exposed. In other words, the bridging chip 120 only needs to expose the conductive bumps 121 on its functional surface. Because the functional surface of the bridging chip 120 is not exposed, the risk of damage to the bridging chip 120 is greatly reduced.

[0056] It should be noted that the material of the conductive bump 121 can be copper, nickel, chromium copper alloy, nickel vanadium alloy, nickel gold alloy, aluminum, etc., and this embodiment does not make specific limitations.

[0057] In this embodiment, the first encapsulation layer 130, in addition to encapsulating the conductive pillar 110 and the bridging chip 120, can also be used as a carrier for the chip packaging process. Compared to using a glass sheet as a carrier to carry the entire packaging process, the first encapsulation layer 130 in this embodiment can reduce the risk of machine identification in subsequent processes.

[0058] The first encapsulation layer 130 can be made of epoxy resin or similar materials, and can be formed using a compression molding process.

[0059] like Figures 2 to 10As shown, exemplarily, the fabrication steps of the first package include: providing a first glass sheet 101 and a second glass sheet 102; forming conductive pillars 110 on the first glass sheet 101; disposing a bridging chip 120 on the first glass sheet 101, with the functional surface of the bridging chip 120 facing away from the first glass sheet 101; forming a first molding compound 103, the first molding compound 103 covering the conductive pillars 110 and the bridging chip 120; separating the first glass sheet 101 and the first molding compound... The side of 103 facing away from the first glass sheet 101 is bonded to the second glass sheet 102; a second molding compound 104 is formed, which covers the first molding compound 103 and the bridging chip 120. The second molding compound 104 and the first molding compound 103 constitute the first encapsulation layer 130; the second glass sheet 102 is separated, and the side of the first molding compound 103 facing away from the second molding compound 104 is thinned to expose the conductive post 110 and the functional surface of the bridging chip 120.

[0060] The first encapsulation layer 130 and the second encapsulation layer 200 can be formed by compression molding.

[0061] The first glass sheet 101 and / or the second glass sheet 102 can be separated by removing the peeling layer.

[0062] It is understood that in the above embodiment for fabricating the first encapsulation body, the first glass sheet 101 and the second glass sheet 102 are used as temporary carriers. To facilitate the separation of the first glass sheet 101 and the second glass sheet 102, a release layer can be formed on the carrier surface of the first glass sheet 101 and the second glass sheet 102 using a thermoplastic organic adhesive, etc. When conditions such as temperature change, the release layer melts, allowing the glass sheets to be separated. For example, a first release layer 140 is formed on the side of the first glass sheet 101 where the conductive post 110 and the bridging chip 120 are located, and a second release layer 150 is formed on the side of the second glass sheet 102 that is bonded to the first encapsulation layer 103.

[0063] The steps of forming conductive pillars 110 on the first glass sheet 101 include: forming a seed layer 160 on the first glass sheet 101; forming a dielectric layer on the side of the seed layer 160 opposite to the first glass sheet 101; patterning the dielectric layer to form a deep hole; depositing conductive pillars 110 in the deep hole; and removing the dielectric layer.

[0064] Optionally, the seed layer 160 is covered by the first encapsulation layer 130, and the seed layer 160 is removed when the second surface of the first molding layer 103 is thinned.

[0065] It is understandable that the seed layer 160 is temporarily retained within the first encapsulation layer 130, which can increase the strength of the carrier and also serve as a protective layer for the bridge chip 120. During the subsequent thinning of the second surface of the first encapsulation layer 130, it can protect the bridge chip 120 from damage.

[0066] S120, an adapter layer 170 is formed on the first surface of the first encapsulation layer 130.

[0067] In this embodiment, the redistribution layer is used to electrically connect to the conductive pillars 110 and the conductive bumps 121.

[0068] like Figure 11 As shown, the transition layer 170 includes three redistribution layers, and its formation steps include: forming a first dielectric layer on the side of the first encapsulation layer 130 away from the carrier board; patterning the first dielectric layer and forming a first metal layer on the patterned first dielectric layer; forming a second dielectric layer on the first dielectric layer and the first metal layer; patterning the second dielectric layer and forming a second metal layer on the patterned second dielectric layer; forming a third dielectric layer on the second dielectric layer and the second metal layer; and patterning the third dielectric layer and forming a third metal layer on the patterned third dielectric layer.

[0069] It should be noted that the dielectric layer material can be polyimide (PI), polybenzoxazole (PBO), etc., and the coating method can be wafer spin coating. This embodiment does not impose specific limitations.

[0070] It should be noted that the material of the metal layer is titanium, copper, etc., and the formation method can be sputtering, electroplating, etc., which are not specifically limited in this embodiment.

[0071] It should be noted that the number of redistribution layers can be fewer or more, for example, 2, 4, or 5 layers, etc. This embodiment does not make a specific limitation.

[0072] S130. A plurality of chips are disposed on the side of the transition layer 170 away from the first surface, wherein at least some of the chips are connected to the conductive pillar 110 circuit through the transition layer 170, and at least some of the adjacent chips are interconnected through the transition layer 170 and the bridge chip 120.

[0073] In this embodiment, the chip is the chip to be packaged, which is soldered onto the adapter layer 170.

[0074] like Figure 12As shown, the chip includes a first chip 181, a second chip 182, and a third chip 183. The first chip 181, the second chip 182, and the third chip 183 are sequentially spaced apart along a direction parallel to the first surface. The functional surfaces of the first chip 181 and the second chip 182 both face the adapter layer 170. The first chip 181 is electrically connected to a set of conductive posts 110 via the adapter layer 170, and the third chip 183 is electrically connected to another set of conductive posts 110 via the adapter layer 170. Furthermore, the first chip 181 and the second chip 182 are interconnected via the adapter layer 170 and a bridge chip 120, and the second chip 182 and the third chip 183 are interconnected via the adapter layer 170 and another bridge chip 120.

[0075] like Figure 12 As shown, the chip has multiple pads 184 on its functional surface. The chip is soldered to the transition layer 170 through the pads 184, and the chip is electrically connected to the transition layer 170 through the pads 184.

[0076] It should be noted that the material of pad 184 can be copper, nickel, chromium copper alloy, nickel vanadium alloy, nickel gold alloy, aluminum, etc., and this embodiment does not make specific limitations.

[0077] To enhance chip connection strength and improve chip drop resistance, underfill technology can be used to fill the bottom of the chip. This is because the functional surfaces of the chip have spaced pads 184, which results in a large void ratio between the chip and the transition layer 170, causing the chip to be unstable. By filling, the chip can be reinforced, its shock resistance can be increased, and the stress at the solder joints can be significantly reduced.

[0078] For example, after a plurality of chips are disposed on the side of the adapter layer 170 opposite to the first surface, the method further includes filling the space between the chips and the adapter layer 170 with an underfill 190.

[0079] like Figure 13 As shown, the vertical cross-section of the bottom filler 190 is trapezoidal, which can improve the stability of the chip in the subsequent lamination process.

[0080] It should be noted that the filler 190 can be epoxy resin, phenolic resin, polyurethane resin, urea-formaldehyde resin, silicone resin, etc., and this embodiment does not make specific limitations.

[0081] S140, Form a second packaging layer 200, the second packaging layer 200 covers the chip and the adapter layer 170.

[0082] like Figure 14 As shown, the second encapsulation layer 200 is located on the first molding layer 103 and covers the top and side surfaces of the chip, the underfill 190 and the adapter layer 170.

[0083] The second encapsulation layer 200 can be made of epoxy resin or similar materials, and can be formed by compression molding process.

[0084] It should be noted that the material of the second encapsulation layer 200 can be a liquid, powder, or other similar material, and this embodiment does not impose any specific limitations.

[0085] S150, the second surface of the first encapsulation layer 130 is thinned to expose the conductive pillars 110.

[0086] like Figure 15 As shown, after the second surface of the first encapsulation layer 130 is thinned, the end of the conductive post 110 facing away from the transition layer 170 is exposed.

[0087] The second surface of the first encapsulation layer 130 can be thinned using a grinding process.

[0088] S160. A plurality of solder balls 210 are provided on the thinned second surface, wherein at least some of the solder balls 210 are electrically connected to the conductive post 110.

[0089] In this embodiment, the solder ball 210 is used to connect the conductive post 110 to the outside world, and also to weld and fix the packaging structure.

[0090] like Figure 16 As shown, multiple solder balls 210 are evenly distributed on the second surface of the first encapsulation layer 130. The encapsulation structure can be fixed to the substrate by soldering multiple solder balls 210. Some of the solder balls 210 are electrically connected to the conductive pillars 110. The encapsulation structure can be connected to the outside world through the solder balls 210 electrically connected to the conductive pillars 110.

[0091] In some embodiments, after forming the second encapsulation layer 200, the method further includes:

[0092] A heat dissipation layer 220 is provided on the side of the second encapsulation layer 200 that is opposite to the first encapsulation layer 130.

[0093] In this embodiment, the heat dissipation layer 220 can reduce the heat of the packaging structure in a timely manner when the chips are interconnected, ensuring the normal operation of the signal interconnection between the chips.

[0094] like Figure 18 As shown, the heat dissipation layer 220 covers the entire side of the second molding layer 104 facing away from the carrier plate, which increases the heat dissipation area and effectively improves the heat dissipation efficiency.

[0095] To improve the heat dissipation effect of the heat dissipation layer 220, the side of the second molding layer 104 facing away from the carrier board can be thinned so that the heat dissipation layer 220 can directly contact the chip.

[0096] Among them, a grinding process can be used to thin the second molding layer 104.

[0097] For example, before providing a heat dissipation layer 220 on the side of the second encapsulation layer 200 opposite to the first encapsulation layer 130, the method further includes:

[0098] The side of the second packaging layer 200 facing away from the first packaging layer 130 is thinned to expose the non-functional surface of the chip.

[0099] The packaging method of this application embodiment first encapsulates the conductive pillar 110 and the bridging chip 120 to form a first package, and then sets the adapter layer 170 and the package chip on the first package. Compared with the existing method of opening holes in the package structure and making conductive pillars 110, the process is simpler. In addition, it can avoid the problem of difficulty in control due to lack of a barrier layer when opening holes later, as well as the situation of invalid connection due to incomplete etching.

[0100] This application also provides a packaging structure formed using the packaging method described above. The specific steps of the packaging method can be found in the preceding descriptions and will not be repeated here. The packaging structure formed using the aforementioned packaging method not only simplifies the process but also avoids the problems of difficulty in controlling the process due to the lack of a barrier layer during later hole opening, as well as the situation of incomplete etching leading to invalid connections.

[0101] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A packaging method, characterized in that, include: A first package is provided, the first package including conductive pillars, bridging chips, and a first encapsulation layer covering the conductive pillars and bridging chips, the first encapsulation layer having opposing first and second surfaces, the conductive pillars and the functional layers of the bridging chips being exposed from the first surface. The provision of the first package includes: Provide a first glass plate and a second glass plate; Conductive pillars are formed on the first glass sheet; A bridging chip is disposed on the first glass sheet, with the functional surface of the bridging chip facing away from the first glass sheet; A first molding layer is formed, which encapsulates the conductive pillar and the bridging chip. Separate the first glass sheet and bond the side of the first molding layer away from the first glass sheet to the second glass sheet; A second molding layer is formed, which covers the first molding layer and the bridge chip. The second molding layer and the first molding layer constitute the first encapsulation layer. The second glass sheet is separated, and the side of the first molding layer opposite to the second molding layer is thinned to expose the conductive pillar and the functional surface of the bridging chip. An adapter layer is formed on the first surface of the first encapsulation layer; A plurality of chips are disposed on the side of the adapter layer opposite to the first surface, wherein at least some of the chips are connected to the conductive pillar circuit through the adapter layer, and at least some of the adjacent chips are interconnected through the adapter layer and the bridging chip. A second encapsulation layer is formed, which encapsulates the chip and the adapter layer; The second surface of the first encapsulation layer is thinned to expose the conductive pillars; A plurality of solder balls are disposed on the thinned second surface, wherein at least some of the solder balls are electrically connected to the conductive pillar.

2. The packaging method according to claim 1, characterized in that, The first glass sheet and / or the second glass sheet are separated by removing the release layer.

3. The packaging method according to claim 1, characterized in that, The process of forming conductive pillars on the first glass sheet includes: A seed layer is formed on the first glass slide; A dielectric layer is formed on the side of the seed layer opposite to the first glass sheet; The dielectric layer is patterned to form deep holes; A conductive pillar is deposited within the deep hole; Remove the dielectric layer.

4. The packaging method according to claim 3, characterized in that, The seed layer is covered by the first encapsulation layer, and the seed layer is removed when the second surface of the first encapsulation layer is thinned.

5. The method according to claim 1, characterized in that, The first encapsulation layer and the second encapsulation layer are formed using a compression molding process.

6. The packaging method according to claim 1, characterized in that, Before forming the second encapsulation layer, the method further includes: An underfill is filled between the chip and the adapter layer.

7. The packaging method according to claim 1, characterized in that, After forming the second encapsulation layer, the method further includes: A heat dissipation layer is provided on the side of the second encapsulation layer opposite to the first encapsulation layer.

8. The packaging method according to claim 7, characterized in that, Before providing a heat dissipation layer on the side of the second encapsulation layer opposite to the first encapsulation layer, the method further includes: The side of the second encapsulation layer opposite to the first encapsulation layer is thinned to expose the non-functional surface of the chip.

9. A packaging structure, characterized in that, The encapsulation structure is formed by the encapsulation method according to any one of claims 1-8.

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