Diode cell structure, chip and vehicle

Abstract

The application provides a diode cell structure, a chip and a vehicle, which comprise a cathode metal region, an anode metal region, an N-type region connected to the cathode metal region, a P-type region connected to the anode metal material region and arranged on the N-type region, and a connecting region connected between the P-type region and the N-type region, wherein the material of the connecting region has a lattice difference with the material of a contact region in the N-type region, the thickness of the connecting region is less than or equal to a preset thickness threshold, and the conductivity of the connecting region is lower than a preset value. The application sets the connecting region between the P-type region and the N-type region, and the connecting region has the characteristics of the lattice difference with the contact region in the N-type region, the low conductivity and the thickness less than or equal to the preset thickness threshold, so that the interface increases defects, the number of recombination centers is increased, the lifetime of the minority carriers is reduced, and the cost is greatly reduced, thereby facilitating mass production.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a diode cell structure, a chip, and a vehicle. Background Technology

[0002] Local lifetime control technology selectively introduces deep-trap recombination centers within a local area in a diode, thereby effectively reducing the reverse recovery time and improving the softness factor. Currently, the technology used for local lifetime control is light ion implantation, such as hydrogen or helium ion implantation. However, the short implantation range of these ions leads to the formation of a localized low-lifetime region with high defect density at the end of the implantation range.

[0003] However, currently, light ion implantation to form localized low-lifetime regions requires high-energy ion implantation equipment, which is expensive, resulting in high costs for each ion implantation. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art.

[0005] Therefore, one object of the present invention is to propose a diode cell structure, which provides a connection region between the P-type region and the N-type region. Since the connection region has the characteristics of having lattice difference, low conductivity and thickness less than or equal to a preset thickness threshold with the contact region in the N-type region, the interface has more defects. This increases the number of recombination centers and reduces minority carrier lifetime, while greatly reducing costs and facilitating mass production.

[0006] Therefore, a second objective of this invention is to provide a method for preparing a diode cell structure.

[0007] Therefore, a third objective of this invention is to provide a chip.

[0008] Therefore, the fourth objective of this invention is to provide a vehicle.

[0009] To achieve the above objectives, a first aspect of the present invention provides a diode cell structure comprising: a cathode metal region; an anode metal region; an N-type region connected to the cathode metal region; a P-type region connected below the anode metal region and disposed above the N-type region; and a connecting region connecting the P-type region and the N-type region, wherein the materials of the contact regions between the connecting region and the N-type region have a lattice difference, the thickness of the connecting region is less than or equal to a preset thickness threshold, and the conductivity of the connecting region is lower than a preset value.

[0010] According to the diode cell structure of the present invention, by setting a connection region between the P-type region and the N-type region, the connection region has the characteristics of having lattice difference, low conductivity and thickness less than or equal to a preset thickness threshold with the contact region in the N-type region, which increases the defects at the interface and forms a local low lifetime region. Moreover, it does not require expensive equipment for ion implantation, thus achieving local lifetime control. This greatly reduces the cost while increasing the number of recombination centers and reducing minority carrier lifetime, and facilitates mass production.

[0011] In some embodiments, the connection region includes a connection film layer connected between the P-type region and the N-type region.

[0012] In some embodiments, the connecting thin film layer is configured as an oxide or a nitride.

[0013] In some embodiments, the oxide thin film layer is continuously disposed between the P-type region and the N-type region.

[0014] In some embodiments, the oxide thin film layer is discontinuously disposed between the P-type region and the N-type region.

[0015] In some embodiments, the preset thickness threshold is 5 nm.

[0016] In some embodiments, the oxide comprises Al2O3, and the nitride comprises AlN.

[0017] In some embodiments, the N-type region includes an epitaxial layer and a substrate layer, the substrate layer being connected above the cathode metal region, and the epitaxial layer being connected above the substrate layer and below the connection region.

[0018] To achieve the above objectives, a second aspect of the present invention provides a method for fabricating a diode cell structure. The method includes: setting a substrate layer; setting an epitaxial layer on top of the substrate layer; setting a connection region on top of the epitaxial layer, wherein the material within the connection region has a lattice difference with the material of the substrate layer, the thickness of the connection region is less than or equal to a preset thickness threshold, and the conductivity of the connection region is lower than a preset value; epitaxially growing an N-type silicon material on top of the connection region; implanting impurities into the front side of the N-type silicon material and activating it to form a P-type region; setting an anode metal region on top of the P-type region; and setting a cathode metal region at the bottom of the substrate layer.

[0019] According to the method for fabricating a diode cell structure according to an embodiment of the present invention, a connection region is set between the P-type region and the N-type region. Since the connection region has the characteristics of having lattice difference, low conductivity and thickness less than or equal to a preset thickness threshold with the contact region in the N-type region, the interface increases defects and forms a local low lifetime region. Moreover, it does not require expensive equipment for ion implantation, thus achieving local lifetime control. This increases the number of recombination centers and reduces minority carrier lifetime while greatly reducing costs and facilitating mass production.

[0020] To achieve the above objectives, a third aspect of the present invention provides a chip comprising the diode cell structure described in the above embodiments.

[0021] According to an embodiment of the present invention, the diode of the chip has a connection region between the P-type region and the N-type region. Since the connection region has the characteristics of having lattice difference, low conductivity and thickness less than or equal to a preset thickness threshold with the contact region in the N-type region, the interface has increased defects and formed a local low lifetime region. Moreover, it does not require expensive equipment for ion implantation, thus achieving local lifetime control. This increases the number of recombination centers and reduces minority carrier lifetime, while greatly reducing costs and facilitating mass production.

[0022] To achieve the above objectives, an embodiment of the fourth aspect of the present invention provides a vehicle comprising the chip described in the above embodiment.

[0023] According to an embodiment of the present invention, the diode of the chip 2 has a connection region between the P-type region and the N-type region. Since the connection region has the characteristics of having lattice difference, low conductivity and thickness less than or equal to a preset thickness threshold with the contact region in the N-type region, the interface has increased defects and formed a local low lifetime region. Moreover, it does not require expensive equipment for ion implantation, thus achieving local lifetime control. This greatly reduces the cost while increasing the number of recombination centers and reducing minority carrier lifetime, making it easy for mass production.

[0024] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0025] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0026] Figure 1 This is a schematic diagram of a diode cell structure according to an embodiment of the present invention;

[0027] Figure 2This is a schematic diagram of the structural distribution of oxides or nitrides according to a specific embodiment of the present invention;

[0028] Figure 3 This is a flowchart of a method for fabricating a diode cell structure according to an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of the substrate layer and epitaxial layer structure according to an embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram of the structure of the connection area according to an embodiment of the present invention;

[0031] Figure 6 This is a schematic diagram of the structure of a P-type region according to an embodiment of the present invention;

[0032] Figure 7 This is a block diagram of a chip according to an embodiment of the present invention;

[0033] Figure 8 This is a block diagram of a vehicle according to an embodiment of the present invention.

[0034] Figure reference numerals: Diode cell structure 1; Cathode metal region 06; Anode metal region 05; N-type region 10; P-type region 04; Connection region 03; Epitaxial layer 02; Substrate layer 01; Chip 2; Vehicle 3. Detailed Implementation

[0035] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.

[0036] The diode cell structure of an embodiment of the present invention will be described below.

[0037] The following is combined with Figure 1 The diode cell structure of an embodiment of the present invention is described as follows: Figure 1 As shown, the diode cell structure 1 of this embodiment includes: a cathode metal region 06, an anode metal region 05, an N-type region 10, a P-type region 04, and a connecting region 03. The N-type region 10 is connected above the cathode metal region 06; the P-type region 04 is connected below the anode metal region 05 and is disposed above the N-type region 10; the connecting region 03 is connected between the P-type region 04 and the N-type region 10. The materials of the connecting region 03 and the contact region 01 in the N-type region 10 have a lattice difference. The thickness of the connecting region 03 is less than or equal to a preset thickness threshold, and the conductivity of the connecting region 03 is lower than a preset value.

[0038] In this embodiment, a connection region 03 is provided between the P-type region 04 and the N-type region 10. Due to the lattice difference between the material of the connection region 03 and the contact region 01 in the N-type region 10, such as silicon, there is a lattice mismatch between the connection region 03 and silicon. At the same time, the connection region 03 has weak conductivity and thinness, which increases the interface defects. While increasing the number of recombination centers and reducing minority carrier lifetime, it is not necessary to use expensive equipment for ion implantation. Local lifetime control can be achieved simply by providing a connection region 03 between the P-type region 04 and the N-type region 10, thereby greatly reducing costs and facilitating mass production.

[0039] According to the diode cell structure 1 of the present invention, a connection region 03 is provided between the P-type region 04 and the N-type region 10. Since the connection region 03 has the characteristics of having lattice difference, low conductivity and thickness less than or equal to a preset thickness threshold with the contact region in the N-type region 10, the interface increases defects and forms a local low lifetime region. Moreover, it does not require expensive equipment for ion implantation, thus achieving local lifetime control. This greatly reduces the cost while increasing the number of recombination centers and reducing minority carrier lifetime, making it easy for mass production.

[0040] In some embodiments, such as Figure 1 As shown, the connection region 03 includes a connection thin film layer, which connects the P-type region 04 and the N-type region 10. Specifically, the materials of the connection thin film layer and the substrate layer 01, such as silicon carbide and silicon, have lattice differences, and the thickness of the connection thin film layer is relatively thin, for example, less than 5 nm. Specifically, the thickness of the connection thin film can be between 2 nm and 5 nm, and the conductivity of the connection thin film layer is relatively weak, which increases the number of defects at the interface. This increases the number of recombination centers and reduces the minority carrier lifetime, while eliminating the need for expensive equipment for ion implantation, thereby greatly reducing costs and facilitating mass production.

[0041] In some embodiments, the connecting thin film layer is configured as an oxide or a nitride. Specifically, such as Figure 2 The diagram shown illustrates the structural distribution of oxides or nitrides according to an embodiment of the present invention. The oxide is, for example, Al₂O₃, and the nitride is, for example, AlN. The Al₂O₃ film is polycrystalline, which reduces the carrier transport velocity during transit, thereby reducing ion implantation and improving the diode's flexibility.

[0042] In some embodiments, combined with Figure 1 and Figure 2As shown, the oxide thin film layer is continuously disposed between the P-type region 04 and the N-type region 10, for example, the epitaxial layer 02. It can be understood that the state in which the oxide thin film layer is disposed between the P-type region 04 and the N-type region 10 can be set according to actual needs, for example, the oxide thin film layer can be continuously disposed between the P-type region 04 and the N-type region 10.

[0043] In some embodiments, combined with Figure 1 and Figure 2 As shown, the oxide thin film layer is discontinuously disposed between the P-type region 04 and the N-type region 10, for example, between the epitaxial layer 02. Specifically, when the oxide thin film layer is discontinuously disposed between the P-type region 04 and the N-type region 10, the discontinuous disposal of the oxide thin film layer is achieved by using a photomask, so that different states of the oxide thin film layer can be disposed according to actual needs.

[0044] In some embodiments, such as Figure 2 As shown, the preset thickness threshold for connection region 03 is 5nm. Specifically, the thickness of connection region 03 is less than the preset thickness threshold. For example, the thickness of connection region 03 can be between 2nm and 5nm, which can avoid the problem of excessive thickness affecting the carrier transport rate and causing excessive forward conduction voltage.

[0045] In some embodiments, such as Figure 1 As shown, the N-type region 10 includes an epitaxial layer 02 and a substrate layer 01. The substrate layer 01 is connected to the cathode metal region 06, and the epitaxial layer 02 is connected to the substrate layer 01 and below the connection region 03. Specifically, an oxide or nitride is disposed between the P-type region 04 and the epitaxial layer 02, that is, between the PN junctions.

[0046] According to the diode cell structure 1 of the present invention, a connection region 03 is provided between the P-type region 04 and the N-type region 10. Since the connection region 03 has the characteristics of having lattice difference, low conductivity and thickness less than or equal to a preset thickness threshold with the contact region in the N-type region 10, the interface increases defects and forms a local low lifetime region. Moreover, it does not require expensive equipment for ion implantation, thus achieving local lifetime control. This greatly reduces the cost while increasing the number of recombination centers and reducing minority carrier lifetime, making it easy for mass production.

[0047] The following describes a method for preparing the diode cell structure according to an embodiment of the present invention.

[0048] like Figure 3The method for fabricating a diode cell structure according to an embodiment of the present invention includes: setting a substrate layer 01; setting an epitaxial layer 02 on top of the substrate layer 01; setting a connection region 03 on top of the epitaxial layer 02, wherein the material in the connection region 03 has a lattice difference with the material in the substrate layer 01, the thickness of the connection region 03 is less than or equal to a preset thickness threshold, and the conductivity of the connection region 03 is lower than a preset value; epitaxially growing an N-type silicon material on top of the connection region 03, implanting impurities on the front side of the N-type silicon material and activating it to form a P-type region 04; setting an anode metal region 05 on top of the P-type region 04; and setting a cathode metal region 06 at the bottom of the substrate layer 01.

[0049] The following is combined with Figures 3-6 as well as Figure 1 The method for preparing the diode cell structure according to embodiments of the present invention will be described in detail.

[0050] In an embodiment, such as Figure 4 The diagram shown is a schematic representation of the substrate and epitaxial layer structure according to an embodiment of the present invention. When fabricating the diode cell structure, a low-resistivity N+ substrate of conductivity type 01, such as 01N+, is provided; an epitaxial layer 02N- is formed on top of the substrate 01N+ using an epitaxial process. In a specific embodiment, the concentration of the substrate 01N+ can be set to e-. 20 m -3 The thickness of the substrate layer 01N+ is 300µm to 500µm; the concentration of the epitaxial layer 02N- can be set to 1e. 13 m -3 -5e 14 m -3 The thickness of the epitaxial layer 02N- can be set from 10um to 200um.

[0051] like Figure 5 The diagram shown is a schematic representation of the connection region according to an embodiment of the present invention. An Al2O3 thin film is sputtered onto the O2N epitaxial layer using magnetron sputtering, with the film thickness controlled to within 5 nm to avoid affecting the carrier transport rate and causing excessive forward conduction voltage due to excessive thickness. In a specific embodiment, a high-purity Al2O3 target is used as the sputtering material, and an Al2O3 thin film of less than 5 nm is sputtered under vacuum.

[0052] like Figure 6 The diagram shown is a schematic representation of the structure of a P-type region according to an embodiment of the present invention. N-type silicon material is epitaxially grown on top of the connection region 03, and P-type impurities are implanted on the front side to activate and form the P-type region 04. Specifically, an N-layer is epitaxially grown on an Al2O3 film with a concentration of 1e. 13 m -3 -5e 14 m -3For thicknesses ranging from 3µm to 10µm, P-type impurity implantation is performed at a dose of 1e. 12 m -3 -1e 14 m -3 And drive it in at 1150℃ for 30 min to 700 min.

[0053] like Figure 1 The diagram shown is a schematic representation of a diode cell structure according to an embodiment of the present invention. Figure 1 It can be seen that an anode metal region 05 is provided on top of the P-type region 04, and a cathode metal region 06 is provided on the bottom of the substrate layer 01, thereby forming a diode cell structure with an oxide thin film. In a specific embodiment, the anode metal region 05 is, for example, Al or Cu metal with a thickness of 1µm to 4µm; the cathode metal region 06 is, for example, Ti, i, or Ag, with a total thickness of 1µm to 2µm.

[0054] According to the method for fabricating a diode cell structure according to an embodiment of the present invention, a connection region 03 is provided between the P-type region 04 and the N-type region 10. Since the connection region 03 has the characteristics of having lattice difference, low conductivity and thickness less than or equal to a preset thickness threshold with the contact region in the N-type region 10, the interface increases defects and forms a local low lifetime region. Moreover, it does not require expensive equipment for ion implantation, thereby achieving local lifetime control. This increases the number of recombination centers and reduces minority carrier lifetime while greatly reducing costs and facilitating mass production.

[0055] The chip according to an embodiment of the present invention is described below.

[0056] like Figure 7 As shown, an embodiment of the present invention proposes a chip 2, which includes: the diode cell structure 1 described in the above embodiment.

[0057] According to the chip 2 of the present invention, the diode has a connection region 03 between the P-type region 04 and the N-type region 10. Since the connection region 03 has the characteristics of having lattice difference, low conductivity and thickness less than or equal to a preset thickness threshold with the contact region in the N-type region 10, the interface has increased defects and formed a local low lifetime region. Moreover, it does not require expensive equipment for ion implantation, thus achieving local lifetime control. This increases the number of recombination centers and reduces minority carrier lifetime, while greatly reducing costs and facilitating mass production.

[0058] The vehicle according to an embodiment of the present invention is described below.

[0059] like Figure 8 As shown, an embodiment of the present invention proposes a vehicle 3, which includes the chip 2 described in the above embodiment.

[0060] According to an embodiment of the present invention, in the vehicle 3, the diode of the chip 2 has a connection region 03 between the P-type region 04 and the N-type region 10. Since the connection region 03 has the characteristics of having lattice difference, low conductivity and thickness less than or equal to a preset thickness threshold with the contact region in the N-type region 10, the interface increases defects and forms a local low lifetime region. Moreover, it does not require expensive equipment for ion implantation, thus achieving local lifetime control. This increases the number of recombination centers and reduces minority carrier lifetime while greatly reducing costs and facilitating mass production.

[0061] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0062] In the description of this invention, it should be understood that the terms "center", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", "circumferential", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0063] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A diode cell structure, characterized in that, include: Cathode metal region; Anode metal region; An N-type region, wherein the N-type region is connected to the cathode metal region; The P-type region is connected below the anode metal region and disposed above the N-type region; A connection region, the connection region being connected between the P-type region and the N-type region, includes a connection thin film layer, the connection thin film layer being connected between the P-type region and the N-type region, the connection thin film layer being configured as a nitride, the nitride including AlN, the material of the contact region between the connection region and the contact region within the N-type region having a lattice difference, the thickness of the connection region being less than or equal to a preset thickness threshold, the preset thickness threshold being 5 nm, and the conductivity of the connection region being lower than a preset value.

2. The diode cell structure according to claim 1, characterized in that, The connecting film layer is continuously disposed between the P-type region and the N-type region.

3. The diode cell structure according to claim 1, characterized in that, The connecting film layer is intermittently disposed between the P-type region and the N-type region.

4. The diode cell structure according to claim 1, characterized in that, The contact area is a substrate layer, and the N-type region includes an epitaxial layer and the substrate layer. The substrate layer is connected to the cathode metal region, and the epitaxial layer is connected to the substrate layer and below the connection region.

5. A method for fabricating a diode cell structure, characterized in that, For the diode cell structure as described in any one of claims 1-4, comprising: Set a substrate layer; An epitaxial layer is disposed on top of the substrate layer; A connection region is provided on the top of the epitaxial layer. The connection region includes a connection thin film layer, which is connected between the P-type region and the N-type region. The material in the connection region has a lattice difference with the material of the substrate layer. The thickness of the connection region is less than or equal to a preset thickness threshold, and the conductivity of the connection region is lower than a preset value. An N-type silicon material is epitaxially grown on the top of the connection region, and impurities are implanted and activated on the front side of the N-type silicon material to form a P-type region. An anode metal region is provided at the top of the P-type region; A cathode metal region is provided at the bottom of the substrate layer.

6. A chip, characterized in that, Includes the diode cell structure as described in any one of claims 1-4.

7. A vehicle, characterized in that, Includes the chip as described in claim 6.

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