A HEMT device with an array side gate structure and a method of manufacturing the same

By designing an array-side gate structure and combining shallow and deep etching techniques, the side gate tilt angle is optimized, solving the problems of high threshold voltage and low on-resistance in GaN power devices. This achieves stable and efficient normally-off operation, making it suitable for large-area wafer production.

CN115881774BActive Publication Date: 2026-05-29DALIAN UNIV OF TECH
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
DALIAN UNIV OF TECH
Filing Date
2022-11-03
Publication Date
2026-05-29

AI Technical Summary

Technical Problem

Existing GaN power devices struggle to achieve normally-off operation with high threshold voltage and low on-resistance, and the uniformity and precision of etching during mass production on large-area wafers are difficult to control, leading to unstable device performance.

Method used

An array-type side gate structure is adopted. By combining shallow and deep etching of the channel region and taking into account the difference in work function between the gate metal and the semiconductor, the channel electron concentration is adjusted, the side gate tilt angle α is optimized, and an isosceles trapezoidal side gate structure is formed to reduce the peak electric field.

Benefits of technology

It achieves stable high threshold voltage and high on-current density, reduces gate leakage current, extends device life, simplifies fabrication process, and is suitable for mass production of large-area wafers.

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Abstract

The application relates to a HEMT device with an array side gate structure and a preparation method thereof, and belongs to the technical field of semiconductor devices. According to the technical scheme, a buffer layer, a channel layer and a barrier layer are sequentially grown on a substrate; a source electrode and a drain electrode are arranged above the barrier layer; and a gate electrode is arranged above the barrier layer and extends to the channel layer; the channel layer, the barrier layer and the gate metal located in the gate electrode area form an array side gate structure; the array side gate comprises a plurality of structures composed of the channel layer and the barrier layer, the longitudinal section of the structure is isosceles trapezoidal, and the outer angle of the side gate structure on one side of the channel layer is an obtuse-angled arc. The application has the beneficial effects that the shallow etching and deep etching of the channel are combined with the difference between the gate metal and the semiconductor work function to adjust the electron concentration of the channel, the threshold voltage and the output current of the device are effectively improved, and the side gate inclination alpha can be optimized to reduce the peak electric field, thereby effectively reducing the gate leakage.
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