A method for fabricating an SGT device

Abstract

The application provides an SGT device manufacturing method and relates to the technical field of semiconductors. First, a silicon wafer with a groove is provided, a field plate oxide layer is grown along the surface of the groove, a first polysilicon layer with a preset thickness is grown in the groove, the thickness of the first polysilicon layer is less than the depth of the groove, the field plate oxide layer above the first polysilicon layer is removed, a silicon dioxide layer is grown along the surface of the first polysilicon layer and the sidewall of the groove, the silicon dioxide layer on the sidewall is doped, then the silicon dioxide layer on the sidewall is etched, and the silicon dioxide layer on the surface of the first polysilicon layer is reserved; wherein the etching rate of the doped silicon dioxide layer is greater than the etching rate of the silicon dioxide layer on the surface of the first polysilicon layer, a gate oxide layer is manufactured along the sidewall of the groove, and finally, polysilicon is deposited in the groove to form a second polysilicon layer. The SGT device manufacturing method provided by the application has the advantages of simple process and lower cost.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a method for fabricating an SGT device. Background Technology

[0002] In the field of medium and low voltage devices with a withstand voltage of 60V and above, shielded gate trench (SGT) devices are widely used due to their low specific on-resistance and low gate-drain coupling capacitance. The gate structure of an SGT device includes a shielded polysilicon (SPS) and a polysilicon gate. The SPS, often referred to as source polysilicon, is formed within a trench. Depending on the arrangement of the SPS and the polysilicon gate within the trench, they are typically classified as either a top-bottom structure or a left-right structure. In a top-bottom structure, the SPS is located at the bottom of the trench, and the polysilicon gate is located at the top of the trench, with the polysilicon gate and the SPS arranged in a top-bottom or left-right relationship.

[0003] However, during the fabrication of the isolation gate, a layer of silicon nitride needs to be deposited as a mask, which must then be removed. Therefore, the current fabrication process of SGT devices is complex and the manufacturing cost is high. Summary of the Invention

[0004] The purpose of this application is to provide a method for fabricating SGT devices to solve the problems of complex fabrication processes and high manufacturing costs of SGT devices in the prior art.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0006] This application provides a method for fabricating an SGT device, the method comprising:

[0007] Provide a silicon wafer with trenches;

[0008] A field plate oxide layer is grown along the surface of the trench;

[0009] A first polysilicon layer of a predetermined thickness is grown within the trench, wherein the thickness of the first polysilicon layer is less than the depth of the trench.

[0010] Remove the field oxide layer located above the first polysilicon layer;

[0011] A silicon dioxide layer is grown along the surface of the first polycrystalline silicon layer and the sidewalls of the trench;

[0012] The silicon dioxide layer located on the sidewall is doped, but the silicon dioxide layer located on the surface of the first polycrystalline silicon layer is not doped;

[0013] The silicon dioxide layer located on the sidewall is etched, while the silicon dioxide layer located on the surface of the first polysilicon layer is retained; wherein the etching rate of the doped silicon dioxide layer is greater than the etching rate of the silicon dioxide layer located on the surface of the first polysilicon layer.

[0014] A gate oxide layer is formed along the sidewall of the trench;

[0015] Polycrystalline silicon is deposited along the trench to form a second polycrystalline silicon layer.

[0016] Optionally, the step of doping the silicon dioxide layer located on the sidewalls includes:

[0017] Boron or hydrogen ions are implanted into the silica layer located on the sidewall at a preset angle using ion implantation.

[0018] Optionally, the step of doping the silicon dioxide layer located on the sidewalls includes:

[0019] The silicon dioxide layer located on the sidewall is doped at a preset angle, wherein the preset angle satisfies the formula:

[0020] A = arctan(xya) / (z-2a)

[0021] Where A represents the preset angle, x represents the depth of the trench, y represents the thickness of the first polysilicon layer, z represents the width of the trench, and a represents the thickness of the silicon dioxide layer.

[0022] Optionally, the target thickness of the silicon dioxide layer is B, and the step of growing the silicon dioxide layer along the surface of the first polysilicon layer and the sidewall of the trench includes:

[0023] A silicon dioxide layer with a thickness greater than B is grown along the surface of the first polycrystalline silicon layer and the sidewall of the trench.

[0024] Optionally, the thickness of the grown silicon dioxide layer satisfies the formula:

[0025] C = 5B / 4

[0026] Where C represents the thickness of the grown silicon dioxide layer, and B represents the target thickness of the silicon dioxide layer.

[0027] Optionally, the step of doping the silicon dioxide layer located on the surface of the first polycrystalline silicon layer, but not doping the silicon dioxide layer on the sidewalls, includes:

[0028] The silicon dioxide layer on the surface of the first polycrystalline silicon layer is doped by ion implantation at absolute zero.

[0029] Optionally, the step of growing a first polysilicon layer of a predetermined thickness within the trench includes:

[0030] Polycrystalline silicon is deposited along the trench, wherein the surface of the polycrystalline silicon is higher than the mesa of the silicon wafer;

[0031] The polysilicon located in the trench is etched back, and a first polysilicon layer of a predetermined thickness is retained in the trench.

[0032] Optionally, the step of growing a silicon dioxide layer along the surface of the first polysilicon layer and the sidewalls of the trench includes:

[0033] A silicon dioxide layer of a predetermined thickness is deposited on the surface of the first polycrystalline silicon layer and the sidewalls of the trench through a thermal oxidation process.

[0034] Optionally, the thickness of the silicon dioxide layer doped on the sidewalls satisfies the formula:

[0035] D = a / cosA

[0036] Where D represents the thickness of the silicon dioxide layer doped on the sidewall, a represents the thickness of the silicon dioxide layer, and A represents the preset angle.

[0037] Optionally, the step of depositing polysilicon along the trench to form a second polysilicon layer includes:

[0038] Polysilicon is deposited along the trench to form a second polysilicon layer within the trench, wherein the surface of the second polysilicon is higher than the mesa of the silicon wafer;

[0039] The second polysilicon layer is polished so that its surface is flush with the mesa of the silicon wafer.

[0040] Remove the gate oxide layer located on the mesa of the silicon wafer.

[0041] Compared with the prior art, this application has the following beneficial effects:

[0042] This application provides a method for fabricating an SGT device. First, a silicon wafer with trenches is provided. Then, a field oxide layer is grown along the surface of the trenches. A first polysilicon layer of a predetermined thickness is grown in the trenches, wherein the thickness of the first polysilicon layer is less than the depth of the trenches. Next, the field oxide layer above the first polysilicon layer is removed. Then, a silicon dioxide layer is grown along the surface of the first polysilicon layer and the sidewalls of the trenches. Then, the silicon dioxide layer located on the sidewalls is doped. Then, the silicon dioxide layer located on the sidewalls is etched, while the silicon dioxide layer on the surface of the first polysilicon layer is retained. The etching rate of the doped silicon dioxide layer is greater than the etching rate of the silicon dioxide layer on the surface of the first polysilicon layer. Then, a gate oxide layer is fabricated along the sidewalls of the trenches. Finally, polysilicon is deposited in the trenches to form a second polysilicon layer. In this application, by doping the silicon dioxide layer located on the sidewall, the etching rate of the silicon dioxide layer on the sidewall is relatively fast. Therefore, when fabricating the isolation layer between the first polysilicon layer and the second polysilicon layer, the silicon dioxide layer can be directly etched. After the silicon dioxide layer on the sidewall is completely etched, a large amount of silicon dioxide layer remains at the bottom, which can then be used as an isolation layer. This reduces the complexity of the fabrication process and lowers the manufacturing cost.

[0043] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0044] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is an exemplary flowchart of an SGT device fabrication method provided in an embodiment of this application.

[0046] Figure 2 An exemplary flowchart of a sub-step of S102 provided in an embodiment of this application.

[0047] Figure 3 This is a cross-sectional schematic diagram corresponding to S1023 provided in the embodiments of this application.

[0048] Figure 4 This is another cross-sectional schematic diagram corresponding to S1023 provided in the embodiment of this application.

[0049] Figure 5 This is a cross-sectional schematic diagram corresponding to S104 provided in the embodiments of this application.

[0050] Figure 6 This is a cross-sectional schematic diagram corresponding to S1061 provided in the embodiments of this application.

[0051] Figure 7 This is a cross-sectional schematic diagram corresponding to S1062 provided in the embodiments of this application.

[0052] Figure 8 This is a cross-sectional schematic diagram corresponding to S108 provided in the embodiments of this application.

[0053] Figure 9 This is a cross-sectional schematic diagram corresponding to S110 provided in the embodiments of this application.

[0054] Figure 10 This is a cross-sectional schematic diagram corresponding to S112 provided in the embodiments of this application.

[0055] Figure 11 This is a cross-sectional schematic diagram corresponding to S114 provided in the embodiments of this application.

[0056] Figure 12 This is a cross-sectional schematic diagram corresponding to S116 provided in the embodiments of this application.

[0057] Figure 13 This is a cross-sectional schematic diagram corresponding to S118 provided in the embodiments of this application. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0059] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0060] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0061] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0062] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0063] The current fabrication process for SGT devices is generally as follows:

[0064] Silicon wafer photolithography trench window — dry etching trench — oxidation — trench filling with polysilicon — polysilicon back etching (retaining some polysilicon in the trench) — oxidation to form gate — silicon nitride deposition — bottom silicon nitride back etching — oxidation (retaining the corresponding oxide layer thickness according to different voltages) — wet removal of silicon nitride — further filling with polysilicon — removal of surface and trench protrusions of polysilicon by CMP (chemical mechanical polishing) to form gate.

[0065] As described in the background section, existing SGT device processes require the deposition of a silicon nitride layer as a mask, which must then be removed, resulting in complex processes and high costs.

[0066] In view of this, the present application provides a method for fabricating an SGT device by doping the silicon dioxide layer located on the sidewall after growing the silicon dioxide layer, thereby simplifying the fabrication process of the SGT device and reducing its manufacturing cost.

[0067] The following is an exemplary description of the SGT device fabrication method provided in this application:

[0068] As an optional implementation, please refer to Figure 1 The SGT device fabrication method provided in this application includes:

[0069] S102 provides a silicon wafer with trenches.

[0070] S104, a field plate oxide layer is grown along the surface of the trench.

[0071] S106, a first polysilicon layer of a predetermined thickness is grown in the trench, wherein the thickness of the first polysilicon layer is less than the depth of the trench.

[0072] S108, remove the field oxide layer located above the first polysilicon layer.

[0073] S110, a silicon dioxide layer is grown along the surface of the first polysilicon layer and the sidewalls of the trench.

[0074] S112 is a silicon dioxide layer doped on the sidewall.

[0075] S114, the silicon dioxide layer located on the sidewall is etched, and the silicon dioxide layer located on the surface of the first polysilicon layer is retained; wherein, the etching rate of the doped silicon dioxide layer is greater than the etching rate of the silicon dioxide layer located on the surface of the first polysilicon layer.

[0076] S116, fabricate the gate oxide layer along the sidewall of the trench.

[0077] S118, polysilicon is deposited along the trench to form a second polysilicon layer.

[0078] The SGT device fabrication method provided in this application damages the silicon dioxide layer located on the sidewalls by doping it. Since the etching rate of the oxide layer in the damaged area is much higher than the wet etching rate of the oxide layer in the undamaged area,

[0079] Therefore, when the silicon dioxide layer on the sidewall is completely etched, the silicon dioxide layer on the surface of the first polysilicon layer is not actually completely etched. It can serve as an isolation layer between the first and second polysilicon layers, avoiding the need to deposit silicon nitride as a mask, simplifying the process and saving costs.

[0080] As an optional implementation, please refer to Figure 2 Step S102 includes:

[0081] S1021 provides a silicon wafer;

[0082] OS1022, fabricate a mask layer along the surface of the silicon wafer and pattern the mask layer;

[0083] S1023, based on a patterned mask layer, etches the silicon wafer and removes the mask layer to form trenches on the silicon wafer.

[0084] The silicon wafer described in this application can be a doped silicon wafer, for example, an N-type doped silicon wafer or a P-type doped silicon wafer, without limitation. Furthermore, in one implementation, the silicon wafer can be formed by growing an epitaxial layer on a substrate. Of course, the substrate and the epitaxial layer can also be doped accordingly; for example, both the substrate and the epitaxial layer can be N-type.

[0085] When trenches need to be fabricated on a silicon wafer, a mask can be used. For example, photoresist can be used as a mask. First, photoresist is coated on the surface of the silicon wafer. Then, the mask layer is patterned by spin coating, exposure, and development. That is, multiple windows are created on the mask layer. The zero windows expose the surface of the silicon wafer, while the remaining areas are covered with photoresist on the silicon wafer.

[0086] Next, the silicon wafer can be etched based on the patterned mask layer to create the trench structure, as shown below. Figure 3 As shown, this application does not limit the etching process. For example, after dry etching to create trenches, interference etching (which involves passing gases such as carbon tetrafluoride and chlorine through the silicon wafer and etching under plasma action) can be used to etch trenches of 1-20 μm in areas without photoresist protection, i.e., in the photoresist window area. The number of trenches can be determined according to actual needs and is not limited here.

[0087] After etching the trenches, the mask layer can be removed to form trenches on the silicon wafer, as shown in the structure. Figure 4 As shown. One method for removing the mask layer is by etching with sulfuric acid and hydrogen peroxide to remove the photoresist.

[0088] After the trench is fabricated and the mask layer is removed, a field oxide layer can be grown along the surface of the trench. Specifically, a field oxide layer of 200-2000 Å can be grown under conditions of 1000-1200 degrees Celsius and 2-10 L of oxygen. Since this application uses silicon wafers, the field oxide layer is fabricated by oxidizing the silicon wafer surface to form silicon dioxide. The structure after growing the field oxide layer is as follows... Figure 5 As shown.

[0089] Depend on Figure 5 It is known that during the growth of the oxide layer on the field plate, an oxide layer will be formed on the mesa of the silicon wafer on the surface of the trench.

[0090] After the oxide layer of the growth field plate is grown, a first polysilicon layer of a predetermined thickness can be grown along the trench, wherein the first polysilicon layer is the shielding polysilicon layer.

[0091] As one implementation, S106 includes:

[0092] S1061, polycrystalline silicon is deposited along the trench, wherein the surface of the polycrystalline silicon is higher than the mesa of the silicon wafer.

[0093] S1062, the polysilicon located in the trench is etched back, and a first polysilicon layer of a preset thickness is retained in the trench.

[0094] like Figure 6 As shown, polycrystalline silicon is first deposited in the trench, for example, by LPCVD, to ensure complete filling of the trench. To guarantee complete filling of the trench with polycrystalline silicon, the surface of the polycrystalline silicon in this application is higher than the mesa of the silicon wafer. For example, the surface of the polycrystalline silicon extends 5000 to 8000 Å above the surface of the silicon wafer.

[0095] Then, the polysilicon in the trench is etched back, and the first polysilicon layer is retained in the trench, as shown in the structure. Figure 7 For example, the polysilicon on the surface can be removed by plasma etching, while the polysilicon in the trench is etched to a certain thickness, which is less than the depth of the trench, for example, the thickness is 4000-10000 Å.

[0096] Next, please refer to Figure 8 Excess field oxide layer can be removed, for example, by wet etching. It should be noted that the excess field oxide layer mentioned in this application refers to the field oxide layer located on the mesa of the silicon wafer and the trench sidewalls above the first polysilicon layer.

[0097] Following this, the isolation layer between the shielding polysilicon and the polysilicon gate is fabricated. First, a silicon dioxide layer is grown along the surface of the first polysilicon layer and the sidewalls of the trench; naturally, a silicon dioxide layer is also grown on the mesa of the silicon wafer, such as... Figure 9 As shown.

[0098] Optionally, this application employs thermal oxidation to deposit a silicon dioxide layer of the same thickness on the surface and trench sidewalls. Wherein, for example... Figure 9 As shown, the silica layer is divided into an area below the dashed line AA and an area above the dashed line AA. The silica layer below the dashed line AA serves as an isolation layer, while the silica layer above the dashed line AA includes the silica layers located on the trench sidewalls and the mesa. Furthermore, the thickness of the silica layer is the same at each location; for example, the thickness can be 2000–10000 Å, and this thickness can be selected according to actual needs, and is not limited here.

[0099] Understandably, the silica layer located above the dashed line AA is actually a sacrificial layer and needs to be removed, while the silica layer located below the dashed line AA needs to be retained.

[0100] Based on this, this application achieves the difference in etching rate by doping the silicon dioxide layer located on the sidewall, while not doping the silicon dioxide layer in the region below the dashed line AA.

[0101] In one implementation, boron or hydrogen ions can be implanted into the silicon dioxide layer located on the sidewall at a preset angle using ion implantation, thereby achieving damage to the silicon dioxide layer located on the sidewall. For example... Figure 10 As shown. The silicon dioxide layer located on the sidewall can be doped at a preset angle, wherein the preset angle satisfies the formula:

[0102] A = arctan(xya) / (z-2a)

[0103] Where A represents the preset angle, x represents the depth of the trench, y represents the thickness of the first polysilicon layer, z represents the width of the trench, and a represents the thickness of the silicon dioxide layer.

[0104] Of course, when doping the silicon dioxide layer located on the sidewall, the silicon dioxide layer on the mesa of the silicon wafer is also actually doped.

[0105] Furthermore, it should be noted that in this application, the trench is rectangular in shape, comprising four sides, therefore requiring doping on all four different sides. Figure 10 In the process, the ion implantation direction is from right to left, which dopes the silicon dioxide layer on the left sidewall. After the silicon dioxide layer on the left side is doped, the ion implantation direction is changed to from left to right, but the implantation angle remains unchanged, which dopes the silicon dioxide layer on the right sidewall, and so on.

[0106] Meanwhile, because ion implantation is performed at a certain angle, the thickness of the doped silicon dioxide layer located on the sidewall satisfies the formula:

[0107] D = a / cosA

[0108] Where D represents the thickness of the silicon dioxide layer doped on the sidewall, a represents the thickness of the silicon dioxide layer, and A represents the preset angle.

[0109] Furthermore, since the bottom silicon dioxide layer is also etched simultaneously when the sidewall silicon dioxide layer is etched, albeit at a relatively low etching rate, the amount of etching is thus smaller. Therefore, step S110 includes:

[0110] A silicon dioxide layer with a thickness greater than B is grown along the surface of the first polysilicon layer and the sidewalls of the trench.

[0111] Studies have shown that the corrosion rate of the oxide layer in the damaged area is 5 times or more than that of the oxide layer in the undamaged area obtained by wet corrosion. Based on this, the thickness of the grown silica layer satisfies the formula:

[0112] C = 5B / 4

[0113] Where C represents the thickness of the grown silicon dioxide layer, and B represents the target thickness of the silicon dioxide layer.

[0114] For example, if the required thickness of the isolation layer of the SGT device is 6000 Å, then the required thickness of the silicon dioxide layer is 7500 Å. Then, the silicon dioxide layer located on the sidewall is etched, and the silicon dioxide layer located on the surface of the first polysilicon layer is retained.

[0115] For example, when the thickness of the silicon dioxide layer on the sidewall is 7500 Å, if this silicon dioxide layer is completely etched, the silicon dioxide layer on the surface of the first polysilicon layer will also be partially etched away. Taking an etching rate of 5:1 as an example, the thickness of the silicon dioxide layer on the surface of the first polysilicon layer will be etched away by 1500 Å, and the remaining silicon dioxide layer will just reach the target thickness of 6000 Å. The structure after etching is as follows. Figure 11 As shown.

[0116] Next, please refer to the product voltage requirements. Figure 12 A gate oxide layer is grown, which is typically thin. Then, polysilicon is deposited along the trench to form a second polysilicon layer.

[0117] The steps in S118 include:

[0118] S1181, depositing polycrystalline silicon along the trench to form a second polycrystalline silicon layer in the trench, wherein the surface of the second polycrystalline silicon is higher than the mesa of the silicon wafer.

[0119] S1182, the second polysilicon is ground so that the surface of the second polysilicon layer is flush with the mesa of the silicon wafer.

[0120] S1183 removes the gate oxide layer located on the mesa of the silicon wafer.

[0121] For example, a polysilicon layer can be deposited in the trench using LPCVD, and a second polysilicon layer can be formed using CMP. Then, the surface gate oxide layer can be removed by etching the oxide layer, thus completing the fabrication of the SGT device. Figure 13 As shown.

[0122] In another implementation, the silicon dioxide layer on the surface of the first polysilicon layer can be doped, but the silicon dioxide layer on the sidewalls can not be doped. The doping element makes the etching rate of the silicon dioxide layer on the surface of the first polysilicon layer less than the etching rate of the silicon dioxide layer on the sidewalls, which can also achieve the purpose of removing the silicon dioxide layer on the sidewalls.

[0123] As an alternative implementation, the silicon dioxide layer on the surface of the first polysilicon layer can be doped by ion implantation at absolute zero.

[0124] In summary, this application provides a method for fabricating an SGT device. First, a silicon wafer with trenches is provided. Then, a field oxide layer is grown along the surface of the trenches. A first polysilicon layer of a predetermined thickness is grown within the trenches, wherein the thickness of the first polysilicon layer is less than the depth of the trenches. Next, the field oxide layer above the first polysilicon layer is removed. Then, a silicon dioxide layer is grown along the surface of the first polysilicon layer and the sidewalls of the trenches. The silicon dioxide layer on the sidewalls is then doped. The silicon dioxide layer on the sidewalls is then etched, while retaining the silicon dioxide layer on the surface of the first polysilicon layer. The etching rate of the doped silicon dioxide layer is greater than the etching rate of the silicon dioxide layer on the surface of the first polysilicon layer. A gate oxide layer is then fabricated along the sidewalls of the trenches. Finally, polysilicon is deposited within the trenches to form a second polysilicon layer. In this application, by doping the silicon dioxide layer located on the sidewall, the etching rate of the silicon dioxide layer on the sidewall is relatively fast. Therefore, when fabricating the isolation layer between the first polysilicon layer and the second polysilicon layer, the silicon dioxide layer can be directly etched. After the silicon dioxide layer on the sidewall is completely etched, a large amount of silicon dioxide layer remains at the bottom, which can then be used as an isolation layer. This reduces the complexity of the fabrication process and lowers the manufacturing cost.

[0125] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0126] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for fabricating an SGT device, characterized in that, The method includes: Provide a silicon wafer with trenches; A field plate oxide layer is grown along the surface of the trench; A first polysilicon layer of a predetermined thickness is grown within the trench, wherein the thickness of the first polysilicon layer is less than the depth of the trench; Remove the field oxide layer located above the first polysilicon layer; A silicon dioxide layer is grown along the surface of the first polycrystalline silicon layer and the sidewalls of the trench; Boron or hydrogen ions are implanted into the silicon dioxide layer located on the sidewall at a preset angle by ion implantation, so as to achieve doping of the silicon dioxide layer located on the sidewall, while not doping the silicon dioxide layer located on the surface of the first polycrystalline silicon layer. The silicon dioxide layer located on the sidewall is etched, while the silicon dioxide layer located on the surface of the first polysilicon layer is retained; wherein the etching rate of the doped silicon dioxide layer is greater than the etching rate of the silicon dioxide layer located on the surface of the first polysilicon layer. A gate oxide layer is formed along the sidewall of the trench; Polycrystalline silicon is deposited along the trench to form a second polycrystalline silicon layer; The step of doping the silicon dioxide layer located on the sidewall includes: The silicon dioxide layer located on the sidewall is doped at a preset angle, wherein the preset angle satisfies the formula: A = arctan(xya) / (z - 2a) Where A represents the preset angle, x represents the depth of the trench, y represents the thickness of the first polysilicon layer, z represents the width of the trench, and a represents the thickness of the silicon dioxide layer.

2. The method for fabricating an SGT device as described in claim 1, characterized in that, The target thickness of the silicon dioxide layer is B. The step of growing the silicon dioxide layer along the surface of the first polysilicon layer and the sidewall of the trench includes: A silicon dioxide layer with a thickness greater than B is grown along the surface of the first polycrystalline silicon layer and the sidewall of the trench.

3. The method for fabricating an SGT device as described in claim 2, characterized in that, The thickness of the grown silica layer satisfies the formula: C=5B / 4 Where C represents the thickness of the grown silicon dioxide layer, and B represents the target thickness of the silicon dioxide layer.

4. The method for fabricating an SGT device as described in claim 1, characterized in that, The step of providing a trenched silicon wafer includes: Provide a silicon wafer; A mask layer is fabricated along the surface of the silicon wafer, and the mask layer is patterned. The silicon wafer is etched based on the patterned mask layer, and the mask layer is removed to form trenches on the silicon wafer.

5. The method for fabricating an SGT device as described in claim 1, characterized in that, The step of growing a first polysilicon layer of a predetermined thickness in the trench includes: Polycrystalline silicon is deposited along the trench, wherein the surface of the polycrystalline silicon is higher than the mesa of the silicon wafer; The polysilicon located in the trench is etched back, and a first polysilicon layer of a predetermined thickness is retained in the trench.

6. The method for fabricating an SGT device as described in claim 1, characterized in that, The step of growing a silicon dioxide layer along the surface of the first polysilicon layer and the sidewalls of the trench includes: A silicon dioxide layer of a predetermined thickness is deposited on the surface of the first polycrystalline silicon layer and the sidewalls of the trench through a thermal oxidation process.

7. The method for fabricating an SGT device as described in claim 1, characterized in that, The thickness of the doped silicon dioxide layer located on the sidewalls satisfies the formula: D=a / cosA Where D represents the thickness of the silicon dioxide layer doped on the sidewall, a represents the thickness of the silicon dioxide layer, and A represents the preset angle.

8. The method for fabricating an SGT device as described in claim 1, characterized in that, The step of depositing polysilicon along the trench to form a second polysilicon layer includes: Polysilicon is deposited along the trench to form a second polysilicon layer within the trench, wherein the surface of the second polysilicon is higher than the mesa of the silicon wafer; The second polysilicon layer is polished so that its surface is flush with the mesa of the silicon wafer. Remove the gate oxide layer located on the mesa of the silicon wafer.

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