A silicon carbide device and method of fabrication thereof

Abstract

The application discloses a silicon carbide device and a preparation method thereof, which comprises a metal drain from bottom to top, an N+ substrate, an N- epitaxial layer, a P-type body region, an N+ source region and a metal source. An N-type current expansion layer is arranged in the middle of the P-type body region on both sides, a P-type doped region is arranged on the surface of the cell source, a heterojunction diode is arranged in the gate on both sides and the P-type doped region, and a gate oxide film is arranged on the surface of the gate. The SiCMOSFET structure has better static quality factor and dynamic quality factor compared with the traditional MOSFET structure, specifically, the structure has lower on-resistance and lower reverse transmission capacitance, the third quadrant conduction characteristic and reverse recovery characteristic of the device are improved, the problems of bipolar degradation effect and excessively high gate oxide electric field are solved, and the device has better reliability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and in particular relates to a silicon carbide device and its fabrication method. Background Technology

[0002] Power semiconductor devices possess advantages such as high drive current, high breakdown voltage, high speed, low power consumption, and high output power, enabling power control and conversion across various ranges. In recent years, with the continuous development of power electronic systems, higher demands have been placed on power devices within these systems. Silicon (Si)-based power electronic devices, due to material limitations, can no longer meet the requirements of system applications. Third-generation semiconductors, such as SiC, feature a wide bandgap (approximately three times that of Si), a high critical breakdown electric field (approximately ten times that of Si), and a high saturation drift rate, making them suitable for high-temperature, high-voltage, and high-frequency operation. This significantly improves system energy conversion efficiency and system reliability. However, due to its wide bandgap, SiC MOSFETs suffer from bipolar degradation during use, which is exacerbated when a body diode is used as a freewheeling diode, reducing device reliability. Therefore, in most power electronic systems, an anti-parallel Schottky diode is typically required as a freewheeling diode. However, this method still increases system cost and introduces additional stray inductance into the circuit due to component interconnection, reducing the system's dynamic performance.

[0003] Planar MOSFETs are more widely used in electronic power systems than trench MOSFETs, and typically have lower reverse transfer capacitance, gate-drain charge, and switching losses. Separating the gate can further reduce the coupling area between the gate and drain, thus reducing reverse transfer capacitance and gate-drain charge. However, this usually increases the on-resistance due to the reduced current channel length, lowering the device's static quality factor. A common solution is to use a high-concentration N-type current spreading layer to reduce on-resistance. However, a high-concentration current spreading layer often exposes the gate oxide layer to a high electric field, potentially causing it to break down before the bulk region, significantly impacting device reliability. Therefore, researchers use various gate oxide reinforcement structures to mitigate electric field concentration in the gate oxide layer, thereby improving device performance. Summary of the Invention

[0004] The purpose of this invention is to provide a silicon carbide device and its fabrication method to solve the problems existing in the prior art. Compared with the traditional MOSFET structure, it has a better static quality factor and dynamic quality factor, and the device's third-quadrant operating performance is improved, while the gate oxide electric field is also effectively reduced.

[0005] To achieve the above objectives, the present invention provides a low-power, high-reliability SiC MOSFET device, comprising:

[0006] Metal drain, N+ substrate, N- epitaxial layer;

[0007] The N+ substrate is formed on the metal drain electrode, and the metal drain electrode has a bottom-up structure.

[0008] The N- epitaxial layer is formed on the N+ substrate;

[0009] The N-epitaxial layer includes an N-drift region, a P-type body region, an N-type current spreading layer, and a P-type doped region; the P-type body region is formed on both sides of the upper end of the N-epitaxial layer, the N-type current spreading layer is formed between the P-type body regions, and the P-type doped region is formed on the cell source surface;

[0010] The N-drift region is formed below the P-type body region, the N-type current extension layer, and the P-type doped region.

[0011] Optionally, the P-type body region is provided with an N+ source region, a metal source electrode, and a gate electrode. P+ polysilicon is disposed between the gate electrode and the P-type doped region, and a gate oxide film is disposed on the surface of the gate electrode.

[0012] Optionally, the thickness of the P-type doped region is 1.2 μm, the width can be 0.8 μm to 1 μm, and the doping concentration is 1 × 10⁻⁶. 18 cm -3 .

[0013] Optionally, the bottom height of the P-type doped region is between the bottom height of the P+ polysilicon and the height of the P-type body region.

[0014] Optionally, the concentration of the N-type current spreading layer is limited to a value higher than the concentration of the N-drift region.

[0015] A method for fabricating a silicon carbide device is also provided, characterized in that,

[0016] Step S1: Prepare an N+ substrate for a semiconductor device, and sequentially form an N- drift region and an N-type current spreading layer through epitaxy;

[0017] Step S2: Form a P-type doped region using ion implantation technology;

[0018] Step S3: Trenches are formed on both sides of the cell using etching technology, and P-body region and N+ source region are formed in the trenches using ion implantation technology;

[0019] Step S4: Use etching technology to etch away the remaining N-type doped regions on the left and right sides of the P-type doped region;

[0020] Step S5: Deposit P+ polysilicon on both sides of the P-type doped region;

[0021] Step S6: Etch back P+ polysilicon to form polysilicon sidewalls;

[0022] Step S7: A gate oxide film is formed under the gate using a thermal oxidation process, polysilicon is deposited on the gate oxide film to form the gate, and a thick oxide is deposited outside the gate.

[0023] Step S8: A source region is fabricated on the surface of the N+ source region, the P- body region, the P-type doped region, and the P+ polysilicon, and a drain region is fabricated under the N+ substrate.

[0024] The technical effects of this invention are as follows:

[0025] This invention proposes a low-power, high-reliability SiC MOSFET device. Its main features include replacing the traditional gate with a discrete gate, forming a P-type doped region on the cell surface through ion implantation, and depositing P+ polysilicon and N-type SiC between the P-type doped region and the gate to form a heterojunction diode, improving third-quadrant conduction and reverse recovery characteristics. The bottom of the P+ polysilicon is at the same height as the bottom of the gate oxide to avoid excessively high gate oxide electric fields caused by curvature in the off-state. A high-concentration current spreading layer improves the device's static quality factor, specifically manifested in lower on-resistance, effectively improving the device's forward conduction characteristics. When the device is in the off-state, a peak electric field is introduced at the bottom of the P-type doped region, which reduces the high electric fields at the gate oxide and P+ polysilicon caused by the high-concentration current spreading layer, preventing dynamic degradation. The reduced drain coupling area improves the device's dynamic quality factor, specifically manifested in lower reverse transfer capacitance and gate-drain charge. The performance of the device has been effectively improved in all aspects. The bipolar degradation effect and the high electric field problem of the gate oxide have been effectively solved, and the reliability of the device has been effectively improved. Attached Figure Description

[0026] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0027] Figure 1 This is a schematic diagram of a conventional planar MOSFET device structure in an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of the cell structure of a low-power, high-reliability SiC MOSFET device in an embodiment of the present invention.

[0029] Figure 3This is a schematic diagram of the fabrication process of a low-power, high-reliability SiC MOSFET device in an embodiment of the present invention. In this diagram, (a) shows the formation of the N+ substrate, N- drift region, and N-type current extension layer; (b) shows the formation of the P-type doped region; (c) shows the formation of the P-body region and N+ source region; (d) shows the etching of the remaining N-type doped region on the left and right sides of the P-type doped region; (e) shows the deposition of P+ polysilicon on both sides of the P-type doped region; (f) shows the effect of etching excess P+ polysilicon; (g) shows the effect of gate processing; and (h) shows the effect of fabricating the drain region.

[0030] Figure 4 This is a comparison of the forward conduction characteristic curve and breakdown voltage curve of the low-power, high-reliability SiC MOSFET device in the embodiments of the present invention with those of a traditional planar MOSFET structure.

[0031] Figure 5 This is a comparison of the reverse transfer capacitance (gate-drain capacitance) curves of the low-power, high-reliability SiC MOSFET device in this embodiment of the invention and the traditional planar MOSFET structure.

[0032] Figure 6 This is a comparison of the gate charge characteristic curves of the low-power, high-reliability SiC MOSFET device in the embodiments of the present invention and the traditional planar MOSFET structure.

[0033] Figure 7 This is a comparison of the third quadrant IV curves of the low-power, high-reliability SiC MOSFET device in this embodiment of the invention with those of a traditional planar MOSFET structure.

[0034] Figure 8 This is a comparison of the reverse recovery characteristic curves of the low-power, high-reliability SiC MOSFET device and the traditional planar MOSFET structure in the embodiments of the present invention. Detailed Implementation

[0035] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0036] Example 1

[0037] This embodiment provides a silicon carbide device and its fabrication method, comprising a metal drain, an N+ substrate, and an N- epitaxial layer from bottom to top. A P-type body region is disposed on the upper end of the N-epitaxial layer, an N-type current spreading layer is disposed between the two P-type body regions, an N+ source region, a metal source, and a gate are disposed on the P-body region. The low-power, high-reliability SiC MOSFET structure further includes a P-type doped region disposed on the surface of the cell source, P+ polysilicon disposed on both sides of the gate and in the P-type doped region to form a heterojunction contact with the N-type SiC, and a gate oxide film disposed on the gate surface.

[0038] Preferably, the thickness of the P-type doped region is 1.2 μm, the width can be 0.8 μm to 1 μm, and the doping concentration is 1 × 10⁻⁶. 18 cm -3 .

[0039] Preferably, the bottom height of the P-type doped region is greater than that of the bottom of the P+ polysilicon, and the bottom height of the P-type doped region is less than that of the bottom of the P-type base region, in order to avoid premature device breakdown caused by electric field concentration.

[0040] Preferably, the bottom of the P+ polysilicon is at the same height as the bottom of the gate to improve the problem of excessive gate oxide electric field caused by curvature.

[0041] Preferably, the concentration of the N-type current spreading layer needs to be greater than that of the N-drift region, and to avoid excessively high electric fields in the P-type doped region, the concentration of the N-type current spreading layer should not be too high. The preferred concentration of the N-type current spreading layer is 6 × 10⁻⁶. 16 cm -3 .

[0042] A method for fabricating a low-power, high-reliability SiC MOSFET device is also provided, comprising:

[0043] Step S1: Prepare the N+ substrate region of the semiconductor device, and sequentially form the N- drift region and the N-type current spreading layer through epitaxy;

[0044] Step S2: Form a P-type doped region using ion implantation technology;

[0045] Step S3: Use etching technology to form trenches on both sides of the cell, and use ion implantation technology to form P-body regions and N+ source regions in the trenches respectively;

[0046] Step S4: The remaining N-type doped regions on the left and right sides of the P-type doped region are etched away again using etching technology. Since the width of the P-type doped region can be 0.8μm to 1μm, the process difficulty can be reduced.

[0047] Step S5: Deposit P+ polycrystalline silicon;

[0048] Step S6: Remove excess P+ polysilicon using back etching technology. The thickness of the P+ polysilicon should be slightly greater than or equal to the thickness of the P-type doped region.

[0049] Step S7: A gate oxide film is formed using a thermal oxidation process, and polysilicon is deposited on it to form the gate, followed by a thick oxide deposition on its exterior.

[0050] Step S8: Fabricate source regions in the N+ source region, P- body region, P-type doped region and P+ polysilicon surface, and fabricate drain regions under the N+ substrate.

[0051] Example 2

[0052] This embodiment provides a silicon carbide device and its fabrication method, including:

[0053] Reference Figure 1 , 2 As shown, this invention provides a low-power, high-reliability SiC MOSFET device suitable for energy conversion in power electronic systems. Figure 1 It is a traditional MOSFET structure, which includes an N+ substrate, an N- drift region, an N-type current extension layer, a P- body region, and an N+ source region stacked sequentially from bottom to top. Figure 2 and Figure 1 The difference lies in the fact that its gate region uses a separate gate and is at the same height as the integrated heterojunction, and is shielded by the electric field of the P-type doped region formed by ion implantation. At the same time, a high-concentration current spreading layer is set on both sides of the cell. The P-type doped region avoids the high electric field of the gate oxide and P+ polysilicon surface under the action of the high-concentration current spreading layer.

[0054] The fabrication process of the low-power, high-reliability SiC MOSFET device is as follows: Figure 3 As shown, it includes the following steps:

[0055] Step S1: Fabricate the N+ substrate region of the semiconductor device, and sequentially form an N-drift region and an N-type current spreading layer through epitaxy. The concentrations of the N-drift region and the N-type current spreading layer are 8×10¹⁵ cm⁻³ and 6×10¹⁶ cm⁻³, respectively. Figure 3 As shown in (a);

[0056] Step S2: A P-type doped region is formed using ion implantation technology. The P-type doped region has a width of 0.8 μm to 1 μm, a thickness of 1.2 μm, and a concentration of 1 × 10¹⁸ cm⁻³. Figure 3 As shown in (b);

[0057] Step S3: Trenches are formed on both sides of the cell using etching technology, and P-body regions and N+ source regions are formed in the trenches using ion implantation technology. The width of the single-sided P-body region is 2.5 μm. Figure 3 As shown in (c);

[0058] Step S4: The remaining N-type doped regions on both sides of the P-type doped region are etched away again using etching technology. Since the width of the P-type doped region can be 0.8 μm to 1 μm, the process difficulty can be reduced. Figure 3 As shown in (d);

[0059] Step S5: Deposit P+ polycrystalline silicon, such as Figure 3 As shown in (e);

[0060] Step S6: Remove excess P+ polysilicon using an etch-back technique, such as... Figure 3 As shown in (f);

[0061] Step S7: A gate oxide film is formed using a thermal oxidation process, and polysilicon is deposited on it to form the gate. Then, a thick oxide layer is deposited on its exterior, such as... Figure 3 (g) is shown;

[0062] Step S8: Fabricate the source region in the N+ source region, P- body region, P-type doped region, and P+ polysilicon surface; fabricate the drain region under the N+ substrate to complete the fabrication of the integrated heterojunction diode and the discrete gate MOSFET. Figure 3 As shown in (h).

[0063] The embodiments of this invention are based on Silvaco TCAD software, and the following are... Figure 1-2 The two device structures were compared and analyzed through simulation.

[0064] like Figure 4 The figure shows the static conduction characteristics of the two device structures obtained from simulation. From... Figure 4 As can be seen, compared with the traditional planar MOSFET structure, the low-power, high-reliability SiC MOSFET device of this invention can achieve a smaller on-resistance and a similar breakdown voltage, which can improve the static quality factor of the device.

[0065] like Figure 5 As shown in the figure, the reverse transfer capacitance (gate-drain capacitance) of the two structures obtained from the simulation varies with the drain voltage. A smaller gate-drain capacitance can reduce the time of Miller voltage during switching, thereby reducing switching time and switching losses. It can be seen from the figure that the low-power, high-reliability SiC MOSFET device of this invention has a lower reverse transfer capacitance. Therefore, the structure of this embodiment has greater advantages in high-frequency applications.

[0066] like Figure 6As shown in the simulation, the gate charge characteristics of the two device structures can be seen. It can be seen that, compared with the traditional planar MOSFET structure, the proposed low-power and high-reliability SiC MOSFET device has a lower Miller plateau time and a significantly reduced gate-drain charge Qgd, indicating that the device has lower switching losses.

[0067] like Figure 7 As shown in the simulation comparison of the third quadrant IV curves of the two device structures, it can be seen that the proposed low-power, high-reliability SiC MOSFET device has a lower third quadrant turn-on voltage compared to the traditional planar MOSFET structure. Since the heterojunction is a majority carrier device that is similar to a Schottky diode, the potential barrier height for electrons is much lower than that for holes, which can suppress the conduction of the parasitic body diode in the SiC MOSFET, avoid bipolar degradation of the device, and improve the reliability of the device.

[0068] like Figure 8 As shown in the comparison of the reverse recovery characteristic curves of the two device structures obtained from the simulation, it can be seen that, compared with the traditional planar MOSFET structure, the proposed low-power and high-reliability SiC MOSFET device has a shorter reverse recovery time, less reverse recovery charge, and a lower reverse recovery current peak. This means that the embodiment proposed in this invention has better reverse recovery characteristics and reduces energy loss during device switching.

[0069] In the description of this invention, it should be understood that the terms "longitudinal", "lateral", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "inner", and "outer" are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this invention, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0070] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A silicon carbide device, characterized in that, include: Metal drain, N+ substrate, N- epitaxial layer; The N+ substrate is formed on the metal drain electrode, and the metal drain electrode has a bottom-up structure. The N- epitaxial layer is formed on the N+ substrate; The N-epitaxial layer includes an N-drift region, a P-type body region, an N-type current spreading layer, and a P-type doped region; the P-type body region is formed on both sides of the upper end of the N-epitaxial layer, the N-type current spreading layer is formed between the P-type body regions, and the P-type doped region is formed on the cell source surface; The N-drift region is formed below the P-type body region, the N-type current spreading layer, and the P-type doped region; The P-type body region is provided with an N+ source region, a metal source electrode, and a gate electrode. P+ polysilicon is disposed between the gate electrode and the P-type doped region, and a gate oxide film is disposed on the surface of the gate electrode. The thickness of the P-type doped region is 1.2 μm, the width can be 0.8 μm to 1 μm, and the doping concentration is 1 × 10⁻⁶. 18 cm -3 ; The bottom height of the P-type doped region is between the bottom height of the P+ polysilicon and the height of the P-type bulk region; The concentration of the N-type current spreading layer is set to a limit value, which is higher than the concentration of the N-drift region; A method for fabricating a silicon carbide device, comprising: Step S1: Prepare an N+ substrate for a semiconductor device, and sequentially form an N- drift region and an N-type current spreading layer through epitaxy; Step S2: Form a P-type doped region using ion implantation technology; Step S3: Trenches are formed on both sides of the cell using etching technology, and P-body region and N+ source region are formed in the trenches using ion implantation technology; Step S4: Use etching technology to etch away the remaining N-type doped regions on the left and right sides of the P-type doped region; Step S5: Deposit P+ polysilicon on both sides of the P-type doped region; Step S6: Etch back P+ polysilicon to form polysilicon sidewalls; Step S7: A gate oxide film is formed under the gate using a thermal oxidation process, polysilicon is deposited on the gate oxide film to form the gate, and a thick oxide is deposited outside the gate. Step S8: A source region is fabricated on the surface of the N+ source region, the P- body region, the P-type doped region, and the P+ polysilicon, and a drain region is fabricated under the N+ substrate.

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