A boost-buck power converter and conversion method supporting brown-out delay

Abstract

The application discloses a kind of support brown-out delay's buck-boost power converter and conversion method, converter includes: input protection module, clamping energy storage module and buck-boost control module;The input protection module is used to provide first voltage for the clamping energy storage module and the buck-boost control module according to surge suppression circuit;The clamping energy storage module is used to when power supply, according to the clamping circuit and the first voltage, the energy storage capacitor is energized;And for the buck-boost control module provides second voltage according to the energy storage capacitor when power supply brown-out;The buck-boost control module is according to the first control chip, the switching control of the buck-boost circuit is carried out, adjusts the first voltage or the second voltage, and outputs preset output voltage.Using the present application can guarantee wide input voltage and brown-out delay function at the same time, prevent energy storage capacitor damage in power converter.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a buck-boost power converter and conversion method that supports power-down delay. Background Technology

[0002] Electronic devices are generally driven by power supplies, and different devices have different requirements for power supply performance parameters. With the development of science and technology and the diversification and refinement of the electronics industry, power supply systems have higher requirements for energy consumption standards, and need to have wider input ranges, surge protection, and delay functions. For wide voltage input ranges, the voltage is generally regulated by a chip, but the chip is driven by a power supply. When the power supply fails, an energy storage capacitor is needed to provide power to the chip and perform a delay. Although surge protection design can protect the circuit, a wide input voltage range may still prevent the energy storage capacitor from operating under normal voltage conditions, thus leading to damage. Summary of the Invention

[0003] This invention provides a buck-boost power converter and conversion method that support power-down delay, in order to solve the technical problem of preventing damage to the energy storage capacitor in the power converter while ensuring wide input voltage and power-down delay functions.

[0004] To address the aforementioned technical problems, this invention provides a buck-boost power converter that supports power-down delay, comprising: an input protection module, a clamping energy storage module, and a buck-boost control module.

[0005] The input protection module has a first input terminal connected to the positive terminal of the power supply, a second input terminal connected to the negative terminal of the power supply, and an output terminal connected to the input terminals of the clamping energy storage module and the buck-boost control module. The input protection module includes a surge suppression circuit. The clamping energy storage module includes a clamping circuit and an energy storage capacitor. The buck-boost control module includes a first control chip and a buck-boost circuit. The input pins of the first control chip are connected to the input terminals of the buck-boost control module.

[0006] The input protection module is used to provide a first voltage within the required range for the clamping energy storage module and the buck-boost control module according to the surge suppression circuit;

[0007] The clamping energy storage module is used to charge the energy storage capacitor according to the clamping circuit and the first voltage when the power supply is on; and to provide a second voltage to the buck-boost control module according to the energy storage capacitor when the power supply is off.

[0008] The buck-boost control module controls the switching of the buck-boost circuit according to the first control chip, adjusts the first voltage or the second voltage, and outputs a preset output voltage.

[0009] This invention prevents surges under wide voltage input ranges through the surge suppression circuit of the input protection module, suppressing excessively high first voltage transmitted to the buck-boost control module and providing a stable drive voltage for the first control chip. The first control chip controls the switching of the buck-boost circuit, adjusting the output voltage to achieve buck-boost control with a wide voltage input range. The energy storage capacitor of the clamping energy storage module stores energy through the input protection module, clamping the input voltage when the input voltage from the input protection module is too high, protecting the energy storage capacitor from damage. Furthermore, when the power supply fails, the energy storage capacitor provides a second voltage to the first control chip, enabling the buck-boost power converter to continue operating under the drive of the second voltage, thus achieving power-down delay.

[0010] Furthermore, the clamping circuit includes: a first PMOS transistor, a second PMOS transistor, a PNP transistor, an NPN transistor, a first Zener diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and a first diode;

[0011] The source of the first PMOS transistor is connected to the source of the second PMOS transistor, the emitter of the PNP transistor, the first end of the first resistor, the first end of the second resistor, the input terminal of the clamping energy storage module, and the voltage source.

[0012] The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, the collector of the PNP transistor, the second end of the second resistor, and the first end of the third resistor.

[0013] The drain of the first PMOS transistor is connected to the drain of the second PMOS transistor, the cathode of the first Zener diode, the first terminal of the fourth resistor, the cathode of the first diode, and the voltage source.

[0014] The second end of the first resistor is connected to the base of the PNP transistor and the first end of the fifth resistor;

[0015] The positive terminal of the first Zener diode is connected to the first terminal of the sixth resistor;

[0016] The first end of the energy storage capacitor is connected to the second end of the fourth resistor and the positive terminal of the first diode, and the second end of the energy storage capacitor is connected to the first end of the seventh resistor, the emitter of the NPN transistor and the signal ground.

[0017] The collector of the NPN transistor is connected to the second end of the fifth resistor, and the base of the NPN transistor is connected to the second ends of the sixth and seventh resistors.

[0018] In this invention, the first and second PMOS transistors, together with the first Zener diode, PNP transistor, and NPN transistor, limit the input voltage to achieve voltage clamping when the input voltage is too high. Specifically, when the input voltage is too high, the first Zener diode is connected to the base of the NPN transistor through a voltage divider resistor, pulling the base of the NPN transistor to a high potential and turning it on. After the NPN transistor turns on, the base of the PNP transistor is pulled to a low potential, and the PNP transistor also turns on through the voltage divider resistor. This causes the gate and source of the first and second PMOS transistors to change dynamically. The source and drain of the first and second PMOS transistors absorb the excess voltage, thus clamping the voltage applied across the energy storage capacitor within a preset range.

[0019] Furthermore, the clamping circuit also includes: a second Zener diode, an eighth resistor, a ninth resistor, and a tenth resistor;

[0020] The negative terminal of the second Zener diode is connected to the positive terminal of the first Zener diode;

[0021] The positive terminal of the second Zener diode is connected to the first terminal of the sixth resistor;

[0022] The first end of the eighth resistor is connected to the base of the PNP transistor;

[0023] The second end of the eighth resistor is connected to the second end of the first resistor and the first end of the fifth resistor;

[0024] The first end of the ninth resistor is connected to the second end of the second resistor, the first end of the third resistor, the gate of the first PMOS transistor, the gate of the second PMOS transistor, and the collector of the PNP transistor.

[0025] The second terminal of the ninth resistor is connected to the emitter of the NPN transistor, the first terminal of the seventh resistor, the second terminal of the third resistor, the second terminal of the energy storage capacitor, and the signal ground;

[0026] The first terminal of the tenth resistor is connected to the first terminal of the fourth resistor, the drain of the first PMOS transistor, the drain of the second PMOS transistor, the negative terminal of the first Zener diode, and the voltage source.

[0027] The second end of the tenth resistor is connected to the second end of the fourth resistor, the first end of the energy storage capacitor, and the positive terminal of the first diode.

[0028] Furthermore, the surge suppression circuit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a second control chip;

[0029] The first output pin of the second control chip is connected to the gate of the first NMOS transistor and the gate of the second NMOS transistor;

[0030] The second output pin of the second control chip is connected to the gate of the third NMOS transistor;

[0031] The drain of the first NMOS transistor is connected to the drain of the second NMOS transistor and the first input terminal of the input protection module;

[0032] The source of the first NMOS transistor is connected to the source of the second NMOS transistor and the source of the third NMOS transistor;

[0033] The drain of the third NMOS transistor is connected to the output terminal of the input protection module.

[0034] This invention employs a second control chip to control the switching of the first NMOS transistor to the third NMOS transistor, so that the first NMOS transistor and the second NMOS transistor form a linear regulated power supply, thereby clamping the voltage briefly and preventing surge phenomena from damaging the circuit. In addition, when the power supply fails, the second control chip controls the third NMOS transistor to disconnect to prevent voltage backflow in the subsequent circuit.

[0035] Furthermore, the input protection module also includes an anti-backflow circuit;

[0036] The anti-reverse current circuit includes a second diode and a third diode.

[0037] The negative terminal of the second diode is connected to the input terminal of the input protection module, the drain of the first NMOS transistor, and the drain of the second NMOS transistor;

[0038] The positive terminal of the second diode is connected to the positive terminal of the third diode;

[0039] The negative terminal of the third diode is connected to the second terminal of the input protection module and the signal ground.

[0040] Furthermore, the buck-boost circuit includes: a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a first inductor, and a first capacitor;

[0041] The first control pin of the first control chip is connected to the gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor;

[0042] The drain of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, the input pin of the first control chip, and the input terminal of the buck-boost control module.

[0043] The source of the fourth NMOS transistor is connected to the source of the fifth NMOS transistor, the drain of the sixth NMOS transistor, the drain of the seventh NMOS transistor, the first switching pin of the first control chip, and the first end of the first inductor.

[0044] The second control pin of the first control chip is connected to the gate of the sixth NMOS transistor and the gate of the seventh NMOS transistor;

[0045] The source of the sixth NMOS transistor is connected to the source of the seventh NMOS transistor and the circuit ground;

[0046] The third control pin of the first control chip is connected to the gate of the eighth NMOS transistor;

[0047] The drain of the eighth NMOS transistor is connected to the second terminal of the first inductor and the source of the ninth NMOS transistor.

[0048] The source of the eighth NMOS transistor is connected to the circuit ground;

[0049] The fourth control pin of the first control chip is connected to the gate of the ninth NMOS transistor;

[0050] The drain of the ninth NMOS transistor is connected to the first terminal of the first capacitor, the output terminal of the buck-boost control module, and the circuit ground.

[0051] The second terminal of the first capacitor is connected to the circuit ground.

[0052] This invention achieves buck-boost conversion through a first control chip. When bucking is required, the first control pin controls the fourth and fifth NMOS transistors to perform high-frequency switching to charge the first inductor, and the second control pin controls the sixth and seventh NMOS transistors to perform freewheeling, thereby reducing the output voltage. When boosting is required, the third control pin controls the eighth NMOS transistor to perform high-frequency switching to charge the first inductor, and the fourth control pin controls the ninth NMOS transistor to store energy in the first capacitor, thereby achieving boosting.

[0053] Furthermore, the buck-boost power converter supporting power-down delay includes: an input filtering module;

[0054] The first input terminal of the input filtering module is connected to the positive terminal of the power supply, the second input terminal of the input filtering module is connected to the negative terminal of the power supply, the first output terminal of the input filtering module is connected to the first input terminal of the input protection module, and the second output terminal of the input filtering module is connected to the second input terminal of the input protection module; wherein, the input filtering module includes a common-mode filter and a differential-mode filter.

[0055] This invention filters out common-mode current and differential-mode current in the power supply using a common-mode filter and a differential-mode filter, respectively, thereby suppressing electromagnetic interference and slowing down the current rise rate.

[0056] On the other hand, embodiments of the present invention provide a buck-boost power conversion method, applied to the buck-boost power converter with power-down delay described in the above embodiments. The buck-boost power conversion method includes:

[0057] When the positive and negative terminals of the power supply are powered on, the input voltage is obtained according to the input protection module;

[0058] Compare the input voltage with a preset value;

[0059] When the input voltage is greater than the preset value, the input voltage is reduced according to the buck-boost circuit, and the preset output voltage is output.

[0060] When the input voltage is less than the preset value, the input voltage is boosted according to the buck-boost circuit, and the preset output voltage is output.

[0061] Furthermore, the step of obtaining the input voltage according to the input protection module when the positive and negative terminals of the power supply are powered on can be replaced by obtaining the input voltage according to the clamping energy storage module when the positive and negative terminals of the power supply are powered off.

[0062] When the power supply is normal, the present invention obtains the input voltage through the input protection module and adjusts the output voltage according to the input voltage and the set value; when the power supply fails, the input voltage is obtained through the clamping energy storage module, the voltage adjustment continues, and a power failure delay is achieved. Attached Figure Description

[0063] Figure 1 A schematic diagram illustrating the connection relationship of an embodiment of the buck-boost power converter supporting power-down delay provided by the present invention;

[0064] Figure 2 This is a schematic diagram showing the connection relationship of one embodiment of the clamping energy storage module provided by the present invention;

[0065] Figure 3 This is a schematic diagram showing the connection relationship of an embodiment of the input protection module provided by the present invention;

[0066] Figure 4 A schematic diagram of the connection relationship of an embodiment of the boost / buck control module provided by the present invention;

[0067] Figure 5 This is a schematic diagram showing the connection relationship of an embodiment of the input filtering module provided by the present invention;

[0068] Figure 6 This is a schematic flowchart of one embodiment of the buck-boost power conversion method provided by the present invention. Detailed Implementation

[0069] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0070] Example 1

[0071] Please refer to Figure 1 This is a schematic diagram of the connection relationship of an embodiment of the buck-boost power converter supporting power-down delay provided by the present invention, including: an input protection module, a clamping energy storage module and a buck-boost control module;

[0072] The input protection module has a first input terminal connected to the positive terminal of the power supply, a second input terminal connected to the negative terminal of the power supply, and an output terminal connected to the input terminals of the clamping energy storage module and the buck-boost control module. The input protection module includes a surge suppression circuit. The clamping energy storage module includes a clamping circuit and an energy storage capacitor. The buck-boost control module includes a first control chip and a buck-boost circuit. The input pins of the first control chip are connected to the input terminals of the buck-boost control module.

[0073] The input protection module is used to provide a first voltage within the required range for the clamping energy storage module and the buck-boost control module according to the surge suppression circuit;

[0074] The clamping energy storage module is used to charge the energy storage capacitor according to the clamping circuit and the first voltage when the power supply is on; and to provide a second voltage to the buck-boost control module according to the energy storage capacitor when the power supply is off.

[0075] The buck-boost control module controls the switching of the buck-boost circuit according to the first control chip, adjusts the first voltage or the second voltage, and outputs a preset output voltage.

[0076] This invention prevents surges under wide voltage input ranges through the surge suppression circuit of the input protection module, suppressing excessively high first voltage transmitted to the buck-boost control module and providing a stable drive voltage for the first control chip. The first control chip controls the switching of the buck-boost circuit, adjusting the output voltage to achieve buck-boost control with a wide voltage input range. The energy storage capacitor of the clamping energy storage module stores energy through the input protection module, clamping the input voltage when the input voltage from the input protection module is too high, protecting the energy storage capacitor from damage. Furthermore, when the power supply fails, the energy storage capacitor provides a second voltage to the first control chip, enabling the buck-boost power converter to continue operating under the drive of the second voltage, thus achieving power-down delay.

[0077] Please refer to Figure 2 This is a schematic diagram of the connection relationship of an embodiment of the clamping energy storage module provided by the present invention. The clamping circuit includes: a first PMOS transistor Q4, a second PMOS transistor Q14, a PNP transistor Q5, an NPN transistor Q6, a first Zener diode V4, a first resistor R8, a second resistor R13, a third resistor R19, a fourth resistor R9, a fifth resistor R14, a sixth resistor R17, a seventh resistor R21, and a first diode V5.

[0078] The source of the first PMOS transistor Q4 is connected to the source of the second PMOS transistor Q14, the emitter of the PNP transistor Q5, the first end of the first resistor R8, the first end of the second resistor R13, the input terminal of the clamping energy storage module, and the voltage source.

[0079] The gate of the first PMOS transistor Q4 is connected to the gate of the second PMOS transistor Q14, the collector of the PNP transistor Q5, the second end of the second resistor R13, and the first end of the third resistor R19.

[0080] The drain of the first PMOS transistor Q4 is connected to the drain of the second PMOS transistor Q14, the cathode of the first Zener diode V4, the first terminal of the fourth resistor R9, the cathode of the first diode V5, and the voltage source VIN+.

[0081] The second end of the first resistor R8 is connected to the base of the PNP transistor Q5 and the first end of the fifth resistor R14;

[0082] The positive terminal of the first Zener diode V4 is connected to the first end of the sixth resistor R17;

[0083] The first terminal of the energy storage capacitor C26 is connected to the second terminal of the fourth resistor R9 and the positive terminal of the first diode V5. The second terminal of the energy storage capacitor C26 is connected to the first terminal of the seventh resistor R21, the emitter of the NPN transistor, the second terminal of the third resistor R19, and the signal ground.

[0084] The collector of the NPN transistor is connected to the second end of the fifth resistor R14, and the base of the NPN transistor is connected to the second end of the sixth resistor R17 and the second end of the seventh resistor R21.

[0085] In this invention, the first PMOS transistor Q4 and the second PMOS transistor Q14, together with the first Zener diode V4, the PNP transistor Q5, and the NPN transistor Q6, limit the input voltage to achieve voltage clamping when the input voltage is too high. Specifically, when the input voltage is too high, the first Zener diode V4 is connected to the base of the NPN transistor Q6 through a voltage divider resistor, pulling the base of the NPN transistor Q6 to a high potential and turning on the NPN transistor Q6. After the NPN transistor Q6 turns on, the base of the PNP transistor Q5 is pulled to a low potential, and the PNP transistor Q5 turns on through the voltage divider resistor. This causes the gate and source of the first PMOS transistor Q4 and the second PMOS transistor Q14 to change dynamically. The source and drain of the first PMOS transistor Q4 and the second PMOS transistor Q14 absorb the excess voltage, thereby clamping the voltage applied across the energy storage capacitor within a preset range.

[0086] In this embodiment, the clamping circuit further includes: a second Zener diode V6, an eighth resistor R11, a ninth resistor R20, and a tenth resistor R10;

[0087] The negative terminal of the second Zener diode V6 is connected to the positive terminal of the first Zener diode V4;

[0088] The positive terminal of the second Zener diode V6 is connected to the first terminal of the sixth resistor R17;

[0089] The first end of the eighth resistor R11 is connected to the base of the PNP transistor;

[0090] The second end of the eighth resistor R11 is connected to the second end of the first resistor R8 and the first end of the fifth resistor R14;

[0091] The first end of the ninth resistor R20 is connected to the second end of the second resistor R13, the first end of the third resistor R19, the gate of the first PMOS transistor Q4, the gate of the second PMOS transistor Q14, and the collector of the PNP transistor Q5.

[0092] The second terminal of the ninth resistor R20 is connected to the emitter of the NPN transistor Q6, the first terminal of the seventh resistor R21, the second terminal of the third resistor R19, the second terminal of the energy storage capacitor C26, and the signal ground.

[0093] The first terminal of the tenth resistor R10 is connected to the first terminal of the fourth resistor R9, the drain of the first PMOS transistor Q4, the drain of the second PMOS transistor Q14, the negative terminal of the first Zener diode V4, and the voltage source VIN+.

[0094] The second terminal of the tenth resistor R10 is connected to the second terminal of the fourth resistor R9, the first terminal of the energy storage capacitor C26, and the positive terminal of the first diode V5.

[0095] In this embodiment, a filter capacitor can be connected between the input terminal of the clamping energy storage module and the NPN transistor Q6. The filter capacitor can be obtained by connecting several capacitors in parallel, including C19, C20, C21, and C22.

[0096] In this embodiment, when the input voltage to the clamping energy storage module is too high, the gate and source voltages of the first PMOS transistor Q4 and the second PMOS transistor Q14 are dynamically changing. The source and drain of the first PMOS transistor Q4 and the second PMOS transistor Q14 absorb the excess voltage, clamping the voltage input to the energy storage capacitor C26 within the voltage range of the first Zener diode V4 and the second Zener diode V6, ensuring safe operation of the capacitor. The energy storage capacitor C26 is charged through the fourth resistor R9 and the tenth resistor R10 to store energy when the power supply is off. When the power is off, the energy storage capacitor C26 discharges through the first diode V5 to supply power to the first control chip U2.

[0097] In this embodiment, after power failure, energy is supplied through an energy storage capacitor. The power failure delay is calculated as follows: Q = P × T, where Q is the work, P is the power, and T is the time; Q = 0.5 × C × (U2 rated - U2 low-end), where C is the capacitor capacity and U is the input voltage. If the rated voltage U of the first control chip is 28V and the low-end voltage U2 low-end is 6V, and the power P to be maintained during power failure is 100W, and the required delay time is 50ms, then substituting into the formula yields 100 × 0.05 = 0.5 × C × (282 - 62). Therefore, the required capacity of the energy storage capacitor C26 is 12260uf; in this embodiment, the capacitor capacity can be 15000uf, or a 50V 18000uf energy storage capacitor can be used to ensure that the power failure delay is greater than or equal to 50ms.

[0098] Please refer to Figure 3This is a schematic diagram of the connection relationship of an embodiment of the input protection module provided by the present invention. The surge suppression circuit includes: a first NMOS transistor Q1, a second NMOS transistor Q2, a third NMOS transistor Q3, and a second control chip U1.

[0099] The first output pin HGATE of the second control chip U1 is connected to the gate of the first NMOS transistor Q1 and the gate of the second NMOS transistor Q2;

[0100] The second output pin DGATE of the second control chip U1 is connected to the gate of the third NMOS transistor Q3;

[0101] The drain of the first NMOS transistor Q1 is connected to the drain of the second NMOS transistor Q2 and the first input terminal of the input protection module;

[0102] The source of the first NMOS transistor Q1 is connected to the source of the second NMOS transistor Q2 and the source of the third NMOS transistor Q3;

[0103] The drain of the third NMOS transistor Q3 is connected to the output terminal of the input protection module.

[0104] The present invention uses a second control chip U1 to control the switching of the first NMOS transistor Q1 to the third NMOS transistor Q3, so that the first NMOS transistor Q1 and the second NMOS transistor Q2 form a linear regulated power supply, thereby clamping the voltage briefly and preventing surge phenomena from damaging the circuit. In addition, when the power supply is lost, the second control chip U1 controls the third NMOS transistor Q3 to disconnect to prevent voltage backflow in the subsequent circuit.

[0105] In this embodiment, the input protection module also includes an anti-backflow circuit;

[0106] The anti-reverse current circuit includes: a second diode D1 and a third diode D2;

[0107] The negative terminal of the second diode D1 is connected to the input terminal of the input protection module, the drain of the first NMOS transistor Q1, and the drain of the second NMOS transistor Q2;

[0108] The positive terminal of the second diode D1 is connected to the positive terminal of the third diode D2;

[0109] The negative terminal of the third diode D2 is connected to the second terminal of the input protection module and the signal ground.

[0110] In this embodiment, the second diode D1 and the third diode D2 can be ideal diodes.

[0111] Please refer to Figure 4The diagram shows the connection relationship of an embodiment of the buck-boost control module provided by the present invention. The buck-boost circuit includes: a fourth NMOS transistor Q8, a fifth NMOS transistor Q9, a sixth NMOS transistor Q10, a seventh NMOS transistor Q11, an eighth NMOS transistor Q13, a ninth NMOS transistor Q12, a first inductor L5, and a first capacitor C100.

[0112] The first control pin TG1 of the first control chip U2 is connected to the gate of the fourth NMOS transistor Q8 and the gate of the fifth NMOS transistor Q9;

[0113] The drain of the fourth NMOS transistor Q8 is connected to the drain of the fifth NMOS transistor Q9, the input pin VIN of the first control chip U2, and the input terminal of the buck-boost control module.

[0114] The source of the fourth NMOS transistor Q8 is connected to the source of the fifth NMOS transistor Q9, the drain of the sixth NMOS transistor Q10, the drain of the seventh NMOS transistor Q11, the first switching pin SW1 of the first control chip U2, and the first end of the first inductor L5.

[0115] The second control pin BG1 of the first control chip U2 is connected to the gate of the sixth NMOS transistor Q10 and the gate of the seventh NMOS transistor Q11;

[0116] The source of the sixth NMOS transistor Q10 is connected to the source of the seventh NMOS transistor Q11 and the circuit ground;

[0117] The third control pin BG2 of the first control chip U2 is connected to the gate of the eighth NMOS transistor Q13;

[0118] The drain of the eighth NMOS transistor Q13 is connected to the second terminal of the first inductor L5 and the source of the ninth NMOS transistor Q12.

[0119] The source of the eighth NMOS transistor Q13 is connected to the circuit ground;

[0120] The fourth control pin TG2 of the first control chip U2 is connected to the gate of the ninth NMOS transistor Q12;

[0121] The drain of the ninth NMOS transistor Q12 is connected to the first terminal of the first capacitor C100, the output terminal of the buck-boost control module, and the circuit ground.

[0122] The second terminal of the first capacitor C100 is connected to the circuit ground.

[0123] In this embodiment, the first control chip U2 can be a Linear Technology LTC3779, which has 34 pins. It is used in conjunction with the chip peripherals for control. When the input voltage is low, it enters boost mode, and when the input voltage is high, it enters buck mode to ensure that the output voltage is stable at the preset value.

[0124] This invention achieves buck-boost conversion through the first control chip U2. When bucking is required, the first control pin TG1 controls the fourth NMOS transistor Q8 and the fifth NMOS transistor Q9 to perform high-frequency switching to charge the first inductor L5. Then, the second control pin BG1 controls the sixth NMOS transistor Q10 and the seventh NMOS transistor Q11 to achieve freewheeling, thereby reducing the output voltage. When boosting is required, the third control pin BG2 controls the eighth NMOS transistor Q13 to perform high-frequency switching to charge the first inductor L5. Then, the fourth control pin TG2 controls the ninth NMOS transistor Q12 to store energy for the first capacitor C100, thereby achieving boosting.

[0125] Please refer to Figure 5 This is a schematic diagram of the connection relationship of an embodiment of the input filtering module provided by the present invention. The buck-boost power converter supporting power-down delay includes: an input filtering module;

[0126] The first input terminal of the input filtering module is connected to the positive terminal of the power supply, the second input terminal of the input filtering module is connected to the negative terminal of the power supply, the first output terminal of the input filtering module is connected to the first input terminal of the input protection module, and the second output terminal of the input filtering module is connected to the second input terminal of the input protection module; wherein, the input filtering module includes a common-mode filter and a differential-mode filter.

[0127] In this embodiment, the common-mode filter includes a first common-mode filter L2 and a second common-mode filter L3, and the differential-mode filter includes a first differential-mode filter L1 and a second differential-mode filter L4.

[0128] Wherein, the first end of the first common-mode filter L2 is connected to one end of the first differential-mode filter L1, the second end of the first common-mode filter L2 is connected to the first end of the second common-mode filter L3, the third end of the first common-mode filter L2 is connected to one end of the second differential-mode filter L4, and the fourth end of the first common-mode filter L2 is connected to the third end of the second differential-mode filter L4.

[0129] The other end of the first differential filter L1 is connected to the first input terminal of the input filtering module;

[0130] The other end of the second differential filter L4 is connected to the second input terminal of the input filter module;

[0131] The second terminal of the second common-mode filter L3 is connected to the first output terminal of the input filtering module;

[0132] The fourth terminal of the second common-mode filter L3 is connected to the second output terminal of the input filtering module.

[0133] In this embodiment, common-mode and differential-mode currents in the power supply are filtered out by a common-mode filter and a differential-mode filter, respectively, to prevent mutual interference between the power supply and the outside world and improve electromagnetic compatibility performance. Furthermore, this embodiment can also connect a circuit consisting of two common-mode capacitors connected in series between the first and second input terminals of the input filter module, between the first and second terminals of the first common-mode filter L2, between the third and fourth terminals of the first common-mode filter L2, and between the first output terminal and the second input terminal of the input filter module. These common-mode capacitors include C1-C5, C7, C9-C13, and C15. Installing these common-mode capacitors ensures reliable discharge of common-mode noise, improves conducted emission (CE) and conducted sensitivity (CS) of the power supply, and slows down the current rise rate.

[0134] Please refer to Figure 6 This is a flowchart illustrating an embodiment of the buck-boost power conversion method provided by the present invention, which mainly includes steps 6011 to 604, as follows:

[0135] Step 6011: When the positive and negative terminals of the power supply are powered on, obtain the input voltage according to the input protection module; execute step 602.

[0136] Step 6012: When the positive and negative terminals of the power supply are de-energized, obtain the input voltage according to the clamping energy storage module; execute step 602.

[0137] In this embodiment, the driving voltage of the first control chip U2 can be provided by the input protection module after surge suppression of the power supply, or by the energy storage capacitor C26 in the clamping energy storage module after the power supply is turned off.

[0138] Step 602: Compare the input voltage with a preset value; when the input voltage is greater than the preset value, proceed to step 603; and when the input voltage is less than the preset value, proceed to step 604.

[0139] Step 603: According to the buck-boost circuit, reduce the input voltage and output the preset output voltage.

[0140] Step 604: According to the buck-boost circuit, increase the input voltage and output the preset output voltage.

[0141] In this embodiment, the buck-boost circuit uses an NMOS transistor as a switch, and the first control chip U2 controls the frequency of the NMOS transistor's on and off states to charge or freewheel the inductor in the buck-boost circuit, thereby regulating the output voltage.

[0142] When the power supply is normal, the present invention obtains the input voltage through the input protection module and adjusts the output voltage according to the input voltage and the set value; when the power supply fails, the input voltage is obtained through the clamping energy storage module, the voltage adjustment continues, and a power failure delay is achieved.

[0143] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A buck-boost power converter supporting power-down delay, characterized in that, include: Input protection module, clamping energy storage module, and buck-boost control module; The input protection module has a first input terminal connected to the positive terminal of the power supply, a second input terminal connected to the negative terminal of the power supply, and an output terminal connected to the input terminals of the clamping energy storage module and the buck-boost control module. The input protection module includes a surge suppression circuit. The clamping energy storage module includes a clamping circuit and an energy storage capacitor. The buck-boost control module includes a first control chip and a buck-boost circuit. The input pins of the first control chip are connected to the input terminals of the buck-boost control module. The input protection module is used to provide a first voltage within the required range for the clamping energy storage module and the buck-boost control module according to the surge suppression circuit; The clamping energy storage module is used to charge the energy storage capacitor according to the clamping circuit and the first voltage when the power supply is on; and to provide a second voltage to the buck-boost control module according to the energy storage capacitor when the power supply is off. The buck-boost control module controls the switching of the buck-boost circuit according to the first control chip, adjusts the first voltage or the second voltage, and outputs a preset output voltage.

2. The buck-boost power converter supporting power-down delay as described in claim 1, characterized in that, The clamping circuit includes: a first PMOS transistor, a second PMOS transistor, a PNP transistor, an NPN transistor, a first Zener diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and a first diode; The source of the first PMOS transistor is connected to the source of the second PMOS transistor, the emitter of the PNP transistor, the first end of the first resistor, the first end of the second resistor, the input terminal of the clamping energy storage module, and the voltage source. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, the collector of the PNP transistor, the second end of the second resistor, and the first end of the third resistor. The drain of the first PMOS transistor is connected to the drain of the second PMOS transistor, the cathode of the first Zener diode, the first terminal of the fourth resistor, the cathode of the first diode, and the voltage source. The second end of the first resistor is connected to the base of the PNP transistor and the first end of the fifth resistor; The positive terminal of the first Zener diode is connected to the first terminal of the sixth resistor; The first end of the energy storage capacitor is connected to the second end of the fourth resistor and the positive terminal of the first diode, and the second end of the energy storage capacitor is connected to the first end of the seventh resistor, the emitter of the NPN transistor and the signal ground. The collector of the NPN transistor is connected to the second end of the fifth resistor, and the base of the NPN transistor is connected to the second ends of the sixth and seventh resistors.

3. The buck-boost power converter supporting power-down delay as described in claim 2, characterized in that, The clamping circuit further includes: a second Zener diode, an eighth resistor, a ninth resistor, and a tenth resistor; The negative terminal of the second Zener diode is connected to the positive terminal of the first Zener diode; The positive terminal of the second Zener diode is connected to the first terminal of the sixth resistor; The first end of the eighth resistor is connected to the base of the PNP transistor; The second end of the eighth resistor is connected to the second end of the first resistor and the first end of the fifth resistor; The first end of the ninth resistor is connected to the second end of the second resistor, the first end of the third resistor, the gate of the first PMOS transistor, the gate of the second PMOS transistor, and the collector of the PNP transistor. The second terminal of the ninth resistor is connected to the emitter of the NPN transistor, the first terminal of the seventh resistor, the second terminal of the third resistor, the second terminal of the energy storage capacitor, and the signal ground; The first terminal of the tenth resistor is connected to the first terminal of the fourth resistor, the drain of the first PMOS transistor, the drain of the second PMOS transistor, the negative terminal of the first Zener diode, and the voltage source. The second end of the tenth resistor is connected to the second end of the fourth resistor, the first end of the energy storage capacitor, and the positive terminal of the first diode.

4. The buck-boost power converter supporting power-down delay as described in claim 1, characterized in that, The surge suppression circuit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a second control chip; The first output pin of the second control chip is connected to the gate of the first NMOS transistor and the gate of the second NMOS transistor; The second output pin of the second control chip is connected to the gate of the third NMOS transistor; The drain of the first NMOS transistor is connected to the drain of the second NMOS transistor and the first input terminal of the input protection module; The source of the first NMOS transistor is connected to the source of the second NMOS transistor and the source of the third NMOS transistor; The drain of the third NMOS transistor is connected to the output terminal of the input protection module.

5. The buck-boost power converter supporting power-down delay as described in claim 4, characterized in that, The input protection module also includes a backflow prevention circuit; The anti-reverse current circuit includes a second diode and a third diode. The negative terminal of the second diode is connected to the first input terminal of the input protection module, the drain of the first NMOS transistor, and the drain of the second NMOS transistor; The positive terminal of the second diode is connected to the positive terminal of the third diode; The negative terminal of the third diode is connected to the second input terminal and signal ground of the input protection module.

6. The buck-boost power converter supporting power-down delay as described in claim 1, characterized in that, The buck-boost circuit includes: a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a first inductor, and a first capacitor; The first control pin of the first control chip is connected to the gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor; The drain of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, the input pin of the first control chip, and the input terminal of the buck-boost control module. The source of the fourth NMOS transistor is connected to the source of the fifth NMOS transistor, the drain of the sixth NMOS transistor, the drain of the seventh NMOS transistor, the first switching pin of the first control chip, and the first end of the first inductor. The second control pin of the first control chip is connected to the gate of the sixth NMOS transistor and the gate of the seventh NMOS transistor; The source of the sixth NMOS transistor is connected to the source of the seventh NMOS transistor and the circuit ground; The third control pin of the first control chip is connected to the gate of the eighth NMOS transistor; The drain of the eighth NMOS transistor is connected to the second terminal of the first inductor and the source of the ninth NMOS transistor. The source of the eighth NMOS transistor is connected to the circuit ground; The fourth control pin of the first control chip is connected to the gate of the ninth NMOS transistor; The drain of the ninth NMOS transistor is connected to the first terminal of the first capacitor and the output terminal of the buck-boost control module. The second terminal of the first capacitor is connected to the circuit ground.

7. The buck-boost power converter supporting power-down delay as described in claim 1, characterized in that, include: Input filtering module; The first input terminal of the input filtering module is connected to the positive terminal of the power supply, the second input terminal of the input filtering module is connected to the negative terminal of the power supply, the first output terminal of the input filtering module is connected to the first input terminal of the input protection module, and the second output terminal of the input filtering module is connected to the second input terminal of the input protection module; wherein, the input filtering module includes a common-mode filter and a differential-mode filter.

8. A method for buck-boost power conversion, characterized in that, The buck-boost power converter supporting power-down delay, applied to any one of claims 1-6, comprises the following buck-boost power conversion method: When the positive and negative terminals of the power supply are powered on, the input voltage is obtained according to the input protection module; Compare the input voltage with a preset value; When the input voltage is greater than the preset value, the input voltage is reduced according to the buck-boost circuit, and the preset output voltage is output. When the input voltage is less than the preset value, the input voltage is boosted according to the buck-boost circuit, and the preset output voltage is output.

9. The step-up / step-down power conversion method as described in claim 8, characterized in that, Instead of obtaining the input voltage from the input protection module when the positive and negative terminals of the power supply are powered on, the input voltage is obtained from the clamping energy storage module when the positive and negative terminals of the power supply are powered off.

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