Frequency division circuit, clock module, chip and computing device applying same
Patent Information
- Application Number
- CN202211366296.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-10-31
- Publication Date
- 2026-09-18
- Estimated Expiration
- 2042-10-31
Smart Images
Figure CN115882852B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a clock divider circuit, and more particularly to a clock divider circuit capable of flexible frequency division, as well as clock modules, chips, and computing devices using the same. Background Technology
[0002] During operation, the chip needs a clock that can provide different frequencies or different duty cycles to adapt to different performance requirements and power consumption requirements.
[0003] In the existing technology, commonly used frequency divider circuits are based on integer frequency division. The frequency of the divided clock is an integer multiple of the original clock, and the duty cycle of the divided clock is 50%.
[0004] Therefore, how to provide a frequency divider circuit that can achieve arbitrary frequency division with a duty cycle other than 50% and flexibly adapt to different needs is a problem that needs to be solved. Summary of the Invention
[0005] To address the aforementioned problems, this invention provides a frequency divider circuit and a clock module, chip, and computing device using the same, which can achieve clock frequencies of different frequencies and arbitrary duty cycles, effectively improving the performance of the computing device and reducing power consumption.
[0006] To achieve the above objectives, the present invention provides a frequency divider circuit, comprising: a counting comparison unit for receiving a first clock signal and a comparison reference signal, and outputting a counting signal; a synchronization unit for receiving an update indication signal and outputting an update request signal; a frequency divider parameter update unit for receiving the counting signal, the update request signal, and a frequency divider parameter, and outputting a frequency divider clock enable signal; and a gated clock unit for receiving the first clock signal and the frequency divider clock enable signal, and outputting a second clock signal; wherein the frequency and / or duty cycle of the second clock signal are determined according to the frequency divider parameter.
[0007] In the frequency divider circuit described above, the number of bits in the frequency divider parameter is N, and each bit in the frequency divider parameter controls the gated clock unit.
[0008] In the aforementioned frequency divider circuit, the number of types of the second clock signal is 2. N .
[0009] In the frequency divider circuit described above, the counting comparison unit has a first terminal, a second terminal, and a third terminal. The first terminal of the counting comparison unit is electrically connected to the first clock signal, the second terminal of the counting comparison unit is electrically connected to the comparison reference signal, and the third terminal of the counting comparison unit is electrically connected to the counting signal.
[0010] The frequency divider circuit described above, wherein the counting comparison unit further includes:
[0011] A counter having a first terminal and a second terminal, wherein the first terminal of the counter is electrically connected to the first clock signal;
[0012] A comparator has a first terminal, a second terminal, and a third terminal. The first terminal of the comparator is electrically connected to the second terminal of the counter, the second terminal of the comparator is electrically connected to the comparison reference signal, and the third terminal of the comparator is electrically connected to the counting signal.
[0013] In the aforementioned frequency divider circuit, the synchronization unit has a first terminal, a second terminal, and a third terminal. The first terminal of the synchronization unit is electrically connected to the update indication signal, the second terminal of the synchronization unit is electrically connected to the first clock signal, and the third terminal of the synchronization unit is electrically connected to the update request signal.
[0014] The frequency divider circuit described above, wherein the synchronization unit further includes:
[0015] A first flip-flop has a first terminal, a second terminal and a third terminal, wherein the first terminal of the first flip-flop is electrically connected to the update indication signal and the second terminal of the first flip-flop is electrically connected to the first clock signal.
[0016] A second flip-flop has a first terminal, a second terminal and a third terminal, wherein the first terminal of the second flip-flop is electrically connected to the third terminal of the first flip-flop, and the second terminal of the second flip-flop is electrically connected to the first clock signal;
[0017] An XOR gate has a first terminal, a second terminal, and a third terminal. The first terminal of the XOR gate is electrically connected to the third terminal of the first flip-flop, the second terminal of the XOR gate is electrically connected to the third terminal of the second flip-flop, and the third terminal of the XOR gate is electrically connected to the update request signal.
[0018] In the aforementioned frequency divider circuit, the frequency divider parameter update unit has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of the frequency divider parameter update unit is electrically connected to the counting signal, the second terminal of the frequency divider parameter update unit is electrically connected to the update request signal, the third terminal of the frequency divider parameter update unit is electrically connected to the first clock signal, the fourth terminal of the frequency divider parameter update unit is electrically connected to the frequency divider parameter, and the fifth terminal of the frequency divider parameter update unit is electrically connected to the frequency divider clock enable signal.
[0019] The frequency division circuit described above, wherein the frequency division parameter update unit further includes:
[0020] A sustaining circuit is used to receive the counting signal and the update request signal and output an update hold signal;
[0021] A parameter update circuit is used to receive the counting signal, the update hold signal, and the frequency division parameter, and output the frequency division clock enable signal.
[0022] The frequency divider circuit described above, wherein the sustaining circuit includes:
[0023] A first inverter has a first terminal and a second terminal, wherein the first terminal of the first inverter is electrically connected to the counting signal;
[0024] A first AND gate has a first terminal, a second terminal and a third terminal, the first terminal of the first AND gate is electrically connected to the second terminal of the first inverter, and the second terminal of the first AND gate is electrically connected to the update hold signal;
[0025] A first OR gate has a first terminal, a second terminal and a third terminal, wherein the first terminal of the first OR gate is electrically connected to the third terminal of the first AND gate, and the second terminal of the first OR gate is electrically connected to the update request signal.
[0026] A third flip-flop has a first terminal, a second terminal, and a third terminal. The first terminal of the third flip-flop is electrically connected to the third terminal of the first OR gate, the second terminal of the third flip-flop is electrically connected to the first clock signal, and the third terminal of the third flip-flop is electrically connected to the update hold signal.
[0027] The frequency divider circuit described above, wherein the parameter update circuit includes:
[0028] A second AND gate has a first terminal, a second terminal and a third terminal, wherein the first terminal of the second AND gate is electrically connected to the update hold signal, and the second terminal of the second AND gate is electrically connected to the count signal;
[0029] A selector has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of the selector is electrically connected to the frequency division parameter, and the control terminal of the selector is electrically connected to the third terminal of the second AND gate.
[0030] A shift register has a first terminal, a second terminal, and a third terminal. The first terminal of the shift register is electrically connected to the third terminal of the selector. The second terminal of the shift register is electrically connected to the first clock signal. The third terminal of the shift register is electrically connected to the second terminal of the selector and is electrically connected to the frequency divider clock enable signal.
[0031] In the aforementioned frequency divider circuit, the gated clock unit has a first terminal, a second terminal, and a third terminal. The first terminal of the gated clock unit is electrically connected to the frequency divider clock enable signal, the second terminal of the gated clock unit is electrically connected to the first clock signal, and the third terminal of the gated clock unit is electrically connected to the second clock signal.
[0032] In the frequency division circuit described above, the comparison reference signal is provided by the frequency division parameter update unit.
[0033] In the aforementioned frequency divider circuit, the frequency divider parameter update unit has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal. The first terminal of the frequency divider parameter update unit is electrically connected to the counting signal, the second terminal of the frequency divider parameter update unit is electrically connected to the update request signal, the third terminal of the frequency divider parameter update unit is electrically connected to the first clock signal, the fourth terminal of the frequency divider parameter update unit is electrically connected to the frequency divider parameter, the fifth terminal of the frequency divider parameter update unit is electrically connected to a current frequency divider parameter, and the sixth terminal of the frequency divider parameter update unit is electrically connected to the frequency divider clock enable signal.
[0034] The frequency division circuit described above, wherein the frequency division parameter update unit further includes:
[0035] A sustaining circuit is used to receive the counting signal and the update request signal and output an update hold signal;
[0036] A parameter update circuit is used to receive the counting signal, the update hold signal, and the frequency division parameter, and output the frequency division clock enable signal and the current frequency division parameter.
[0037] The frequency divider circuit described above, wherein the sustaining circuit includes:
[0038] A second inverter has a first terminal and a second terminal, wherein the first terminal of the second inverter is electrically connected to the counting signal;
[0039] A third AND gate has a first terminal, a second terminal and a third terminal, wherein the first terminal of the third AND gate is electrically connected to the second terminal of the second inverter, and the second terminal of the second AND gate is electrically connected to the update hold signal;
[0040] A second OR gate has a first terminal, a second terminal and a third terminal, wherein the first terminal of the second OR gate is electrically connected to the third terminal of the first AND gate, and the second terminal of the second OR gate is electrically connected to the update request signal;
[0041] A fourth flip-flop has a first terminal, a second terminal, and a third terminal. The first terminal of the fourth flip-flop is electrically connected to the third terminal of the second OR gate, the second terminal of the fourth flip-flop is electrically connected to the first clock signal, and the third terminal of the fourth flip-flop is electrically connected to the update hold signal.
[0042] The frequency divider circuit described above, wherein the parameter update circuit includes:
[0043] A fourth AND gate has a first terminal, a second terminal and a third terminal, wherein the first terminal of the fourth AND gate is electrically connected to the third terminal of the fourth flip-flop, and the second terminal of the fourth AND gate is electrically connected to the counting signal;
[0044] An enable trigger has a first terminal, a second terminal, a third terminal, and an enable terminal. The first terminal of the enable trigger is electrically connected to the frequency division parameter, the second terminal of the enable trigger is electrically connected to the first clock signal, and the third terminal of the enable trigger is electrically connected to the current frequency division parameter.
[0045] A fifth flip-flop has a first terminal, a second terminal, and a third terminal. The first terminal of the fifth flip-flop is electrically connected to the counting signal, the second terminal of the fifth flip-flop is electrically connected to the first clock signal, and the third terminal of the fifth flip-flop is electrically connected to the frequency divider clock enable signal.
[0046] In the frequency divider circuit described above, the number of bits in the frequency divider parameter is N, and the ratio between the frequency of the second clock signal and the frequency of the first clock signal is 1 / (N+1).
[0047] To better achieve the above objectives, the present invention also provides a clock module, wherein at least one frequency divider circuit as described above is included.
[0048] To better achieve the above objectives, the present invention also provides a chip, wherein it includes at least one clock module as described above.
[0049] To better achieve the above objectives, the present invention also provides a computing device, wherein at least one of the chips described above is included.
[0050] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention. Attached Figure Description
[0051] Figure 1 This is a schematic diagram of the circuit structure of a frequency divider circuit according to an embodiment of the present invention;
[0052] Figure 2This is a waveform diagram of a frequency divider circuit according to an embodiment of the present invention;
[0053] Figure 3A This is a schematic diagram of the circuit structure of a synchronization unit according to an embodiment of the present invention;
[0054] Figure 3B This is a waveform diagram of a synchronization unit according to an embodiment of the present invention;
[0055] Figure 4A This is a schematic diagram of the circuit structure of a synchronization unit according to another embodiment of the present invention;
[0056] Figure 4B This is a waveform diagram of a synchronization unit according to another embodiment of the present invention;
[0057] Figure 5A This is a schematic diagram of the circuit structure of a synchronization unit according to another embodiment of the present invention;
[0058] Figure 5B This is a waveform diagram of a synchronization unit according to another embodiment of the present invention;
[0059] Figure 6 This is a schematic diagram of the structure of a sustaining circuit according to an embodiment of the present invention;
[0060] Figure 7A This is a schematic diagram of the circuit structure of a frequency divider circuit according to another embodiment of the present invention;
[0061] Figure 7B This is a waveform diagram of a frequency divider circuit according to another embodiment of the present invention. Detailed Implementation
[0062] The structural and working principles of the present invention will be described in detail below with reference to the accompanying drawings:
[0063] Certain terms are used in the specification and subsequent claims to refer to specific components. It will be understood by those skilled in the art that manufacturers may use different names to refer to the same component. This specification and subsequent claims do not distinguish components by differences in name, but rather by differences in function.
[0064] Throughout this specification and in the following claims, the terms "comprising" and "including" are open-ended and should be interpreted as "comprising but not limited to". Furthermore, the term "connection" here includes any direct and indirect electrical connection means. Indirect electrical connection means include connections made through other means.
[0065] Figure 1 This is a schematic diagram of the circuit structure of a frequency divider circuit according to an embodiment of the present invention; Figure 2 This is a waveform diagram of a frequency divider circuit according to an embodiment of the present invention; Figure 3AThis is a schematic diagram of the circuit structure of a synchronization unit according to an embodiment of the present invention; Figure 3B This is a waveform diagram of a synchronization unit according to an embodiment of the present invention; Figure 4A This is a schematic diagram of the circuit structure of a synchronization unit according to another embodiment of the present invention; Figure 4B This is a waveform diagram of a synchronization unit according to another embodiment of the present invention; Figure 5A This is a schematic diagram of the circuit structure of a synchronization unit according to another embodiment of the present invention; Figure 5B This is a waveform diagram of a synchronization unit according to another embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of a sustaining circuit according to an embodiment of the present invention.
[0066] like Figures 1 to 6 As shown, the frequency divider circuit 100 of the present invention includes a counting comparison unit 101, used to receive a first clock signal clkin and a comparison reference signal WID, and output a counting signal upd_last; a synchronization unit 102, used to receive an update indication signal upd, and output an update request signal upd_req; a frequency divider parameter update unit 103, used to receive the counting signal upd_last, the update request signal upd_req, and the frequency divider parameter div_pat, and output a frequency divider clock enable signal div_clk_gate_en; and a gated clock unit 104, used to receive the first clock signal clkin and the frequency divider clock enable signal div_clk_gate_en, and output a second clock signal clkout; wherein the frequency and / or duty cycle of the second clock signal clkout are determined according to the frequency divider parameter div_pat.
[0067] Furthermore, in this invention, the number of bits in the frequency division parameter div_pat is N, and each bit in the frequency division parameter div_pat controls the gated clock unit 104. The figure only uses N=8 as an example, but this invention is not limited thereto. Thus, various different types of second clock signals clkout can be generated, with a total of 2t types. N .
[0068] Specifically, the counting comparison unit 101 of the present invention has a first terminal, a second terminal, and a third terminal. The first terminal of the counting comparison unit 101 is electrically connected to a first clock signal clkin, the second terminal is electrically connected to a comparison reference signal WID, and the third terminal is electrically connected to a counting signal upd_last. Furthermore, the counting comparison unit 101 further includes a counter 1011 and a comparator 1012. The first terminal of the counter 1011 is electrically connected to the first clock signal clkin; the first terminal of the comparator 1012 is electrically connected to the second terminal of the counter 1011, the second terminal of the comparator 1012 is electrically connected to the comparison reference signal WID, and the third terminal of the comparator 1012 is electrically connected to the counting signal upd_last.
[0069] The counting comparison unit 101 of the present invention is used to count according to the clock signal clkin. When the counter 1011 counts div_cnt to full, that is, when the comparator 1012 compares the count div_cnt with the comparison reference signal WID and the result is equal, the counting signal upd_last is enabled. At this time, upd_last is valid, for example, it is 1.
[0070] In this invention, a high level "1" represents valid and a low level "0" represents invalid. Alternatively, a low level "0" can represent valid and a high level "1" can represent invalid; this invention is not limited to these limitations. Of course, the counting and comparison unit can also have other implementations, as long as it can generate a valid counting signal when the counting result equals the reference value; this invention is not limited to these limitations.
[0071] Specifically, the synchronization unit 102 has a first terminal, a second terminal, and a third terminal. The first terminal of the synchronization unit 102 is electrically connected to the update indication signal upd, the second terminal is electrically connected to the first clock signal clkin, and the third terminal is electrically connected to the update request signal upd_req. The synchronization unit 102 further includes: a first flip-flop DFF1, the first terminal of which is electrically connected to the update indication signal upd, and the second terminal of which is electrically connected to the first clock signal clkin; a second flip-flop DFF2, the first terminal of which is electrically connected to the third terminal of the first flip-flop DFF1, and the second terminal of which is electrically connected to the first clock signal clkin; and an XOR gate, the first terminal of which is electrically connected to the third terminal of the first flip-flop, the second terminal of which is electrically connected to the third terminal of the second flip-flop, and the third terminal of which is electrically connected to the update request signal upd_req.
[0072] In the synchronization unit 102 of the present invention, the update indication signal upd generates a first synchronization signal upd_d1 after being synchronized by the first stage of the first flip-flop DFF1. The first synchronization signal upd_d1 generates a second synchronization signal upd_d2 after being synchronized by the second flip-flop DFF2. That is, the update request signal upd generates the first synchronization signal upd_d1 and the second synchronization signal upd_d2 after being synchronized by the first flip-flop DFF1 and the second flip-flop DFF2, respectively. The first synchronization signal upd_d1 and the second synchronization signal upd_d2 are then XORed to obtain the update request signal upd_req.
[0073] like Figure 3B As shown, after passing through the synchronization unit 102, the update request signal upd will be obtained in the form of a pulse, upd_req, regardless of whether it changes from 1 to 0 or from 0 to 1.
[0074] In this invention, a positive pulse is used to represent the validity of the update request signal, but a negative pulse can also be used. Furthermore, the synchronization unit 102 can also use more counting synchronization signals to obtain the synchronization signal; this invention is not limited thereto.
[0075] In this invention, with Figure 3A The synchronization unit 102 shown is used as an example for explanation, but for... Figure 4A , 5A The synchronization units 102' and 102'' shown can also generate the update request signal upd_req. The specific circuit structure and waveform diagram are as follows. Figures 3A-5B As shown, it will not be elaborated further here. Of course, the synchronization unit can also have other implementation forms, as long as it can ensure that a valid update request signal is generated when the update indication signal flips. This invention is not limited to this.
[0076] Furthermore, the first terminal of the frequency division parameter update unit 103 is electrically connected to the counting signal upd_last, the second terminal is electrically connected to the update request signal upd_req, the third terminal is electrically connected to the first clock signal clkin, the fourth terminal is electrically connected to the frequency division parameter div_pat, and the fifth terminal is electrically connected to the frequency division clock enable signal div_clk_gate_en.
[0077] The frequency division parameter update unit 103 further includes a sustaining circuit 1031, which is used to receive the counting signal upd_last and the update request signal upd_req and output the update hold signal upd_hold; the parameter update circuit 1032 is used to receive the counting signal upd_last, the update hold signal upd_hold and the frequency division parameter div_pat, and output the frequency division clock enable signal div_clk_gate_en.
[0078] Specifically, the sustaining circuit 1031 includes a first inverter, the first terminal of which is electrically connected to the counting signal upd_last; a first AND gate, the first terminal of which is electrically connected to the second terminal of the first inverter, and the second terminal of which is electrically connected to the update hold signal upd_hold; a first OR gate, the first terminal of which is electrically connected to the third terminal of the first AND gate, and the second terminal of which is electrically connected to the update request signal upd_req; and a third flip-flop, the first terminal of which is electrically connected to the third terminal of the first OR gate, the second terminal of which is electrically connected to the first clock signal clkin, and the third terminal of which is electrically connected to the update hold signal upd_hold.
[0079] like Figure 2As shown, when the update request signal upd_req is valid, i.e., a positive pulse, the update hold signal upd_hold also becomes 1 through the first-level synchronization. At this time, the update request signal upd_req becomes 0, until the count signal upd_last becomes 1, at which point the update hold signal upd_hold becomes 0.
[0080] In this invention, with Figure 1 The sustaining circuit 1031 shown is used as an example for detailed explanation, but for Figure 6 The sustaining circuit 1031' shown can also generate a frequency divider parameter update request state. The specific circuit structure is as follows: Figure 6 As shown, it will not be elaborated further here.
[0081] Of course, the holding circuit can also be implemented in other ways, as long as it can generate a valid update holding signal when the update request signal is valid, until the count signal is valid and the update holding signal becomes invalid. This invention is not limited to this.
[0082] The parameter update circuit 1032 includes a second AND gate, the first terminal of which is electrically connected to the update hold signal upd_hold, and the second terminal is electrically connected to the count signal upd_last; a gate, the first terminal of which is electrically connected to the frequency division parameter div_pat, and the control terminal of which is electrically connected to the third terminal of the second AND gate; and a shift register, the first terminal of which is electrically connected to the third terminal of the gate, the second terminal of which is electrically connected to the first clock signal clkin, the third terminal of which is electrically connected to the second terminal of the gate, and the third terminal of which is electrically connected to the frequency division clock enable signal div_clk_gate_en.
[0083] like Figure 2 As shown, when both the update hold signal `upd_hold` and the count signal `upd_last` are valid (e.g., both are 1), they are ANDed to generate a pulse signal `upd_pulse`, which is used to update the divider parameters. When the pulse signal `upd_pulse` is valid (e.g., 1), the input divider parameter `div_pat` is updated in the shift register `cur_pat`. When the pulse signal `upd_pulse` is invalid (e.g., 0), the shift register `cur_pat` continuously performs cyclic shifting. The highest bit of the shift register `cur_pat`, `cur_pat[WIDTH]`, and the original clock are entered into the ICG, ultimately generating the output clock `clkout`.
[0084] In this invention, a high level "1" represents valid and a low level "0" represents invalid. Alternatively, a low level "0" can represent valid and a high level "1" can represent invalid; this invention is not limited to these limitations. Of course, the parameter update circuit can also have other implementations, as long as it can update the frequency divider parameters when the pulse signal is valid; this invention is not limited to these limitations.
[0085] In this invention, the first terminal of the gated clock unit 104 is electrically connected to the divider clock enable signal div_clk_gate_en, the second terminal is electrically connected to the first clock signal clkin, and the third terminal is electrically connected to the second clock signal clkout.
[0086] Figure 7A This is a schematic diagram of the circuit structure of a frequency divider circuit according to another embodiment of the present invention. Figure 7B This is a waveform diagram of a frequency divider circuit according to another embodiment of the present invention.
[0087] like Figure 7A , Figure 7B As shown, in the frequency divider circuit 100' of the present invention, the comparison reference signal is provided by the frequency divider parameter update unit.
[0088] Figure 7A In the illustrated embodiment, the parameter update circuit includes an AND gate, the first terminal of which is electrically connected to the update hold signal upd_hold, and the second terminal of which is electrically connected to the count signal upd_last; an enable trigger, the first terminal of which is electrically connected to the frequency divider parameter div_pat, the second terminal of which is electrically connected to the first clock signal clkin, and the third terminal of which is electrically connected to the current frequency divider parameter cur_pat; and a trigger, the first terminal of which is electrically connected to the count signal upd_last, the second terminal of which is electrically connected to the first clock signal clkin, and the third terminal of which is electrically connected to the frequency divider clock enable signal div_clk_bit.
[0089] refer to Figure 7B The value of the frequency division parameter div_pat is M, and the ratio between the frequency of the second clock signal clkout and the frequency of the first clock signal clkin is 1 / (M+1).
[0090] like Figure 7B As shown, when the pulse signal upd_pulse is valid, for example, when it is 1, the input frequency divider parameter div_pat is updated to the enable trigger cur_pat and provided to comparator 1012 as a comparison reference signal.
[0091] The output clock is a division of the original clock by div_pat + 1, for example... Figure 7BWhen the frequency division parameter is 2, the output clock is 3 times the original clock; when the frequency division parameter is 5, the output clock is 6 times the original clock. When the frequency division parameter is 0, div_clk_bit remains unchanged at 1, and the output clock is the original clock.
[0092] In this invention, a high level "1" represents valid and a low level "0" represents invalid. Alternatively, a low level "0" can represent valid and a high level "1" can represent invalid; this invention is not limited to these limitations. Of course, the parameter update circuit can also have other implementations, as long as it can update the input frequency divider parameters when the pulse signal is valid and provide them to the comparator as a comparison reference signal; this invention is not limited to these limitations.
[0093] Working principle:
[0094] Combination Figures 1-7B clkin is the original clock, div_pat is the divider parameter (usually CPU configuration), and upd is the divider parameter update indicator signal; each toggle indicates that the divider parameters need to be updated. Taking toggle triggering as an example, upd is XORed after two stages of synchronization to obtain a pulse signal upd_req. Thus, regardless of whether upd changes from 1 to 0 or from 0 to 1, a toggle will generate the pulse signal upd_req. The synchronization of upd can vary slightly depending on the specific situation; if upd is active high, only the rising edge of upd needs to be sampled.
[0095] When `upd_req` is 1, `upd_hold` becomes 1, and continues until `div_cnt` is full (i.e., `upd_last` is 1), at which point `upd_hold` becomes 0. The AND operation between `upd_hold` and `upd_last` generates a pulse signal `upd_pulse`, which is used to update the divider parameters. The above logic ensures that the new divider coefficients are only updated after the old divider parameters have generated a complete clock signal. The counter counts according to the divider parameter bit width, and generates the `upd_last` signal when the count reaches the divider bit width.
[0096] When upd_pulse is 1, the input divider parameter div_pat is updated to the shift register cur_pat. When upd_pulse is invalid, the shift register cur_pat continuously performs cyclic shifting. The highest bit of the shift register cur_pat[WIDTH] and the original clock are entered into the ICG, eventually generating the output clock clkout.
[0097] Synchronization unit: Used to synchronize the input update indication signal upd and generate a synchronized update request signal.
[0098] The counter is used for periodic counting. For example, when div_pat is 8 bits wide, the counter's counting period is 0 to 7. When the count value reaches 7, it returns to 0 and starts counting again. When an extended scheme is used, such as div_pat being 3, the counter's counting period is 0 to 3.
[0099] Comparator: Used to generate a flag indicating the end of a counting cycle, which signifies the end of a set of regularly changing clock cycles.
[0100] The sustaining circuit is used to generate the divider parameter update request status. `upd_hold` being 1 indicates that a divider parameter update is currently being requested. The generation of `upd_hold` is triggered by `upd_req`. When `upd_req` is 1, `upd_hold` is pulled high, indicating that a divider parameter update is currently being requested. When `upd_last` is 1, `upd_hold` is pulled low, indicating that the divider parameter update has been completed.
[0101] Parameter update circuit: Used to update the divider parameter div_pat to the current divider parameter register, i.e., the shift register cur_pat. When upd_pulse is 1, it indicates that the divider parameter is being updated, because when upd_pulse is 1, upd_last is 1, and a complete clock cycle has ended, so updating the divider parameter at this time is appropriate.
[0102] Frequency divider circuit: The current frequency divider parameter register, i.e., the shift register cur_pat, is cyclically shifted, and the highest bit is used as a gating signal.
[0103] Gating circuit: also known as gated clock unit, which gates the input clock to generate the required clock waveform.
[0104] `div_pattern` is a pattern of a fixed width, where each bit in the pattern indicates whether gating is applied to the original clock. For example:
[0105] 10010010 indicates that 3 out of 8 original clock cycles are enabled and 5 cycles are gated, meaning the generated clock is 3 / 8 of the original clock.
[0106] 10101011 indicates that 5 out of the 8 original clock cycles are enabled and 3 cycles are gated, meaning the generated clock is 5 / 8 of the original clock.
[0107] An 8-bit divider parameter can achieve n / 256 division of the original clock, where n: 1~256.
[0108] In another embodiment, the counting comparison unit in the previous scheme is replaced by comparing the count value with the current frequency divider parameter cur_pat. The result of the comparator, upd_last, is delayed by one clock cycle to generate the gating enable signal div_clk_bit.
[0109] When upd_pulse is 1, the frequency division coefficient div_pat is updated to the enable trigger and cur_pat is output.
[0110] The output clock clkout is a division of the original clock clkin by (div_pat + 1). When the division parameter is 2, the output clock clkout is a division of the original clock clkin by 3; when the division parameter is 5, the output clock clkout is a division of the original clock clkin by 6. When the division parameter is 0, div_clk_bit remains unchanged at 1, and the output clock is the original clock clkin.
[0111] To better achieve the above objectives, the present invention also provides a clock module, wherein at least one frequency divider circuit as described above is included.
[0112] To better achieve the above objectives, the present invention also provides a chip, wherein it includes at least one clock module as described above.
[0113] To better achieve the above objectives, the present invention also provides a computing board for a computing device, wherein it includes at least one of the chips described above.
[0114] To better achieve the above objectives, the present invention also provides a computing device, including a power board, a control board, a connection board, a heat sink, and multiple computing boards. The control board is connected to the computing boards via the connection board. The heat sink is disposed around the computing boards. The power board is used to provide power to the connection board, the control board, the heat sink, and the computing boards. The computing boards are as described above. It should be noted that in the description of the present invention, the terms "horizontal," "vertical," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.
[0115] In other words, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.
Claims
1. A frequency divider circuit, characterized in that, include: A counting comparison unit is used to receive a first clock signal and a comparison reference signal, and output a counting signal; A synchronization unit is used to receive an update indication signal and output an update request signal; A frequency divider parameter update unit is used to receive the counting signal, the update request signal, and the frequency divider parameter, and output a frequency divider clock enable signal. A gated clock unit is used to receive the first clock signal and the frequency-divided clock enable signal, and output a second clock signal; wherein, The frequency and / or duty cycle of the second clock signal are determined according to the frequency division parameter; The frequency division parameter update unit further includes: A parameter update circuit is used to receive the counting signal, an update hold signal, and the frequency division parameter, and output the frequency division clock enable signal; wherein, the update hold signal is generated by the counting signal and the update request signal; The parameter update circuit includes: A second AND gate has a first terminal, a second terminal and a third terminal, wherein the first terminal of the second AND gate is electrically connected to an update hold signal, and the second terminal of the second AND gate is electrically connected to the counting signal; A selector has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of the selector is electrically connected to the frequency division parameter, and the control terminal of the selector is electrically connected to the third terminal of the second AND gate. A shift register has a first terminal, a second terminal, and a third terminal. The first terminal of the shift register is electrically connected to the third terminal of the selector. The second terminal of the shift register is electrically connected to the first clock signal. The third terminal of the shift register is electrically connected to the second terminal of the selector. The third terminal of the shift register outputs a current division parameter. The most significant bit of the current division parameter is electrically connected to the division clock enable signal.
2. The frequency divider circuit as described in claim 1, characterized in that: The frequency division parameter has N bits, and each bit in the frequency division parameter controls the gated clock unit.
3. The frequency divider circuit as described in claim 2, characterized in that: The second clock signal has 2 types. N .
4. The frequency divider circuit as described in claim 1, characterized in that: The counting comparison unit has a first terminal, a second terminal and a third terminal. The first terminal of the counting comparison unit is electrically connected to the first clock signal, the second terminal of the counting comparison unit is electrically connected to the comparison reference signal, and the third terminal of the counting comparison unit is electrically connected to the counting signal.
5. The frequency divider circuit as described in claim 4, characterized in that: The counting comparison unit further includes: A counter having a first terminal and a second terminal, wherein the first terminal of the counter is electrically connected to the first clock signal; A comparator has a first terminal, a second terminal, and a third terminal. The first terminal of the comparator is electrically connected to the second terminal of the counter, the second terminal of the comparator is electrically connected to the comparison reference signal, and the third terminal of the comparator is electrically connected to the counting signal.
6. The frequency divider circuit as described in claim 1, characterized in that: The synchronization unit has a first terminal, a second terminal, and a third terminal. The first terminal of the synchronization unit is electrically connected to the update indication signal, the second terminal of the synchronization unit is electrically connected to the first clock signal, and the third terminal of the synchronization unit is electrically connected to the update request signal.
7. The frequency divider circuit as described in claim 6, characterized in that: The synchronization unit further includes: A first flip-flop has a first terminal, a second terminal and a third terminal, wherein the first terminal of the first flip-flop is electrically connected to the update indication signal and the second terminal of the first flip-flop is electrically connected to the first clock signal. A second flip-flop has a first terminal, a second terminal and a third terminal, wherein the first terminal of the second flip-flop is electrically connected to the third terminal of the first flip-flop, and the second terminal of the second flip-flop is electrically connected to the first clock signal; An XOR gate has a first terminal, a second terminal, and a third terminal. The first terminal of the XOR gate is electrically connected to the third terminal of the first flip-flop, the second terminal of the XOR gate is electrically connected to the third terminal of the second flip-flop, and the third terminal of the XOR gate is electrically connected to the update request signal.
8. The frequency divider circuit as described in claim 1, characterized in that: The frequency division parameter update unit has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of the frequency division parameter update unit is electrically connected to the counting signal, the second terminal of the frequency division parameter update unit is electrically connected to the update request signal, the third terminal of the frequency division parameter update unit is electrically connected to the first clock signal, the fourth terminal of the frequency division parameter update unit is electrically connected to the frequency division parameter, and the fifth terminal of the frequency division parameter update unit is electrically connected to the frequency division clock enable signal.
9. The frequency divider circuit as described in claim 8, characterized in that: The frequency division parameter update unit further includes: A sustaining circuit is used to receive the counting signal and the update request signal and output the update hold signal.
10. The frequency divider circuit as described in claim 9, characterized in that: The sustaining circuit includes: A first inverter has a first terminal and a second terminal, wherein the first terminal of the first inverter is electrically connected to the counting signal; A first AND gate has a first terminal, a second terminal and a third terminal, the first terminal of the first AND gate is electrically connected to the second terminal of the first inverter, and the second terminal of the first AND gate is electrically connected to the update hold signal; A first OR gate has a first terminal, a second terminal and a third terminal, wherein the first terminal of the first OR gate is electrically connected to the third terminal of the first AND gate, and the second terminal of the first OR gate is electrically connected to the update request signal. A third flip-flop has a first terminal, a second terminal, and a third terminal. The first terminal of the third flip-flop is electrically connected to the third terminal of the first OR gate, the second terminal of the third flip-flop is electrically connected to the first clock signal, and the third terminal of the third flip-flop is electrically connected to the update hold signal.
11. The frequency divider circuit as described in claim 1, characterized in that: The gated clock unit has a first terminal, a second terminal, and a third terminal. The first terminal of the gated clock unit is electrically connected to the frequency division clock enable signal, the second terminal of the gated clock unit is electrically connected to the first clock signal, and the third terminal of the gated clock unit is electrically connected to the second clock signal.
12. A frequency divider circuit, characterized in that, include: A counting comparison unit is used to receive a first clock signal and a comparison reference signal, and output a counting signal; A synchronization unit is used to receive an update indication signal and output an update request signal; A frequency divider parameter update unit is used to receive the counting signal, the update request signal, and the frequency divider parameter, and output a frequency divider clock enable signal. A gated clock unit is used to receive the first clock signal and the frequency-divided clock enable signal, and output a second clock signal; wherein, The frequency and / or duty cycle of the second clock signal are determined according to the frequency division parameter; The comparison reference signal is provided by the frequency division parameter update unit, which includes: A parameter update circuit is used to receive the counting signal, an update hold signal and the frequency division parameter, and output the frequency division clock enable signal; The parameter update circuit includes: A fourth AND gate has a first terminal, a second terminal and a third terminal, wherein the first terminal of the fourth AND gate is electrically connected to the update hold signal, and the second terminal of the fourth AND gate is electrically connected to the counting signal; An enable trigger has a first terminal, a second terminal, a third terminal, and an enable terminal. The first terminal of the enable trigger is electrically connected to the frequency division parameter, the second terminal of the enable trigger is electrically connected to the first clock signal, and the third terminal of the enable trigger is electrically connected to the current frequency division parameter. The current frequency division parameter is input to the counting comparison unit as the comparison reference signal. A fifth flip-flop has a first terminal, a second terminal, and a third terminal. The first terminal of the fifth flip-flop is electrically connected to the counting signal, the second terminal of the fifth flip-flop is electrically connected to the first clock signal, and the third terminal of the fifth flip-flop is electrically connected to the frequency divider clock enable signal.
13. The frequency divider circuit as described in claim 12, characterized in that: The frequency division parameter has N bits, and each bit in the frequency division parameter controls the gated clock unit.
14. The frequency divider circuit as described in claim 13, characterized in that: The second clock signal has 2 types. N .
15. The frequency divider circuit as described in claim 12, characterized in that: The counting comparison unit has a first terminal, a second terminal and a third terminal. The first terminal of the counting comparison unit is electrically connected to the first clock signal, the second terminal of the counting comparison unit is electrically connected to the comparison reference signal, and the third terminal of the counting comparison unit is electrically connected to the counting signal.
16. The frequency divider circuit as described in claim 12, characterized in that: The counting comparison unit further includes: A counter having a first terminal and a second terminal, wherein the first terminal of the counter is electrically connected to the first clock signal; A comparator has a first terminal, a second terminal, and a third terminal. The first terminal of the comparator is electrically connected to the second terminal of the counter, the second terminal of the comparator is electrically connected to the comparison reference signal, and the third terminal of the comparator is electrically connected to the counting signal.
17. The frequency divider circuit as described in claim 12, characterized in that: The synchronization unit has a first terminal, a second terminal, and a third terminal. The first terminal of the synchronization unit is electrically connected to the update indication signal, the second terminal of the synchronization unit is electrically connected to the first clock signal, and the third terminal of the synchronization unit is electrically connected to the update request signal.
18. The frequency divider circuit as described in claim 17, characterized in that: The synchronization unit further includes: A first flip-flop has a first terminal, a second terminal and a third terminal, wherein the first terminal of the first flip-flop is electrically connected to the update indication signal and the second terminal of the first flip-flop is electrically connected to the first clock signal. A second flip-flop has a first terminal, a second terminal and a third terminal, wherein the first terminal of the second flip-flop is electrically connected to the third terminal of the first flip-flop, and the second terminal of the second flip-flop is electrically connected to the first clock signal; An XOR gate has a first terminal, a second terminal, and a third terminal. The first terminal of the XOR gate is electrically connected to the third terminal of the first flip-flop, the second terminal of the XOR gate is electrically connected to the third terminal of the second flip-flop, and the third terminal of the XOR gate is electrically connected to the update request signal.
19. The frequency divider circuit as described in claim 12, characterized in that: The frequency division parameter update unit has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal. The first terminal of the frequency division parameter update unit is electrically connected to the counting signal, the second terminal of the frequency division parameter update unit is electrically connected to the update request signal, the third terminal of the frequency division parameter update unit is electrically connected to the first clock signal, the fourth terminal of the frequency division parameter update unit is electrically connected to the frequency division parameter, the fifth terminal of the frequency division parameter update unit is electrically connected to a current frequency division parameter, and the sixth terminal of the frequency division parameter update unit is electrically connected to the frequency division clock enable signal.
20. The frequency divider circuit as described in claim 19, characterized in that: The frequency division parameter update unit further includes: A sustaining circuit is used to receive the counting signal and the update request signal and output the update hold signal.
21. The frequency divider circuit as described in claim 20, characterized in that: The sustaining circuit includes: A second inverter has a first terminal and a second terminal, wherein the first terminal of the second inverter is electrically connected to the counting signal; A third AND gate has a first terminal, a second terminal and a third terminal, wherein the first terminal of the third AND gate is electrically connected to the second terminal of the second inverter, and the second terminal of the third AND gate is electrically connected to the update hold signal; A second OR gate has a first terminal, a second terminal and a third terminal, wherein the first terminal of the second OR gate is electrically connected to the third terminal of the third AND gate, and the second terminal of the second OR gate is electrically connected to the update request signal; A fourth flip-flop has a first terminal, a second terminal, and a third terminal. The first terminal of the fourth flip-flop is electrically connected to the third terminal of the second OR gate, the second terminal of the fourth flip-flop is electrically connected to the first clock signal, and the third terminal of the fourth flip-flop is electrically connected to the update hold signal.
22. The frequency divider circuit as described in claim 12, characterized in that: The value of the frequency division parameter is M, and the ratio between the frequency of the second clock signal and the frequency of the first clock signal is 1 / (M+1).
23. A clock module, characterized in that: It includes at least one frequency divider circuit as described in any one of claims 1-11.
24. A clock module, characterized in that: It includes at least one frequency divider circuit as described in any one of claims 12-22.
25. A chip, characterized in that, It includes at least one clock module as described in claim 24.
26. A computing device, characterized in that, It includes at least one chip as described in claim 25.
Citation Information
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