A semi-parallel look-ahead sc decoder design method and system
By designing a semi-parallel forward-looking SC decoder, combining LLR processing and forward-looking G operations, the high latency problem of the SC decoder is solved, and hardware efficiency is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHINA UNIV OF GEOSCIENCES (WUHAN)
- Filing Date
- 2022-12-26
- Publication Date
- 2026-07-21
Smart Images
Figure CN115882875B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the technical fields of channel coding and 5G mobile communication, and specifically relates to a semi-parallel forward-looking SC decoder design method and system. Background Technology
[0002] Since Professor Erdal Arikan proposed the concept of channel polarization, polar codes, as the only coding scheme rigorously mathematically proven to achieve the Shannon limit for channel capacity, have received widespread attention. Among the decoding methods proposed by Professor Arikan in his paper, the Successive Cancellation (SC) decoding algorithm has good decoding performance and lower algorithm complexity. Furthermore, with the application of polar codes to the control channel coding scheme in 5G enhanced mobile broadband (eMBB) applications in 2016, polar codes have been widely used in the field of channel coding.
[0003] Algorithmically, SC decoding is sequential; the next codeword can only be decoded if the previous codeword is known. This low parallelism results in high decoding latency. Initially proposed tree-based, linear, and pipelined decoder implementations offer high parallelism but also have high hardware complexity. Later, semi-parallel decoding structures, by dividing long data into multiple cycles of computation with a fixed number of units, significantly reduced hardware complexity but still increased latency to some extent. Summary of the Invention
[0004] In view of this, the present invention proposes a semi-parallel prospective SC decoder design method and system, wherein the method includes the following steps:
[0005] S1 and LLR processing modules receive LLR, and the decoder updates the decoding instructions.
[0006] The S2 and LLR processing modules perform operations on the LLR according to the decoding instructions and obtain the decoding results;
[0007] S3. The decoder saves the decoded result and updates parts and modules based on the decoded result;
[0008] The S4 and LLR processing modules continue decoding using the updated parts and modules. After decoding is complete, the decoding output module outputs the result.
[0009] Furthermore, step S1 specifically includes:
[0010] S11: After receiving the LLR, the LLR processing module stores it sequentially in the channel RAM.
[0011] S12. After all LLRs are received, the decoding enable signal is pulled high, and the control module begins to read the control instructions sequentially and updates the control signals required by each module according to the control instructions.
[0012] S13. When the calculated number of LLRs is 2, the decoding stage begins, and the PE module reads two fixed bits from the fixed bit set rom.
[0013] Furthermore, step S2 specifically includes:
[0014] S21, the PE module processes LLR and calculates two intermediate results. The intermediate results f_out and g_out are stored in the internal RAM and the G result RAM, respectively. The G processing unit selects the data based on the input and the output in the G result RAM. The data selector sends the data output in the G result RAM to the PE for processing according to the control signal.
[0015] S22. The LLR received in the channel RAM is the LLR that has been reversed by the transmitter. The LLR in the channel is reversed in advance. According to the number of PEs n, the code length m is divided into m / n groups of data and stored in the channel RAM. The bits of the n LLRs in the group are reversed. The upper half and lower half of the data in the channel RAM are interleaved and combined.
[0016] S23. When reading LLR from the channel RAM, the values are taken from high to low order. The upper and lower parts are written from high to low with intervals between addresses to the internal RAM and the G result RAM, thus achieving the same reverse order operation as the sending end.
[0017] S24. When the number of LLR operations is 2, perform two-bit decoding, calculate the two-bit decoding result through a special PE, and output it.
[0018] Furthermore, step S3 specifically includes:
[0019] S31. After executing step S24, two decoded bits are obtained. The decoded bits are passed to the decoding output module and the partial sum module. After each decoding is completed, the two bits are stored in the shift register. When the shift register is full, the result is stored in the decoding result RAM.
[0020] S32. After the decoding result enters the partial sum module, it first enters the partial sum network. The matrix rom in the partial sum module stores the P-order Kronecker matrix. Each update reads 2P bits of data, that is, the two row vectors of the matrix, and inputs them into the partial sum network.
[0021] S33. After completing the partial and network updates, the output partial sums are processed by the partial sum reversal module. If the required partial sum is less than P, the required number of partial sums are read according to the offset in the control signal, and the required partial sums are fully reversed. If the required number of partial sums is greater than or equal to P, all P-bit partial sums are fully reversed.
[0022] S34. After updating the parts and network, use it during the forward G calculation.
[0023] Furthermore, step S4 specifically includes:
[0024] S41. When the number of partial sums required for the look-ahead G operation is greater than P, 4PQ LLRs are taken from the G result RAM, where P represents the number of PE units in the PE module and Q represents the bit width of the quantized LLR. 2PQ LLRs are obtained by selecting 2P partial sums. The number of partial sums required for each cycle is 2P. The partial sums are updated while the look-ahead G operation is performed.
[0025] S42. Complete the forward-looking semi-parallel decoding part and network update in 2-bit decoding. After decoding is completed, read data from the decoding result RAM in cycles, output the data address, and pull up the decoding output enable signal.
[0026] One type of semi-parallel forward-looking SC decoder design system includes: a control module, an LLR processing module, a partial sum module, and a decoder output module;
[0027] The control module includes: a control signal ROM, a control signal generation module, and a fixed bit set ROM;
[0028] The LLR processing module includes: channel RAM, internal RAM, G result RAM, G processing unit, data selector, and PE module; the PE module comprises two parts: a special PE module and a regular PE module.
[0029] The parts and modules include: matrix ROM, part and network, part and reverse module, and part and control;
[0030] The decoding output module includes: a decoding result RAM and a shift register;
[0031] The LLR processing module receives the channel LLR input and stores it in the channel RAM. The internal RAM and G result RAM are used to store the F operation result and look-ahead G operation result calculated by the PE module when processing the LLR. The G processing unit selects the output in the G result RAM based on the input part. The data selector sends the data output in the G result RAM to the PE for processing according to the control signal. The two-bit decoding result is calculated by the special PE and output.
[0032] The aforementioned part and module, and the decoding output module, are used to receive a two-bit decoding result calculated by a special PE. After each decoding operation, the two-bit result is stored in a shift register; when the register is full, it is stored in the decoding result RAM. After the decoding result enters the part and module, it first enters the part and network. The matrix ROM in the part and module stores a P-order Kronecker matrix. Each update reads 2P bits of data, i.e., the two row vectors of the matrix, and inputs them into the part and network. After the part and network update is completed, the output part and sum passes through the part and reverse module. When the required part and sum is less than P, according to the offset in the control signal, the required number of part and sums are read, and the required part and sum are fully reversed. When the number of partial sums is greater than or equal to P, all P-bit partial sums are reversed. After updating the partial sum network, when the number of partial sums required for the look-ahead G operation is greater than P, 4PQ LLRs are taken from the G result RAM, and 2PQ LLRs are obtained by selecting from 2P partial sums. P represents the number of PE units in the PE module, and Q represents the bit width of the quantized LLR. The number of partial sums required in each cycle is 2P. The partial sums are updated simultaneously with the look-ahead G operation. The look-ahead semi-parallel decoding partial sum network update is completed every 2 bits. After decoding is completed, data is read from the decoding result RAM in cycles, and the data address is output. The decoding output enable signal is pulled high.
[0033] The control module is used to release control signals. When the decoding enable signal is high, the control signal rom reads the address from the control signal generation module. The control signal generation module starts to read the control instructions stored in the control signal rom in sequence and updates the control signals required by each module according to the control instructions. When the calculated LLR number is 2, the decoding stage is entered and the PE reads two fixed bits from the fixed bit set rom.
[0034] The beneficial effects of the technical solution provided by this invention are:
[0035] This invention reduces the latency of the semi-parallel SC decoder by introducing a forward-looking G operation, thereby improving the hardware implementation efficiency. Attached Figure Description
[0036] Figure 1 This is a flowchart of a semi-parallel, forward-looking SC decoder design method according to the present invention;
[0037] Figure 2 This is a block diagram of a semi-parallel, forward-looking SC decoder design system according to the present invention.
[0038] Figure 3 This is a block diagram of the internal structure of the control module in an embodiment of the present invention;
[0039] Figure 4 This is a block diagram of the internal structure of the LLR processing module in an embodiment of the present invention;
[0040] Figure 5 This is a structural block diagram of some parts and modules of an embodiment of the present invention;
[0041] Figure 6 This is a structural block diagram of the decoding output module in an embodiment of the present invention.
[0042] Figure 7 These are the 9 control information bits in the decoding instructions of this embodiment of the invention;
[0043] Figure 8 This is a diagram of the internal structure of the PE in this embodiment of the invention, applicable to forward-looking G operations and two-bit decoding;
[0044] Figure 9 This is a storage and scheduling diagram of an LLR decoder with a code length of 32 and a PE number of 4, according to an embodiment of the present invention.
[0045] Figure 10 The internal structure diagram of the network in this embodiment of the invention is GP, which is the input Kronecker matrix, and the network is updated internally.
[0046] Figure 11 This is a portion of the code with a length of 8 and an updated data flow graph in an embodiment of the present invention. Detailed Implementation
[0047] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described below with reference to the accompanying drawings.
[0048] Please refer to Figure 2 , Figure 2 This is a block diagram of a semi-parallel forward-looking SC decoder design system according to the present invention. The semi-parallel forward-looking SC decoder design system includes: a control module, an LLR processing module, a partial and a final module, and a decoding output module.
[0049] refer to Figure 3 , Figure 3 This is a block diagram of the internal structure of the control module in an embodiment of the present invention.
[0050] The control module includes: a control signal ROM, a control signal generation module, and a fixed bit set ROM.
[0051] The control module is used to release control signals. When the decoding enable signal is high, the control signal ROM reads the address from the control signal generation module. The control signal generation module starts to read the control instructions stored in the control signal ROM in sequence and updates the control signals required by each module according to the control instructions. When the calculated LLR number is 2, the decoding stage begins and the PE reads two fixed bits from the fixed bit set ROM.
[0052] refer to Figure 4 , Figure 4This is a block diagram of the internal structure of the LLR processing module in an embodiment of the present invention.
[0053] The LLR processing module includes: channel RAM, internal RAM, G result RAM, G processing unit, data selector, and PE module; the PE module consists of two parts: a special PE module and a regular PE module. Their functions are as follows:
[0054] Ordinary PE: The PE processes LLR using a sign and amplitude separation method. The numerical processing module has the functions of a full adder and a full subtractor. Bi is the borrow of the full subtractor, diff is the result of the full subtractor, and sum is the result of the full adder. TtoS can realize the data conversion from binary two's complement to sign plus amplitude form. Finally, the sign and amplitude are merged to obtain three results: f_out, g0_out, and g1_out. g0_out and g1_out are concatenated to obtain the two results of G operation, g_out, with a bit width of 2Q.
[0055] Special PEs: Special PEs can be decoded using intermediate calculated values, which can shorten latency and reduce complexity. Figure 6 The dashed line is a unique structure; it represents the 0th PE unit in the PE module. In the numerical detection module, if either of the two LLR amplitude values is 0, the output f0 is high; otherwise, it is low. When sum and abs_diff are both low, f1 or f2 outputs high; otherwise, it outputs low. The condition signal in the four-input selector below is a two-bit fixed bit.
[0056] The channel input LLR is stored in the channel RAM. The channel LLR is read as input for calculation, and the output includes the F operation result and the look-ahead G operation result. The look-ahead G operation result is for partial sum positions, assuming the G operation on the input yields two G operation results: a partial sum of 0 or 1, which are stored in their respective RAMs. The internal RAM and the G result RAM are used to store the F operation result and the look-ahead G operation result calculated by the PE module when processing the LLR. The G processing unit selects the look-ahead G result based on the partial sum, uses the selection result as input for the next F operation, and sends the data output from the G result RAM to the PE for processing. The data selector selects different signals according to the control signal to perform different operations. A special PE calculates and outputs the two-bit decoding result.
[0057] refer to Figure 5 , Figure 5 This is a structural block diagram of some parts and modules of an embodiment of the present invention.
[0058] The components and modules include: matrix ROM, network components, reverse order modules, and control components.
[0059] The partial sum module and decoding output module receive the two-bit decoding result calculated by a special PE. After each decoding operation, the two bits are stored in a shift register; when the register is full, they are stored in the decoding result RAM. The decoding result enters the partial sum module, first passing through the partial sum network. The matrix ROM in the partial sum module stores a P-order Kronecker matrix. Each update reads 2P bits of data (two row vectors of the matrix) and inputs them to the partial sum network. After the partial sum network update is complete, the output partial sum passes through the partial sum reversal module. When the required partial sum is less than P, the required number of partial sums are read according to the offset in the control signal. The partial sums need to be fully reversed; when the number of required partial sums is greater than or equal to P, all P-bit partial sums are fully reversed; after updating the partial sum network, when the number of required partial sums for the look-ahead G operation is greater than P, 4PQ LLRs are taken from the G result RAM, and 2PQ LLRs are obtained by selecting from 2P partial sums. The number of partial sums required in each cycle is 2P. The partial sums are updated simultaneously with the look-ahead G operation; the look-ahead semi-parallel decoding partial sum network update is completed every 2 bits of decoding. After decoding is completed, data is read from the decoding result RAM in cycles, and the data address is output. The decoding output enable signal is pulled high.
[0060] refer to Figure 6 , Figure 6 This is a structural block diagram of the decoding output module in an embodiment of the present invention.
[0061] The decoding output module includes: decoding result RAM and shift register.
[0062] The decoding output module stores the results in a shift register, passes them in blocks to the decoding result RAM, and finally outputs all the decoding results.
[0063] refer to Figure 1 , Figure 1 This is a flowchart of a semi-parallel, forward-looking SC decoder design method according to the present invention.
[0064] A semi-parallel prospective SC decoder design method includes the following steps:
[0065] The S1 and LLR processing modules receive the channel log-likelihood ratio (LLR) and the decoder updates the decoding instructions.
[0066] S11. After receiving the channel LLR, the decoder stores it sequentially in the channel RAM, such as... Figure 7 As shown, the decoder's instructions consist of 9 bits, generated by software. The information represented by the arrow is stored in the instruction set ROM. The 9-bit decoding instructions are divided into three parts, and their functions and specific meanings are as follows:
[0067] Bits 8-6: Provide control information for the folding high-performance components and network. Bit 8 being 1 indicates the cycle of the first half of this stage, and 0 indicates the cycle of the second half of this stage. Bits 7 and 6 being 1 indicate the last and first computation cycles of this stage, respectively.
[0068] Bits 5-4: Indicate the type of operation at this stage. When both bits are 01, it indicates an F operation; when they are 10, it indicates a forward-looking G operation.
[0069] Bits 3-0: Used to indicate the number of LLRs that need to be processed during the decoding stage. For example, if the lower four bits are 1010 (decimal 10), it means that the number of LLRs that need to be processed is 2 to the power of 10 (i.e., 1024).
[0070] S12. After completing the reception of all LLR channels, the decoding enable signal is pulled high, and the control module begins to read the control instructions sequentially and updates the control signals required by each module according to the control instructions.
[0071] S13. When the calculated number of LLRs is 2, the decoding stage begins, and the PE module reads two fixed bits from the fixed bit set rom.
[0072] The S2 and LLR processing modules perform operations on the LLR according to the decoding instructions and obtain the decoding results.
[0073] S21, Channel transmission LLR is stored in Figure 4 In the channel RAM of the LLR processing module, P in the figure represents the number of PE units in the PE module, and Q represents the bit width of the LLR after quantization. Figure 8 The diagram shows the internal structure of a single PE unit. Solid lines represent the general internal structure of a PE, while dashed lines represent the additional structures of a special PE with two-bit decoding capabilities. Based on the PE structure, the intermediate results f_out and g_out are stored in the internal RAM and the G result RAM, respectively. Figure 4 In the process, the G processing unit selects data based on the input portion and the output in the G result RAM. The data width input to the PE is 2PQ. The data selector determines which set of data to send to the PE for processing based on the control signal.
[0074] S22, The LLR received in the channel RAM has been reversed by the transmitter, such as... Figure 9This diagram illustrates the storage and scheduling of LLRs, showing the data storage in each RAM when the code length is 32 and the number of PEs is 4. STAGE represents the decoding stage, L is the LLR result of the F operation, with the first bit of its index indicating the decoding stage and the second bit indicating the LLR index value. G is the LLR result of the forward G operation; the first two bits of the index have the same meaning as L, and the third bit indicates whether the corresponding partial sum of the LLR is 0 or 1. When the third bit of the G index is omitted, it indicates the result of the two-bit LLR after partial sum selection. C represents the calculation operation. The steps for reversing the channel LLR in advance are as follows:
[0075] S221. Divide the 32-bit code length into 8 groups based on the PE number 4. Reverse the bit order of the 4 LLRs within each group, such as... Figure 7 The first group of data in the intermediate channel RAM is {L 5,0 L 5,2 L 5,1 L 5,3}, where the first subscript represents STAGE and the second subscript represents the index of the input / output PE data.
[0076] S222, The upper and lower halves are interspersed and combined, such as the second group of data after the first group being the lower half of the first group {L 5,16 L 5,18 L 5,17 L 5,19}
[0077] S23, Figure 9 As shown, data is only read from the channel RAM at STAGE5. The address allocation for each stage in the G result RAM is the same as that of the internal RAM, but the bit width is twice that of the internal RAM. During calculations, to conform to the folded sections and network update characteristics described below, as follows... Figure 9 C11-C14 in the LLR are read in descending order of value, while the upper and lower parts are written to the internal RAM and the G result RAM simultaneously in descending order of value with address intervals. Figure 7 The process of operating on the result of G is omitted in the text, so as to achieve the same reverse operation as the sending end.
[0078] S24. Refer to the table below. The table below is the data schedule table for a decoder with a code length of 32 and a PE number of 4. The table lists the data schedule of the decoder. The first row (CC) in the table represents the cycle number, and the second and third rows represent the data read and written. The first index represents the STAGE, and the second index represents the LLR index of the input and output PE data, for example, L... 5,12&28 This indicates that: STAGE is 5, two data points are fed into PE at once, with LLR indices of 12 and 28 respectively; type is the calculation type for this cycle. When the number of LLR operations is 2, two-bit decoding is performed, and the two-bit decoding result is calculated and output through a special PE.
[0079]
[0080] S3. The decoder saves the decoded result and updates parts and modules based on the decoded result.
[0081] S31. After executing step S24, two decoded bits are obtained. These decoded bits are then passed to the decoding module and the partial sum module. Figure 6 The decoding output module has a K-bit shift register. After each decoding operation, two bits of the result are stored in the shift register. Once the K bits are full, the result is stored in the decoding result RAM.
[0082] S32, Figure 5 After the Chinese decoding result enters the partial sum module, it first enters the partial sum network. The matrix ROM in the partial sum module stores a P-order Kronecker matrix. To update the two-bit decoding result within one cycle, each update reads 2P bits of data, i.e., the two row vectors of the matrix, and inputs them into the partial sum network. For example... Figure 10 In the portions and network structures shown, where G P The input is a P-order Kronecker matrix, and the two vectors correspond to two decoding bits.
[0083] S33. After completing the part and network update, the output part and the part that needs to be passed Figure 5 The inversion module in the partial sum network can update the partial sum of up to P bits. Its inversion logic is as follows:
[0084] Case 1: When the required partial sum is less than P, it is necessary to read the required number of partial sums starting from a certain bit according to the offset in the control signal, and then reverse the required partial sums completely.
[0085] Case 2: When the required partial sum is greater than or equal to P, reverse the order of all P-bit partial sums.
[0086] S34. After updating the parts and network, use it during the forward G calculation.
[0087] The S4 and LLR processing modules continue decoding using the updated parts and modules. After decoding is complete, the decoding output module outputs the result.
[0088] S41. In case 2 of the reverse order in S33, when the sum and number of parts required for the forward G operation are greater than P, it is necessary to start from... Figure 4 4PQ LLRs are extracted from the G result RAM. 2PQ LLRs are obtained through 2P partial sum selections. Therefore, the number of partial sums required for each cycle is 2P, and the partial sums need to be updated simultaneously with the lookahead G operation. For example... Figure 11 It is the part with a code length of 8 and the update flow graph.
[0089] S42. The discussion proceeds with decoding every 2 bits. The prospective semi-parallel decoding part with P=2 and the network update process are as follows:
[0090] At the second bit, the partial sum network update obtains the partial sum data. After completing the g operation, the superscript of the partial sum data represents the stage (decoding stage), and the subscript represents the index of the partial sum.
[0091] For the 4th bit, it needs to be calculated within one cycle. Figure 11 The first half of the first phase because and The same, just need to respectively with XOR operation You can then obtain the required portion;
[0092] At bit 6, the partial and network updates are obtained. Complete the g operation;
[0093] At the 8th bit, the partial sum is now known. and It takes two cycles to complete the forward G operation, which is performed from high to low bits. The first cycle needs to calculate... and Figure 10 middle and same, Can be used directly Get, will and Perform XOR operations on each to obtain The second cycle needs to be calculated. and use and XOR each to obtain and and The same, then the obtained and Perform XOR operations on each to obtain Completed the update of the part and the part.
[0094] After decoding is complete, proceed in stages from Figure 8 The decoded result is read from RAM, and the data address is output. The decoded output enable signal is then pulled high.
[0095] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A semi-parallel prospective SC decoder design method, characterized in that, Includes the following steps: S1 and LLR processing modules receive LLR, and the decoder updates the decoding instructions. The S2 and LLR processing modules perform operations on the LLR according to the decoding instructions and obtain the decoding results; S3. The decoder saves the decoded result and updates parts and modules based on the decoded result; S4 and LLR processing modules continue decoding using the updated parts and modules. After decoding is complete, the decoding output module outputs the result. Step S2 is as follows: S21. The PE module processes LLR and calculates two intermediate results. The intermediate results f_out and g_out are stored in the internal RAM and the G result RAM, respectively. The G processing unit selects the output in the G result RAM based on the input and the output in the G result RAM. The data selector sends the data output in the G result RAM to the PE module for processing according to the control signal. S22. The LLR received in the channel RAM is the LLR that has been reversed by the transmitter. The LLR in the channel is reversed in advance. According to the number of PEs n, the code length m is divided into m / n groups of data and stored in the channel RAM. The bits of the n LLRs in the group are reversed. The upper half and lower half of the data in the channel RAM are interleaved and combined. S23. When reading LLR from the channel RAM, the values are taken from high to low order. The upper and lower parts are written from high to low with intervals between addresses to the internal RAM and the G result RAM, thus achieving the same reverse order operation as the sending end. S24. When the number of LLR operations is 2, perform two-bit decoding, calculate the two-bit decoding result through a special PE module and output it.
2. The semi-parallel prospective SC decoder design method according to claim 1, characterized in that, Step S1 is as follows: S11: After receiving the LLR, the LLR processing module stores it sequentially in the channel RAM. S12. After all LLRs are received, the decoding enable signal is pulled high, and the control module begins to read the control instructions sequentially and updates the control signals required by each module according to the control instructions. S13. When the calculated number of LLRs is 2, the decoding stage begins, and the PE module reads two fixed bits from the fixed bit set rom.
3. The semi-parallel prospective SC decoder design method according to claim 1, characterized in that, Step S3 is as follows: S31. After executing step S24, two decoded bits are obtained. The decoded bits are passed to the decoding output module and the partial sum module. After each decoding is completed, the two bits are stored in the shift register. When the shift register is full, the result is stored in the decoding result RAM. S32. After the decoding result enters the partial sum module, it first enters the partial sum network. The matrix rom in the partial sum module stores the P-order Kronecker matrix. Each update reads 2P bits of data, that is, the two row vectors of the matrix, and inputs them into the partial sum network. S33. After completing the partial and network updates, the output partial sums are processed by the partial sum reversal module. If the required partial sum is less than P, the required number of partial sums are read according to the offset in the control signal, and the required partial sums are fully reversed. If the required number of partial sums is greater than or equal to P, all P-bit partial sums are fully reversed. S34. After updating the parts and network, use it during the forward G calculation.
4. The semi-parallel prospective SC decoder design method according to claim 3, characterized in that, Step S4 is as follows: S41. When the number of partial sums required for the look-ahead G operation is greater than P, 4PQ LLRs are taken from the G result RAM, where P represents the number of PE units in the PE module and Q represents the bit width of the quantized LLR. 2PQ LLRs are obtained by selecting 2P partial sums. The number of partial sums required for each cycle is 2P. The partial sums are updated while the look-ahead G operation is performed. S42. Complete the forward-looking semi-parallel decoding part and network update in 2-bit decoding. After decoding is completed, read data from the decoding result RAM in cycles, output the data address, and pull up the decoding output enable signal.
5. A semi-parallel forward-looking SC decoder design system, characterized in that, A semi-parallel forward-looking SC decoder design method as described in any one of claims 1-4 includes: a control module, an LLR processing module, a partial sum module, and a decoder output module; The control module includes: a control signal ROM, a control signal generation module, and a fixed bit set ROM; The LLR processing module includes: channel RAM, internal RAM, G result RAM, G processing unit, data selector, and PE module; the PE module comprises two parts: a special PE module and a regular PE module. The parts and modules include: matrix ROM, part and network, part and reverse module, and part and control; The decoding output module includes: a decoding result RAM and a shift register; The LLR processing module receives the channel LLR input and stores it in the channel RAM. The internal RAM and G result RAM store the F operation result and look-ahead G operation result calculated by the ordinary PE module when processing LLR. The G processing unit selects the output in the G result RAM based on the input and the output in the G result RAM. The data selector sends the data output in the G result RAM to the special PE module for processing according to the control signal. The special PE module calculates and outputs the two-bit decoding result. The aforementioned partial sum module and decoding output module are used to receive the two-bit decoding result calculated by the special PE module. After each decoding operation, the two-bit result is stored in a shift register; once full, it is stored in the decoding result RAM. After the decoding result enters the partial sum module, it first enters the partial sum network. The matrix ROM in the partial sum module stores a P-order Kronecker matrix. Each update reads 2P bits of data, i.e., the two row vectors of the matrix, and inputs them into the partial sum network. After the partial sum network update is completed, the output partial sum passes through the partial sum reversal module. If the required partial sum is less than P, the required number of partial sums are read according to the offset in the control signal. The required partial sums are completely reversed; when the number of required partial sums is greater than or equal to P, all P-bit partial sums are completely reversed; after updating the partial sum network, when the number of partial sums required for the look-ahead G operation is greater than P, 4PQ LLRs are taken from the G result RAM, and 2PQ LLRs are obtained by selecting from 2P partial sums. The number of partial sums required in each cycle is 2P. The partial sums are updated simultaneously with the look-ahead G operation; the look-ahead semi-parallel decoding partial sum network update is completed every 2 bits of decoding. After decoding is completed, data is read from the decoding result RAM in cycles, and the data address is output. The decoding output enable signal is pulled high. The control module is used to release control signals. When the decoding enable signal is high, the control signal ROM reads the address from the control signal generation module. The control signal generation module starts to read the control instructions stored in the control signal ROM in sequence and updates the control signals required by each module according to the control instructions. When the calculated LLR number is 2, the decoding stage is entered and the PE module reads two fixed bits from the fixed bit set ROM.