Techniques for performing wireless communication signal data decoding

Abstract

Devices, systems, and techniques for decoding quasi-cyclic low-density parity-check, QC-LDPC, encoded data for fifth generation (5G) new radio (NR). In at least one embodiment, a processor includes one or more circuits to select one or more data decoding operations to decode one or more 5G signals based at least in part on a sparsity of data received by the processor, wherein the one or more decoding operations are minimum-sum and LDPC decoding operations, and the one or more circuits are to perform a first type of operation in response to a row degree of a QC-LDPC base graph being less than or equal to a predetermined threshold, and to perform a second type of operation in response to the row degree being greater than the predetermined threshold, wherein the row degree is indicative of a number of non-empty elements in a row and is related to the sparsity of data.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Patent Application No. 17 / 153,795, filed January 20, 2021, entitled “Technique to Perform Decodeing of Wireless Communications Signal Data,” the entire contents of which are incorporated herein by reference and for all purposes. Technical Field

[0003] At least one embodiment relates to processing resources for decoding wireless communications. For example, at least one embodiment relates to a parallel processor or computing system for decoding coded signal data according to various novel techniques described herein. Background Technology

[0004] Processing wireless communication signals and data consumes significant computing resources and time. Methods for decoding wireless communication signals and data can be improved. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating a low-density parity-check (LDPC) decoding environment according to at least one embodiment;

[0006] Figure 2 This is a block diagram illustrating a fifth-generation (5G) signal processing environment according to at least one embodiment;

[0007] Figure 3 This is a schematic diagram illustrating a quasi-cyclic low-density parity-check (QC-LDPC) base map according to at least one embodiment;

[0008] Figure 4 It is a schematic diagram illustrating a matrix represented by a quasi-cyclic low-density parity-check (QC-LDPC) base map according to at least one embodiment;

[0009] Figure 5 A histogram of row degree values ​​for a quasi-cyclic low-density parity-check (QC-LDPC) basemap according to at least one embodiment is shown.

[0010] Figure 6 The low-density parity-check (LDPC) decoder input according to at least one embodiment is shown;

[0011] Figure 7 This is a schematic diagram illustrating the variable-to-verification (V2C) message update according to at least one embodiment of the min-sum technique;

[0012] Figure 8 This is a schematic diagram illustrating the minimal and technical update of a Check to Variable (C2V) message according to at least one embodiment;

[0013] Figure 9 This is a schematic diagram illustrating the variable-to-verification (V2C) message update of a second verification node according to at least one embodiment;

[0014] Figure 10 This is a diagram illustrating the update of a Check to Variable (C2V) message from a second check node according to at least one embodiment;

[0015] Figure 11 A flowchart illustrating a technique for selecting and performing decoding operations according to at least one embodiment is shown;

[0016] Figure 12 A flowchart of a parallel decoding technique according to at least one embodiment is shown;

[0017] Figure 13 An example data center system according to at least one embodiment is shown;

[0018] Figure 14A An example of an autonomous vehicle according to at least one embodiment is shown;

[0019] Figure 14B The illustration shows an embodiment according to at least one of the embodiments. Figure 14A Examples of camera positions and field of view for autonomous vehicles.

[0020] Figure 14C This is an illustration based on at least one embodiment. Figure 14A A block diagram of an example system architecture for autonomous vehicles.

[0021] Figure 14D The illustration is based on at least one embodiment for use in cloud-based servers and Figure 14A A schematic diagram of a system for communication between autonomous vehicles.

[0022] Figure 15 This is a block diagram illustrating a computer system according to at least one embodiment;

[0023] Figure 16 This is a block diagram illustrating a computer system according to at least one embodiment;

[0024] Figure 17 A computer system according to at least one embodiment is shown;

[0025] Figure 18 A computer system according to at least one embodiment is shown;

[0026] Figure 19A A computer system according to at least one embodiment is shown;

[0027] Figure 19B A computer system according to at least one embodiment is shown;

[0028] Figure 19C A computer system according to at least one embodiment is shown;

[0029] Figure 19D A computer system according to at least one embodiment is shown;

[0030] Figure 19E and 19F A shared programming model according to at least one embodiment is shown;

[0031] Figure 20 An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0032] Figure 21A and Figure 21B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0033] Figure 22A and Figure 22B Additional exemplary graphics processor logic according to at least one embodiment is shown;

[0034] Figure 23 A computer system according to at least one embodiment is shown;

[0035] Figure 24A A parallel processor according to at least one embodiment is shown;

[0036] Figure 24B A partitioning unit according to at least one embodiment is shown;

[0037] Figure 24C A processing cluster according to at least one embodiment is shown;

[0038] Figure 24D A graphics multiprocessor according to at least one embodiment is shown;

[0039] Figure 25 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated;

[0040] Figure 26 A graphics processor according to at least one embodiment is shown;

[0041] Figure 27 It is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0042] Figure 28 At least a portion of a graphics processor according to one or more embodiments is shown;

[0043] Figure 29 At least a portion of a graphics processor according to one or more embodiments is shown;

[0044] Figure 30 At least a portion of a graphics processor according to one or more embodiments is shown;

[0045] Figure 31 It is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0046] Figure 32 It is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0047] Figure 33A and Figure 33B The thread execution logic is shown, which includes an array of processing elements of a graphics processor core;

[0048] Figure 34 A parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0049] Figure 35 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated;

[0050] Figure 36 A memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0051] Figure 37 A streaming multiprocessor according to at least one embodiment is shown;

[0052] Figure 38 The illustration shows a network for transmitting data within a 5G wireless communication network according to at least one embodiment;

[0053] Figure 39 The illustration depicts a network architecture for a 5G LTE wireless network according to at least one embodiment;

[0054] Figure 40 This is a diagram illustrating some basic functions of a mobile telecommunications network / system operating according to LTE and 5G principles according to at least one embodiment;

[0055] Figure 41 A radio access network, which may be part of a 5G network architecture according to at least one embodiment, is shown;

[0056] Figure 42 An example illustration of a 5G mobile communication system using multiple different types of devices according to at least one embodiment is provided;

[0057] Figure 43 An example advanced system according to at least one embodiment is shown;

[0058] Figure 44 The architecture of a network system according to at least one embodiment is shown;

[0059] Figure 45 Example components of a device according to at least one embodiment are shown;

[0060] Figure 46 An example interface of a baseband circuit according to at least one embodiment is shown;

[0061] Figure 47 An example of an uplink channel according to at least one embodiment is shown;

[0062] Figure 48 The architecture of a network system according to at least one embodiment is shown;

[0063] Figure 49 A control plane protocol stack according to at least one embodiment is shown;

[0064] Figure 50 A user plane protocol stack according to at least one embodiment is shown;

[0065] Figure 51 The components of a core network according to at least one embodiment are shown; and

[0066] Figure 52 Components of a system supporting Network Function Virtualization (NFV) according to at least one embodiment are shown. Detailed Implementation

[0067] Figure 1 This is a block diagram illustrating a low-density parity-check (LDPC) decoding environment 100 according to at least one embodiment. In at least one embodiment, the LDPC decoder 102 includes a processor 104, a first memory 106, and a second memory 108. In at least one embodiment, the first memory 106 is a high-performance memory (e.g., registers of the processor 104) closely associated with the processor 104. In at least one embodiment, the second memory 108 is accessible by the processor 104 but has a lower performance level associated with the processor 104 than the first memory 106. In at least one embodiment, the LDPC decoder 102 is a quasi-cyclic LDPC (QC-LDPC) decoder that uses one or more base maps 110 and cyclic matrices 112 to perform decoding operations.

[0068] In at least one embodiment, the LDPC decoder 102 decodes the encoded input data 114 to generate output data 116. In at least one embodiment, the encoded input data 114 includes data representing information bits and data representing parity bits. In at least one embodiment, the encoded input data 114 is in the form of a log-likelihood ratio (LLR). In at least one embodiment, the LLR of the encoded input data 114 is represented as a floating-point number.

[0069] In at least one embodiment, the LDPC decoder 102 performs one or more data decoding operations at least partially based on the basemap to generate output data 116, for example by selecting the basemap from the basemap 110 at least partially based on the basemap identifier 118 (e.g., an indicator identifying a specific basemap to be used in a QC-LDPC basemap). In at least one embodiment, the data decoding operation is an LDPC decoding operation (e.g., a QC-LDPC decoding operation). In at least one embodiment, the LDPC decoder 102 performs data decoding operations on a subset of the rows of the basemap, starting from the beginning of the basemap, for example by using the row number identified by the row number 120. In at least one embodiment, the LDPC decoder 102 performs the data decoding operation at least partially based on a cyclic matrix (e.g., from cyclic matrix 112) represented by non-empty elements in the rows of the basemap. In at least one embodiment, the cyclic matrix 112 is a shifted identity matrix. In at least one embodiment, the LDPC decoder 102 also performs the data decoding operation at least partially based on a lifting size Z that specifies the size of the cyclic matrix to be used.

[0070] In at least one embodiment, the LDPC decoder 102 decodes signal data for the 3GPP 5G New Radio (NR) wireless communication protocol. In at least one embodiment, the LDPC decoder 102 performs data decoding operations using LDPC codes employed by a wireless communication protocol for forward error correction (FEC), wherein the FEC scheme uses redundancy in the transmitted data to allow the receiver to correct some errors that occur during transmission over a noisy communication channel. In at least one embodiment, the LDPC decoder 102 decodes the signal data according to a quasi-cyclic (QC) LDPC encoder / decoder scheme with a basemap (BG). In at least one embodiment, the LDPC decoder 102 is at least partially based on the BG specified by the 3GPP 5G specification (e.g., the basemap described in Section 5.3.2 of 3GPP Technical Specification (TS) 38.212, Release 15, v15.9.0). Figure 1 or base Figure 2The decoding operation is performed. In at least one embodiment, the BG structure describes a family of encoding and decoding operations and includes codewords of different sizes and code rates (e.g., for different signal-to-noise ratio environments). In at least one embodiment, the LDPC decoder 102 receives a basemap identifier 118 and a row number 120 from another component of the 5G NR signal processing pipeline (e.g., the base station scheduler). In at least one embodiment, the LDPC decoder 102 also receives a boost size Z (not shown for clarity) from another component of the signal processing pipeline.

[0071] In at least one embodiment, the LDPC decoder 102 employs a row-level approach that applies an updated "soft" estimate to each bit of consecutive rows in the base graph. In at least one embodiment, the LDPC decoder 102 uses the same soft estimate as input to all used base graph rows and updates the soft estimate as a group before the next iteration. In at least one embodiment, the LDPC decoder 102 performs the decoding operation at least in part based on a min-sum algorithm, a mathematical approximation of the sum-product algorithm. In at least one embodiment, the min-sum method of the LDPC decoder 102 replaces the transcendental function with magnitude comparisons and sign operations of the soft bit estimates.

[0072] In at least one embodiment, the LDPC decoder 102 uses a hybrid basemap row processing method. This method applies a first type of data decoding operation to basemap rows (e.g., check nodes) whose basemap row degree is less than or equal to a predefined threshold (e.g., a predefined threshold), where the basemap row degree is the number of non-empty elements in the row. In at least one embodiment, the LDPC decoder 102 uses a second type of data decoding operation to basemap rows whose basemap row degree is greater than the predefined threshold. In at least one embodiment, the first type of data decoding operation includes a box-plus operation, which has the advantage of increased parallelism but stores the entire update sequence of the basemap row. In at least one embodiment, the second type of data decoding operation includes a compressed check-to-value (C2V) operation of a compressed minimum sum method. In at least one embodiment, the second type of data decoding operation includes a compressed C2V algorithm. In at least one embodiment, the LDPC decoder 102 selects the data decoding operation at least in part based on the degree of the specific basemap row to be processed and performs the selected operation (e.g., a box-plus operation or a compressed C2V operation). In at least one embodiment, the LDPC decoder 102 selects a first type of data decoding operation in response to a row degree less than or equal to a predefined threshold, and selects a second type of data decoding operation in response to a row degree greater than the predefined threshold. In at least one embodiment, the LDPC decoder 102 selects a first type of data decoding operation in response to a data sparsity less than or equal to a predefined threshold, and selects a second type of data decoding operation in response to a data sparsity greater than the predefined threshold, wherein the data is represented by rows of a QC-LDPC basemap. In at least one embodiment, the LDPC decoder 102 selects a data decoding operation at least in part based on the sparsity of the data received by the processor 104, wherein the sparsity of the data is related to the degree of a particular basemap row.

[0073] In at least one embodiment, a hybrid approach offers performance advantages compared to conventional methods that use a single technique to perform decoding. In at least one embodiment, selecting a compressed C2V method when the row degree exceeds a predefined threshold provides a performance advantage because using only the box-plus method requires slower memory (e.g., second memory 108) when intermediate results do not fit in registers (e.g., first memory 106), which degrades the performance of the otherwise ideal box-plus method. In at least one embodiment, the LDPC decoder 102 selects the compressed C2V method when the row degree exceeds a predefined threshold (e.g., when using the box-plus method might lead to register overflow and use of second memory 108). In at least one embodiment, the box-plus method is an efficient instruction-level implementation but has increased storage requirements for C2V messages, while the compressed C2V method has reduced storage requirements for compressed C2V messages but has a higher instruction count for compression and extraction. In at least one embodiment, the LDPC decoder 102 uses a hybrid approach that retains the performance advantages of the box-plus method for most rows and reduces the disadvantages of using the box-plus method to handle high-degree rows.

[0074] Figure 2 This is a block diagram illustrating a fifth-generation (5G) new radio (NR) signal processing environment 200 including a low-density parity-check (LDPC) decoder 202 according to at least one embodiment. In at least one embodiment, at least one aspect of the LDPC decoder 202 is performed in parallel. In at least one embodiment, at least one aspect of the LDPC decoder 202 is, for example, related to... Figure 1 and / or Figures 3-12 At least one of the described LDPC decoders (e.g., LDPC decoder 102) is used to perform LDPC decoding 202. In at least one embodiment, LDPC decoding 202 is performed by at least one circuit, at least one system, at least one processor, at least one graphics processing unit, at least one parallel processor and / or at least some other processors or components described and / or shown herein. In at least one embodiment, LDPC decoder 102 performs LDPC decoding 202.

[0075] In at least one embodiment, at least some 5G NR signal processing environment 200 is included in a virtual radio access network (vRAN). In at least one embodiment, the 5G NR signal processing environment 200 includes a low physical (PHY) layer 208, a high PHY layer 210, a media access control (MAC) layer 212, a radio link control (RLC) layer 214, and a packet data convergence protocol (PDCP) layer 216. In at least one embodiment, the low PHY layer 208 and the high PHY layer 210 are referred to as PHY layers, rather than being referred to as separately. In at least one embodiment, the 5G vRAN stack 206 communicates with at least one user equipment (UE) 218, shown as UE1 to UEn, via a radio frequency (RF) layer 220 and a radio channel 222. In at least one embodiment, the 5G vRAN stack 206 communicates with the 5G packet core 224 using Internet Protocol (IP) packets.

[0076] In at least one embodiment, the low PHY layer 208 and the high PHY layer 210 include signal processing components 226, shown in an extended block diagram between the analog-to-digital converter (ADC) / digital-to-analog converter (DAC) 228 and the MAC layer 212. In at least one embodiment, the uplink path 230 includes orthogonal frequency division multiplexing (OFDM) demodulation 232, receiver (Rx) beamforming 234, channel estimation 236, channel equalization 238, scrambling demodulation 239, rate matching removal 240, low-density parity check (LDPC) decoding 202, and transport block cyclic redundancy check (CRC) 242. In at least one embodiment, scrambling demodulation 239 is referred to as soft demapping. In at least one embodiment, a soft demapping unit performs scrambling demodulation 239. In at least one embodiment, the downlink path 244 includes CRC segmentation 246, LDPC coding 248, rate matching 250, scrambling modulation 252, precoding 254, transmit (Tx) beamforming 256, and OFDM modulation 258. In at least one embodiment, the downlink PHY layer operates as a virtual network function (VNF). In at least one embodiment, the VNF running the downlink PHY layer operates in a clustered computing environment. In at least one embodiment, the downlink PHY layer processes data related to the multiple-input multiple-output (MIMO) layer.

[0077] In at least one embodiment, at least one aspect of the uplink path 230, including LDPC decoder 202, is executed in a software-defined radio environment (e.g., using at least one GPU of LDPC decoder 102). In at least one embodiment, the uplink path 230 is performance-sensitive, and as per [reference to...] Figure 1 Environment 100, About Figure 3-9 One or more figures shown or described Figure 11Technology 1100 and / or Figure 12 The LDPC decoding 202 described in at least one of the technologies 1200 provides advantages over conventional technologies by reducing latency, increasing throughput and / or providing other improvements in computation, time, power and / or other resource utilization.

[0078] Figure 3 This is a schematic diagram illustrating a quasi-cyclic low-density parity-check (QC-LDPC) basemap 300 according to at least one embodiment. In at least one embodiment, the QC-LDPC basemap 300 is constructed to have a set of rows 302 representing check nodes and a set of columns 304 representing variable nodes. In at least one embodiment, the QC-LDPC basemap 300 includes empty elements such as empty element 306 and non-empty elements such as non-empty element 308. In at least one embodiment, empty squares in the QC-LDPC basemap 300 are empty elements, and solid squares in the QC-LDPC basemap 300 are non-empty elements. In at least one embodiment, the QC-LDPC basemap 300 is stored in a data structure (e.g., a table, array, matrix, list, or some other suitable data structure), and it should be understood that, for clarity and ease of understanding, it is presented in a simplified manner. Figure 3 The visual representation of the QC-LDPC basemap 300 is shown. In at least one embodiment, the data structure representing the QC-LDPC basemap 300 is stored in the basemap 110 of the LDPC decoder 102.

[0079] In at least one embodiment, the QC-LDPC base map 300 corresponds to the base map specified in Section 5.3.2 of 3GPP Technical Specification (TS) 38.212, Version 15, v15.9.0. Figure 1 (BG1). In at least one embodiment, the QC-LDPC basemap 300 is a 46×68 basemap, which can be expanded by increasing the size Z to create different parity check matrices. In at least one embodiment, the QC-LDPC basemap 300 has a minimum row degree of 3 and a maximum row degree of 19. In at least one embodiment, the LDPC decoder 102 determines the basemap to be used for decoding (e.g., basemap identifier 118) based at least in part on parameters (e.g., basemap identifier 118) determined by another part of the signal processing pipeline (e.g., the scheduler in the base station). Figure 1 or base Figure 2 The parameter specifies whether to use BG1 or BG2. In at least one embodiment, BG2, which is not shown for clarity, is a 42×52 base... Figure 2 It is used for smaller code blocks and lower code rates.

[0080] Figure 4This is a schematic diagram illustrating a matrix represented by a base map 400 according to at least one embodiment. In at least one embodiment, base map 400 is a QC-LDPC base map. In at least one embodiment, base map 400 includes empty elements represented by empty squares, such as empty element 402, and non-empty elements represented by solid squares, such as non-empty element 404. In at least one embodiment, the empty elements of base map 400 represent zero matrices such as zero matrix 406, which are shown as being represented by the last element in the first row of base map 400. In at least one embodiment, the non-empty elements of base map 400 represent cyclic matrices, such as cyclic matrix 408, which are shown as being represented by the first element in the last row of base map 400. In at least one embodiment, cyclic matrix 408 is a Z-by-Z cyclic matrix (e.g., a shifted identity matrix), where Z is the lift size. In at least one embodiment, the shift amount of the cyclic matrix in base map 400 varies with the position of the matrix in base map 400. In at least one embodiment, the shift amount of the cyclic matrix corresponds to those specified in the 3GPP 5G NR specification.

[0081] Figure 5 A histogram of row degree values ​​of a QC-LDPC base graph according to at least one embodiment is shown. In at least one embodiment, the row degree value of the QC-LDPC base graph is the number of non-empty entries in a particular row. In at least one embodiment, a first histogram 500 shows the distribution of row degree values ​​of a first base graph named BG1. In at least one embodiment, BG1 corresponds to... Figure 3 The QC-LDPC basemap 300. In at least one embodiment, the second histogram 502 shows the distribution of row degree values ​​of the second basemap named BG2. In at least one embodiment, BG2 corresponds to the basemap described in 3GPP 5G NR TS38.212, version 15, v15.9.0, section 5.3.2. Figure 2 In at least one embodiment, the third histogram 504 shows the combined distribution of row degree values ​​of the two base graphs. In at least one embodiment, the third histogram 504 shows a combined histogram of BG1 and BG2. In at least one embodiment, the LDPC decoder 102 uses a predefined row degree threshold 10 to select the type of decoding operation, resulting in mostly checkbox addition operations rather than compressed C2V operations, as can be seen by viewing the first histogram 500, where a small subset of rows are shown as having a row degree greater than 10.

[0082] Figure 6An LDPC decoder input according to at least one embodiment is illustrated. In at least one embodiment, Figure 600 represents a pair of values ​​as input 602, located at a first distance from a first axis 606 and a second distance 608 from a second axis 610. In at least one embodiment, Figure 600 illustrates an example input using two-bit Quadrature Phase Shift Keying (QPSK). In at least one embodiment, input 602 is an equal complex value. In at least one embodiment, an increase in the likelihood of distance indicator bit 0 along the positive direction from the first axis 606 is 0, and an increase in the likelihood of distance indicator bit 0 along the negative direction from the first axis 606 is 1. In at least one embodiment, an increase in the likelihood of distance indicator bit 1 along the positive direction from the second axis 610 is 0, and an increase in the likelihood of distance indicator bit 1 along the negative direction from the second axis 610 is 1. In at least one embodiment, as shown in the figure, bit 1 of input 602 is likely to be 1, bit 0 of input 602 is likely to be 0, and is shown to be associated with first point 612, second point 614, third point 616 and fourth point 618, each point having a very high likelihood of bit patterns of 10, 11, 00 and 01 respectively.

[0083] In at least one embodiment, for each decoded bit u i and each observation y i The log-likelihood ratio (LLR) is defined as:

[0084]

[0085] In at least one embodiment, a soft demapper (e.g., performing scrambling and demodulation 239) provides initial LLR values. In at least one embodiment, an LDPC decoder (e.g., LDPC decoder 102 performing LDPC decoding 202) receives LLR values ​​after they have been derate-matched (e.g., at derate-match 240). In at least one embodiment, an LDPC decoder (e.g., LDPC decoder 102) updates the LLR values. In at least one embodiment, the updated LLR values ​​are estimates referred to as posterior probabilities (APP). In at least one embodiment, the bit outputs (e.g., hard values) are described by pseudocode: u_i = (APP(u_i) >= 0) ? 0 : 1;

[0086] In at least one embodiment, normalization minimization and techniques (e.g., performed by LDPC decoder 102) are described regarding initialization, Verification-to-Variable (V2C) message updates, Verification-to-Variable (C2V) updates, and APP updates. In at least one embodiment, the V2C message updates, C2V updates, and APP updates are performed iteratively for N iterations. In at least one embodiment, N is a predetermined number. In at least one embodiment, initialization is described as follows:

[0087]

[0088] In at least one embodiment, V2C message updates are described as follows:

[0089]

[0090] In at least one embodiment, C2V message updates are described as follows:

[0091]

[0092] In at least one embodiment, the APP update is described as follows:

[0093]

[0094] In at least one embodiment, the LDPC decoder (e.g., LDPC decoder 102) selects one or more data decoding operations to perform C2V message updates for each specific row (e.g., check node) of the QC-LDPC basemap. In at least one embodiment, the LDPC decoder selects a box-plus operator or a compressed C2V technique based at least in part on the row degree of the QC-LDPC basemap, where the row degree is the number of non-empty elements in the row. In at least one embodiment, the LDPC decoder selects a box-plus operator or a compressed C2V technique based at least in part on the sparsity of the data, where the sparsity of the data is related to the row degree (e.g., negatively related when the data is a cyclic matrix represented by row elements). In at least one embodiment, the LDPC decoder selects a box-plus operator if the row degree is less than or equal to a predefined threshold, and selects compressed C2V if the row degree is greater than the predefined threshold. In at least one embodiment, the LDPC decoder selects a box-plus operator if the data sparsity (e.g., in a cyclic matrix represented by elements in the basemap rows) is greater than or equal to a predefined threshold, and selects compressed C2V if the data sparsity is less than the predefined threshold.

[0095] In at least one embodiment, the box addition operator is described as follows:

[0096] bp(a,b)=sgn(a)sgn(b)min(|a|,|b|)

[0097] In the last embodiment, when the LDPC decoder select box is added, the C2V update from check node i to variable node j is described as follows:

[0098]

[0099] In at least one embodiment, when the LDPC decoder selects the compressed C2V technique, a single line of C2V messages in the QC-LDPC basemap is compressed by storing two minimum V2C values ​​(e.g., min0 and min1), an index of the minimum V2C value (e.g., min0_index), and a symbol for each V2C value. In at least one embodiment, when the LDPC decoder selects the compressed C2V operation, the C2V update from check node i to variable node j is described as follows:

[0100]

[0101] In at least one embodiment, the pseudocode used by the LDPC decoder to compress the data structure of the C2V message is:

[0102]

[0103] Figure 7 This is a diagram illustrating a minimum and technically-based variable-to-verification (V2C) message update according to at least one embodiment. In at least one embodiment, the V2C update uses a hierarchical (e.g., row) scheduling messaging technique. In at least one embodiment, an LDPC decoder (e.g., LDPC decoder 102) performs the V2C message update at least partially based on a QC-LDPC basemap 700. In at least one embodiment, the LDPC decoder performs the V2C message update based on an APP value set 702 associated with a first row 704 of the QC-LDPC basemap 700. In at least one embodiment, the LDPC decoder uses APP values ​​from the APP value set 702 to update a first verification node. In at least one embodiment, the V2C message update is described as follows:

[0104]

[0105] In at least one embodiment, the LDPC decoder initializes the APP value set before performing V2C message updates based at least in part on values ​​from the soft demapper (e.g., after scrambling and demodulation 239 and rate matching 240).

[0106] Figure 8This is a schematic diagram illustrating a minimal and technical check-to-variable (C2V) message update according to at least one embodiment. In at least one embodiment, the C2V message update uses a hierarchical (e.g., row) scheduling messaging technique. In at least one embodiment, an LDPC decoder (e.g., LDPC decoder 102) performs the C2V message update at least partially based on a QC-LDPC basemap 800. In at least one embodiment, the QC-LDPC basemap 800 is a QC-LDPC basemap 700. In at least one embodiment, the LDPC decoder performs a C2V message update from a first row 804 (e.g., a first check node) of the QC-LDPC basemap 800 to an APP value set 802. In at least one embodiment, the LDPC decoder adds the contribution from the first check node (e.g., the first row 804) to the APP value set 802. In at least one embodiment, the C2V message update is indicated by arrows from non-empty elements of the first row 804 to specific APP values ​​in the APP value set 802. In at least one embodiment, the C2V message update is described as follows:

[0107] and

[0108]

[0109] In at least one embodiment, the LDPC decoder performs C2V message updates (e.g., as shown in line 804) based at least in part on the updated line information in the first line after the V2C update. Figure 7 (As shown).

[0110] Figure 9 This is a schematic diagram illustrating the update of a Verification-to-Variable (V2C) message for a second verification node according to at least one embodiment. In at least one embodiment, Figure 9 V2C message update occurs Figure 8 Following the C2V message update. In at least one embodiment, the LDPC decoder (e.g., LDPC decoder 102) performs the V2C message update at least partially based on the QC-LDPC basemap 900. In at least one embodiment, the QC-LDPC basemap 900 is the QC-LDPC basemap 800. In at least one embodiment, the LDPC decoder performs the V2C message update at least partially based on the APP value set 902 and the second row 906 (e.g., the second check node) of the QC-LDPC basemap 900. In at least one embodiment, the APP value set 902 includes... Figure 8The value in APP value 902 after the C2V message update. In at least one embodiment, the LDPC decoder uses the new APP value from APP value set 902 (e.g., after the contribution from the first check node is added to the APP value in APP value set 802) to update the second check node (e.g., second row 906).

[0111] Figure 10 This is a schematic diagram illustrating the update of a Check to Variable (C2V) message from a second check node according to at least one embodiment. In at least one embodiment, Figure 10 The C2V message update occurs Figure 9 Following the V2C message update. In at least one embodiment, the LDPC decoder (e.g., LDPC decoder 102) performs the C2V message update at least partially based on the QC-LDPC basemap 1000. In at least one embodiment, the QC-LDPC basemap 1000 is the QC-LDPC basemap 900. In at least one embodiment, the LDPC decoder performs the C2V message update from the second row 1006 of the QC-LDPC basemap 1000 to the APP value set 1002. In at least one embodiment, the C2V message update is indicated by arrows from non-empty elements of the second row 1006 to specific APP values ​​in the APP value set 1002. In at least one embodiment, the LDPC decoder is at least partially based on the updated row information in the second row 1006 after the V2C update (e.g., such as...). Figure 9 (As shown) to execute Figure 10 C2V message update.

[0112] In at least one embodiment, V2C and C2V message updates are performed for all parity nodes (e.g., the number of rows used from the QC-LDPC basemap) in relation to... Figure 9 and Figure 10 The description continues in a similar manner. In at least one embodiment, the LDPC iteration includes sequential APP updates from all parity nodes (e.g., specified by the number of rows to be used from the base graph). In at least one embodiment, the LDPC decoder performs N sequential APP update iterations from all parity nodes. In at least one embodiment, N is a predetermined number of iterations. In at least one embodiment, hierarchical scheduling converges faster than conventional methods using flooding scheduling because the updated APP values ​​are used faster than with flooding scheduling.

[0113] Figure 11A flowchart illustrating a technique 1100 for selecting and performing decoding operations according to at least one embodiment is shown. In at least one embodiment, technique 1100 is performed by at least one circuit, at least one system, at least one processor, at least one graphics processing unit, at least one parallel processor and / or at least some other processors or components described and / or shown herein. In at least one embodiment, an LDPC decoder 102 performs at least one aspect of technique 1100. In at least one embodiment, multiple threads of at least one thread block execute at least one aspect of technique 1100 in parallel.

[0114] In at least one embodiment, at block 1102, technique 1100 includes determining a base map to use. In at least one embodiment, at block 1104, technique 1100 includes determining the number of rows to use from the base map. In at least one embodiment, determining the number of rows is based at least in part on parameters received by LDPC decoder 102 (e.g., number of rows 120). In at least one embodiment, at block 1106, technique 1100 includes determining the type of decoding operation to be used for each of the determined number of rows, at least in part on the row degree. In at least one embodiment, determining the type of decoding operation includes selecting one or more data decoding operations (e.g., box-add or compression C2V) to decode one or more 5G NR signals, at least in part on the sparsity of the data. In at least one embodiment, determining the type of decoding operation includes selecting one or more data decoding operations, at least in part on the row degree of the base map. In at least one embodiment, the sparsity of the data corresponds to the sparsity of the data in both the cyclic matrix and the zero matrix represented by elements in a particular row of the base map. In at least one embodiment, at block 1108, technique 1100 includes performing the determined decoding operation. In at least one embodiment, at block 1110, technique 1100 includes performing additional actions. In at least one embodiment, performing additional actions includes storing decoded data (e.g., in one or more memories such as first memory 106 and / or second memory 108). In at least one embodiment, performing additional actions includes sending a retransmission request for data that has not been corrected by performing the decoding operation.

[0115] Figure 12 A flowchart of a parallel decoding technique 1200 according to at least one embodiment is shown. In at least one embodiment, technique 1200 is executed by at least one circuit, at least one system, at least one processor, at least one graphics processing unit, at least one parallel processor, and / or at least some other processors or components thereof described and / or shown herein. In at least one embodiment, an LDPC decoder 102 executes at least one aspect of technique 1200. In at least one embodiment, multiple threads of at least one thread block execute at least one aspect of technique 1200 in parallel.

[0116] In at least one embodiment, technology 1200 is... Figure 11 The method of performing a determined decoding operation is described in block 1108. In at least one embodiment, in block 1202, technique 1200 includes determining non-empty elements of a specific row of a basemap to be processed. In at least one embodiment, in block 1204, technique 1200 includes determining a cyclic matrix corresponding to the determined non-empty elements. In at least one embodiment, in block 1206, technique 1200 includes assigning threads to rows of the determined cyclic matrix. In at least one embodiment, in block 1208, technique 1200 includes performing a decoding operation (e.g., having a thread in...) using the assigned thread. Figure 11 Block 1106 defines the block addition or compression of the C2V operation (QC-LDPC decoding operation). In at least one embodiment, in block 1210, technique 1200 includes performing additional actions. In at least one embodiment, performing additional actions includes storing decoded data. In at least one embodiment, performing additional actions includes sending a retransmission request for data that has not passed error correction by performing the decoding operation.

[0117] Data Center

[0118] Figure 13 An example data center 1300 that can be used with at least one embodiment is shown. In at least one embodiment, the data center 1300 includes a data center infrastructure layer 1310, a framework layer 1320, a software layer 1330, and an application layer 1340.

[0119] In at least one embodiment, such as Figure 13 As shown, the data center infrastructure layer 1310 may include a resource coordinator 1312, grouped computing resources 1314, and node computing resources (“nodes CR”) 1316(1)-1316(N), where “N” represents any integer, a positive integer. In at least one embodiment, nodes CR 1316(1)-1316(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 1316(1)-1316(N) may be servers having one or more of the aforementioned computing resources.

[0120] In at least one embodiment, the grouped computing resources 1314 may include individual groups (not shown) of node CRs housed in one or more racks, or a plurality of racks (also not shown) housed in data centers in various geographical locations. In at least one embodiment, the individual groups of node CRs within the grouped computing resources 1314 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0121] In at least one embodiment, resource coordinator 1312 may be configured or otherwise control one or more nodes CR1316(1)-1316(N) and / or grouped computing resources 1314. In at least one embodiment, resource coordinator 1312 may include a software design infrastructure (“SDI”) management entity for data center 1300. In at least one embodiment, resource coordinator may include hardware, software, or some combination thereof.

[0122] In at least one embodiment, such as Figure 13As shown, framework layer 1320 includes a job scheduler 1332, a configuration manager 1334, a resource manager 1336, and a distributed file system 1338. In at least one embodiment, framework layer 1320 may include a framework of software 1332 supporting software layer 1330 and / or one or more applications 1342 supporting application layer 1340. In at least one embodiment, software 1332 or application 1342 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1320 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark") which can leverage distributed file system 1338 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 1332 may include Spark drivers to facilitate the scheduling of workloads supported by the various layers of data center 1300. In at least one embodiment, configuration manager 1334 may be able to configure different layers, such as software layer 1330 and framework layer 1320 including Spark and distributed file system 1338 for supporting large-scale data processing. In at least one embodiment, resource manager 1336 is able to manage cluster or group computing resources mapped to or allocated to support distributed file system 1338 and job scheduler 1332. In at least one embodiment, cluster or group computing resources may include group computing resources 1314 on data center infrastructure layer 1310. In at least one embodiment, resource manager 1336 may coordinate with resource coordinator 1312 to manage these mapped or allocated computing resources.

[0123] In at least one embodiment, the software 1332 included in the software layer 1330 may include software used by at least a portion of the nodes CR1316(1)-1316(N), the grouped computing resources 1314, and / or the distributed file system 1338 of the framework layer 1320. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0124] In at least one embodiment, the one or more applications 1342 included in the application layer 1340 may include one or more types of applications used by at least a portion of nodes CR1316(1)-1316(N), grouped computing resources 1314, and / or the distributed file system 1338 of the framework layer 1320. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0125] In at least one embodiment, any of the configuration manager 1334, resource manager 1336, and resource coordinator 1312 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 1300 and can prevent underutilization and / or poor performance of the data center.

[0126] In at least one embodiment, data center 1300 may include tools, services, software, or other resources to train one or more machine learning models or to use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 1300. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 1300 by using weight parameters calculated through one or more training techniques described herein.

[0127] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0128] In at least one embodiment, regarding Figure 13 At least one component shown or described is used to achieve the combination Figure 1-12The described technologies and / or functions. In at least one embodiment, at least one of the packet computing resources 1314 and node CR1316 is used to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to a row in the QC-LDPC basemap). In at least one embodiment, at least one of the packet computing resources 1314 and node CR1316 is used to perform the selected data decoding operation (e.g., a frame-plus operation or a compressed C2V operation). In at least one embodiment, at least one of the packet computing resources 1314 and node CR1316 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technology 1100, and / or technology 1200.

[0129] Figure 14A An example of an autonomous vehicle 1400 according to at least one embodiment is shown. In at least one embodiment, the autonomous vehicle 1400 (which may alternatively be referred to herein as "vehicle 1400") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle capable of accommodating one or more passengers. In at least one embodiment, vehicle 1400 may be a semi-tractor-trailer for hauling goods. In at least one embodiment, vehicle 1400 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0130] Autonomous vehicles can be described according to the levels of automation defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation in their standard “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., standard number J3016-2011406, published June 15, 2014; standard number J3016-201609, published September 30, 2016; and previous and future versions of this standard). In one or more embodiments, vehicle 1400 may be able to function according to one or more of the levels of autonomous driving from Level 1 to Level 5. For example, in at least one embodiment, vehicle 1400 may be able to perform conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5).

[0131] In at least one embodiment, vehicle 1400 may include, but is not limited to, components such as chassis, body, wheels (e.g., 2, 4, 6, 14, 114, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1400 may include, but is not limited to, propulsion system 1450, such as an internal combustion engine, a hybrid powertrain, a fully electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1450 may be connected to the drivetrain of vehicle 1400, which may include, but is not limited to, a transmission, to enable propulsion of vehicle 1400. In at least one embodiment, propulsion system 1450 may be controlled in response to receiving a signal from throttle / accelerator 1452.

[0132] In at least one embodiment, when the propulsion system 1450 is operating (e.g., when the vehicle 1400 is traveling), the steering system 1454 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 1400 (e.g., along a desired path or route). In at least one embodiment, the steering system 1454 may receive signals from the steering actuator 1456. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, the brake sensor system 1446 may be used to operate the vehicle brakes in response to signals received from the brake actuator 1448 and / or brake sensors.

[0133] In at least one embodiment, the controller 1436 may include, but is not limited to, one or more system-on-chips (“SoCs”). Figure 14AA controller 1436 (not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1400. For example, in at least one embodiment, controller 1436 may send signals to operate vehicle braking via brake actuator 1448, to operate steering system 1454 via one or more steering actuators 1456, and to operate propulsion system 1450 via one or more throttles / accelerators 1452. In at least one embodiment, one or more controllers 1436 may include one or more onboard (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a driver in driving vehicle 1400. In at least one embodiment, one or more controllers 1436 may include a first controller 1436 for autonomous driving functions, a second controller 1436 for functional safety functions, a third controller 1436 for artificial intelligence functions (e.g., computer vision), a fourth controller 1436 for infotainment functions, a fifth controller 1436 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 1436 may handle two or more of the above functions, and two or more controllers 1436 may handle a single function and / or any combination thereof.

[0134] In at least one embodiment, one or more controllers 1436 provide signals for controlling one or more components and / or systems of vehicle 1400 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data can be received from sensors, including but not limited to one or more Global Navigation Satellite System (“GNSS”) sensors 1458 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 1460, one or more ultrasonic sensors 1462, one or more LIDAR sensors 1464, one or more inertial measurement unit (IMU) sensors 1466 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1496, one or more stereo cameras 1468, one or more wide-angle cameras 1470 (e.g., fisheye cameras), one or more infrared cameras 1472, one or more surround cameras 1474 (e.g., 360-degree cameras), and remote cameras (…). Figure 14A (not shown in the image), medium-range camera ( Figure 14A(Not shown in the image) One or more speed sensors 1444 (e.g., for measuring the speed of vehicle 1400), one or more vibration sensors 1442, one or more steering sensors 1440, one or more brake sensors (e.g., as part of brake sensor system 1446) and / or other sensor types are received.

[0135] In at least one embodiment, one or more controllers 1436 may receive input (e.g., represented by input data) from the dashboard 1432 of the vehicle 1400 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1434, a voice signaler, a speaker, and / or other components of the vehicle 1400. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high-definition map). Figure 14A The HMI display 1434 may display information such as (not shown in the image), location data (e.g., the location of vehicle 1400, for example on a map), direction, the location of other vehicles (e.g., occupancy raster), information about objects, and the state of objects perceived by one or more controllers 1436. For example, in at least one embodiment, the HMI display 1434 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving operations that the vehicle has already made, is making, or will make (e.g., changing lanes now, exiting exit 34B within two miles, etc.).

[0136] In at least one embodiment, vehicle 1400 further includes a network interface 1424 that can communicate over one or more networks using one or more wireless antennas 1426 and / or one or more modems. For example, in at least one embodiment, network interface 1424 may be able to communicate over Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multicarrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 1426 may also enable communication between objects in the environment (e.g., vehicles, mobile devices) using one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (hereinafter “LPWAN”) (e.g., LoRaWAN, SigFox, etc. protocols).

[0137] In at least one embodiment, regarding Figure 14A At least one component shown or described is used to achieve the combination Figure 1-12The described techniques and / or functions. In at least one embodiment, regarding... Figure 1-12 The described technologies and / or functions can receive and decode information from vehicle 1400 (e.g., at a base station, such as a gNodeB) for its autonomous operation, and / or can be used to provide a remote operator with the ability to remotely control vehicle 1400.

[0138] Figure 14B The illustration shows an embodiment according to at least one of the embodiments. Figure 14A Examples of camera positions and fields of view for the autonomous vehicle 1400. In at least one embodiment, the camera and its respective field of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 1400.

[0139] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera suitable for use with components and / or systems of vehicle 1400. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 140 fps, 240 fps, etc. In at least one embodiment, the camera may be able to use a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red-to-clear (“RCCC”) color filter array, a red-to-clear-blue (“RCCB”) color filter array, a red-blue-green (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera with an array of RCCC, RCCB and / or RBGC color filters, may be used to improve photosensitivity.

[0140] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0141] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (3D-printed) assembly, to cut out stray light and reflections within the vehicle 1400 (e.g., reflections from the dashboard in the windshield mirror), which may interfere with the camera's image data capture capabilities. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly may be 3D-printed custom-made such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras may also be integrated within four pillars at each corner of the cabin.

[0142] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view including a portion of the environment in front of the vehicle 1400 can be used for surround view and, with the assistance of one or more controllers 1436 and / or control SoCs, to help identify the forward path and obstacles, thereby providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (e.g., traffic sign recognition).

[0143] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal-oxide-semiconductor”) color imager. In at least one embodiment, a wide-angle camera 1470 can be used to sense objects entering from the periphery (e.g., pedestrians, crosswalkers, or bicycles). Although in Figure 14B Only one wide-angle camera 1470 is shown; however, in other embodiments, the vehicle 1400 may have any number (including zero) of wide-angle cameras. In at least one embodiment, any number of remote cameras 1498 (e.g., a pair of remote stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, the remote camera 1498 can also be used for object detection and classification, as well as basic object tracking.

[0144] In at least one embodiment, any number of stereo cameras 1468 may also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1468 may include an integrated control unit comprising a scalable processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 1400, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1468 may include, but are not limited to, a compact stereo vision sensor, which may include, but is not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that can measure the distance from the vehicle 1400 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1468 may also be used in addition to those described herein.

[0145] In at least one embodiment, a camera (e.g., a side-view camera) having a field of view including a portion of the environment on the side of the vehicle 1400 can be used for surround viewing, thereby providing information for creating and updating the occupied grid, and generating a side collision warning. For example, in at least one embodiment, a surround camera 1474 (e.g., as...) Figure 14B The four surround cameras 1474 shown can be positioned on the vehicle 1400. In at least one embodiment, one or more surround cameras 1474 may include, but are not limited to, any number and combination of wide-angle cameras 1470, one or more fisheye lenses, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye lens cameras may be located at the front, rear, and sides of the vehicle 1400. In at least one embodiment, the vehicle 1400 may use three surround cameras 1474 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0146] In at least one embodiment, a camera (e.g., a rear-view camera) having a field of view including a portion of the environment behind the vehicle 1400 can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy raster. In at least one embodiment, a wide variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1498 and / or one or more mid-range cameras 1476, one or more stereo cameras 1468, one or more infrared cameras 1472, etc.), as described herein.

[0147] In at least one embodiment, regarding Figure 14B At least one component shown or described is used to achieve the combination Figure 1-12 The described techniques and / or functions. In at least one embodiment, combined with Figure 1-12 The described technologies and / or functions can receive and decode information from vehicle 1400 (e.g., at a base station, such as a gNodeB) for its autonomous operation, and / or can be used to provide a remote operator with the ability to remotely control vehicle 1400.

[0148] Figure 14C The illustration shows an embodiment according to at least one of the embodiments. Figure 14A A block diagram of an example system architecture for an autonomous vehicle 1400. In at least one embodiment, Figure 14C Each of one or more components, one or more features, and one or more systems of vehicle 1400 is shown connected via bus 1402. In at least one embodiment, bus 1402 may include, but is not limited to, a CAN data interface (which may alternatively be referred to herein as “CAN bus”). In at least one embodiment, CAN may be a network within vehicle 1400 used to help control various features and functions of vehicle 1400, such as brake actuation, acceleration, braking, steering, windshield wipers, etc. In one embodiment, bus 1402 may be configured to have dozens or even hundreds of nodes, each node having its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 1402 can be read to find steering wheel angle, ground speed, engine rotation speed (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1402 may be an ASIL B compliant CAN bus.

[0149] In at least one embodiment, FlexRay and / or Ethernet may be used in addition to or from CAN. In at least one embodiment, there may be any number of buses 1402, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 1402 may be used to perform different functions and / or may be used for redundancy. For example, a first bus 1402 may be used for a collision avoidance function, and a second bus 1402 may be used for actuation control. In at least one embodiment, each bus 1402 may communicate with any component of vehicle 1400, and two or more buses 1402 may communicate with the same component. In at least one embodiment, each of any number of system-on-chip (“SoC”) 1404, each of one or more controllers 1436, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of vehicle 1400) and may be connected to a common bus, such as a CAN bus.

[0150] In at least one embodiment, vehicle 1400 may include one or more controllers 1436, such as those described herein. Figure 14A As described above. In at least one embodiment, controller 1436 can be used for a variety of functions. In at least one embodiment, controller 1436 can be coupled to any of various other components and systems of vehicle 1400 and can be used to control vehicle 1400, artificial intelligence of vehicle 1400, infotainment and / or other functions of vehicle 1400.

[0151] In at least one embodiment, vehicle 1400 may include any number of SoCs 1404. In at least one embodiment, each of the SoCs 1404 may include, but is not limited to, a central processing unit (“one or more CPUs”) 1406, a graphics processing unit (“one or more GPUs”) 1408, one or more processors 1410, one or more caches 1412, one or more accelerators 1414, one or more data storage devices 1416, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1404 may be used to control vehicle 1400 on various platforms and systems. For example, in at least one embodiment, one or more SoCs 1404 may be combined with a high-definition (“HD”) map 1422 in a system (e.g., the system of vehicle 1400), the high-definition map 1422 being accessible from one or more servers via a network interface 1424. Figure 14C(Not shown in the image) Get map refresh and / or update.

[0152] In at least one embodiment, one or more CPUs 1406 may include CPU clusters or CPU complexes (which may alternatively be referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1406 may include multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more CPUs 1406 may include eight cores in an intercoupled multiprocessor configuration. In at least one embodiment, one or more CPUs 1406 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., 2MB L2 cache). In at least one embodiment, one or more CPUs 1406 (e.g., CCPLEX) may be configured to support simultaneous cluster operation, such that any combination of clusters of one or more CPUs 1406 can be active at any given time.

[0153] In at least one embodiment, one or more CPUs 1406 may implement power management functions, including but not limited to one or more of the following features: automatic clock gating of individual hardware modules to conserve dynamic power when idle; clock gating of each core when the core is not actively executing instructions due to executing Wait for Interrupt (“WFI”) / Event Wait (“WFE”) instructions; independent power supply for each core; independent clock gating for each core cluster when all cores are clock-gated or power-gated; and / or independent power gating for each core cluster when all cores are power-gated. In at least one embodiment, one or more CPUs 1406 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state for cores, clusters, and CCPLEX inputs. In at least one embodiment, the processing core may support a simplified power state input sequence in software, wherein the work is offloaded to the microcode.

[0154] In at least one embodiment, one or more GPUs 1408 may include integrated GPUs (or "iGPUs" herein). In at least one embodiment, one or more GPUs 1408 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1408 may use an enhanced tensor instruction set. In one embodiment, one or more GPUs 1408 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a Level 1 ("L1") cache (e.g., an L1 cache with at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 514KB of storage capacity). In at least one embodiment, one or more GPUs 1408 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1408 may use a computation application programming interface (API). In at least one embodiment, one or more GPUs 1408 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0155] In at least one embodiment, one or more GPU 1408s may be power-optimized for optimal performance in automotive and embedded use cases. For example, in one embodiment, one or more GPU 1408s may be fabricated on FinFET (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores divided into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores may be divided into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 14 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level-zero (“L0”) instruction cache, a thread bundle scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix computation and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0156] In at least one embodiment, one or more GPUs 1408 may include high-bandwidth memory (“HBM”) and / or a 16GB HBM2 memory subsystem to provide a peak storage bandwidth of approximately 900GB / s in some examples. In at least one embodiment, in addition to or instead of HBM memory, synchronous graphics random access memory (“SGRAM”) may be used, such as graphics double data rate type five synchronous random access memory (“GDDR5”).

[0157] In at least one embodiment, one or more GPUs 1408 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support may be used to allow one or more GPUs 1408 to directly access the page tables of one or more CPUs 1406. In at least one embodiment, when a memory management unit (“MMU”) of one or more GPUs 1408 experiences a miss, an address translation request may be sent to one or more CPUs 1406. In response, in at least one embodiment, two CPUs of one or more CPUs 1406 may look up the virtual-physical mapping of the address in their page tables and transfer the translation back to one or more GPUs 1408. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for the memory of both one or more CPUs 1406 and one or more GPUs 1408, thereby simplifying the programming of one or more GPUs 1408 and the porting of applications to one or more GPUs 1408.

[0158] In at least one embodiment, one or more GPUs 1408 may include any number of access counters that can track the frequency of memory accesses by one or more GPUs 1408 to other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently, thereby improving the efficiency of shared memory ranges between processors.

[0159] In at least one embodiment, one or more SoCs 1404 may include any number of caches 1412, including those described herein. For example, in at least one embodiment, one or more caches 1412 may include a Level 3 (“L3”) cache available for one or more CPUs 1406 and one or more GPUs 1408 (e.g., connected to CPUs 1406 and GPUs 1408). In at least one embodiment, one or more caches 1412 may include a write-back cache that can, for example, track the state of a line using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, according to an embodiment, the L3 cache may include 4 MB of memory or more.

[0160] In at least one embodiment, one or more SoCs 1404 may include one or more accelerators 1414 (e.g., hardware accelerators, software accelerators, or combinations thereof). In at least one embodiment, one or more SoCs 1404 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1408 and offload some tasks from one or more GPUs 1408 (e.g., freeing up more cycles from one or more GPUs 1408 to perform other tasks). In at least one embodiment, one or more accelerators 1414 may be used for a target workload (e.g., perceptual, convolutional neural network (“CNN”), recurrent neural network (“RNN”), etc.) that is sufficiently stable to withstand acceleration testing. In at least one embodiment, the CNN may include region-based or region convolutional neural networks (“RCNN”) and fast RCNN (e.g., for object detection) or other types of CNNs.

[0161] In at least one embodiment, one or more accelerators 1414 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more Tensor Processing Units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for specific sets of neural network types and floating-point operations and inference. In at least one embodiment, one or more DLAs are designed to provide higher performance per millimeter than typical general-purpose GPUs and typically significantly outperform CPUs. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions supporting, for example, INT14, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can execute neural networks, particularly CNNs, quickly and efficiently on processed or unprocessed data for any of the various functions, including, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection, recognition, and identification using data from microphone 1496; CNNs for face recognition and vehicle owner recognition using data from camera sensors; and / or CNNs for safety and / or safety-related events.

[0162] In at least one embodiment, the DLA can perform any function of one or more GPUs 1408, and by using inference accelerators, for example, the designer can target one or more DLAs or one or more GPUs 1408 for any function. For example, in at least one embodiment, the designer can concentrate the CNN processing and floating-point operations on one or more DLAs, leaving other functions to one or more GPUs 1408 and / or one or more accelerators 1414.

[0163] In at least one embodiment, one or more accelerators 1414 (e.g., a hardware acceleration cluster) may include programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1438, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0164] In at least one embodiment, the RISC core can interact with an image sensor (e.g., the image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, the RISC core may use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or storage devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0165] In at least one embodiment, DMA enables components of the PVA to access system memory independently of one or more CPUs 1406. In at least one embodiment, DMA can support any number of features for providing optimization to the PVA, including but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0166] In at least one embodiment, the vector processor may be a programmable processor designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may serve as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as a Single Instruction Multiple Data (“SIMD”) or Very Long Instruction Word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0167] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute general-purpose computer vision algorithms, except on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on a single image, or even execute different algorithms on a sequence of images or portions of images. In at least one embodiment, among others, any number of PVAs may be included in the hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error-correcting code (“ECC”) memory to enhance overall system security.

[0168] In at least one embodiment, one or more accelerators 1414 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory (“SRAM”) for providing high-bandwidth, low-latency SRAM to one or more accelerators 1414. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, comprising, for example, but not limited to, eight field-configurable memory blocks accessible to both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an Advanced Peripheral Bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone providing high-speed access to the memory for both the PVA and DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using an APB).

[0169] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as bursty communication for continuous data transmission. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 615014 standard.

[0170] In at least one embodiment, one or more SoCs 1404 may include a real-time eye-tracking hardware accelerator. In at least one embodiment, the real-time eye-tracking hardware accelerator may be used to quickly and efficiently determine the location and extent of an object (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or for other purposes.

[0171] In at least one embodiment, one or more accelerators 1414 (e.g., a hardware acceleration cluster) have broad applications for autonomous driving. In at least one embodiment, the PVA can be a programmable vision accelerator used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA at low power and low latency are well-matched to algorithmic domains requiring predictable processing. In other words, the PVA performs well in semi-intensive or intensive conventional computations, even on small datasets that may require predictable runtimes with low latency and low power consumption. In at least one embodiment, in an autonomous vehicle, such as vehicle 1400, the PVA may be designed to run classical computer vision algorithms, as they are efficient in object detection and integer mathematical operations.

[0172] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching during operation (e.g., structure recovery from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0173] In at least one embodiment, the PVA can be used to perform intensive optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0174] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, but not limited to, neural networks whose output is used for a confidence score for each object detection. In at least one embodiment, the confidence score can be represented or interpreted as a probability, or as providing a relative “weight” for each detection relative to other detections. In at least one embodiment, the confidence score measurement enables the system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, the system can set a threshold for the confidence score and only consider detections exceeding the threshold as true positives. In embodiments using an Automatic Emergency Braking (“AEB”) system, false positives would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score value. In at least one embodiment, the neural network may take at least a subset of parameters as its input, such as bounding box size, obtained ground plane estimate (e.g., from another subsystem), and outputs of one or more IMU sensors 1466 related to the vehicle 1400 orientation, distance, and 3D position estimate of the object obtained from the neural network and / or other sensors (e.g., one or more LiDAR sensors 1464 or one or more RADAR sensors 1460).

[0175] In at least one embodiment, one or more SoCs 1404 (e.g., a hardware acceleration cluster) may include one or more data storage devices 1416 (e.g., memory). In at least one embodiment, one or more data storage devices 1416 may be on-chip memory of one or more SoCs 1404, which may store neural networks to be executed on one or more GPUs 1408 and / or DLAs. In at least one embodiment, one or more data storage devices 1416 may have a sufficiently large capacity to store multiple instances of the neural network for redundancy and security. In at least one embodiment, one or more data storage devices 1412 may include L2 or L3 caches.

[0176] In at least one embodiment, one or more SoCs 1404 may include any number of processors 1410 (e.g., embedded processors). In at least one embodiment, one or more processors 1410 may include a startup and power management processor, which may be a dedicated processor and subsystem for handling startup power and management functions, as well as associated security implementations. In at least one embodiment, the startup and power management processor may be part of a startup sequence of one or more SoCs 1404 and may provide runtime power management services. In at least one embodiment, the startup power and management processor may provide clock and voltage programming, assist system low-power state transitions, thermal and temperature sensor management of one or more SoCs 1404s, and / or power state management of one or more SoCs 1404s. In at least one embodiment, each temperature sensor may be implemented with its output frequency proportional to temperature, and one or more SoCs 1404s may use the ring oscillator to detect the temperature of one or more CPUs 1406s, one or more GPUs 1408s, and / or one or more accelerators 1414s. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the startup and power management processor may enter a temperature fault routine and place one or more SoCs 1404s into a lower power state and / or place the vehicle 1400 into a driver's safe stopping pattern (e.g., bring the vehicle 1400 to a safe stop).

[0177] In at least one embodiment, one or more processors 1410 may further include a set of embedded processors that can serve as an audio processing engine. The audio processing engine may be an audio subsystem capable of providing full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor having dedicated RAM.

[0178] In at least one embodiment, one or more processors 1410 may further include an always-on processor engine. In at least one embodiment, the automatic processing engine may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processor on the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, support for peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0179] In at least one embodiment, one or more processors 1410 may further include a secure clustering engine, which includes, but is not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the secure clustering engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In secure mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1410 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1410 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0180] In at least one embodiment, one or more processors 1410 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by the video playback application to produce the final video for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1470, one or more surround cameras 1474, and / or one or more cabin monitoring camera sensors. In at least one embodiment, preferably, the cabin monitoring camera sensors are monitored by a neural network running on another instance of SoC 1404, the neural network being configured to recognize cabin events and respond accordingly. In at least one embodiment, the cabin system may perform, but is not limited to, lip reading to activate cellular service and make phone calls, instruct emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, and are otherwise disabled.

[0181] In at least one embodiment, the video image synthesizer may include enhanced temporal denoising for simultaneous spatial and temporal denoising. For example, in at least one embodiment, when motion occurs in the video, denoising appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, when the image or a portion of the image does not contain motion, temporal denoising performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0182] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic correction on the input stereo lens frames. In at least one embodiment, when using an operating system desktop, the video image compositor can also be used for user interface compositing and does not require one or more GPUs 1408 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1408 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 1408 to improve performance and responsiveness.

[0183] In at least one embodiment, one or more SoCs of SoC 1404 may further include a Mobile Industrial Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block that can be used for receiving video and input from a camera and associated pixel input functions. In at least one embodiment, one or more SoCs of SoC 1404 may further include an input / output controller that can be software controlled and can be used to receive I / O signals not assigned to a specific role.

[0184] In at least one embodiment, one or more SoCs of SoC 1404 may further include extensive peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management and / or other devices. In at least one embodiment, one or more SoCs of SoC 1404 may be used to process data from (e.g., connected via gigabit multimedia serial links and Ethernet channels) cameras, sensors (e.g., one or more LiDAR sensors 1464, one or more RADAR sensors 1460, etc., which may be connected via Ethernet channels), data from bus 1402 (e.g., vehicle 1400 speed, steering wheel position, etc.), data from one or more GNSS sensors 1458 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more SoCs of SoC 1404 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to free one or more CPUs 1406 from routine data management tasks.

[0185] In at least one embodiment, one or more SoCs 1404 can be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and effectively utilizes computer vision and ADAS technologies to achieve diversity and redundancy. This provides a platform offering a flexible and reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 1404 can be faster, more reliable, and even more energy and space efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1414, when combined with one or more CPUs 1406, one or more GPUs 1408, and one or more data storage devices 1416, can provide a fast and efficient platform for Level 3-5 autonomous vehicles.

[0186] In at least one embodiment, the computer vision algorithm can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute multiple processing algorithms on a variety of visual data. However, in at least one embodiment, the CPU typically cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in automotive ADAS applications and practical Level 3-5 autonomous vehicles.

[0187] The embodiments described herein allow for the simultaneous and / or sequential execution of multiple neural networks and allow for the combination of results to achieve Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPUs 1420) may include text and word recognition, thereby allowing a supercomputer to read and understand traffic signs, including signs for which the neural network has not yet been specifically trained. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing semantic understanding of symbols, and passing this semantic understanding to a path planning module running on a CPU Complex.

[0188] In at least one embodiment, for drives of levels 3, 4, or 5, multiple neural networks can run simultaneously. For example, in at least one embodiment, a warning sign consisting of a light bulb accompanied by the warning sign “Caution: flashing lights indicate icy conditions” can be interpreted independently or jointly by multiple neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text “flashing lights indicate icy conditions” can be interpreted by a second deployed neural network, which informs the vehicle’s path planning software (preferably executed on the CPU Complex) that icing conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network across multiple frames, informing the vehicle’s path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1408.

[0189] In at least one embodiment, the CNN for facial recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or the owner of vehicle 1400. In at least one embodiment, a normally open sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves it. In this way, one or more SoCs 1404 provide protection against theft and / or carjacking.

[0190] In at least one embodiment, the CNN for emergency vehicle detection and identification can use data from microphone 1496 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1404 use the CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, the CNN running on DLA is trained to identify the relative approach speed of emergency vehicles (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles in the area where the vehicle is operating, as identified by one or more GNSS sensors 1458. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in the United States, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 1462, to execute emergency vehicle safety routines, slow down the vehicle, pull the vehicle to the side of the road, stop, and / or leave the vehicle idle until the emergency vehicle passes.

[0191] In at least one embodiment, vehicle 1400 may include one or more CPUs 1418 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 1404 via high-speed interconnects (e.g., PCIe). In at least one embodiment, for example, one or more CPUs 1418 may include x86 processors. One or more CPUs 1418 may be used to perform any of a variety of functions, such as arbitrating the results of potential inconsistencies between ADAS sensors and one or more SoCs 1404, and / or monitoring the status and health of one or more controllers 1436 and / or on-chip infotainment system (“infotainment SoC”) 1430.

[0192] In at least one embodiment, vehicle 1400 may include one or more GPUs 1420 (e.g., one or more discrete GPUs or one or more dGPUs) coupled to one or more SoCs 1404 via high-speed interconnects (e.g., NVIDIA's NVLINK channels). In at least one embodiment, one or more GPUs 1420 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on inputs from sensors of vehicle 1400 (e.g., sensor data).

[0193] In at least one embodiment, vehicle 1400 may further include a network interface 1424, which may include, but is not limited to, one or more wireless antennas 1426 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1424 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., passenger client devices) via Internet cloud services (e.g., using servers and / or other network devices). In at least one embodiment, for communication with other vehicles, a direct link and / or an indirect link (e.g., via a network and on the Internet) may be established between vehicle 1400 and another vehicle. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1400 with information about vehicles near vehicle 1400 (e.g., vehicles in front, to the side, and / or behind vehicle 1400). In at least one embodiment, the foregoing functionality may be part of a cooperative adaptive cruise control function of vehicle 1400.

[0194] In at least one embodiment, network interface 1424 may include a System-on-Chip (SoC) that provides modulation and demodulation functions and enables one or more controllers 1436 to communicate over a wireless network. In at least one embodiment, network interface 1424 may include a radio frequency (RF) front-end for up-conversion from baseband to radio frequency (RF) and down-conversion from RF to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed using known processes and / or using a superheterodyne process. In at least one embodiment, the RF front-end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0195] In at least one embodiment, the vehicle 1400 may further include one or more data storage devices 1428, which may include, but are not limited to, off-chip (e.g., one or more SoC 1404) storage. In at least one embodiment, the one or more data storage devices 1428 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disk and / or other components and / or devices capable of storing at least one bit of data.

[0196] In at least one embodiment, the vehicle 1400 may further include one or more GNSS sensors 1458 (e.g., GPS and / or auxiliary GPS sensors) to assist in map creation, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1458 may be used, including, for example, but not limited to, GPS sensors connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0197] In at least one embodiment, vehicle 1400 may further include one or more RADAR sensors 1460. In at least one embodiment, one or more RADAR sensors 1460 may be used by vehicle 1400 for remote vehicle detection, even in dark and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, one or more RADAR sensors 1460 may use a CAN bus and / or bus 1402 (e.g., to transmit data generated by one or more RADAR sensors 1460) for control and access to object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, but not limited to, one or more of the RADAR sensors 1460 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 1460 are pulse Doppler RADAR sensors.

[0198] In at least one embodiment, one or more RADAR sensors 1460 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a 250m range). In at least one embodiment, one or more RADAR sensors 1460 can help distinguish between stationary and moving objects and can be used by the ADAS system 1438 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 1460 included in the long-range RADAR system may include, but are not limited to, a monostatic multimode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the four central antennas, can create a focused beammap designed to record the surrounding environment of the vehicle 1400 at a high speed while minimizing traffic interference from adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view, thereby enabling rapid detection of vehicles 1400 entering or leaving the lane.

[0199] In at least one embodiment, as an example, a mid-range RADAR system may include, for example, a range of up to 160m (front) or 140m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1460 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the rearward direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system may be used in ADAS system 1438 for blind spot detection and / or lane change assistance.

[0200] In at least one embodiment, the vehicle 1400 may further include one or more ultrasonic sensors 1462. In at least one embodiment, one or more ultrasonic sensors 1462, which may be positioned at the front, rear, and / or sides of the vehicle 1400, may be used for parking assistance and / or creating and updating occupancy detectors. In at least one embodiment, a wide variety of ultrasonic sensors 1462 may be used, and different ultrasonic sensors 1462 may be used for different detection ranges (e.g., 2.5m, 4m). In at least one embodiment, the ultrasonic sensors 1462 may operate at the ASIL B functional safety level.

[0201] In at least one embodiment, vehicle 1400 may include one or more LiDAR sensors 1464. In at least one embodiment, one or more LiDAR sensors 1464 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LiDAR sensors 1464 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 1400 may include multiple (e.g., two, four, six, etc.) LiDAR sensors 1464 that can use Ethernet (e.g., providing data to a Gigabit Ethernet switch).

[0202] In at least one embodiment, one or more LiDAR sensors 1464 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LiDAR sensors 1464 may, for example, have an advertising range of approximately 100m, an accuracy of 2cm-3cm, and support a 100Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LiDAR sensors may be used. In such an embodiment, one or more LiDAR sensors 1464 may include small devices that can be embedded in the front, rear, side, and / or corner locations of vehicle 1400. In at least one embodiment, one or more LiDAR sensors 1464, in such an embodiment, can provide a horizontal field of view of up to 140 degrees and a vertical field of view of 35 degrees, even for objects with low reflectivity, and have a range of 200m. In at least one embodiment, one or more forward-facing LiDAR sensors 1464 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0203] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200m around vehicle 1400. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and reflected light on each pixel, which in turn corresponds to the range from vehicle 1400 to the object. In at least one embodiment, flash LIDAR can allow the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of vehicle 1400. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per frame and can capture reflected laser light as intensity data for 3D ranging point clouds and co-registration.

[0204] In at least one embodiment, vehicle 1400 may further include one or more IMU sensors 1466. In at least one embodiment, one or more IMU sensors 1466 may be located at the center of the rear axle of vehicle 1400. In at least one embodiment, one or more IMU sensors 1466 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, a magnetic compass, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 1466 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 1466 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0205] In at least one embodiment, one or more IMU sensors 1466 may be implemented as a miniature, high-performance GPS-assisted inertial navigation system (“GPS / INS”) combining a microelectromechanical system (“MEMS”) inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm to provide position, velocity, and attitude estimations; in at least one embodiment, one or more IMU sensors 1466 may enable vehicle 1400 to estimate heading by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1466 without input from magnetic sensors. In at least one embodiment, one or more IMU sensors 1466 and one or more GNSS sensors 1458 may be combined in a single integrated unit.

[0206] In at least one embodiment, vehicle 1400 may include one or more microphones 1496 placed inside and / or around vehicle 1400. In at least one embodiment, in addition, one or more microphones 1496 may be used for emergency vehicle detection and identification.

[0207] In at least one embodiment, vehicle 1400 may further include any number of camera types, including one or more stereo cameras 1468, one or more wide-angle cameras 1470, one or more infrared cameras 1472, one or more surround cameras 1474, one or more long-range cameras 1498, one or more mid-range cameras 1476, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire perimeter of vehicle 1400. In at least one embodiment, the type of camera used depends on vehicle 1400. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 1400. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1400 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may be, by way of example but not limited to, supporting gigabit multimedia serial link (“GMSL”) and / or gigabit Ethernet communication. In at least one embodiment, previously referenced herein Figure 14A and Figure 14B Each camera can be described in more detail.

[0208] In at least one embodiment, the vehicle 1400 may further include one or more vibration sensors 1442. In at least one embodiment, the one or more vibration sensors 1442 may measure vibrations of components of the vehicle 1400 (e.g., axles). For example, in at least one embodiment, changes in vibration may indicate changes in road surface conditions. In at least one embodiment, when two or more vibration sensors 1442 are used, differences between vibrations may be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a power drive axle and a free-rotating axle).

[0209] In at least one embodiment, vehicle 1400 may include ADAS system 1438. In at least one embodiment, ADAS system 1438 may include, but is not limited to, SoC. In at least one embodiment, ADAS system 1438 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions, and combinations thereof.

[0210] In at least one embodiment, the ACC system may use one or more RADAR sensors 1460, one or more LIDAR sensors 1464, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle adjacent to the vehicle 1400 and automatically adjusts the speed of the vehicle 1400 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance holding and suggests that the vehicle 1400 change lanes if necessary. In at least one embodiment, the lateral ACC is associated with other ADAS applications, such as LC and CW.

[0211] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from other vehicles via network interface 1424 and / or one or more wireless antennas 1426 via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Typically, V2V communication provides information about the vehicle immediately preceding it (e.g., a vehicle immediately in front of vehicle 1400 and in the same lane as it), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles preceding vehicle 1400, the CACC system can be more reliable and has the potential to improve traffic flow smoothness and reduce road congestion.

[0212] In at least one embodiment, the FCW system is designed to warn the driver of danger so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1460, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to components providing driver feedback, such as a display, speaker, and / or vibration. In at least one embodiment, the FCW system can provide warnings, for example, in the form of audible, visual warnings, vibrations, and / or rapid braking pulses.

[0213] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply brakes if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 1460 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system may automatically apply brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic braking to support and / or brakes for impending collisions.

[0214] In at least one embodiment, when vehicle 1400 crosses lane markings, the LDW system provides visual, auditory, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver. In at least one embodiment, the LDW system is inactive when the driver indicates intentional lane departure, such as by activating turn signals. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 1400 begins to leave the lane, the LKA system provides steering input or braking to correct vehicle 1400.

[0215] In at least one embodiment, the BSW system detects and warns the driver of a vehicle in the blind spot. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses the turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1460 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback, such as a display, speaker, and / or vibration assembly.

[0216] In at least one embodiment, the RCTW system can provide visual, auditory, and / or tactile notifications when an object is detected outside the range of the rear camera while the vehicle 1400 is reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure the applied vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear-facing RADAR sensors 1460 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as displays, speakers, and / or vibration components.

[0217] In at least one embodiment, conventional ADAS systems may be prone to generating false alarms, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to determine whether a safe situation truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, the vehicle 1400 itself decides whether to follow the result of the primary computer or the secondary computer (e.g., the first or second controller of controller 1436). For example, in at least one embodiment, ADAS system 1438 may be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor may run redundant software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from ADAS system 1438 may be provided to a monitoring MCU. In at least one embodiment, if the output from the primary computer and the output from the auxiliary computer conflict, the monitoring MCU decides how to reconcile the conflict to ensure safe operation.

[0218] In at least one embodiment, the master computer may be configured to provide a confidence score to the supervisory MCU to indicate the master computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the master computer's instructions regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the master computer and the auxiliary computer indicate different results (e.g., conflicting), the supervisory MCU may arbitrate between the computers to determine the appropriate result.

[0219] In at least one embodiment, the supervisory MCU may be configured to run a neural network trained and configured to determine, at least in part, the conditions under which the auxiliary computer provides a false alarm based on outputs from a host computer and an auxiliary computer. In at least one embodiment, the neural network in the supervisory MCU may learn when the outputs of the auxiliary computer can be trusted and when they cannot. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, the neural network in the supervisory MCU may learn when the FCW system recognizes a metallic object that is not actually dangerous, such as a drain grating or manhole cover that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest operation. In at least one embodiment, the supervisory MCU may include at least one of a DLA or GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoC 1404s.

[0220] In at least one embodiment, the ADAS system 1438 may include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the auxiliary computer may use classic computer vision rules (if-then), and the presence of a neural network in the supervisory MCU can improve reliability, security, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if a software vulnerability or bug exists in the software running on the host computer, and different software code running on the auxiliary computer provides consistent overall results, the supervisory MCU can more confidently assume that the overall result is correct and that the vulnerability in the software or hardware on the host computer will not lead to a significant error.

[0221] In at least one embodiment, the output of the ADAS system 1438 may be input to the perception module and / or the dynamic driving task module of the host computer. For example, in at least one embodiment, if the ADAS system 1438 indicates a forward collision warning due to an object directly ahead, the perception block may use this information when identifying the object. In at least one embodiment, as described herein, the assistance computer may have its own neural network trained to reduce the risk of false alarms.

[0222] In at least one embodiment, vehicle 1400 may further include an infotainment SoC 1430 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1430 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1430 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total coverage distance, brake fuel level, fuel level, door opening / closing, air filter information, etc.) to vehicle 1400. For example, the infotainment SoC 1430 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, vehicle, in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, head-up display (“HUD”), HMI display 1434, telematics device, control panel (e.g., for controlling and / or interacting with various components, features and / or systems) and / or other components. In at least one embodiment, the infotainment SoC 1430 may further be used to provide information (e.g., visual and / or auditory) to a user of vehicle 1400, such as information from ADAS system 1438, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.) and / or other information.

[0223] In at least one embodiment, the infotainment SoC 1430 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1430 may communicate with other devices, systems, and / or components of the vehicle 1400 via bus 1402 (e.g., CAN bus, Ethernet, etc.). In at least one embodiment, the infotainment SoC 1430 may be coupled to a monitoring MCU, enabling the GPU of the infotainment system to perform some autonomous driving functions in the event of a failure of the main controller 1436 (e.g., the main computer and / or backup computer of the vehicle 1400). In at least one embodiment, the infotainment SoC 1430 may cause the vehicle 1400 to enter a driver-to-safe-stop mode, as described herein.

[0224] In at least one embodiment, vehicle 1400 may further include instrument panel 1432 (e.g., digital instrument panel, electronic instrument panel, digital instrument control panel, etc.). In at least one embodiment, instrument panel 1432 may include, but is not limited to, controllers and / or supercomputers (e.g., discrete controllers or supercomputers). In at least one embodiment, instrument panel 1432 may include, but is not limited to, any number and combination of a set of instruments, such as speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 1430 and instrument panel 1432. In at least one embodiment, instrument panel 1432 may be included as part of infotainment SoC 1430, or vice versa.

[0225] In at least one embodiment, regarding Figure 14C At least one component shown or described is used to achieve the combination Figure 1-12 The described techniques and / or functions. In at least one embodiment, regarding... Figure 1-12 The described technologies and / or functions can receive and decode information from vehicle 1400 (e.g., at a base station, such as a gNodeB) for its autonomous operation, and / or can be used to provide a remote operator with the ability to remotely control vehicle 1400.

[0226] Figure 14D It is based on at least one embodiment in a cloud-based server and Figure 14AA diagram of a system 1476 for communication between autonomous vehicles 1400. In at least one embodiment, system 1476 may include, but is not limited to, one or more servers 1478, one or more networks 1490, and any number and type of vehicles, including vehicle 1400. In at least one embodiment, one or more servers 1478 may include, but is not limited to, multiple GPUs 1484(A)-1484(H) (collectively referred to herein as GPU 1484), PCIe switches 1482(A)-1482(D) (collectively referred to herein as PCIe switch 1482), and / or CPUs 1480(A)-1480(B) (collectively referred to herein as CPU 1480). GPU 1484, CPU 1480, and PCIe switch 1482 may be interconnected with high-speed cables, such as, but not limited to, NVLink interface 1488 developed by NVIDIA and / or PCIe connection 1486. In at least one embodiment, the GPU 1484 is connected via NVLink and / or NVSwitchSoC, and the GPU 1484 and PCIe switch 1482 are connected via PCIe interconnect. In at least one embodiment, although eight GPUs 1484, two CPUs 1480, and four PCIe switches 1482 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 1478 may include, but is not limited to, any combination of any number of GPUs 1484, CPUs 1480, and / or PCIe switches 1482. For example, in at least one embodiment, one or more servers 1478 may each include eight, sixteen, thirty-two, and / or more GPUs 1484.

[0227] In at least one embodiment, one or more servers 1478 may receive image data representing an image from a vehicle via one or more networks 1490, the image showing unexpected or changed road conditions, such as recently commenced roadworks. In at least one embodiment, one or more servers 1478 may transmit a neural network 1492, an updated neural network 1492, and / or map information 1494, including but not limited to information about traffic and road conditions, to the vehicle via one or more networks 1490. In at least one embodiment, updates to the map information 1494 may include, but are not limited to, updates to an HD map 1422, such as information about construction sites, potholes, sidewalks, floods, and / or other obstacles. In at least one embodiment, the neural network 1492, the updated neural network 1492, and / or map information 1494 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or at least based on training performed in a data center (e.g., using one or more servers 1478 and / or other servers).

[0228] In at least one embodiment, one or more servers 1478 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by the vehicle, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1490), and / or the machine learning model may be used by one or more servers 1478 to remotely monitor the vehicle.

[0229] In at least one embodiment, one or more servers 1478 may receive data from the vehicle and apply the data to state-of-the-art real-time neural networks for real-time intelligent inference. In at least one embodiment, one or more servers 1478 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1484, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1478 may include a deep learning infrastructure in a data center using CPU power.

[0230] In at least one embodiment, the deep learning infrastructure of one or more servers 1478 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processor, software, and / or associated hardware in vehicle 1400. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1400, such as image sequences and / or objects located by vehicle 1400 in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 1400, and if the results do not match and the deep learning infrastructure determines that the AI ​​in vehicle 1400 is malfunctioning, one or more servers 1478 may signal to vehicle 1400 to instruct the fail-safe computer of vehicle 1400 to take control, notify passengers, and complete a safe stopping operation.

[0231] In at least one embodiment, one or more servers 1478 may include one or more GPUs 1484 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, the combination of GPU-driven servers and inference acceleration enables real-time response. In at least one embodiment, for example, where performance is less critical, servers driven by CPUs, FPGAs, and other processors may be used for inference. In at least one embodiment, hardware architecture 1315 is used to execute one or more embodiments. This document incorporates... Figure 13 A and / or Figure 13 B provides details about the hardware architecture 1315.

[0232] Computer System

[0233] Figure 15 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system of interconnected devices and components, a system-on-a-chip (SOC), or some combination thereof 1500 formed with a processor, which may include an execution unit to execute instructions. In at least one embodiment, according to this disclosure, such as the embodiments described herein, the computer system 1500 may include, but is not limited to, components such as processor 1502, whose execution unit includes logic to execute algorithms for process data. In at least one embodiment, the computer system 1500 may include a processor, such as those available from Intel Corporation of Santa Clara, California. Processor family, Xeon™ XScale™ and / or StrongARM™ Core TM or Nervana TM A microprocessor may be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, computer system 1500 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0234] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0235] In at least one embodiment, computer system 1500 may include, but is not limited to, processor 1502, which may include, but is not limited to, one or more execution units 1508, to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, system 15 is a single-processor desktop or server system, but in another embodiment, system 15 may be a multiprocessor system. In at least one embodiment, processor 1502 may include, but is not limited to, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1502 may be coupled to processor bus 1510, which can transmit data signals between processor 1502 and other components in computer system 1500.

[0236] In at least one embodiment, processor 1502 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1504. In at least one embodiment, processor 1502 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1502. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 1506 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0237] In at least one embodiment, an execution unit 1508, including but not limited to logic for performing integer and floating-point operations, is also located within processor 1502. In at least one embodiment, processor 1502 may further include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, execution unit 1508 may include logic for processing a packaged instruction set 1509. In at least one embodiment, by including the packaged instruction set 1509 in the instruction set of a general-purpose processor, along with associated circuitry for executing the instructions, packaged data in general-purpose processor 1502 can be used to perform operations used by numerous multimedia applications. In one or more embodiments, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor’s data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor’s data bus to perform one or more operations on one data element at a time.

[0238] In at least one embodiment, execution unit 1508 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 1500 may include, but is not limited to, memory 1520. In at least one embodiment, memory 1520 may be implemented as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or another storage device. In at least one embodiment, memory 1520 may store instructions 1519 and / or data 1521 represented by data signals that can be executed by processor 1502.

[0239] In at least one embodiment, the system logic chip may be coupled to processor bus 1510 and memory 1520. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1516, and processor 1502 may communicate with MCH 1516 via processor bus 1510. In at least one embodiment, MCH 1516 may provide a high-bandwidth memory path 1518 to memory 1520 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1516 may direct data signals between processor 1502, memory 1520, and other components in computer system 1500, and bridge data signals between processor bus 1510, memory 1520, and system I / O 1522. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1516 may be coupled to memory 1520 via high-bandwidth memory path 1518, and graphics / video card 1512 may be coupled to MCH 1516 via Accelerated Graphics Port (“AGP”) interconnect 1514.

[0240] In at least one embodiment, computer system 1500 may use system I / O 1522, which is a proprietary hub interface bus, to couple MCH 1516 to I / O controller hub (“ICH”) 1530. In at least one embodiment, ICH 1530 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 1520, chipset, and processor 1502. Examples may include, but are not limited to, audio controller 1529, firmware hub (“Flash BIOS”) 1528, wireless transceiver 1526, data storage 1524, a conventional I / O controller 1523 including user input and keyboard interfaces, serial expansion port 1527 (e.g., Universal Serial Bus (USB)), and network controller 1534. In at least one embodiment, data storage 1524 may include hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

[0241] In at least one embodiment, Figure 15 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 15 A system-on-a-chip (SoC) can be shown. In at least one embodiment, Figure 15The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1500 are interconnected using a compute fast link (CXL) interconnect.

[0242] In at least one embodiment, regarding Figure 15 At least one component shown or described is used to implement about Figure 1-12 The described techniques and / or functions. In at least one embodiment, at least one of the processor 1502 and the graphics card 1512 is configured to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to rows of the QC-LDPC basemap). In at least one embodiment, at least one of the processor 1502 and the graphics card 1512 is configured to perform a selected data decoding operation (e.g., a frame-plus operation or a compressed C2V operation). In at least one embodiment, at least one of the processor 1502 and the graphics card 1512 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technique 1100, and / or technique 1200. In at least one embodiment, the processor 1502 performs a kernel boot function that passes parameters to at least one kernel on the graphics card 1512, the graphics card 1512 selects one or more data decoding operations, and / or performs the data decoding operation with respect to LDPC decoder 102, LDPC decoder 202, technique 1100, and / or technique 1200. Figure 1-12 The data decoding operation described.

[0243] Figure 16 This is a block diagram illustrating an electronic device 1600 for utilizing a processor 1610 according to at least one embodiment. In at least one embodiment, the electronic device 1600 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0244] In at least one embodiment, system 1600 may include, but is not limited to, processor 1610 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1610 uses a bus or interface coupling, such as an I²C bus, system management bus (“SMBus”), low pin count (LPC) bus, serial peripheral interface (“SPI”), high-definition audio (“HDA”) bus, serial advanced technology accessory (“SATA”) bus, universal serial bus (“USB”) (versions 1, 2, 3, etc.), or universal asynchronous receiver / transmitter (“UART”) bus. In at least one embodiment, Figure 16 The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 16 An exemplary system-on-a-chip (SoC) can be illustrated. In at least one embodiment, Figure 16 The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 16 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0245] In at least one embodiment, Figure 16 It may include a display 1624, a touch screen 1625, a touchpad 1630, a near field communication unit (“NFC”) 1645, a sensor hub 1640, a thermal sensor 1646, a fast chipset (“EC”) 1635, a trusted platform module (“TPM”) 1638, a BIOS / firmware / flash (“BIOS, FW Flash”) 1622, a DSP 1660, a drive “SSD or HDD” 1620 (e.g., a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1650, a Bluetooth unit 1652, a wireless wide area network unit (“WWAN”) 1656, a global positioning system (GPS) 1655, a camera (“USB 3.0 camera”) 1654 (e.g., a USB 3.0 camera), or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1615 implemented in, for example, the LPDDR3 standard. These components can each be implemented in any suitable way.

[0246] In at least one embodiment, other components may be communicatively coupled to processor 1610 via the components described above. In at least one embodiment, accelerometer 1641, ambient light sensor (“ALS”) 1642, compass 1643, and gyroscope 1644 may be communicatively coupled to sensor hub 1640. In at least one embodiment, thermal sensor 1639, fan 1637, keyboard 1646, and touchpad 1630 may be communicatively coupled to EC 1635. In at least one embodiment, speaker 1663, earphone 1664, and microphone (“mic”) 1665 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1664, which in turn may be communicatively coupled to DSP 1660. In at least one embodiment, audio unit 1664 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1657 may be communicatively coupled to WWAN unit 1656. In at least one embodiment, components such as WLAN unit 1650, Bluetooth unit 1652, and WWAN unit 1656 can be implemented as next-generation form factor (NGFF).

[0247] In at least one embodiment, regarding Figure 16 At least one component shown or described is used to implement about Figure 1-12 The described techniques and / or functions. In at least one embodiment, processor 1610 is configured to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to rows in the QC-LDPC basemap). In at least one embodiment, processor 1610 is configured to perform the selected data decoding operation (e.g., a frame-plus operation or a compressed C2V operation). In at least one embodiment, processor 1610 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technique 1100, and / or technique 1200.

[0248] Figure 17 A computer system 1700 according to at least one embodiment is shown. In at least one embodiment, the computer system 1700 is configured to implement various processes and methods described throughout this disclosure.

[0249] In at least one embodiment, the computer system 1700 includes, but is not limited to, at least one central processing unit (“CPU”) 1702 connected to a communication bus 1710 implemented using any suitable protocol, such as PCI (“Peripheral Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1700 includes, but is not limited to, main memory 1704 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data may be stored in main memory 1704 in the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“Network Interface”) 1722 provides an interface to other computing devices and networks for receiving data from the computer system 1700 and transferring data to other systems.

[0250] In at least one embodiment, the computer system 1700 includes, but is not limited to, an input device 1708, a parallel processing system 1712, and a display device 1706, which may be implemented using conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light-emitting diode (“LED”), plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1708 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the foregoing modules may reside on a single semiconductor platform to form the processing system.

[0251] In at least one embodiment, regarding Figure 17 At least one component shown or described is used to implement about Figure 1-12The described techniques and / or functions. In at least one embodiment, at least one of the parallel processing system 1712 and CPU 1702 is used to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to the row of the QC-LDPC basemap). In at least one embodiment, at least one of the parallel processing system 1712 and CPU 1702 is used to perform the selected data decoding operation (e.g., a frame-plus operation or a compressed C2V operation). In at least one embodiment, at least one of the parallel processing system 1712 and CPU 1702 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technique 1100, and / or technique 1200. In at least one embodiment, CPU 1702 executes a kernel startup function that passes parameters to at least one kernel on PPU 1714, PPU 1714 selecting one or more data decoding operations and / or executing the selected... Figure 1-12 The data decoding operation described.

[0252] Figure 18 A computer system 1800 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1800 includes, but is not limited to, a computer 1810 and a USB stick 1820. In at least one embodiment, the computer 1810 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1810 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0253] In at least one embodiment, the USB stick 1820 includes, but is not limited to, a processing unit 1830, a USB interface 1840, and USB interface logic 1850. In at least one embodiment, the processing unit 1830 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1830 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 1830 includes an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1830 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing core 1830 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0254] In at least one embodiment, the USB interface 1840 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1840 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1840 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1850 may include any amount and type of logic enabling the processing unit 1830 to connect to a device (e.g., computer 1810) via the USB connector 1840.

[0255] In at least one embodiment, regarding Figure 18 At least one component shown or described is used to implement about Figure 1-12 The described techniques and / or functions. In at least one embodiment, computer 1810 is configured to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to rows in the QC-LDPC basemap). In at least one embodiment, computer 1810 is configured to perform a selected data decoding operation (e.g., a frame-plus operation or a compressed C2V operation). In at least one embodiment, computer 1810 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technique 1100, and / or technique 1200.

[0256] Figure 19A An exemplary architecture is illustrated, in which multiple GPUs 1910-1913 are communicatively coupled to multiple multi-core processors 1905-1906 via high-speed links 1940-1943 (e.g., bus / point-to-point interconnect, etc.). In one embodiment, the high-speed links 1940-1943 support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0257] Furthermore, in one embodiment, two or more GPUs 1910-1913 are interconnected via high-speed links 1929-1930, which may use the same or different protocols / links as those used for high-speed links 1940-1943. Similarly, two or more multi-core processors 1905-1906 may be connected via high-speed link 1928, which may be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, the same protocols / links (e.g., via a common interconnect structure) may be used. Figure 19A This shows all communication between the various system components.

[0258] In one embodiment, each multi-core processor 1905-1906 is communicatively coupled to processor memories 1901-1902 via memory interconnects 1926-1927, and each GPU 1910-1913 is communicatively coupled to GPU memories 1920-1923 via GPU memory interconnects 1950-1953. Memory interconnects 1926-1927 and 1950-1953 may utilize the same or different memory access technologies. By way of example and not limitation, processor memories 1901-1902 and GPU memories 1920-1923 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM. In one embodiment, some portions of the processor memories 1901-1902 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0259] As described in this article, although the various processors 1905-1906 and GPUs 1910-1913 can be physically coupled to specific memories 1901-1902 and 1920-1923 respectively, a unified memory architecture can be implemented, in which the same virtual system address space (also known as the “effective address” space) is distributed across the various physical memories. For example, processor memories 1901-1902 can each contain 64GB of system memory address space, and GPU memories 1920-1923 can each contain 32GB of system memory address space (resulting in a total addressable memory size of 256GB in this example).

[0260] Figure 19BAdditional details are shown regarding the interconnection between a multi-core processor 1907 and a graphics acceleration module 1946 according to an exemplary embodiment. The graphics acceleration module 1946 may include one or more GPU chips integrated on a line card coupled to the processor 1907 via a high-speed link 1940. Alternatively, the graphics acceleration module 1946 may be integrated on the same package or chip as the processor 1907.

[0261] In at least one embodiment, the processor 1907 shown includes multiple cores 1960A-1960D, each core having a translation back buffer 1961A-1961D and one or more caches 1962A-1962D. In at least one embodiment, cores 1960A-1960D may include various other components (not shown) for executing instructions and processing data. Caches 1962A-1962D may include level 1 (L1) and level 2 (L2) caches. Furthermore, one or more shared caches 1956 may be included in caches 1962A-1962D and shared by the respective groups of cores 1960A-1960D. For example, one embodiment of the processor 1907 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1907 and the graphics acceleration module 1946 are connected to a system memory 1918, which may include... Figure 19A The processor memory in the memory is 1901-1902.

[0262] The coherence bus 1964 maintains consistency for data and instructions stored in the various caches 1962A-1962D, 1956, and system memory 1918 via inter-core communication. For example, each cache may have associated cache coherence logic / circuit to communicate via the coherence bus 1964 in response to the detection of a read or write to a specific cache line. In one implementation, a cache snooping protocol is implemented via the coherence bus 1964 to snoop on cache accesses.

[0263] In one embodiment, proxy circuitry 1925 communicatively couples graphics acceleration module 1946 to coherence bus 1964, thereby allowing graphics acceleration module 1946 to participate in cache coherence protocols as a peer of cores 1960A-1960D. Specifically, interface 1935 provides connectivity to proxy circuitry 1925 via high-speed link 1940 (e.g., PCIe bus, NVLink, etc.), and interface 1937 connects graphics acceleration module 1946 to link 1940.

[0264] In one implementation, the accelerator integrated circuit 1936 represents multiple graphics processing engines 1931, 1932, N of the graphics acceleration module 1946, providing cache management, memory access, context management, and interrupt management services. The graphics processing engines 1931, 1932, N may each include a separate graphics processing unit (GPU). Optionally, the graphics processing engines 1931, 1932, N may selectively include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1946 may be a GPU having multiple graphics processing engines 1931-1932, N, or the graphics processing engines 1931-1932, N may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0265] In one embodiment, the accelerator integrated circuit 1936 includes a memory management unit (MMU) 1939 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1914. MMU 1939 may also include a translation back buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 1938 may store commands and data for effective access by graphics processing engines 1931-1932,N. In one embodiment, data stored in cache 1938 and graphics memories 1933-1934,M is kept consistent with core caches 1962A-1962D,1956 and system memory 1914. As previously mentioned, this task can be accomplished via proxy circuitry 1925 representing cache 1938 and graphics memory 1933-1934, M (e.g., sending updates related to modifications / accesses to cache lines on processor caches 1962A-1962D, 1956 to cache 1938 and receiving updates from cache 1938).

[0266] A set of registers 1945 stores the context data of the threads executed by graphics processing engines 1931, 1932, N, and context management circuitry 1948 manages the thread context. For example, context management circuitry 1948 can perform save and restore operations to save and restore the context of individual threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 1948 can store the current register value into a designated area in memory (e.g., identified by the context pointer). The register value can then be restored when returning to the context. In one embodiment, interrupt management circuitry 1947 receives and processes interrupts received from system devices.

[0267] In one implementation, MMU 1939 translates virtual / effective addresses from graphics processing engine 1931 into real / physical addresses in system memory 1914. One embodiment of accelerator integrated circuit 1936 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1946 and / or other accelerator devices. Graphics accelerator module 1946 may be dedicated to a single application executing on processor 1907, or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, where the resources of graphics processing engines 1931, 1932, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” based on processing requirements and priorities associated with VMs and / or applications, which are allocated to different VMs and / or applications.

[0268] In at least one embodiment, the accelerator integrated circuit 1936 acts as a system bridge for the graphics acceleration module 1946 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1936 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 1931-1932.

[0269] Because the hardware resources of the graphics processing engines 1931-1932 and N are explicitly mapped into the real address space seen by the host processor 1907, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 1936 is to physically separate the graphics processing engines 1931-1932 and N, making them appear as independent units to the system.

[0270] In at least one embodiment, one or more graphics memories 1933-1934,M are coupled to each graphics processing engine 1931-1932,N. The graphics memories 1933-1934,M store instructions and data processed by each graphics processing engine 1931-1932,N. The graphics memories 1933-1934,M can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-RAM.

[0271] In one embodiment, to reduce data traffic on link 1940, a biasing technique can be used to ensure that the data stored in graphics memories 1933-1934, M is the data most frequently used by graphics processing engines 1931-1932, N, and preferably not used (or at least infrequently used) by cores 1960A-1960D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep the data needed by the cores (and preferably not graphics processing engines 1931-1932, N) in the core caches 1962A-1962D, 1956 and system memory 1914.

[0272] Figure 19C Another exemplary embodiment is shown, in which the accelerator integrated circuit 1936 is integrated within the processor 1907. In this embodiment, the graphics processing engines 1931-1932,N communicate directly with the accelerator integrated circuit 1936 via a high-speed link 1940 through interfaces 1937 and 1935 (which can also utilize any form of bus or interface protocol). The accelerator integrated circuit 1936 can perform operations related to... Figure 19B The operations described are the same. However, due to its close proximity to the coherence bus 1964 and caches 1962A-1962D, 1956, it may have higher throughput. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1936 and a programming model controlled by the graphics acceleration module 1946.

[0273] In at least one embodiment, graphics processing engines 1931-1932,N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 1931-1932,N, thereby providing virtualization within a VM / partition.

[0274] In at least one embodiment, graphics processing engines 1931-1932, N can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1931-1932, N to allow each operating system to access them. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns graphics processing engines 1931-1932, N. In at least one embodiment, the operating system can virtualize graphics processing engines 1931-1932, N to provide access to each process or application.

[0275] In at least one embodiment, the graphics acceleration module 1946 or the respective graphics processing engines 1931-1932, N uses a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1914 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engines 1931-1932, N (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0276] Figure 19D An exemplary accelerator integration slice 1990 is shown. As used herein, a “slice” includes a designated portion of the processing resources of the accelerator integrated circuit 1936. The application’s effective address space 1982 in system memory 1918 stores process element 1983. In one embodiment, process element 1983 is stored in response to a GPU call 1981 from an application 1980 executing on processor 1907. Process element 1983 contains the process state of the corresponding application 1980. A job descriptor (WD) 1984 contained in process element 1983 may be a single job requested by the application, or it may contain a pointer to a job queue. In at least one embodiment, WD 1984 is a pointer to a job request queue in the application’s address space 1982.

[0277] The graphics acceleration module 1946 and / or the various graphics processing engines 1931-1932, N, can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 1984 to the graphics acceleration module 1946 to begin operations in a virtualized environment.

[0278] In at least one embodiment, the dedicated process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns either the graphics acceleration module 1946 or an individual graphics processing engine 1931. When the graphics acceleration module 1946 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 1936 for the owned partition; when the graphics acceleration module 1946 is assigned, the operating system initializes the accelerator integrated circuit 1936 for the owned process.

[0279] In operation, the WD acquisition unit 1991 in the accelerator integrated slice 1990 acquires the next WD 1984, which includes instructions for the work to be performed by one or more graphics processing engines of the graphics acceleration module 1946. Data from the WD 1984 can be stored in register 1945 and used by the MMU 1939, interrupt management circuitry 1947, and / or context management circuitry 1948, as shown. For example, one embodiment of the MMU 1939 includes segment / page roaming circuitry for accessing segment / page tables 1986 within the OS virtual address space 1985. The interrupt management circuitry 1947 can handle interrupt events 1992 received from the graphics acceleration module 1946. When performing graphics operations, the effective address 1993 generated by the graphics processing engines 1931-1932,N is translated into a real address by the MMU 1939.

[0280] In one embodiment, for each graphics processing engine 1931-1932, N and / or graphics acceleration module 1946, the same set of registers 1945 is copied, and said registers 1945 can be initialized by a hypervisor or operating system. Each of these copied registers can be included in the accelerator integration slice 1990. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0281]

[0282] Table 2 shows exemplary registers that can be initialized by the operating system.

[0283]

[0284] In one embodiment, each WD 1984 is specific to a particular graphics acceleration module 1946 and / or graphics processing engine 1931-1932,N. It contains all the information required for the graphics processing engine 1931-1932,N to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0285] Figure 19EAdditional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1998, in which a list of process elements 1999 is stored. The hypervisor real address space 1998 can be accessed via a hypervisor 1996, which virtualizes the graphics acceleration module engine for operating system 1995.

[0286] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1946. In at least one embodiment, there are two programming models, wherein the graphics acceleration module 1946 is shared by multiple processes and partitions, time-slice sharing, and graphics-oriented sharing.

[0287] In this model, the hypervisor 1996 owns the graphics acceleration module 1946 and makes its functionality available to all operating systems 1995. For the graphics acceleration module 1946 to support virtualization through the hypervisor 1996, the graphics acceleration module 1946 may comply with the following: (1) the job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1946 must provide a context saving and restoration mechanism; (2) the graphics acceleration module 1946 guarantees that the job requests of the application are completed within a specified amount of time, including any translation errors, or the graphics acceleration module 1946 provides the ability to preempt job processing; and (3) when operating in a directed shared programming model, fairness among the processes of the graphics acceleration module 1946 must be ensured.

[0288] In at least one embodiment, application 1980 needs to make an operating system 1995 system call using the graphics acceleration module 1946 type, working descriptor (WD), authority mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module 1946 type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module 1946 type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for the graphics acceleration module 1946 and can take the form of a graphics acceleration module 1946 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure describing the work to be performed by the graphics acceleration module 1946. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1936 and the graphics acceleration module 1946 does not support the User Authority Mask Overwrite Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1996 may selectively apply the Current Privilege Mask Overwrite Register (AMOR) value before placing the AMR into process element 1983. In at least one embodiment, the CSRP is one of registers 1945 that contains the effective address of a region in the application's address space 1982 for the graphics acceleration module 1946 to save and restore context state. This pointer is optional if saving state between jobs is not required or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0289] Upon receiving a system call, operating system 1995 can verify that application 1980 has been registered and granted permission to use graphics acceleration module 1946. Then, operating system 1995 uses the information shown in Table 3 to invoke hypervisor 1996.

[0290]

[0291] Upon receiving a hypervisor call, hypervisor 1996 verifies that operating system 1995 has been registered and granted permission to use graphics acceleration module 1946. Then, hypervisor 1996 adds process element 1983 to the linked list of process elements of the corresponding graphics acceleration module 1946 type. The process element may include the information shown in Table 4.

[0292]

[0293]

[0294] In at least one embodiment, the management program initializes multiple accelerator integration slice 1990 registers 1945.

[0295] like Figure 19F As shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1901-1902 and GPU memories 1920-1923. In this implementation, operations performed on GPUs 1910-1913 utilize the same virtual / effective memory address space to access processor memories 1901-1902, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1901, a second portion to second processor memory 1902, a third portion to GPU memory 1920, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1901-1902 and GPU memories 1920-1923, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0296] In one embodiment, the bias / coherence management circuitry 1994A-1994E within one or more MMUs 1939A-1939E ensures cache coherence between the caches of one or more host processors (e.g., 1905) and the GPUs 1910-1913, and implements biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, although in Figure 19F Several instances of bias / coherence management circuitry 1994A-1994E are shown, but bias / coherence circuitry can be implemented within the MMU of one or more host processors 1905 and / or within the accelerator integrated circuit 1936.

[0297] One embodiment allows GPU-attached memories 1920-1923 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU-attached memories 1920-1923 as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. This arrangement allows the host processor 1905 to software-set operands and access computation results without the overhead of conventional I / O DMA data copying. Such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU-attached memories 1920-1923 without cache coherence overhead can be critical for the execution time of offloaded computations. For example, in cases with high streaming write traffic to memory, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 1910-1913. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0298] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which may be a page-granular structure (e.g., controlled at the memory page level) comprising 1 or 2 bits of memory pages attached to each GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in GPUs 1910-1913, the bias table can be implemented across one or more stolen memory ranges of GPU-attached memories 1920-1923. Alternatively, the entire bias table can be maintained within the GPU.

[0299] In at least one embodiment, prior to actual access to GPU memory, the bias table entry associated with each access to GPU-attached memory 1920-1923 is accessed, causing the following operations: First, a local request from GPUs 1910-1913 to find its page in the GPU bias is directly forwarded to the corresponding GPU memory 1920-1923. A local request from the GPU to find its page in the host bias is forwarded to processor 1905 (e.g., via the high-speed link described above). In one embodiment, a request from processor 1905 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, requests to GPU bias pages can be forwarded to GPUs 1910-1913. In at least one embodiment, if the GPU is not currently using the page, the GPU may subsequently migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed through software-based mechanisms, hardware-assisted software mechanisms, or, in limited cases, purely hardware-based mechanisms.

[0300] One mechanism for changing the bias state employs an API call (e.g., OpenCL) that subsequently invokes the GPU's device driver, which then sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migrations, performs a cache refresh operation on the host. In at least one embodiment, the cache refresh operation is used for migrations from the host processor 1905 bias to the GPU bias, but not for the reverse migration.

[0301] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 1905 cannot cache. To access these pages, the processor 1905 may request access from the GPU 1910, which may or may not grant access immediately. Therefore, to reduce communication between the processor 1905 and the GPU 1910, it is beneficial to ensure that the GPU bias pages are those required by the GPU, not those required by the host processor 1905, and vice versa.

[0302] One or more hardware structures 1315 are used to execute one or more embodiments. This document may combine... Figure 13 A and / or Figure 13 B provides details about one or more hardware structures 1315.

[0303] In at least one embodiment, regarding Figure 19A F shows or describes at least one component for implementing about Figure 1-12The described techniques and / or functions. In at least one embodiment, regarding... Figures 19A-19F At least one GPU and / or multi-core processor, shown or described, is used to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to rows in the QC-LDPC basemap). In at least one embodiment, regarding... Figures 19A-19F At least one GPU and / or multi-core processor shown or described is used to perform a selected data decoding operation (e.g., a frame-plus operation or a compressed C2V operation). In at least one embodiment, regarding Figures 19A-19F At least one GPU and / or multi-core processor shown or described performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technique 1100, and / or technique 1200. In at least one embodiment, the multi-core processor, such as multi-core processor 1905, executes a kernel startup function that passes parameters to at least one core on a graphics processor such as GPU 1910, which selects a data decoding operation and / or performs an operation related to LDPC decoder 102, LDPC decoder 202, technique 1100, and / or technique 1200. Figure 1-12 The data decoding operation is described.

[0304] Figure 20 Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores, may be included in at least one embodiment.

[0305] Figure 20This is a block diagram illustrating an exemplary system on a chip integrated circuit 2000 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 2000 includes one or more application processors 2005 (e.g., CPUs), at least one graphics processor 2010, and may additionally include an image processor 2015 and / or a video processor 2020, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 2000 includes peripheral or bus logic including a USB controller 2025, a UART controller 2030, an SPI / SDIO controller 2035, and an I.sup.2S / I.sup.2C controller 2040. In at least one embodiment, the integrated circuit 2000 may include a display device 2045 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 2050 and a Mobile Industrial Processor Interface (MIPI) display interface 2055. In at least one embodiment, storage may be provided by a flash memory subsystem 2060, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 2065 for accessing an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits also include an embedded security engine 2070.

[0306] In at least one embodiment, regarding Figure 20 At least one component shown or described is used to achieve the combination Figure 1-12 The described techniques and / or functions. In at least one embodiment, the graphics processor 2010 is configured to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to rows in the QC-LDPC basemap). In at least one embodiment, the graphics processor 2010 is configured to perform the selected data decoding operation (e.g., a frame-plus operation or a compressed C2V operation). In at least one embodiment, the graphics processor 2010 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technique 1100, and / or technique 1200.

[0307] Figures 21A-21B Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0308] Figures 21A-21B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 21A An exemplary graphics processor 2110, which can be fabricated using one or more IP cores according to at least one embodiment, is shown. Figure 21B An additional exemplary graphics processor 2140, which can be fabricated using one or more IP cores, is shown according to at least one embodiment. In at least one embodiment, Figure 21A The graphics processor 2110 is a low-power graphics processor core. In at least one embodiment, Figure 21B The graphics processor 2140 is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 2110 and 2140 may be... Figure 18 A variant of the 1810 graphics processor.

[0309] In at least one embodiment, the graphics processor 2110 includes a vertex processor 2105 and one or more fragment processors 2115A-2115N (e.g., 2115A, 2115B, 2115C, 2115D to 2115N-1 and 2115N). In at least one embodiment, the graphics processor 2110 may execute different shader programs via separate logic, such that the vertex processor 2105 is optimized to perform operations for the vertex shader program, while one or more fragment processors 2115A-2115N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 2105 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 2115A-2115N use the primitive and vertex data generated by the vertex processor 2105 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 2115A-2115N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0310] In at least one embodiment, the graphics processor 2110 additionally includes one or more memory management units (MMUs) 2120A-2120B, one or more caches 2125A-2125B, and one or more circuit interconnects 2130A-2130B. In at least one embodiment, one or more MMUs 2120A-2120B provide virtual-to-physical address mappings for the graphics processor 2110, including virtual-to-physical address mappings for the vertex processor 2105 and / or fragment processors 2115A-2115N. Besides referencing vertex or image / texture data stored in one or more caches 2125A-2125B, this mapping may also reference vertex or image / texture data stored in memory. In at least one embodiment, one or more MMUs 2120A-2120B may be synchronized with other MMUs within the system, including with… Figure 18 One or more application processors 1805, graphics processors 1815, and / or video processors 1820 are associated with one or more MMUs, enabling each processor 1805-1820 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2130A-2130B enable the graphics processor 2110 to connect to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0311] In at least one embodiment, the graphics processor 2140 includes Figure 21A The graphics processor 2110 includes one or more MMUs 2120A-2120B, caches 2125A-2125B, and circuit interconnects 2130A-2130B. In at least one embodiment, the graphics processor 2140 includes one or more shader cores 2155A-2155N (e.g., 2155A, 2155B, 2155C, 2155D, 2155E, 2155F to 2155N-1 and 2155N) that provide a unified shader core architecture, wherein a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores may vary. In at least one embodiment, the graphics processor 2140 includes an inter-core task manager 2145 that acts as a thread dispatcher to assign execution threads to one or more shader cores 2155A-2155N and tile units 2158 to accelerate tile-based rendering operations, wherein rendering operations of a scene are subdivided in image space, for example, to take advantage of local spatial consistency within the scene or to optimize the use of internal caches.

[0312] In at least one embodiment, regarding Figure 21A and 21B At least one component shown or described is used to implement about Figure 1-12 The described techniques and / or functions. In at least one embodiment, at least one graphics processor 2110 is configured to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to rows in the QC-LDPC basemap). In at least one embodiment, at least one graphics processor 2110 is configured to perform the selected data decoding operation (e.g., a frame-plus operation or a compressed C2V operation). In at least one embodiment, at least one graphics processor 2110 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technique 1100, and / or technique 1200.

[0313] Figures 22A-22B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, Figure 22A It shows that it can be included in Figure 20 The graphics core 2200 within the graphics processor 2010, and in at least one embodiment, may be as follows: Figure 21B The Unified Shader Core 2155A-2155N shown is an example. Figure 22B A highly parallel general-purpose graphics processing unit 2230 suitable for deployment on a multi-chip module is shown in at least one embodiment.

[0314] In at least one embodiment, the graphics core 2200 includes a shared instruction cache 2202, texture units 2218, and a cache / shared memory 2220, which are shared for execution resources within the graphics core 2200. In at least one embodiment, the graphics core 2200 may include multiple slices 2201A-2201N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 2200. Slices 2201A-2201N may include supporting logic, including local instruction caches 2204A-2204N, thread schedulers 2206A-2206N, thread dispatchers 2208A-2208N, and a set of registers 2210A-2210N. In at least one embodiment, slices 2201A-2201N may include a set of additional functional units (AFU2212A-2212N), floating-point units (FPU 2214A-2214N), integer arithmetic logic units (ALU 2216-2216N), address calculation units (ACU 2213A-2213N), double-precision floating-point units (DPFPU 2215A-2215N), and matrix processing units (MPU2217A-2217N).

[0315] In at least one embodiment, the FPU 2214A-2214N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 2215A-2215N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 2216A-2216N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 2217A-2217N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 2217-2217N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 2212A-2212N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0316] In at least one embodiment, regarding Figure 22A At least one component shown or described is used to implement about Figure 1-12The described technologies and / or functions. In at least one embodiment, at least one graphics processor 2200 is configured to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to rows in the QC-LDPC basemap). In at least one embodiment, at least one graphics processor 2200 is configured to perform the selected data decoding operation (e.g., a frame-plus operation or a compressed C2V operation). In at least one embodiment, at least one graphics processor 2200 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technology 1100, and / or technology 1200.

[0317] Figure 22B A general-purpose processing unit (GPGPU) 2230 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by a set of graphics processing units. In at least one embodiment, the GPGPU 2230 can be directly linked to other instances of the GPGPU 2230 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 2230 includes a host interface 2232 for connection to a host processor. In at least one embodiment, the host interface 2232 is a PCI Express interface. In at least one embodiment, the host interface 2232 can be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 2230 receives commands from the host processor and uses a global scheduler 2234 to allocate execution threads associated with those commands to a set of compute clusters 2236A-2236H. In at least one embodiment, the compute clusters 2236A-2236H share a cache memory 2238. In at least one embodiment, cache memory 2238 can be used as a higher-level cache within the cache memory of computing clusters 2236A-2236H.

[0318] In at least one embodiment, the GPGPU 2230 includes memories 2244A-2244B, which are coupled to computing clusters 2236A-2236H via a set of memory controllers 2242A-2242B. In at least one embodiment, memories 2244A-2244B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0319] In at least one embodiment, each of the computing clusters 2236A-2236H includes a set of graphics cores, for example... Figure 22A The graphics core 2200 may include various types of integer and floating-point logic units that can perform computational operations across a range of precisions, including precisions suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 2236A-2236H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0320] In at least one embodiment, multiple instances of GPGPU 2230 can be configured as a computing cluster. In at least one embodiment, the communication used for synchronization and data exchange by computing clusters 2236A-2236H varies between embodiments. In at least one embodiment, multiple instances of GPGPU 2230 communicate via host interface 2232. In at least one embodiment, GPGPU 2230 includes an I / O hub 2239 that couples GPGPU 2230 to GPU link 2240, enabling direct connection to other instances of GPGPU 2230. In at least one embodiment, GPU link 2240 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 2230. In at least one embodiment, GPU link 2240 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2230 reside in a separate data processing system and communicate via network devices accessible through host interface 2232. In at least one embodiment, GPU link 2240 may be configured to enable connection to a host processor other than or as a replacement for host interface 2232.

[0321] In at least one embodiment, the GPGPU 2230 can be configured to train a neural network. In at least one embodiment, the GPGPU 2230 can be used within an inference platform. In at least one embodiment, when the GPGPU 2230 is used for inference, the GPGPU 2230 may include fewer compute clusters 2236A-2236H compared to when the GPGPU 2230 is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 2244A-2244B can differ between inference and training configurations, wherein a higher bandwidth memory technology is dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2230 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during the inference operation of the deployed neural network.

[0322] In at least one embodiment, regarding Figure 22B At least one component shown or described is used to implement about Figure 1-12 The described techniques and / or functions. In at least one embodiment, at least one GPGPU 2230 is used to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to rows in the QC-LDPC basemap). In at least one embodiment, at least one GPGPU 2230 is used to perform the selected data decoding operation (e.g., a frame-plus operation or a compressed C2V operation). In at least one embodiment, at least one GPGPU 2230 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technique 1100, and / or technique 1200.

[0323] Figure 23A block diagram of a computer system 2300 according to at least one embodiment is shown. In at least one embodiment, the computer system 2300 includes a processing subsystem 2301 having one or more processors 2302 and a system memory 2304 communicating via an interconnect path that may include a memory hub 2305. In at least one embodiment, the memory hub 2305 may be a separate component within a chipset component or may be integrated within one or more processors 2302. In at least one embodiment, the memory hub 2305 is coupled to an I / O subsystem 2311 via a communication link 2306. In at least one embodiment, the I / O subsystem 2311 includes an I / O hub 2307 that enables the computer system 2300 to receive input from one or more input devices 2308. In at least one embodiment, the I / O hub 2307 enables a display controller to provide output to one or more display devices 2310A, the display controller being included in one or more processors 2302. In at least one embodiment, one or more display devices 2310A coupled to the I / O hub 2307 may include local, internal or embedded display devices.

[0324] In at least one embodiment, the processing subsystem 2301 includes one or more parallel processors 2312 coupled to the memory hub 2305 via a bus or other communication link 2313. In at least one embodiment, the communication link 2313 can be any of many standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication architecture. In at least one embodiment, the one or more parallel processors 2312 form a computationally concentrated parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as multi-core integrated (MIC) processors. In at least one embodiment, the one or more parallel processors 2312 form a graphics processing subsystem that can output pixels to one or more display devices 2310A coupled via an I / O hub 2307. In at least one embodiment, the one or more parallel processors 2312 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 2310B.

[0325] In at least one embodiment, system storage unit 2314 may be connected to I / O hub 2307 to provide a storage mechanism for computer system 2300. In at least one embodiment, I / O switch 2316 may be used to provide an interface mechanism to enable connectivity between I / O hub 2307 and other components, such as network adapter 2318 and / or wireless network adapter 2319 which may be integrated into the platform, and various other devices that can be added via one or more additional devices 2320. In at least one embodiment, network adapter 2318 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 2319 may include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more wireless devices.

[0326] In at least one embodiment, the computer system 2300 may include other components not explicitly shown, such as USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 2307. In at least one embodiment, the interconnection can be implemented using any suitable protocol (e.g., a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interfaces and / or protocols). Figure 23 The communication paths of various components, such as NV-Link high-speed interconnect or interconnect protocols.

[0327] In at least one embodiment, one or more parallel processors 2312 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 2312 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computer system 2300 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2312, memory hub 2305, processor 2302, and I / O hub 2307 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computer system 2300 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 2300 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computer system.

[0328] In at least one embodiment, regarding Figure 23 At least one component shown or described is used to implement about Figure 1-12 The described techniques and / or functions. In at least one embodiment, at least one of processor 2302 and parallel processor 2312 is configured to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to rows of the QC-LDPC basemap). In at least one embodiment, at least one of processor 2302 and parallel processor 2312 is configured to execute the selected data decoding operation (e.g., a frame-plus operation or a compressed C2V operation). In at least one embodiment, at least one of processor 2302 and parallel processor 2312 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technique 1100, and / or technique 1200. In at least one embodiment, processor 2302 executes a kernel startup function that passes parameters to at least one kernel on at least one parallel processor 2312, which selects a data decoding operation and / or performs the data decoding operation with respect to LDPC decoder 102, LDPC decoder 202, technique 1100, and / or technique 1200. Figure 1-12 The data decoding operation described.

[0329] processor

[0330] Figure 24A A parallel processor 2400 according to at least one embodiment is illustrated. In at least one embodiment, various components of the parallel processor 2400 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2400 is according to an exemplary embodiment. Figure 23 The variant of the 2312, which includes one or more parallel processors, is shown.

[0331] In at least one embodiment, the parallel processor 2400 includes a parallel processing unit 2402. In at least one embodiment, the parallel processing unit 2402 includes an I / O unit 2404 that enables communication with other devices, including other instances of the parallel processing unit 2402. In at least one embodiment, the I / O unit 2404 can be directly connected to other devices. In at least one embodiment, the I / O unit 2404 is connected to other devices using a hub or switch interface (e.g., a memory hub 2305). In at least one embodiment, the connection between the memory hub 2305 and the I / O unit 2404 forms a communication link 2313. In at least one embodiment, the I / O unit 2404 is connected to a host interface 2406 and a memory crossbar switch 2416, wherein the host interface 2406 receives commands for performing processing operations, and the memory crossbar switch 2416 receives commands for performing memory operations.

[0332] In at least one embodiment, when host interface 2406 receives a command buffer via I / O unit 2404, host interface 2406 can direct work operations to execute those commands to front end 2408. In at least one embodiment, front end 2408 is coupled to scheduler 2410, which is configured to assign commands or other work items to processing cluster array 2412. In at least one embodiment, scheduler 2410 ensures that processing cluster array 2412 is correctly configured and in an active state before assigning tasks to processing cluster array 2412. In at least one embodiment, scheduler 2410 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2410 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing array 2412. In at least one embodiment, host software can demonstrate workloads scheduled on processing array 2412 via one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed on the processing array 2412 by the scheduler 2410 logic within the microcontroller, which includes the scheduler 2410.

[0333] In at least one embodiment, the processing cluster array 2412 may include up to "N" processing clusters (e.g., clusters 2414A, 2414B to 2414N). In at least one embodiment, each cluster 2414A-2414N of the processing cluster array 2412 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2410 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2414A-2414N of the processing cluster array 2412, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2410, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2412. In at least one embodiment, different clusters 2414A-2414N of the processing cluster array 2412 may be assigned to process different types of programs or to perform different types of computations.

[0334] In at least one embodiment, the processing cluster array 2412 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2412 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2412 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0335] In at least one embodiment, the processing cluster array 2412 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2412 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2412 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2402 may transfer data from system memory via I / O unit 2404 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2422) and then written back to system memory.

[0336] In at least one embodiment, when the parallel processing unit 2402 is used to perform graphics processing, the scheduler 2410 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among the multiple clusters 2414A-2414N of the processing cluster array 2412. In at least one embodiment, portions of the processing cluster array 2412 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2414A-2414N may be stored in a buffer to allow intermediate data to be transferred between the clusters 2414A-2414N for further processing.

[0337] In at least one embodiment, the processing cluster array 2412 may receive processing tasks to be executed via a scheduler 2410, which receives commands defining the processing tasks from a front end 2408. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 2410 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 2408. In at least one embodiment, the front end 2408 may be configured to ensure that the processing cluster array 2412 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0338] In at least one embodiment, each of one or more instances of the parallel processing unit 2402 may be coupled to the parallel processor memory 2422. In at least one embodiment, the parallel processor memory 2422 may be accessed via a memory crossbar switch 2416, which may receive memory requests from the processing cluster array 2412 and the I / O unit 2404. In at least one embodiment, the memory crossbar switch 2416 may be accessed via a memory interface 2418. In at least one embodiment, the memory interface 2418 may include a plurality of partition units (e.g., partition units 2420A, 2420B to 2420N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 2422. In at least one embodiment, the plurality of partition units 2420A-2420N are configured to be equal to the number of memory units, such that the first partition unit 2420A has a corresponding first memory unit 2424A, the second partition unit 2420B has a corresponding memory unit 2424B, and the Nth partition unit 2420N has a corresponding Nth memory unit 2424N. In at least one embodiment, the number of partition units 2420A-2420N may not be equal to the number of memory devices.

[0339] In at least one embodiment, memory cells 2424A-2424N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 2424A-2424N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 2424A-2424N, allowing partitioning cells 2420A-2420N to write portions of each rendering target in parallel, to efficiently utilize the available bandwidth of the parallel processor memory 2422. In at least one embodiment, local instances of the parallel processor memory 2422 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0340] In at least one embodiment, any of the clusters 2414A-2414N of the processing cluster array 2412 can process data to be written to any memory cell 2424A-2424N within the parallel processor memory 2422. In at least one embodiment, the memory crossbar switch 2416 can be configured to transfer the output of each cluster 2414A-2414N to any partition cell 2420A-2420N or another cluster 2414A-2414N, and the clusters 2414A-2414N can perform further processing operations on the output. In at least one embodiment, each cluster 2414A-2414N can communicate with the memory interface 2418 via the memory crossbar switch 2416 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 2416 has a connection to a memory interface 2418 for communication with I / O unit 2404, and a connection to a local instance of parallel processor memory 2422, thereby enabling processing units within different processing clusters 2414A-2414N to communicate with system memory or other memory not local to parallel processing unit 2402. In at least one embodiment, the memory crossbar switch 2416 may use virtual channels to separate traffic flows between clusters 2414A-2414N and partition units 2420A-2420N.

[0341] In at least one embodiment, multiple instances of the parallel processing unit 2402 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2402 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2402 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 2402 or the parallel processor 2400 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0342] Figure 24B This is a block diagram of a partitioning unit 2420 according to at least one embodiment. In at least one embodiment, the partitioning unit 2420 is... Figure 24AAn example of one of the partitioning units 2420A-2420N. In at least one embodiment, partitioning unit 2420 includes L2 cache 2421, frame buffer interface 2425, and ROP 2426 (raster operation unit). L2 cache 2421 is a read / write cache configured to perform load and store operations received from memory crossbar switch 2416 and ROP 2426. In at least one embodiment, L2 cache 2421 outputs read miss and urgent write-back requests to frame buffer interface 2425 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via frame buffer interface 2425. In at least one embodiment, frame buffer interface 2425 interacts with one of the memory cells in the parallel processor memory (such as memory cells 2424A-2424N of FIG. 24 (e.g., within parallel processor memory 2422)).

[0343] In at least one embodiment, ROP 2426 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2426 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 2426 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2426 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0344] In at least one embodiment, ROP 2426 is included within each processing cluster (e.g., clusters 2414A-2414N of FIG. 24), rather than within partition unit 2420. In at least one embodiment, read and write requests for pixel data are made via memory crossbar switch 2416 instead of pixel fragment data transfer. In at least one embodiment, the processed graphics data may be displayed on a display device (such as one or more display devices 2110 of FIG. 21), routed by processor 2102 for further processing, or... Figure 24A One of the processing entities within the parallel processor 2400 is routed for further processing.

[0345] Figure 24CThis is a block diagram of a processing cluster 2414 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is an example of one of the processing clusters 2414A-2414N of FIG. 24. In at least one embodiment, the processing cluster 2414 can be configured to execute a number of threads in parallel, wherein the term "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0346] In at least one embodiment, the operation of the processing cluster 2414 can be controlled by a pipeline manager 2432 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2432 receives instructions from the scheduler 2410 of FIG. 24 and manages the execution of these instructions via the graphics multiprocessor 2434 and / or texture unit 2436. In at least one embodiment, the graphics multiprocessor 2434 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2414 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 2414 may include one or more instances of the graphics multiprocessor 2434. In at least one embodiment, the graphics multiprocessor 2434 can process data, and the data crossover switch 2440 can be used to distribute the processed data to one of several possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2432 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossover switch 2440.

[0347] In at least one embodiment, each graphics multiprocessor 2434 within the processing cluster 2414 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0348] In at least one embodiment, instructions sent to the processing cluster 2414 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a general program on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 2434. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2434. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2434. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2434, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2434.

[0349] In at least one embodiment, the graphics multiprocessor 2434 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2434 may forgo the internal cache and use a cache memory (e.g., L1 cache 2448) within the processing cluster 2414. In at least one embodiment, each graphics multiprocessor 2434 may also access an L2 cache within partition units (e.g., partition units 2420A-2420N of FIG. 24), which are shared among all processing clusters 2414 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2434 may also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2402 may be used as global memory. In at least one embodiment, the processing cluster 2414 includes multiple instances of the graphics multiprocessor 2434, which may share common instructions and data that may be stored in the L1 cache 2448.

[0350] In at least one embodiment, each processing cluster 2414 may include a memory management unit (“MMU”) 2445 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2445 may reside within the memory interface 2418 of FIG. 24. In at least one embodiment, the MMU 2445 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more specifically, tiling) and optionally to cache line indices. In at least one embodiment, the MMU 2445 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 2434 or the L1 cache or processing cluster 2414. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0351] In at least one embodiment, the processing cluster 2414 may be configured such that each graphics multiprocessor 2434 is coupled to a texture unit 2436 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2434, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2434 outputs a processed task to a data crossbar switch 2440 to provide the processed task to another processing cluster 2414 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 2416. In at least one embodiment, the preROP 2442 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2434 and direct the data to a ROP unit that may be located together with partitioning units described herein (e.g., partitioning units 2420A-2420N of FIG. 24). In at least one embodiment, the PreROP 2442 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0352] In at least one embodiment, regarding Figure 24A -C shows or describes at least one component for implementing about Figure 1-12The described techniques and / or functions. In at least one embodiment, at least one parallel processor 2400 is configured to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to rows of the QC-LDPC basemap). In at least one embodiment, at least one parallel processor 2400 is configured to execute the selected data decoding operation (e.g., a frame-plus operation or a compressed C2V operation). In at least one embodiment, at least one of the parallel processors 2400 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technique 1100, and / or technique 1200.

[0353] Figure 24D A graphics multiprocessor 2434 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 2434 is coupled to a pipeline manager 2432 of a processing cluster 2414. In at least one embodiment, the graphics multiprocessor 2434 has an execution pipeline including, but not limited to, an instruction cache 2452, an instruction unit 2454, an address mapping unit 2456, a register file 2458, one or more general-purpose graphics processing unit (GPGPU) cores 2462, and one or more load / store units 2466. The GPGPU cores 2462 and the load / store units 2466 are coupled to a cache memory 2472 and a shared memory 2470 via a memory and cache interconnect 2468.

[0354] In at least one embodiment, instruction cache 2452 receives a stream of instructions to be executed from pipeline manager 2432. In at least one embodiment, instructions are cached in instruction cache 2452 and dispatched to instruction unit 2454 for execution. In at least one embodiment, instruction unit 2454 may dispatch instructions as thread groups (e.g., thread bundles), assigning each thread of the thread group to a different execution unit within GPGPU core 2462. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2456 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by load / store unit 2466.

[0355] In at least one embodiment, register file 2458 provides a set of registers for functional units of graphics multiprocessor 2434. In at least one embodiment, register file 2458 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 2434 (e.g., GPGPU core 2462, load / store unit 2466). In at least one embodiment, register file 2458 is partitioned among each functional unit, such that a dedicated portion of register file 2458 is allocated to each functional unit. In at least one embodiment, register file 2458 is partitioned among different thread bundles being executed by graphics multiprocessor 2434.

[0356] In at least one embodiment, each of the GPGPU cores 2462 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2434. In at least one embodiment, the GPGPU cores 2462 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2462 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 2434 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2462 may also include fixed-function or special-function logic.

[0357] In at least one embodiment, the GPGPU core 2462 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 2462 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed using a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel using a single SIMD8 logic unit.

[0358] In at least one embodiment, the memory and cache interconnect 2468 is an interconnect network connecting each functional unit of the graphics multiprocessor 2434 to the register file 2458 and the shared memory 2470. In at least one embodiment, the memory and cache interconnect 2468 is a cross-switch interconnect that allows the load / store unit 2466 to perform load and store operations between the shared memory 2470 and the register file 2458. In at least one embodiment, the register file 2458 can operate at the same frequency as the GPGPU core 2462, resulting in very low latency for data transfer between the GPGPU core 2462 and the register file 2458. In at least one embodiment, the shared memory 2470 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 2434. In at least one embodiment, the cache memory 2472 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 2436. In at least one embodiment, the shared memory 2470 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in cache memory 2472, the thread executing on GPGPU core 2462 can also programmatically store data in shared memory.

[0359] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core in the same package or on the same chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor.

[0360] In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0361] In at least one embodiment, regarding Figure 24D At least one component shown or described is used to implement about Figure 1-12The described techniques and / or functions. In at least one embodiment, at least one graphics multiprocessor 2434 is used to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to rows in the QC-LDPC basemap). In at least one embodiment, at least one graphics multiprocessor 2434 is used to perform the selected data decoding operation (e.g., a frame-plus operation or a compressed C2V operation). In at least one embodiment, at least one graphics multiprocessor 2434 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technique 1100, and / or technique 1200.

[0362] Figure 25 A multi-GPU computing system 2500 according to at least one embodiment is illustrated. In at least one embodiment, the multi-GPU computing system 2500 may include a processor 2502 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2506A-D via a host interface switch 2504. In at least one embodiment, the host interface switch 2504 is a PCI Express switch device that couples the processor 2502 to a PCI Express bus, through which the processor 2502 communicates with the GPGPUs 2506A-D. The GPGPUs 2506A-D may be interconnected via a set of high-speed P2P GPU-to-GPU links 2516. In at least one embodiment, the GPU-to-GPU links 2516 are connected to each of the GPGPUs 2506A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 2516 enable direct communication between each GPGPU 2506A-D without communication via the host interface bus 2504 to which the processor 2502 is connected. In at least one embodiment, when GPU-to-GPU traffic is directed to the P2P GPU link 2516, the host interface bus 2504 remains available for system memory access or, for example, communication with other instances of the multi-GPU computing system 2500 via one or more network devices. While in at least one embodiment, the GPGPUs 2506A-D are connected to the processor 2502 via the host interface switch 2504, in at least one embodiment, the processor 2502 includes direct support for the P2P GPU link 2516 and can be directly connected to the GPGPUs 2506A-D.

[0363] In at least one embodiment, regarding Figure 25At least one component shown or described is used to implement about Figure 1-12 The described technologies and / or functions. In at least one embodiment, at least one GPGPU 2506 is used to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to the row of the QC-LDPC basemap). In at least one embodiment, at least one GPGPU 2506 is used to perform the selected data decoding operation (e.g., a box-plus operation or a compressed C2V operation). In at least one embodiment, at least one GPGPU 2506 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technology 1100, and / or technology 1200. In at least one embodiment, processor 2502 executes a kernel startup function that passes parameters to at least one kernel on at least one GPGPU 2506, which selects the data decoding operation and / or performs the data decoding operation with respect to LDPC decoder 102, LDPC decoder 202, technology 1100, and / or technology 1200. Figure 1-12 The data decoding operation described.

[0364] Figure 26 This is a block diagram of a graphics processor 2600 according to at least one embodiment. In at least one embodiment, the graphics processor 2600 includes a ring interconnect 2602, a pipeline front end 2604, a media engine 2637, and graphics cores 2680A-2680N. In at least one embodiment, the ring interconnect 2602 couples the graphics processor 2600 to other processing units, said processing units including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2600 is one of many processors integrated within a multi-core processing system.

[0365] In at least one embodiment, the graphics processor 2600 receives multiple batches of commands via a ring interconnect 2602. In at least one embodiment, the input commands are interpreted by a command streamer 2603 in a pipeline front-end 2604. In at least one embodiment, the graphics processor 2600 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2680A-2680N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2603 provides the commands to the geometry pipeline 2636. In at least one embodiment, for at least some media processing commands, the command streamer 2603 provides the commands to a video front-end 2634, which is coupled to a media engine 2637. In at least one embodiment, the media engine 2637 includes a video quality engine (VQE) 2630 for video and image post-processing, and a multi-format encoding / decoding (MFX) engine 2633 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2636 and the media engine 2637 each generate an execution thread for the thread execution resources provided by at least one graphics core 2680A.

[0366] In at least one embodiment, the graphics processor 2600 includes scalable thread execution resources featuring modular cores 2680A-2680N (sometimes referred to as core slices), each graphics core having multiple sub-cores 2650A-550N, 2660A-2660N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2600 may have any number of graphics cores 2680A to 2680N. In at least one embodiment, the graphics processor 2600 includes a graphics core 2680A having at least a first sub-core 2650A and a second sub-core 2660A. In at least one embodiment, the graphics processor 2600 is a low-power processor with a single sub-core (e.g., 2650A). In at least one embodiment, the graphics processor 2600 includes multiple graphics cores 2680A-2680N, each graphics core including a set of first sub-cores 2650A-2650N and a set of second sub-cores 2660A-2660N. In at least one embodiment, each of the first sub-cores 2650A-2650N includes at least a first set of execution units 2652A-2652N and media / texture samplers 2654A-2654N. In at least one embodiment, each of the second sub-cores 2660A-2660N includes at least a second set of execution units 2662A-2662N and samplers 2664A-2664N. In at least one embodiment, each of the sub-cores 2650A-2650N and 2660A-2660N shares a set of shared resources 2670A-2670N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0367] In at least one embodiment, regarding Figure 26 At least one component shown or described is used to implement about Figure 1-12 The described technologies and / or functions. In at least one embodiment, at least one graphics processor 2600 is configured to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to rows in the QC-LDPC basemap). In at least one embodiment, at least one graphics processor 2600 is configured to perform the selected data decoding operation (e.g., a frame-plus operation or a compressed C2V operation). In at least one embodiment, at least one graphics processor 2600 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technology 1100, and / or technology 1200.

[0368] Figure 27 This is a block diagram illustrating a microarchitecture for a processor 2700 according to at least one embodiment, the processor 2700 including logic circuitry for executing instructions. In at least one embodiment, the processor 2700 can execute instructions, including x86 instructions, ARM instructions, and special-purpose instructions for application-specific integrated circuits (ASICs). In at least one embodiment, the processor 2710 may include registers for storing packaged data, such as the 64-bit wide MMX registers used in Intel Corporation's Santa Clara, California-enabled MMX technology microprocessors. TM Registers. In at least one embodiment, MMX registers available in integer and floating-point forms can operate alongside packaged data elements accompanied by Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technologies can hold such packaged data operands. In at least one embodiment, processor 2710 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0369] In at least one embodiment, processor 2700 includes an ordered front end (“front end”) 2701 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, front end 2701 may include several units. In at least one embodiment, instruction prefetcher 2726 fetches instructions from memory and provides the instructions to instruction decoder 2728, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2728 decodes the received instructions into one or more machine-executable so-called “micro-instructions” or “micro-operations” (also referred to as “micro-operations” or “micro-instructions”). In at least one embodiment, instruction decoder 2728 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, trace cache 2730 may assemble the decoded micro-instructions into a program-ordered sequence or trace in micro-instruction queue 2734 for execution. In at least one embodiment, when the trace cache 2730 encounters complex instructions, the microcode ROM 2732 provides the microinstructions required to complete the operation.

[0370] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-instructions are required to complete an instruction, the instruction decoder 2728 may access the microcode ROM 2732 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-instructions for processing at the instruction decoder 2728. In at least one embodiment, if multiple micro-instructions are required to complete the operation, the instructions may be stored in the microcode ROM 2732. In at least one embodiment, the trace cache 2730 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2732 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2732 has completed the micro-operation ordering of the instructions, the machine front end 2701 may resume fetching micro-operations from the trace cache 2730.

[0371] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2703 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions descend the pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 2703 includes, but is not limited to, an allocator / register renamer 2740, a memory microinstruction queue 2742, an integer / floating-point microinstruction queue 2744, a memory scheduler 2746, a fast scheduler 2702, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2704, and a simple floating-point scheduler (“simple FP scheduler”) 2706. In at least one embodiment, the fast scheduler 2702, the slow / general-purpose floating-point scheduler 2704, and the simple floating-point scheduler 2706 are also collectively referred to as “microinstruction schedulers 2702, 2704, 2706”. In at least one embodiment, the allocator / register renamer 2740 allocates the machine buffers and resources required for the sequential execution of each microinstruction. In at least one embodiment, the allocator / register renamer 2740 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 2740 also allocates entries for each microinstruction in one of two microinstruction queues, a memory microinstruction queue 2742 for memory operations and an integer / floating-point microinstruction queue 2744 for non-memory operations, preceding the memory scheduler 2746 and microinstruction schedulers 2702, 2704, and 2706. In at least one embodiment, the microinstruction schedulers 2702, 2704, and 2706 determine when they are ready to execute a microinstruction based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. The fast scheduler 2702 of at least one embodiment can schedule on each half of the master clock cycle, while the slow / general-purpose floating-point scheduler 2704 and the simple floating-point scheduler 2706 can schedule once per master processor clock cycle. In at least one embodiment, microinstruction schedulers 2702, 2704, and 2706 arbitrate the scheduling port to schedule microinstructions for execution.

[0372] In at least one embodiment, execution block b11 includes, but is not limited to, integer register file / tribute network 2708, floating-point register file / tribute network (“FP register file / tribute network”) 2710, address generation units (“AGU”) 2712 and 2714, fast arithmetic logic units (“fast ALU”) 2716 and 2718, slow arithmetic logic unit (“slow ALU”) 2720, floating-point ALU (“FP”) 2722, and floating-point move unit (“FP move”) 2724. In at least one embodiment, integer register file / tribute network 2708 and floating-point register file / bypass network 2710 are also referred to herein as “register files 2708, 2710”. In at least one embodiment, AGUs 2712 and 2714, fast ALUs 2716 and 2718, slow ALU 2720, floating-point ALU 2722, and floating-point movement unit 2724 are also referred to herein as "execution units 2712, 2714, 2716, 2718, 2720, 2722, and 2724". In at least one embodiment, execution block b11 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0373] In at least one embodiment, register files 2708, 2710 may be arranged between microinstruction schedulers 2702, 2704, 2706 and execution units 2712, 2714, 2716, 2718, 2720, 2722, and 2724. In at least one embodiment, integer register file / tribute network 2708 performs integer operations. In at least one embodiment, floating-point register file / tribute network 2710 performs floating-point operations. In at least one embodiment, each of register files 2708, 2710 may include, but is not limited to, a tribute network that can bypass or forward recently completed results not yet written to the register file to a new dependent object. In at least one embodiment, register files 2708, 2710 can communicate data with each other. In at least one embodiment, integer register file / tribute network 2708 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, the floating-point register file / branch network 2710 may include, but is not limited to, entries with a width of 128 bits, since floating-point instructions typically have operands with a width of 64 to 128 bits.

[0374] In at least one embodiment, execution units 2712, 2714, 2716, 2718, 2720, 2722, and 2724 can execute instructions. In at least one embodiment, register files 2708 and 2710 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2700 can be, but is not limited to, any number of execution units 2712, 2714, 2716, 2718, 2720, 2722, and 2724, and combinations thereof. In at least one embodiment, floating-point ALU 2722 and floating-point move unit 2724 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2722 can be, but is not limited to, a 64-bit multiplication-64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to the fast ALUs 2716 and 2718. In at least one embodiment, the fast ALUs 2716 and 2718 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to the slow ALU 2720, because the slow ALU 2720 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by AGUS 2712 and 2714. In at least one embodiment, the fast ALU 2716, fast ALU 2718, and slow ALU 2720 can perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 2716, fast ALU 2718, and slow ALU 2720 can be implemented to support various data bit sizes, including sixteen, thirty-two, 128, 276, etc. In at least one embodiment, the floating-point ALU 2722 and the floating-point movement unit 2724 can be implemented to support a range of operands with various bit widths. In at least one embodiment, the floating-point ALU 2722 and the floating-point movement unit 2724 can operate on 128-bit wide packaged data operands in conjunction with SIMD and multimedia instructions.

[0375] In at least one embodiment, microinstruction schedulers 2702, 2704, and 2706 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed within processor 2700, processor 2700 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily deprives the scheduler of the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and may allow independent operations to be completed. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0376] In at least one embodiment, the term "register" may refer to an onboard processor storage location that can be used as part of an instruction that identifies operands. In at least one embodiment, a register may be one that can be used externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented using a variety of different techniques via circuitry within the processor, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

[0377] In at least one embodiment, regarding Figure 27 At least one component shown or described is used to implement about Figure 1-12The described technologies and / or functions. In at least one embodiment, at least one processor 2700 is configured to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to rows in the QC-LDPC basemap). In at least one embodiment, at least one processor 2700 is configured to perform the selected data decoding operation (e.g., a frame-plus operation or a compressed C2V operation). In at least one embodiment, at least one processor 2700 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technology 1100, and / or technology 1200.

[0378] Figure 28 A block diagram of a processing system according to at least one embodiment is shown. In at least one embodiment, system 2800 includes one or more processors 2802 and one or more graphics processors 2808, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2802 or processor cores 2807. In at least one embodiment, system 2800 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0379] In at least one embodiment, system 2800 may include or be integrated into a server-based gaming platform, including a game console, mobile game console, handheld game console, or online game console, which are game and media consoles. In at least one embodiment, system 2800 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, processing system 2800 may also include components coupled to or integrated into a wearable device, such as a smartwatch, smart glasses, augmented reality, or virtual reality device. In at least one embodiment, processing system 2800 is a television or set-top box device having one or more processors 2802 and a graphical interface generated by one or more graphics processors 2808.

[0380] In at least one embodiment, each of the one or more processors 2802 includes one or more processor cores 2807 for processing instructions that, when executed, perform operations against the system and user software. In at least one embodiment, each of the one or more processor cores 2807 is configured to process a particular instruction set 2809. In at least one embodiment, the instruction set 2809 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, each processor core 2807 may process a different instruction set 2809, which may include instructions that facilitate the emulation of other instruction sets. In at least one embodiment, the processor core 2807 may also include other processing devices, such as a digital signal processor (DSP).

[0381] In at least one embodiment, processor 2802 includes cache memory 2804. In at least one embodiment, processor 2802 may have a single internal cache or more levels of internal caches. In at least one embodiment, the cache memory is shared among various components of processor 2802. In at least one embodiment, processor 2802 also uses an external cache (e.g., a Level 3 (L3) cache or a last-level cache (LLC)) (not shown), which can be shared among processor cores 2807 using known cache coherence techniques. In at least one embodiment, processor 2802 further includes a register file 2806, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 2806 may include general-purpose registers or other registers.

[0382] In at least one embodiment, one or more processors 2802 are coupled to one or more interface buses 2810 to transmit communication signals, such as address, data, or control signals, between the processors 2802 and other components in the system 2800. In at least one embodiment, the interface bus 2810 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface 2810 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 2802 includes an integrated memory controller 2816 and a platform controller hub 2830. In at least one embodiment, the memory controller 2816 facilitates communication between memory devices and other components of the processing system 2800, while the platform controller hub (PCH) 2830 provides connectivity to input / output (I / O) devices via a local I / O bus.

[0383] In at least one embodiment, memory device 2820 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or a device with suitable performance for use as processor memory. In at least one embodiment, memory device 2820 may be used as system memory of processing system 2800 to store data 2822 and instructions 2821 for use when one or more processors 2802 execute an application or process. In at least one embodiment, memory controller 2816 is also coupled to an optional external graphics processor 2812, which may communicate with one or more graphics processors 2808 of processor 2802 to perform graphics and media operations. In at least one embodiment, display device 2811 may be connected to processor 2802. In at least one embodiment, display device 2811 may include one or more internal display devices, such as in mobile electronic devices or laptop devices, or external display devices connected via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 2811 may include a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) or augmented reality (AR) applications.

[0384] In at least one embodiment, the platform controller hub 2830 enables peripheral devices to connect to the storage device 2820 and the processor 2802 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 2846, a network controller 2834, a firmware interface 2828, a wireless transceiver 2826, a touch sensor 2825, and a data storage device 2824 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 2824 may be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2825 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2826 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or LTE transceiver. In at least one embodiment, the firmware interface 2828 enables communication with the system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2834 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to interface bus 2810. In at least one embodiment, audio controller 2846 is a multi-channel high-definition audio controller. In at least one embodiment, processing system 2800 includes an optional legacy I / O controller 2840 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. In at least one embodiment, platform controller hub 2830 may also be connected to one or more Universal Serial Bus (USB) controllers 2842 that connect input devices, such as a keyboard and mouse combination 2843, a camera 2844, or other USB input devices.

[0385] In at least one embodiment, instances of the memory controller 2816 and platform controller hub 2830 may be integrated into a discrete external graphics processor, such as external graphics processor 2812. In at least one embodiment, the platform controller hub 2830 and / or the memory controller 2816 may be external to one or more processors 2802. For example, in at least one embodiment, system 2800 may include an external memory controller 2816 and platform controller hub 2830, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset communicating with processor 2802.

[0386] In at least one embodiment, regarding Figure 28 At least one component shown or described is used to implement about Figure 1-12The described technologies and / or functions. In at least one embodiment, at least one graphics processor 2808 is used to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to rows of the QC-LDPC basemap). In at least one embodiment, at least one graphics processor 2808 is used to perform the selected data decoding operation (e.g., a frame-plus operation or a compressed C2V operation). In at least one embodiment, at least one of the graphics processors 2808 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technology 1100, and / or technology 1200. In at least one embodiment, processor core 2807 executes a kernel startup function that passes parameters to at least one core on at least one graphics processor 2808, which selects the data decoding operation and / or performs the data decoding operation with respect to LDPC decoder 102, LDPC decoder 202, technology 1100, and / or technology 1200. Figure 1-12 The data decoding operation described.

[0387] Figure 29 This is a block diagram of a processor 2900 having one or more processor cores 2902A-2902N, an integrated memory controller 2914, and an integrated graphics processor 2908 according to at least one embodiment. In at least one embodiment, the processor 2900 may include additional cores, up to and including additional cores 2902N indicated by dashed boxes. In at least one embodiment, each processor core 2902A-2902N includes one or more internal cache units 2904A-2904N. In at least one embodiment, each processor core may also access one or more shared cache units 2906.

[0388] In at least one embodiment, internal cache units 2904A-2904N and shared cache unit 2906 represent a cache memory hierarchy within processor 2900. In at least one embodiment, cache memory units 2904A-2904N may include at least one level of instruction and data cache within each processor core and one or more levels of cache in a shared intermediate cache, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, wherein the highest level of cache preceding external memory is classified as LLC. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2906 and 2904A-2904N.

[0389] In at least one embodiment, the processor 2900 may further include a set of one or more bus controller units 2916 and a system agent core 2910. In at least one embodiment, one or more bus controller units 2916 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 2910 provides management functions for various processor components. In at least one embodiment, the system agent core 2910 includes one or more integrated memory controllers 2914 to manage access to various external memory devices (not shown).

[0390] In at least one embodiment, one or more processor cores 2902A-2902N include support for multi-threaded concurrent processing. In at least one embodiment, system agent core 2910 includes components for coordinating and operating cores 2902A-2902N during multi-threaded processing. In at least one embodiment, system agent core 2910 may additionally include a power control unit (PCU) including logic and components for regulating one or more power states of processor cores 2902A-2902N and graphics processor 2908.

[0391] In at least one embodiment, processor 2900 further includes a graphics processor 2908 for performing graph processing operations. In at least one embodiment, graphics processor 2908 is coupled to a shared cache unit 2906 and a system proxy core 2910 including one or more integrated memory controllers 2914. In at least one embodiment, system proxy core 2910 further includes a display controller 2911 for driving graphics processor outputs to one or more coupled displays. In at least one embodiment, display controller 2911 may also be a separate module coupled to graphics processor 2908 via at least one interconnect, or it may be integrated within graphics processor 2908.

[0392] In at least one embodiment, ring-based interconnect unit 2912 is used to couple internal components of processor 2900. In at least one embodiment, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, may be used. In at least one embodiment, graphics processor 2908 is coupled to ring interconnect 2912 via I / O link 2913.

[0393] In at least one embodiment, I / O link 2913 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory module 2918 (e.g., eDRAM module). In at least one embodiment, each of processor cores 2902A-2902N and graphics processor 2908 uses embedded memory module 2918 as a shared last-level cache.

[0394] In at least one embodiment, processor cores 2902A-2902N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2902A-2902N are heterogeneous in terms of instruction set architecture (ISA), with one or more processor cores 2902A-2902N executing a common instruction set, while one or more other processor cores 2902A-2902N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, processor cores 2902A-2902N are heterogeneous in terms of microarchitecture, with one or more cores having relatively high power consumption coupled to one or more power cores having lower power consumption. In at least one embodiment, processor 2900 may be implemented on one or more chips or implemented as a SoC integrated circuit.

[0395] In at least one embodiment, regarding Figure 29 At least one component shown or described is used to implement about Figure 1-12 The described technologies and / or functions. In at least one embodiment, at least one graphics processor 2908 is used to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to rows of the QC-LDPC basemap). In at least one embodiment, at least one graphics processor 2908 is used to perform the selected data decoding operation (e.g., a box-plus operation or a compressed C2V operation). In at least one embodiment, at least one graphics processor 2908 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technology 1100, and / or technology 1200. In at least one embodiment, at least one processor core 2902 executes a kernel startup function that passes parameters to at least one core on at least one graphics processor 2908, which selects the data decoding operation and / or performs the data decoding operation with respect to LDPC decoder 102, LDPC decoder 202, technology 1100, and / or technology 1200. Figure 1-12 The data decoding operation described.

[0396] Figure 30 This is a block diagram of a graphics processing unit 3000, which may be a discrete graphics processing unit or a graphics processing unit integrated with multiple processing cores. In at least one embodiment, the graphics processing unit 3000 communicates with registers on the graphics processing unit 3000 and commands placed in memory via a memory-mapped I / O interface. In at least one embodiment, the graphics processing unit 3000 includes a memory interface 3014 for accessing memory. In at least one embodiment, the memory interface 3014 is an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0397] In at least one embodiment, the graphics processor 3000 further includes a display controller 3002 for driving display output data to the display device 3020. In at least one embodiment, the display controller 3002 includes a combination of hardware for one or more overlay planes of the display device 3020 and multi-layer video or user interface elements. In at least one embodiment, the display device 3020 may be an internal or external display device. In at least one embodiment, the display device 3020 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In at least one embodiment, the graphics processor 3000 includes a video codec engine 3006 for encoding, decoding, or transcoding media into one or more media encoding formats, encoding, decoding, or transcoding from one or more media encoding formats, or encoding, decoding, or transcoding between one or more media encoding formats, including but not limited to Moving Picture Experts Group (MPEG) formats (e.g., MPEG-2), Advanced Video Coding (AVC) formats (e.g., H.264 / MPEG-4 AVC, and SMPTE 421M / VC-1), and Joint Picture Experts Group (JPEG) formats (e.g., JPEG) and MotionJPEG (MJPEG) formats.

[0398] In at least one embodiment, the graphics processor 3000 includes a block image transfer (BLIT) engine 3004 to perform two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfer. However, in at least one embodiment, one or more components of a graphics processing engine (GPE) 3010 are used to perform 2D graphics operations. In at least one embodiment, the GPE 3010 is a computational engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0399] In at least one embodiment, GPE 3010 includes a 3D pipeline 3012 for performing 3D operations, such as rendering 3D images and scenes using processing functions that manipulate 3D primitive shapes (e.g., rectangles, triangles, etc.). In at least one embodiment, 3D pipeline 3012 includes programmable and fixed function elements that perform various tasks and / or generate execution threads to 3D / media subsystem 3015. While 3D pipeline 3012 can be used to perform media operations, in at least one embodiment, GPE 3010 also includes a media pipeline 3016 for performing media operations such as video post-processing and image enhancement.

[0400] In at least one embodiment, the media pipeline 3016 includes fixed-function or programmable logic units for performing one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, replacing or representing the video codec engine 3006. In at least one embodiment, the media pipeline 3016 also includes a thread generation unit for generating threads to execute on the 3D / media subsystem 3015. In at least one embodiment, the generated threads perform computations of media operations on one or more graphics execution units included in the 3D / media subsystem 3015.

[0401] In at least one embodiment, the 3D / media subsystem 3015 includes logic for executing threads generated by the 3D pipeline 3012 and the media pipeline 3016. In at least one embodiment, the 3D pipeline 3012 and the media pipeline 3016 send thread execution requests to the 3D / media subsystem 3015, which includes thread dispatch logic for arbitrating various requests and dispatching them to available thread execution resources. In at least one embodiment, the execution resources include an array of graphics execution units for processing 3D and media threads. In at least one embodiment, the 3D / media subsystem 3015 includes one or more internal caches for thread instructions and data. In at least one embodiment, the subsystem 3015 also includes shared memory, including registers and addressable memory, for sharing data between threads and storing output data.

[0402] In at least one embodiment, regarding Figure 30 At least one component shown or described is used to implement about Figure 1-12The described technologies and / or functions. In at least one embodiment, at least one graphics processor 3000 is configured to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to rows in the QC-LDPC basemap). In at least one embodiment, at least one graphics processor 3000 is configured to perform the selected data decoding operation (e.g., a frame-plus operation or a compressed C2V operation). In at least one embodiment, at least one graphics processor 3000 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technology 1100, and / or technology 1200.

[0403] Figure 31 This is a block diagram of a graphics processing engine 3110 of a graphics processor according to at least one embodiment. In at least one embodiment, the graphics processing engine (GPE) 3110 is... Figure 28 The version of GPE 2810 shown is illustrated. In at least one embodiment, the media pipeline 3116 is optional and may not be explicitly included in GPE 3110. In at least one embodiment, a separate media and / or image processor is coupled to GPE 3110.

[0404] In at least one embodiment, GPE 3110 is coupled to or includes command stream converter 3103, which provides command streams to 3D pipeline 3112 and / or media pipeline 3116. In at least one embodiment, command stream converter 3103 is coupled to memory, which may be system memory, or one or more of internal cache memory and shared cache memory. In at least one embodiment, command stream converter 3103 receives commands from memory and sends the commands to 3D pipeline 3112 and / or media pipeline 3116. In at least one embodiment, the commands are instructions, primitives, or micro-operations retrieved from a circular buffer that stores commands for 3D pipeline 3112 and media pipeline 3116. In at least one embodiment, the circular buffer may further include a batch command buffer storing multiple commands in batches. In at least one embodiment, commands for 3D pipeline 3112 may further include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 3112 and / or image data and memory objects for media pipeline 3116. In at least one embodiment, the 3D pipeline 3112 and the media pipeline 3116 process commands and data by performing operations or by dispatching one or more execution threads to the graphics core array 3114. In at least one embodiment, the graphics core array 3114 includes one or more graphics core blocks (e.g., one or more graphics cores 3115A, one or more graphics cores 3115B), each block including one or more graphics cores. In at least one embodiment, each graphics core includes a set of graphics execution resources, which include general and graphics-specific execution logic for performing graphics and computation operations, as well as fixed-function texture processing and / or machine learning and artificial intelligence acceleration logic.

[0405] In at least one embodiment, the 3D pipeline 3112 includes fixed functions and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 3114. In at least one embodiment, the graphics core array 3114 provides a unified execution resource block for processing shader programs. In at least one embodiment, the multipurpose execution logic (e.g., execution units) within the graphics cores 3115A-3115B of the graphics core array 3114 includes support for various 3D API shader languages ​​and can execute multiple concurrently running threads associated with multiple shaders.

[0406] In at least one embodiment, the graphics core array 3114 further includes execution logic for performing media functions, such as video and / or image processing. In at least one embodiment, in addition to graphics processing operations, the execution unit also includes general-purpose logic programmable to perform parallel general-purpose computing operations.

[0407] In at least one embodiment, output data can be output to memory in a unified return buffer (URB) 3118, the output data being generated by a thread executing on the graphics core array 3114. In at least one embodiment, the URB 3118 can store data from multiple threads. In at least one embodiment, the URB 3118 can be used to send data between different threads executing on the graphics core array 3114. In at least one embodiment, the URB 3118 can also be used for synchronization between threads on the graphics core array 3114 and fixed-function logic within shared-function logic 3120.

[0408] In at least one embodiment, the graphics core array 3114 is scalable, such that it includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of the GPE 3110. In at least one embodiment, the execution resources are dynamically scalable, such that they can be enabled or disabled as needed.

[0409] In at least one embodiment, the graphics core array 3114 is coupled to shared function logic 3120, which includes multiple resources shared among the graphics cores in the graphics core array 3114. In at least one embodiment, the shared functions performed by the shared function logic 3120 are embodied in hardware logic units that provide dedicated supplementary functions to the graphics core array 3114. In at least one embodiment, the shared function logic 3120 includes, but is not limited to, a sampler 3121, math 3122, and inter-thread communication (ITC) logic 3123. In at least one embodiment, one or more caches 3125 are included in or coupled to the shared function logic 3120.

[0410] In at least one embodiment, shared functionality is used if the demand for dedicated functionality is insufficient to be contained within the graphics core array 3114. In at least one embodiment, a single instance of the dedicated functionality is used within shared functionality logic 3120 and shared among other execution resources within the graphics core array 3114. In at least one embodiment, a specific shared functionality may be included within shared functionality logic 3116 within the graphics core array 3114, said specific shared functionality being widely used within shared functionality logic 3120 of the graphics core array 3114. In at least one embodiment, shared functionality logic 3116 within the graphics core array 3114 may include some or all of the logic within shared functionality logic 3120. In at least one embodiment, all logic elements within shared functionality logic 3120 may be replicated within shared functionality logic 3116 of the graphics core array 3114. In at least one embodiment, shared functionality logic 3120 is excluded to support shared functionality logic 3116 within the graphics core array 3114.

[0411] In at least one embodiment, regarding Figure 31 At least one component shown or described is used to implement about Figure 1-12 The described technologies and / or functions. In at least one embodiment, at least one graphics processing engine 3110 is used to select one or more data decoding operations to perform LDPC decoding. In at least one embodiment, the data decoding operation is selected at least in part based on the row degree of the QC-LDPC basemap. In at least one embodiment, the data decoding operation is used to decode one or more 5G signals. In at least one embodiment, the data decoding operation is selected at least in part based on the sparsity of the data (e.g., corresponding to rows in the QC-LDPC basemap). In at least one embodiment, at least one graphics processing engine 3110 is used to perform the selected data decoding operation (e.g., a frame-plus operation or a compressed C2V operation). In at least one embodiment, at least one graphics processing engine 3110 performs at least one aspect described with respect to LDPC decoder 102, LDPC decoder 202, technology 1100, and / or technology 1200.

[0412] Figure 32This is a block diagram of the hardware logic of a graphics processor core 3200 according to at least one embodiment described herein. In at least one embodiment, the graphics processor core 3200 is included within a graphics core array. In at least one embodiment, the graphics processor core 3200 (sometimes referred to as a core slice) may be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 3200 is an example of a graphics core slice, and the graphics processor described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 3200 may include a fixed-function block 3230 coupled to a plurality of subcores 3201A-3201F, the subcores also referred to as subslices, which include modular blocks of general-purpose and fixed-function logic.

[0413] In at least one embodiment, the fixed-function block 3230 includes a geometry and fixed-function pipeline 3236, which, for example, may be shared by all sub-cores of the graphics processor 3200 in a lower-performance and / or lower-power graphics processor implementation. In at least one embodiment, the geometry and fixed-function pipeline 3236 includes a 3D fixed-function pipeline, a video front-end unit, a thread generator and a thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0414] In at least one fixed embodiment, the fixed functional block 3230 further includes a graphics SoC interface 3237, a graphics microcontroller 3238, and a media pipeline 3239. In at least one embodiment, the graphics SoC interface 3237 provides an interface between the graphics core 3200 and other processor cores in the on-chip integrated circuit system. In at least one embodiment, the graphics microcontroller 3238 is a programmable subprocessor configurable to manage various functions of the graphics processor 3200, including thread dispatch, scheduling, and preemption. In at least one embodiment, the media pipeline 3239 includes logic that facilitates decoding, encoding, preprocessing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 3239 implements media operations via requests for computation or sampling logic within subcores 3201-3201F.

[0415] In at least one embodiment, the SoC interface 3237 enables the graphics core 3200 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared last-level cache, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 3237 also enables communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enables the use and / or implementation of global memory atoms that can be shared between the graphics core 3200 and the CPU within the SoC. In at least one embodiment, the SoC interface 3237 also implements power management control for the graphics core 3200 and enables interfacing between the clock domain of the graphics core 3200 and other clock domains within the SoC. In at least one embodiment, the SoC interface 3237 enables the receipt of command buffers from a command stream converter and a global thread dispatcher, configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, when a media operation is to be performed, commands and instructions can be dispatched to the media pipeline 3239, or when a graphics processing operation is to be performed, they can be assigned to the geometry and fixed-function pipeline (e.g., geometry and fixed-function pipeline 3236, and / or geometry and fixed-function pipeline 3214).

[0416] In at least one embodiment, the graphics microcontroller 3238 can be configured to perform various scheduling and management tasks on the graphics core 3200. In at least one embodiment, the graphics microcontroller 3238 can perform graphics and / or compute workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 3202A-3202F, 3204A-3204F in subcores 3201A-3201F. In at least one embodiment, host software executing on the CPU core of the SoC including the graphics core 3200 can submit a workload of one of a plurality of graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operation includes determining which workload should be run next, submitting the workload to a command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In at least one embodiment, the graphics microcontroller 3238 may also facilitate a low-power or idle state of the graphics core 3200, thereby providing the graphics core 3200 with the ability to save and restore registers across low-power state transitions within the graphics core 3200, independent of the operating system and / or the graphics driver software on the system.

[0417] In at least one embodiment, the graphics core 3200 may have up to N more or fewer modular sub-cores than the illustrated sub-cores 3201A-3201F. For each group of N sub-cores, in at least one embodiment, the graphics core 3200 may further include shared functional logic 3210, shared and / or cache memory 3212, geometry / fixed-function pipeline 3214, and additional fixed-function logic 3216 to accelerate various graphics and computational processing operations. In at least one embodiment, the shared functional logic 3210 may include logic units (e.g., samplers, mathematical and / or inter-thread communication logic) that can be shared by each of the N sub-core...

Claims

1. A processor, comprising: One or more circuits are configured to select one of a plurality of 5G signal decoding operations based at least in part on the sparsity of error correction information associated with a fifth-generation (5G) signal, wherein the 5G signal decoding operation is a low-density parity-check (LDPC) decoding operation, and the one or more circuits are configured to select a first type of LDPC decoding operation in response to the sparsity of the error correction information being less than or equal to a predefined threshold, and to select a second type of LDPC decoding operation in response to the sparsity of the error correction information being greater than the predefined threshold, wherein the error correction information is represented using a quasi-cyclic low-density parity-check (QC-LDPC) basemap.

2. The processor of claim 1, wherein the 5G signal decoding operation is a quasi-cyclic low-density parity-check (QC-LDPC) decoding operation, and the one or more circuits are configured to perform QC-LDPC decoding at least in part based on the row degree of the QC-LDPC basemap, wherein the row degree indicates the number of non-empty elements in a row.

3. The processor of claim 1, wherein the 5G signal decoding operation is a low-density parity-check (LDPC) decoding operation, and the one or more circuits are configured to perform a first type of operation in response to a row degree of a quasi-cyclic low-density parity-check (QC-LDPC) basemap being less than or equal to a predefined threshold, and to perform a second type of operation in response to a row degree being greater than the predefined threshold, wherein the row degree indicates the number of non-empty elements in a row and is related to the sparsity of the error correction information.

4. The processor of claim 1, wherein the one or more circuits are configured to perform a frame-plus-decoding operation in response to the sparsity of the error correction information being less than or equal to the predefined threshold.

5. The processor of claim 1, wherein the one or more circuits are configured to perform a frame-plus decoding operation in response to the sparsity of the error correction information being less than or equal to the predefined threshold, and to perform a compression-to-value decoding operation in response to the sparsity of the error correction information being greater than the predefined threshold.

6. The processor of claim 1, wherein the processor is a parallel processor, the 5G signal decoding operation is a quasi-cyclic low-density parity-check (QC-LDPC) decoding operation, and the one or more circuits execute multiple threads, wherein each row in the cyclic matrix corresponding to the non-empty elements of the QC-LDPC basemap is processed by a thread among the multiple threads.

7. A system comprising: One or more processors are configured to select one of a plurality of 5G signal decoding operations based at least in part on the sparsity of error correction information associated with a fifth-generation (5G) signal, wherein the 5G signal decoding operation is a low-density parity-check (LDPC) decoding operation, and the one or more processors are configured to perform a first type of data decoding operation in response to the sparsity of the error correction information being less than or equal to a predefined threshold, and to perform a second type of data decoding operation in response to the sparsity of the error correction information being greater than the predefined threshold.

8. The system of claim 7, wherein the first type of data decoding operation is a frame-plus-decoding operation.

9. The system of claim 7, wherein the one or more processors are configured to perform decoding at least in part based on the row degree of a quasi-cyclic low-density parity-check (QC-LDPC) basemap, wherein the row degree indicates the number of non-empty elements in a row.

10. The system of claim 7, wherein the one or more processors are configured to perform a selection box plus decoding operation in response to the sparsity of the error correction information being less than or equal to the predefined threshold, and to select a compression checksum to value decoding operation in response to the sparsity of the error correction information being greater than the predefined threshold.

11. The system of claim 7, wherein the one or more processors are configured to execute multiple threads in parallel, wherein each row in the cyclic matrix corresponding to the non-empty elements of the quasi-cyclic low-density parity-check (QC-LDPC) basemap is processed by a thread among the multiple threads.

12. The system of claim 7, wherein the one or more processors are further configured to select the 5G signal decoding operation based at least in part on an indicator of a quasi-cyclic low-density parity-check (QC-LDPC) basemap.

13. The system of claim 7, wherein the one or more processors are included in a graphics processing unit (GPU) or a parallel processing unit (PPU).

14. A non-transitory machine-readable medium having an instruction set stored thereon, said instruction set, if executed by one or more processors, causes said one or more processors to at least: One of a plurality of 5G signal decoding operations is selected based at least in part on the sparsity of error correction information associated with a fifth-generation (5G) signal, wherein the 5G signal decoding operation is a low-density parity-check (LDPC) decoding operation, and wherein the instruction set, if executed by the one or more processors, further causes the one or more processors to execute the selected 5G signal decoding operation, wherein if the sparsity of the error correction information is less than or equal to a predefined threshold, the selected 5G signal decoding operation is a first type of low-density parity-check (LDPC) decoding operation, and if the sparsity of the error correction information is greater than the predefined threshold, the selected 5G signal decoding operation is a second type of LDPC decoding operation.

15. The non-transitory machine-readable medium of claim 14, wherein the selected 5G signal decoding operation is a quasi-cyclic low-density parity-check (QC-LDPC) decoding operation.

16. The non-transitory machine-readable medium of claim 14, wherein the instruction set, if executed by the one or more processors, further enables the one or more processors to perform selected 5G signal decoding operations based at least in part on an input dataset using a cyclic matrix and a log-likelihood ratio (LLR).

17. The non-transitory machine-readable medium of claim 14, wherein if the instruction set is executed by the one or more processors, the one or more processors further cause the one or more processors to execute multiple threads in parallel, wherein each row of the cyclic matrix is ​​processed by a thread among the multiple threads.

18. The non-transitory machine-readable medium of claim 14, wherein the instruction set, if executed by the one or more processors, causes the one or more processors to perform either a block-plus decoding operation or a compression-checked-value decoding operation based at least in part on a selected 5G signal decoding operation.

19. The non-transitory machine-readable medium of claim 14, wherein the instruction set, if executed by the one or more processors, causes the one or more processors to perform a first type of operation in response to a row degree of a quasi-cyclic low-density parity-check (QC-LDPC) basemap being less than or equal to a predefined threshold, and to perform a second type of operation in response to a row degree being greater than the predefined threshold, wherein the row degree indicates the number of non-empty elements in a row and is related to the sparsity of the error correction information.

20. The non-transitory machine-readable medium of claim 14, wherein the instruction set, if executed by the one or more processors, further causes the one or more processors to select the 5G signal decoding operation based at least in part on parameters of a specified quasi-cyclic low-density parity-check (QC-LDPC) basemap.

21. A method comprising: One of a plurality of 5G signal decoding operations is selected based at least in part on the sparsity of error correction information associated with the fifth-generation (5G) signal, wherein a first type of low-density parity-check (LDPC) data decoding operation is selected in response to the sparsity of the error correction information being less than or equal to a predefined threshold, and a second type of LDPC data decoding operation is selected in response to the sparsity of the error correction information being greater than the predefined threshold.

22. The method of claim 21, wherein the selected 5G signal decoding operation is a quasi-cyclic low-density parity-check (QC-LDPC) decoding operation, and the method further comprises performing QC-LDPC decoding using a data decoding operation that is at least partially based on row degree selection of the QC-LDPC basemap, wherein the row degree indicates the number of non-empty elements in a row.

23. The method of claim 21, wherein the selected 5G signal decoding operation is a low-density parity-check (LDPC) data decoding operation in the uplink signal processing pipeline.

24. The method of claim 21, wherein selecting one of the 5G signal decoding operations includes selecting a box plus decoding operation in response to the sparsity of the error correction information being less than or equal to a predefined threshold, wherein the error correction information is represented by rows in a quasi-cyclic low-density parity-check (QC-LDPC) base graph.

25. The method of claim 21, wherein selecting the 5G signal decoding operation includes selecting a compressed check-to-value decoding operation in response to the sparsity of the error correction information being greater than a predefined threshold, wherein the error correction information is represented by rows in a quasi-cyclic low-density parity-check (QC-LDPC) graph, and the method further includes performing the selected 5G signal decoding operation.

26. The method of claim 21, wherein the method further comprises executing multiple threads in parallel to perform selected 5G signal decoding operations, wherein each row in the cyclic matrix corresponding to the non-empty elements of the quasi-cyclic low-density parity-check (QC-LDPC) basemap is processed by a thread of the plurality of threads.

27. The method of claim 21, wherein the method further comprises: In response to a QC-LDPC base map having a row degree greater than or equal to a predefined row degree threshold, select one or more boxes and add a decoding operation, wherein the row degree is related to the sparsity of the error correction information; And perform one or more selected data decoding operations in the uplink signal processing pipeline.

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