Display substrate and display panel

Abstract

A display substrate and a display panel, the display substrate comprising: a substrate substrate; a plurality of sub-pixels arranged on the substrate substrate; each sub-pixel comprising a light emitting element (20) and a pixel circuit (10); the pixel circuit (10) comprising a driving circuit (11), a data writing circuit (12), a first control circuit (14), a second control circuit (15) and a light emitting control circuit (16); the driving circuit (11) is configured to control the driving current flowing through the light emitting element; the light emitting control circuit (16) is configured to apply the driving current to the light emitting element (20); the first control circuit (14) is configured to write a reference voltage to the control end of the driving circuit (11); the second control circuit (15) is configured to write an initial voltage to the first pole of the light emitting element (20); the orthographic projection of at least part of the pixel circuits (10) of every two adjacent sub-pixels in the same row of sub-pixels on the substrate substrate is mirror symmetric. In the display substrate, the structure is simple while ensuring compensation accuracy.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display substrate and a display panel. Background Technology

[0002] With the rapid development of Organic Light-Emitting Diodes (OLEDs) in the display field, people have increasingly higher requirements for display quality. Due to their advantages such as high display quality, high-resolution display devices are finding wider and wider applications. In the display field, pixel circuit design is a crucial technology. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a display substrate, comprising: a substrate; a plurality of sub-pixels disposed on the substrate; the plurality of sub-pixels arranged in multiple rows and columns, each sub-pixel including a light-emitting element and a pixel circuit for driving the light-emitting element to emit light, the light-emitting element being configured to emit light according to a received driving current; the pixel circuit including a driving circuit, a data writing circuit, a storage circuit, a first control circuit, a second control circuit, and a light-emitting control circuit; the driving circuit including a control terminal, a first terminal, and a second terminal, and configured to control the driving current flowing through the light-emitting element, the first terminal of the driving circuit receiving a first voltage from a first voltage line, and the second terminal of the driving circuit being connected to the light-emitting control circuit; the data writing circuit being connected to the control terminal of the driving circuit, and configured to write a data signal to the control terminal of the driving circuit in response to a first scan signal; the light-emitting control circuit... The first terminal of the control circuit is connected to the second terminal of the driving circuit, and the second terminal of the light-emitting control circuit is connected to the first electrode of the light-emitting element. The light-emitting control circuit is configured to apply a driving current to the light-emitting element in response to a light-emitting control signal. The first terminal of the storage circuit is connected to the control terminal of the driving circuit, and the second terminal of the storage circuit is connected to the second terminal of the light-emitting control circuit. The storage circuit is configured to store the data signal written by the data writing circuit. The first control circuit is connected to the control terminal of the driving circuit and is configured to write a reference voltage to the control terminal of the driving circuit in response to a second scan signal. The second control circuit is connected to the first electrode of the light-emitting element and is configured to write an initial voltage to the first electrode of the light-emitting element in response to a third scan signal. At least a portion of the pixel circuits of every two adjacent sub-pixels in the same row are mirror-symmetrical in their orthographic projection on the substrate.

[0004] For example, in some embodiments of this disclosure, multiple sub-pixels are divided into multiple pixel units. Each pixel unit includes three adjacent sub-pixels located in the same row. Each pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along a first direction. The data writing circuit in the pixel circuit of the first sub-pixel is connected to a first data line to receive a corresponding data signal. The data writing circuit in the pixel circuit of the second sub-pixel is connected to a second data line to receive a corresponding data signal. The data writing circuit in the pixel circuit of the third sub-pixel is connected to a third data line to receive a corresponding data signal. The first data line, the second data line, and the third data line are parallel to each other and extend along a second direction, which is perpendicular to the first direction. The orthographic projections of the pixel circuits of the first and second sub-pixels on the substrate are mirror-symmetrical about the center line between the first and second data lines. The orthographic projections of the pixel circuits of the second and third sub-pixels on the substrate are mirror-symmetrical about the center line between the second and third data lines.

[0005] For example, in some embodiments of this disclosure, the first data line is located on the side of the first sub-pixel away from the second sub-pixel, and the second data line and the third data line are located between the second sub-pixel and the third sub-pixel; or the first data line and the second data line are located between the first sub-pixel and the second sub-pixel, and the third data line is located on the side of the third sub-pixel away from the second sub-pixel.

[0006] For example, in some embodiments of this disclosure, for two adjacent pixel units in the same row, the distribution positions of the multi-line pattern composed of the first data line, the second data line, and the third data line in the two pixel units are mirror symmetrical.

[0007] For example, in some embodiments of this disclosure, the first voltage line includes a first voltage main line and a first voltage crossover line. The first voltage main line extends along a second direction and is parallel to the first data line, the second data line, and the third data line. The first voltage crossover line extends along a first direction and is connected to the first voltage main line through a first via. The first voltage crossover line is configured to provide a first voltage to two rows of sub-pixels located on both sides of the first voltage crossover line and adjacent to the first voltage crossover line.

[0008] For example, in some embodiments of this disclosure, the second control circuit includes a first terminal and a second terminal. The first terminal of the second control circuit is connected to the first electrode of the light-emitting element, and the second terminal of the second control circuit is connected to an initial signal line to receive an initial voltage. The initial signal line is parallel to the first voltage cross line and is located between the orthographic projection of the first voltage cross line on the substrate and the orthographic projection of the second control circuit on the substrate.

[0009] For example, in some embodiments of this disclosure, the second control circuit includes a first transistor, the first transistor including a gate, the gate of the first transistor being connected to a third scan line to receive a third scan signal, the third scan line being parallel to a first voltage crossing line and located on the side of the initial signal line away from the first voltage crossing line, the first transistor including an active layer, at least a portion of the active layer of the first transistor having an orthographic projection on the substrate located between the orthographic projection of the third scan line and the initial signal line on the substrate.

[0010] For example, in some embodiments of this disclosure, the first voltage line further includes a plurality of first voltage transition portions, each of the plurality of first voltage transition portions being configured to provide a first voltage to two sub-pixels located in the same column, on both sides of the first voltage cross line and adjacent to the first voltage cross line, each first voltage transition portion extending along a second direction and connected to the first voltage cross line through a second via, the first voltage transition portion including a first end and a second end, the first end and the second end of the first voltage transition portion being located on both sides of the first voltage cross line respectively, the first end of the first voltage transition portion being connected to the sub-pixel located on one side of the first voltage cross line, and the second end of the first voltage transition portion being connected to the sub-pixel located on the other side of the first voltage cross line.

[0011] For example, in some embodiments of this disclosure, the orthographic projection of the first voltage switching section on the substrate overlaps with the orthographic projection of the initial signal line on the substrate and the orthographic projection of the third scan line on the substrate.

[0012] For example, in some embodiments of this disclosure, the light emission control circuit includes a control terminal, which is connected to a control signal line to receive a light emission control signal. The control signal line is parallel to the first voltage crossing line and is located on the side of the third scan line away from the first voltage crossing line.

[0013] For example, in some embodiments of this disclosure, the control signal line and the third scan line are located on opposite sides of the orthographic projection of the driving circuit onto the substrate. The storage circuit includes a first capacitor plate and a second capacitor plate, the orthographic projection of the first capacitor plate onto the substrate is located between the orthographic projection of the third scan line onto the substrate and the orthographic projection of the control signal line onto the substrate, and the orthographic projections of the first capacitor plate and the second capacitor plate onto the substrate at least partially overlap. The driving circuit includes a second transistor, the second transistor including a gate, and the first capacitor plate serving as the gate of the second transistor.

[0014] For example, in some embodiments of this disclosure, the data writing circuit includes a control terminal connected to a first scan line to receive a first scan signal. The first scan line is parallel to a first voltage crossover line, and the first scan line is located on the side of the control signal line away from the first voltage crossover line.

[0015] For example, in some embodiments of this disclosure, the data writing circuit includes a third transistor, the third transistor including an active layer, and the orthographic projection of the active layer of the third transistor on the substrate is located between the orthographic projection of the first scan line on the substrate and the orthographic projection of the control signal line on the substrate.

[0016] For example, in some embodiments of this disclosure, the first control circuit includes a control terminal connected to a second scan line to receive a second scan signal, the second scan line being parallel to a first voltage crossing line and located on the side of the first scan line away from the first voltage crossing line.

[0017] For example, in some embodiments of this disclosure, the first control circuit includes a fourth transistor, the fourth transistor including an active layer, and the orthographic projection of the active layer of the fourth transistor on the substrate is located between the orthographic projection of the first scan signal line on the substrate and the orthographic projection of the second scan signal line on the substrate.

[0018] For example, in some embodiments of this disclosure, the first control circuit further includes a first terminal and a second terminal. The first terminal of the first control circuit is connected to a reference voltage line to receive a reference voltage, and the second terminal of the first control circuit is connected to a control terminal of a drive circuit. The reference voltage line includes a reference voltage main line and a reference voltage cross line. The reference voltage main line extends along a second direction and is parallel to the first voltage main line. The reference voltage cross line extends along a first direction and is connected to the reference voltage main line through a third via. The reference voltage cross line is connected to the first control circuit of a plurality of sub-pixels located in the same row and is configured to provide a reference voltage to the first control circuit of the plurality of sub-pixels located in the same row.

[0019] For example, in some embodiments of this disclosure, multiple sub-pixels located in the same row have a center line extending along a second direction, and the reference voltage main line overlaps with the center line.

[0020] For example, in some embodiments of this disclosure, the reference voltage across lines is configured to provide a reference voltage to the first control circuitry of each of the six sub-pixels located in the same row.

[0021] For example, in some embodiments of this disclosure, the reference voltage crossover is located on the side of the second scan line away from the first voltage crossover.

[0022] For example, in some embodiments of this disclosure, the second end of the first control circuit and the first capacitor plate are connected to the second end of the data writing circuit through a first bridging portion. The first bridging portion extends along a second direction and is connected to the second end of the data writing circuit through a fourth via. The orthographic projection of the first bridging portion on the substrate overlaps with the orthographic projection of the first scan line on the substrate and the orthographic projection of the control signal line on the substrate. The first bridging portion includes a first end and a second end. The first end of the first bridging portion is located on the side of the first scan line away from the control signal line and is connected to the second end of the first control circuit. The second end of the first bridging portion is located on the side of the control signal line away from the first scan line and is connected to the first capacitor plate.

[0023] For example, in some embodiments of this disclosure, the extension line of the first bridging portion along the second direction overlaps with the extension line of the first voltage switching portion along the second direction.

[0024] For example, in some embodiments of this disclosure, the orthographic projection of the pixel circuits of two adjacent sub-pixels in the same column onto the substrate is mirror-symmetrical about a first symmetry line. The distribution of the reference voltage cross line, initial signal line, second scan line, first scan line, control signal line, and third scan line in two adjacent sub-pixels in the same column is mirror-symmetrical about the first symmetry line. When the first voltage cross line is located between two adjacent sub-pixels in the same column, the first symmetry line overlaps with the first voltage cross line. Alternatively, when the first voltage cross line is not located between two adjacent sub-pixels in the same column, the first symmetry line is the center line of the first voltage cross line that is connected to the two adjacent sub-pixels in the same column respectively.

[0025] For example, in some embodiments of this disclosure, multiple sub-pixels are divided into multiple pixel units, each pixel unit includes three adjacent sub-pixels located in the same row, and multiple spaced first voltage main lines are provided on the display substrate, with a pixel unit provided between every two adjacent first voltage main lines.

[0026] For example, in some embodiments of this disclosure, the second end of the light-emitting control circuit is connected to the first adapter line in sequence via the fifth via and the sixth via, and the first adapter line is connected to the first end of the second control circuit in sequence via the seventh via and the eighth via. The orthographic projections of the fifth via and the sixth via on the substrate are adjacent to each other, and the fifth via and the sixth via are distributed along the first direction. The orthographic projections of the seventh via and the eighth via on the substrate are adjacent to each other, and the seventh via and the eighth via are distributed along the second direction.

[0027] For example, in some embodiments of this disclosure, the light-emitting control circuit includes a fifth transistor, and the first transistor, second transistor, third transistor, fourth transistor and fifth transistor each include an active layer. The orthogonal projection of the active layers of the first transistor, second transistor, third transistor, fourth transistor and fifth transistor onto the substrate forms a transistor pattern; the transistor patterns of every two adjacent sub-pixels in the same row are mirror symmetrical.

[0028] For example, in some embodiments of this disclosure, the first electrode of the light-emitting element covers the corresponding sub-pixel.

[0029] For example, in some embodiments of this disclosure, the first electrode of the light-emitting element is connected to the first end of the second control circuit through an anode connection portion. The anode connection portion extends along a second direction and includes a first end and a second end. The first end of the anode connection portion is located on the side of the third scan line close to the first capacitor plate, and the second end of the anode connection portion is located on the side of the third scan line away from the first capacitor plate. The first end of the anode connection portion is connected to the first end of the second control circuit through a ninth via. The orthographic projection of the anode connection portion on the substrate overlaps with the orthographic projection of the third scan line on the substrate.

[0030] Another aspect of this disclosure provides a display panel that includes any of the display substrates provided in this disclosure. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0032] Figure 1A A schematic block diagram of a display substrate provided for some embodiments of this disclosure;

[0033] Figure 1B A schematic block diagram of a pixel circuit provided for some embodiments of this disclosure;

[0034] Figure 2A for Figure 1B A schematic diagram of a specific example of a pixel circuit is shown;

[0035] Figure 2B Figure 2A The diagram shows the timing sequence of the pixel circuit.

[0036] Figures 2C-2E This diagram illustrates the effect of the pixel circuit providing current compensation according to an embodiment of the present disclosure.

[0037] Figure 3A schematic diagram of a display substrate 300 provided in at least one embodiment of the present disclosure is shown;

[0038] Figure 4 This is a schematic diagram of the layout of a pixel circuit provided for some embodiments of this disclosure;

[0039] Figure 5A-5Q A schematic diagram of the various layer structures of a pixel circuit provided in some embodiments of this disclosure; and

[0040] Figure 6 This is a schematic diagram of a display panel provided for at least one embodiment of the present disclosure. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0042] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0043] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and known components have been omitted.

[0044] In the display field, there are various types of pixel circuits used to drive OLEDs, such as a 2T1C circuit consisting of two thin-film transistors (TFTs) and one capacitor (C), or 4T1C and 4T2C circuits with threshold voltage compensation functions. To achieve better compensation, the number of transistors in the pixel circuit can be increased. However, as the complexity of the pixel circuit and the number of transistors increase, the layout design becomes more difficult, and interference between signals can occur. This disclosure provides at least some embodiments of a display substrate and a display panel. The display substrate includes: a substrate; a plurality of sub-pixels disposed on the substrate; the plurality of sub-pixels are arranged in multiple rows and columns, each sub-pixel including a light-emitting element and a pixel circuit for driving the light-emitting element to emit light, the light-emitting element being configured to emit light according to a received driving current; the pixel circuit includes a driving circuit, a data writing circuit, a storage circuit, a first control circuit, a second control circuit, and a light-emitting control circuit; the driving circuit includes a control terminal, a first terminal, and a second terminal, and is configured to control the driving current flowing through the light-emitting element, the first terminal of the driving circuit receiving a first voltage from a first voltage line, and the second terminal of the driving circuit being connected to the light-emitting control circuit; the data writing circuit is connected to the control terminal of the driving circuit and is configured to write a data signal to the control terminal of the driving circuit in response to a first scan signal; the light-emitting control circuit... The first terminal of the circuit is connected to the second terminal of the driving circuit, and the second terminal of the light-emitting control circuit is connected to the first electrode of the light-emitting element. The light-emitting control circuit is configured to apply the driving current to the light-emitting element in response to a light-emitting control signal. The first terminal of the storage circuit is connected to the control terminal of the driving circuit, and the second terminal of the storage circuit is connected to the second terminal of the light-emitting control circuit. The storage circuit is configured to store the data signal written by the data writing circuit. The first control circuit is connected to the control terminal of the driving circuit and is configured to write a reference voltage to the control terminal of the driving circuit in response to a second scan signal. The second control circuit is connected to the first electrode of the light-emitting element and is configured to write an initial voltage to the first electrode of the light-emitting element in response to a third scan signal. At least a portion of the pixel circuits of every two adjacent sub-pixels in the same row are mirror-symmetrical in their orthographic projection on the substrate.

[0045] In the display substrate provided in this embodiment, by connecting the light-emitting control circuit and the driving circuit, the multiplexing design of the data driver can be compatible. Furthermore, the light-emitting control circuit is connected between the driving circuit and the light-emitting element. While ensuring control effect, current compensation capability and compensation accuracy, the display substrate has a simple structure, is easy to design and manufacture, and has a low cost.

[0046] The following describes several embodiments of the present disclosure in detail with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0047] Figure 1A This is a schematic block diagram of a display substrate provided in some embodiments of the present disclosure. Figure 1B This is a schematic block diagram of a pixel circuit provided for some embodiments of this disclosure.

[0048] For example, such as Figure 1A As shown, the display substrate 100 provided in the embodiments of this disclosure includes a substrate 101 and a plurality of sub-pixels 102 disposed on the substrate 101.

[0049] For example, the display substrate 100 can be applied to a display panel, such as an active matrix organic light-emitting diode (AMOLED) display panel. The display substrate 100 can be an array substrate.

[0050] For example, the substrate 101 can be a flexible substrate or a rigid substrate. For example, the substrate 101 can be made of glass, plastic, quartz or other suitable materials, and the embodiments of this disclosure are not limited thereto.

[0051] like Figure 1A As shown, for example, multiple sub-pixels 102 are arranged in multiple rows and columns to form a pixel array. For example, each sub-pixel 102 includes a pixel circuit 10 and a light-emitting element 20, the light-emitting element 20 being located on the side of the pixel circuit 10 away from the substrate 101. The light-emitting element 20 is configured to emit light according to a received drive current.

[0052] For example, pixel circuit 10 is configured to drive light-emitting element 20 to emit light. The following is in conjunction with... Figure 1B and Figure 2A The pixel circuit and its working principle are explained.

[0053] For example, such as Figure 1B As shown, each pixel circuit 10 includes a driving circuit 11, a data writing circuit 12, a storage circuit 13, a first control circuit 14, a second control circuit 15, and a light emission control circuit 16.

[0054] The driving circuit 11 includes a control terminal 113, a first terminal 111, and a second terminal 112, and is configured to control the driving current flowing through the light-emitting element. The first terminal 111 of the driving circuit 11 receives a first voltage from the first voltage line VDD, and the second terminal 112 of the driving circuit 11 is connected to the light-emitting control circuit 16. For example, in some examples, the first terminal 111 of the driving circuit 11 can be directly connected to the first voltage line VDD. For example, in other examples, the first terminal 111 of the driving circuit 11 can also be connected to the first voltage line VDD via other components.

[0055] The data writing circuit 12 is connected to the control terminal 113 of the drive circuit 11 and is configured to write a data signal to the control terminal 113 of the drive circuit 11 in response to a first scan signal. For example, the data writing circuit 12 is connected to the data line Vd to receive a data signal, which may be a voltage signal. The data writing circuit 12 is also connected to the first scan line G1 to receive the first scan signal.

[0056] The first terminal 161 of the light-emitting control circuit 16 is connected to the second terminal 112 of the driving circuit 11, and the second terminal 162 of the light-emitting control circuit 16 is connected to the first electrode 21 of the light-emitting element 20. The light-emitting control circuit 16 is configured to apply a driving current to the light-emitting element 20 in response to a light-emitting control signal. For example, the light-emitting control circuit 16 is connected to the control signal line EM to receive the light-emitting control signal.

[0057] The first terminal 131 of the storage circuit 13 is connected to the control terminal 113 of the driving circuit 11, and the second terminal 132 of the storage circuit 13 is connected to the second terminal 162 of the light-emitting control circuit 16. The storage circuit 13 is configured to store the data signal written by the data writing circuit 12.

[0058] The first control circuit 14 is connected to the control terminal 113 of the drive circuit 11 and is configured to write a reference voltage to the control terminal 113 of the drive circuit 11 in response to a second scan signal. For example, the first control circuit 14 is connected to the reference voltage line Vref to receive the reference voltage. The first control circuit 14 is also connected to the second scan line G2 to receive the second scan signal.

[0059] The second control circuit 15 is connected to the first electrode 21 of the light-emitting element 20 and is configured to write an initial voltage to the first electrode 21 of the light-emitting element 20 in response to a third scan signal. For example, the second control circuit 15 is connected to the initial voltage line Vini to receive the initial voltage, and the second control circuit 15 is connected to the third scan line G3 to receive the third scan signal.

[0060] like Figure 1B As shown, the second electrode of the light-emitting element 20 can be connected to the second voltage line VSS to receive the second voltage from the second voltage line VSS.

[0061] Figure 2A for Figure 1B A schematic diagram of a specific example of a pixel circuit is shown. For example... Figure 2AAs shown, the driving circuit 11 may include a second transistor T2, the data writing circuit 12 may include a third transistor T3, the first control circuit 14 may include a fourth transistor T4, the second control circuit 15 may include a first transistor T1, and the light-emitting control circuit 16 may include a fifth transistor T5. The storage circuit 13 may include a storage capacitor Cst, which includes two stacked capacitor plates. The structure of the capacitor plates will be described later and will not be detailed here.

[0062] like Figure 2A As shown, for example, the first transistor T1 to the fifth transistor T5 can be N-type transistors. For example, the gate of the second transistor T2 serves as the control terminal 113 of the drive circuit 11, the first terminal of the second transistor T2 serves as the first terminal 111 of the drive circuit 11, and the second terminal of the second transistor T2 serves as the second terminal 112 of the drive circuit 11. The first terminal of the second transistor T2 is connected to the first voltage line VDD.

[0063] The gate of the third transistor T3 is connected to the first scan line G1 to receive the first scan signal. The first terminal of the third transistor T3 is connected to the data line Vd to receive the data signal. The second terminal of the third transistor T3 is connected to the gate of the second transistor T2.

[0064] The gate of the fourth transistor T4 is connected to the second scan line G2 to receive the second scan signal. The second terminal of the fourth transistor T4 is connected to the gate of the second transistor T2. The first terminal of the fourth transistor T4 is connected to the reference voltage line Vref.

[0065] One of the two capacitor plates of the storage capacitor Cst serves as the first terminal of the storage circuit 13, and the other capacitor plate of the storage capacitor Cst serves as the second terminal of the storage circuit 13. That is, the first terminal of the storage capacitor Cst is connected to the gate of the second transistor T2 as the first terminal of the storage circuit 13, and the second terminal of the storage capacitor Cst is connected to the first terminal of the light-emitting element 20 as the second terminal of the storage circuit 13.

[0066] For example, the gate of the second transistor T2, the second terminal of the fourth transistor T4, the second terminal of the third transistor T3, and the first terminal of the storage capacitor Cst can be connected to the first node G.

[0067] The gate of the fifth transistor T5 can be used as the control terminal of the light-emitting control circuit 16. The first terminal of the fifth transistor T5 can be used as the first terminal of the light-emitting control circuit 16 and connected to the second terminal of the second transistor T2. The second terminal of the fifth transistor T5 can be used as the second terminal of the light-emitting control circuit 16 and connected to the first terminal of the light-emitting element 20.

[0068] The gate of the first transistor T1 is connected to the third scan line G3 to receive the third scan signal. The first terminal of the first transistor T1 is connected to the first terminal of the second control circuit 15 and the first terminal of the light-emitting element 20. The second terminal of the first transistor T1 is connected to the initial signal line Vini as the second terminal of the second control circuit 15 to receive the initial voltage.

[0069] For example, the second terminal of the fifth transistor T5, the first terminal of the first transistor T1, the second terminal of the storage capacitor Cst, and the first terminal of the light-emitting element 20 are connected to the second node S.

[0070] For example, such as Figure 2A As shown, the second electrode of the light-emitting element 20 is electrically connected to the second voltage line VSS to receive the second voltage.

[0071] For example, the light-emitting element 20 can be a light-emitting diode (LED). The LED can be a micro LED, an organic light-emitting diode (OLED), or a quantum dot LED (QLED). The light-emitting element 20 is configured to receive a light-emitting signal (e.g., a drive current) and emit light of an intensity corresponding to that signal during operation. The light-emitting element 20 may include a first electrode, a second electrode, and a light-emitting layer disposed between the first and second electrodes. The first electrode of the light-emitting element 20 can be an anode, and the second electrode can be a cathode. It should be noted that, in embodiments of this disclosure, the light-emitting layer of the light-emitting element may include an electroluminescent layer itself and other common layers located on both sides of the electroluminescent layer, such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer. Generally, the light-emitting element 20 has a light-emitting threshold voltage, and emits light when the voltage between the first and second electrodes of the light-emitting element 20 is greater than or equal to the light-emitting threshold voltage. In practical applications, the specific structure of the light-emitting element 20 can be designed and determined according to the actual application environment, and no limitation is made here.

[0072] For example, the first transistor T1 to the fifth transistor T5 are N-type thin film transistors (TFTs).

[0073] For example, the voltage output from the first voltage line VDD and the voltage output from the second voltage line VSS may be either high or low. Figure 2A In the illustrated embodiment, the voltage output by the first voltage line VDD is a constant first voltage, which is a positive voltage; while the voltage output by the second voltage line VSS is a constant second voltage, which is a negative voltage, and so on. For example, in some examples, the second voltage line VSS may be grounded.

[0074] It should be noted that the transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. Thin-film transistors can include oxide semiconductor thin-film transistors, amorphous silicon thin-film transistors, or polycrystalline silicon thin-film transistors, etc. The source and drain of the transistor can be symmetrical in structure, so their source and drain can be indistinguishable in physical structure. In the embodiments of this disclosure, in order to distinguish the transistors, except for the gate, which serves as the control electrode, one electrode is directly described as the first electrode and the other electrode as the second electrode. Therefore, in the embodiments of this disclosure, the first and second electrodes of all or some transistors can be interchanged as needed.

[0075] The following is combined with Figure 2B describe Figure 2A The working process of the pixel circuit shown.

[0076] For example, such as Figure 2B As shown, G1 represents the first scan signal provided by the first scan line, G2 represents the second scan signal provided by the second scan line, G3 represents the third scan signal output by the third scan line, and EM represents the light emission control signal output by the control signal line. It should be noted that in the embodiments of this disclosure, the reference numerals G1, G2, G3, EM, Vref, VDD, Vini, and VSS represent both the corresponding signal lines or signal terminals, and the signals transmitted on the signal lines or signal terminals.

[0077] For example, the operation of a pixel circuit in a display frame may include: a reset phase p0, a compensation phase p1, a data writing phase p2, and a light emission phase p3.

[0078] During the reset phase p0, the first scan signal G1 is low, while the second scan signal G2, the third scan signal G3, and the light emission control signal EM are high. Consequently, the third transistor T3 is turned off under the control of the low level of the first scan signal G1, the first transistor T1 is turned on under the control of the high level of the third scan signal G3, the fourth transistor T4 is also turned on under the control of the high level of the second scan signal G2, and the fifth transistor T5 is turned on under the control of the high level of the light emission control signal EM. Since the third transistor T3 is off, the first transistor T1 is on, and the fourth transistor T4 is also on, applying a reference voltage Vref to the fourth transistor T4 and an initial voltage Vini to the first transistor T1 during this phase can reset the pixel circuit. That is, the first node G is written with the reference voltage Vref, and the second node S is written with the initial voltage Vini. This ensures that the pixel circuit is not affected by the previous frame when performing compensation in the next phase.

[0079] In some embodiments of this disclosure, Vref > Vini + Vth, where Vth is the threshold voltage of the second transistor T2.

[0080] For example, in some embodiments, the first transistor T1 can be a dual-gate transistor, which allows the current of the first transistor T1 to be larger, thereby enabling the second node S to quickly reach the initial voltage Vini and improve the reset efficiency.

[0081] During the compensation phase p1, the first scan signal G1 is low, the second scan signal G2 is high, the third scan signal G3 is low, and the light emission control signal EM is high. Consequently, the third transistor T3 is turned off under the control of the low level of the first scan signal G1, the first transistor T1 is turned off under the control of the low level of the third scan signal G3, the fourth transistor T4 is turned on under the control of the high level of the second scan signal G2, and the fifth transistor T5 is turned on under the control of the high level of the light emission control signal EM. Since the third transistor T3 and the first transistor T1 are turned off, and the fourth transistor T4 and the fifth transistor T5 are turned on, the voltage of the first node G is maintained at Vref during this phase. The second node S begins charging until Vs = Vref - Vth, at which point it is turned off, where Vs is the voltage of the second node S.

[0082] During the data writing phase p2, the first scan signal G1 is high, the second scan signal G2 is low, the third scan signal G3 is low, and the light emission control signal EM is low. Consequently, the third transistor T3 is turned on under the control of the high level of the first scan signal G1, the first transistor T1 is turned off under the control of the low level of the third scan signal G3, the fourth transistor T4 is turned off under the control of the low level of the second scan signal G2, and the fifth transistor T5 is turned off under the control of the low level of the light emission control signal EM. Since the third transistor T3 is on, the first transistor T1, the fourth transistor T4, and the fifth transistor T5 are off. Therefore, during this phase, the first node G is written with data signals from the data signal line Vd, and the second node S is coupled with a voltage to Vs. The voltage VG of the first node G and the voltage Vs of the second node S satisfy the following relationship:

[0083] VG=Vdata

[0084] Vs = a(Vdata - Vref) + Vref - Vth

[0085] a = Cst / (Cst + Coled)

[0086] VGS=VG-Vs=(1-a)(Vdata-Vref)+Vth

[0087] Cst represents the capacitance of capacitor Cst, Coled represents the capacitance generated by the light-emitting element 20 itself, and VGS represents the voltage difference between the first node G and the second node S.

[0088] During the light-emitting stage p3, the first scan signal G1 is low, the second scan signal G2 is low, the third scan signal G3 is low, and the light-emitting control signal EM is high. Therefore, the third transistor T3 is cut off under the control of the low level of the first scan signal G1, the first transistor T1 is cut off under the control of the low level of the third scan signal G3, the fourth transistor T4 is cut off under the control of the low level of the second scan signal G2, and the fifth transistor T5 is turned on under the control of the high level of the light-emitting control signal EM. Since the third transistor T3, the first transistor T1, and the fourth transistor T4 are cut off, and the fifth transistor T5 is turned on, the voltage difference VGS between the first node G and the second node S is maintained at VGS = VG - Vs = (1 - a)(Vdata - Vref) + Vth during this stage.

[0089] The formula for calculating the luminous current is as follows:

[0090] Ids=1 / 2*u*Cox*(W / L)*(vgs-Vth)^2

[0091] Ids=1 / 2*u*Cox*(W / L)[(1-a)^2(Vdata-Vref)^2]

[0092] As can be seen from the above formula for calculating the luminous current, the luminous current flowing through the luminous element 20 is no longer related to the threshold voltage Vth of the second transistor T2, thus achieving compensation.

[0093] Figures 2C-2E A schematic diagram illustrating the effect of current compensation achieved by the pixel circuit provided in the embodiments of this disclosure is shown.

[0094] exist Figure 2C In the table shown, T represents the duration of the compensation phase p1. For example, in a pixel circuit with a compensation time of 110 μs and a threshold voltage of 0.5 V for the driving circuit, the current I_oled flowing through the light-emitting element is 96.43 nA and 83.94 nA, respectively. Using the pixel circuit provided in this disclosure, with a compensation time of 130 μs and a threshold voltage of 0.5 V for the driving circuit, the current I_oled flowing through two different light-emitting elements is 96.43 nA and 70.58 nA.

[0095] The above tests were repeated with threshold voltages of 1V, 1.5V, 2V, and 2.5V for the driving circuit, and the uniformity of the light-emitting element was calculated at 0.5V, 1V, 1.5V, 2V, and 2.5V. For example, a pixel circuit with a compensation time of 110μs exhibited a uniformity of 86.64% for the light-emitting element's current I_oled. For example, the pixel circuit of this disclosure exhibited a uniformity of 80% for the light-emitting element's current I_oled with a compensation time of 130μs. For example, the pixel circuit of this disclosure exhibited a uniformity of 81.7% for the light-emitting element's current I_oled with a compensation time of 150μs.

[0096] Therefore, through Figure 2C The table comparing conventional pixel circuits and the pixel circuit solution provided in this disclosure shows that, by appropriately extending the time length of the compensation stage p1, the compensation capability of the pixel circuit provided in this disclosure at least meets or even exceeds that of conventional solutions. Furthermore, the pixel circuit provided in this disclosure reduces the structural complexity of the display substrate, making it easier to design and manufacture, and resulting in lower costs.

[0097] Figure 2D for Figure 2C The table shown is a graph showing the relationship between current uniformity and the threshold voltage of the drive circuit. Figure 2DCurve 210 represents the relationship between the current uniformity of a pixel circuit and the driving circuit when the compensation time is 110μs; curve 220 represents the relationship between the current uniformity of a pixel circuit and the driving circuit when the compensation time is 150μs; curve 230 represents the relationship between the current uniformity of a pixel circuit and the driving circuit when the compensation time is 130μs; and curve 240 represents the relationship between the current uniformity of a pixel circuit and the driving circuit when the compensation time is 110μs.

[0098] exist Figure 2E In this context, Vgs_o represents the current flowing through even-numbered sub-pixels, and Vgs_e represents the current flowing through odd-numbered sub-pixels. Mux_g1 represents multiplexing circuit g1, and Mux_g1 represents multiplexing circuit g2. For example... Figure 2E As shown, under the same gray level, after passing through the multiplexing circuit, the current Vgs_o flowing through the even-numbered sub-pixels is equal to the current Vgs_e flowing through the odd-numbered sub-pixels. In other words, the pixel circuit provided in this disclosure can make the current of two adjacent sub-pixels indistinguishable. Therefore, the pixel circuit provided in this disclosure can be compatible with the multiplexing design of the data driver.

[0099] Figure 3 A schematic diagram of a display substrate 300 provided in at least one embodiment of the present disclosure is shown.

[0100] like Figure 3 As shown, the display substrate 300 may include a pixel array comprising multiple rows and columns formed by multiple sub-pixels. The multiple sub-pixels are divided into multiple pixel units.

[0101] For example, in Figure 3 The diagram schematically illustrates two pixel units 301 and 302 in the first row. Each pixel unit includes three adjacent sub-pixels located in the same row, and each pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along a first direction X. For example, pixel unit 301 includes a first sub-pixel 311, a second sub-pixel 312, and a third sub-pixel 313. As another example, pixel unit 302 includes a first sub-pixel 314, a second sub-pixel 315, and a third sub-pixel 316. In some embodiments of this disclosure, for example, the three adjacent sub-pixels are respectively a sub-pixel for emitting red light, a sub-pixel for emitting green light, and a sub-pixel for emitting blue light.

[0102] The data writing circuit in the pixel circuit of the first sub-pixel is connected to the first data line to receive the corresponding data signal; the data writing circuit in the pixel circuit of the second sub-pixel is connected to the second data line to receive the corresponding data signal; and the data writing circuit in the pixel circuit of the third sub-pixel is connected to the third data line to receive the corresponding data signal. For example, the data writing circuit in the pixel circuit of the first sub-pixel 311 is connected to the first data line 31 to receive the data signal of the first data line 31; the data writing circuit in the pixel circuit of the second sub-pixel 312 is connected to the second data line 32 to receive the data signal of the second data line 32; and the data writing circuit in the pixel circuit of the third sub-pixel 313 is connected to the third data line 33 to receive the data signal of the third data line 33. For example, the data writing circuit in the pixel circuit of the first sub-pixel 314 is connected to the first data line 34 to receive the data signal of the first data line 34; the data writing circuit in the pixel circuit of the second sub-pixel 315 is connected to the second data line 35 to receive the data signal of the second data line 35; and the data writing circuit in the pixel circuit of the third sub-pixel 316 is connected to the third data line 36 to receive the data signal of the third data line 36.

[0103] In some embodiments of this disclosure, for example, the first data line provides a corresponding data signal Data_R for the sub-pixel emitting red light, the second data line provides a corresponding data signal Data_G for the sub-pixel emitting green light, and the third data line provides a corresponding data signal Data_B for the sub-pixel emitting blue light.

[0104] like Figure 3 As shown, for example, the first data line, the second data line, and the third data line are parallel to each other and extend along the second direction Y, which is perpendicular to the first direction X.

[0105] For example, such as Figure 3 As shown, the first direction X is parallel to the row direction of the pixel array, and the second direction Y is parallel to the column direction of the pixel array.

[0106] In some embodiments of this disclosure, at least a portion of the pixel circuitry of every two adjacent sub-pixels in the same row is mirror-symmetrical in its orthographic projection onto the substrate.

[0107] For example, the orthographic projections of the pixel circuits of the first sub-pixel and the second sub-pixel on the substrate are mirror-symmetrical about the center line between the first data line and the second data line, and the orthographic projections of the pixel circuits of the second sub-pixel and the third sub-pixel on the substrate are mirror-symmetrical about the center line between the second data line and the third data line.

[0108] For example, in Figure 3In the display substrate 300 shown, for pixel unit 301, the orthographic projection 311 of the pixel circuit of the first sub-pixel 311 and the orthographic projection 312 of the pixel circuit of the second sub-pixel 312 on the substrate are mirror-symmetrical about the center line 38 between the first data line 31 and the second data line 32. The orthographic projection 312 of the pixel circuit of the second sub-pixel 312 and the orthographic projection 313 of the pixel circuit of the third sub-pixel 313 on the substrate are mirror-symmetrical about the center line 37 between the second data line 32 and the third data line 33. Pixel unit 302 is similar to pixel unit 301 described above, and will not be repeated here.

[0109] It should be noted that in the embodiments of this disclosure, reference numerals 311, 312, 313, 314, 315, and 316 represent sub-pixels, and also represent the orthographic projection of the pixel circuit of the sub-pixel onto the substrate. It should also be noted that the rectangular frames marked 311, 312, 313, 314, 315, and 316 in the figures are only schematic representations of the positions of the corresponding pixel circuits and do not represent the actual shape or actual projected shape of the pixel circuits.

[0110] In some embodiments of this disclosure, the first data line is located on the side of the first sub-pixel away from the second sub-pixel, and the second and third data lines are located between the second and third sub-pixels.

[0111] For example, such as Figure 3 As shown, for pixel unit 301, the first data line 31 is located on the side of the first sub-pixel 311 away from the second sub-pixel 312, and the second data line 32 and the third data line 33 are located between the second sub-pixel 312 and the third sub-pixel 313.

[0112] In some other embodiments of this disclosure, the first data line and the second data line are located between the first sub-pixel and the second sub-pixel, and the third data line is located on the side of the third sub-pixel away from the second sub-pixel.

[0113] For example, such as Figure 3 As shown, for pixel unit 302, the first data line 34 and the second data line 35 are located between the first sub-pixel 314 and the second sub-pixel 315, and the third data line 36 is located on the side of the third sub-pixel 316 away from the second sub-pixel 315.

[0114] In some embodiments of this disclosure, for two adjacent pixel units in the same row, the distribution positions of the multi-line pattern composed of the first data line, the second data line, and the third data line in the two pixel units are mirror-symmetrical.

[0115] For example, such as Figure 3As shown, for adjacent pixel units 301 and 302 in the same row, the multi-line pattern formed by the first data line 31, the second data line 32 and the third data line 33 is mirror-symmetrical about the multi-line pattern formed by the first data line 34, the second data line 35 and the third data line 36 about the center line 39.

[0116] In some embodiments of this disclosure, the first voltage line includes a first voltage main line and a first voltage crossover line. The first voltage main line extends along a second direction Y and is parallel to the first data line, the second data line, and the third data line. The first voltage crossover line extends along a first direction X and is connected to the first voltage main line through a first via. The first voltage crossover line is configured to provide a first voltage to two rows of sub-pixels located on both sides of the first voltage crossover line and adjacent to the first voltage crossover line.

[0117] For example, such as Figure 3 As shown, the first voltage line VDD may include a first voltage main line 304 and a first voltage crossover line 305. The first voltage main line 304 extends along a second direction Y (e.g., the column direction of the pixel array) and is parallel to the first data line, the second data line, and the third data line. The first voltage crossover line 305 extends along a first direction X (e.g., the row direction of the pixel array), and is connected to the first voltage main line 304 through a first via 312. The first voltage crossover line 305 is configured to provide a first voltage to two rows of sub-pixels located on both sides of and adjacent to the first voltage crossover line 305.

[0118] For example, if sub-pixels 311-316 are multiple sub-pixels in the first row of the pixel array, then the first voltage cross line 305 is configured to provide a first voltage to the multiple sub-pixels 311-316 in the first row and the multiple sub-pixels in the second row.

[0119] The first voltage cross line 305 provides a first voltage to two adjacent rows of sub-pixels. That is, two adjacent rows of sub-pixels share a first voltage cross line 305, which simplifies the display substrate and saves the space occupied by the wiring.

[0120] Figure 4 This is a schematic diagram of the layout of a pixel circuit provided in some embodiments of this disclosure. Figure 5A-5Q This is a schematic diagram of the layer structure of a pixel circuit provided in some embodiments of this disclosure. For example, as... Figure 4 As shown, a dashed box represents one Figure 2A The pixel circuit shown.

[0121] For example, such as Figure 4 As shown, the display substrate may include at least pixel circuit 40 and pixel circuit 50, which belong to different sub-pixels. The structure of the pixel circuit in this disclosure will be described below using pixel circuit 40 as an example.

[0122] The display substrate may include an active semiconductor layer, a first conductive layer, a first source / drain metal layer, a second conductive layer, a second source / drain metal layer, and an anode layer. The active semiconductor layer 410, for example... Figure 5A As shown, the first conductive layer 420 is as follows Figure 5B As shown, the first source / drain metal layer 490 Figure 5E As shown, the second conductive layer 440 is as follows Figure 5F As shown, the second source / drain metal layer 450 Figure 5I As shown, the anode layer 480 Figure 5L As shown. In a direction perpendicular to the substrate 101, the active semiconductor layer 410 is located between the substrate 101 and the first conductive layer 420. The first conductive layer 420 is located between the active semiconductor layer 410 and the first source-drain metal layer 490. The first source-drain metal layer 490 is located between the first conductive layer 420 and the second conductive layer 440. The second conductive layer 440 is located between the first source-drain metal layer 490 and the second source-drain metal layer 450. The second source-drain metal layer 450 is located between the second conductive layer 440 and the anode layer 480.

[0123] In some embodiments of this disclosure, the second control circuit includes a first terminal and a second terminal. The first terminal of the second control circuit is connected to the first electrode of the light-emitting element, and the second terminal of the second control circuit is connected to an initial signal line to receive an initial voltage. The initial signal line is parallel to the first voltage cross line and is located between the orthographic projection of the first voltage cross line on the substrate and the orthographic projection of the second control circuit on the substrate.

[0124] It is important to understand that "orthographic projection" in this article refers to projection in a direction perpendicular to the substrate.

[0125] For example, such as Figure 2A As shown, the second control circuit can be a first transistor T1. The first transistor T1 includes a first terminal and a second terminal. The first terminal of the first transistor T1 is connected to the first electrode of the light-emitting element 20, and the second terminal of the first transistor T1 is connected to the initial signal line to receive the initial voltage. Figure 4 As shown, the second terminal of the first transistor T1 is connected to the initial signal line 401. The initial signal line 401 is parallel to the first voltage crossing line 305 and is located between the orthogonal projection of the first voltage crossing line 305 on the substrate and the orthogonal projection of the first transistor T1 on the substrate.

[0126] For example, the first transistor T1 includes a gate. (As...) Figure 2A As shown, the gate of the first transistor T1 is connected to the third scan line G3 to receive the third scan signal. Figure 4 and 5CAs shown, the third scan line G3 is parallel to the first voltage crossing line 305 and is located on the side of the initial signal line 401 away from the first voltage crossing line 305. The first transistor T1 includes an active layer, and the orthographic projection of at least part of the active layer of the first transistor T1 onto the substrate 101 lies between the orthographic projections of the third scan line G3 and the initial signal line 401 onto the substrate.

[0127] For example, such as Figure 5C As shown, the first transistor T1 includes a first channel 4251 and a second channel 4252. The orthographic projection of the first channel 4251 onto the substrate is perpendicular to the first voltage crossing line 305, and the orthographic projection of the second channel 4252 onto the substrate is parallel to the first voltage crossing line 305. That is, the first channel 4251 and the second channel 4252 form an L-shaped channel region. Figure 4 As shown, the orthographic projection of the second channel 4252 on the substrate is located between the orthographic projection of the third scan line G3 and the orthographic projection of the initial signal line 401 on the substrate.

[0128] For example, such as Figure 3 , Figure 4 , Figure 5D and Figure 5E As shown, the first power line VDD also includes a plurality of first voltage transition sections 402. Each first voltage transition section 402 is configured to provide a first voltage to two sub-pixels (e.g., pixel circuit 40 and pixel circuit 50) located in the same column, on both sides of the first voltage cross line 305 and adjacent to the first voltage cross line 305.

[0129] For example, a first voltage adapter 402 extends along the second direction Y and is connected to a first voltage cross-line 305 through a second via 403. The first voltage adapter 402 includes a first end 412 and a second end 413. The first end 412 and the second end 413 of the first voltage adapter 402 are located on opposite sides of the first voltage cross-line 305. The first end 412 of the first voltage adapter 402 is connected to the pixel circuit 40 of the sub-pixel located on one side of the first voltage cross-line 305, and the second end 413 of the first voltage adapter 402 is connected to the pixel circuit 50 of the sub-pixel located on the other side of the first voltage cross-line 305. Providing a first voltage to two adjacent sub-pixels located in the same column through a first voltage adapter 402 can reduce the complexity of the pixel circuit.

[0130] In some embodiments of this disclosure, such as Figure 4 As shown, the orthographic projection of the first voltage converter 402 on the substrate overlaps with the orthographic projection of the initial signal line 401 on the substrate and the orthographic projection of the third scan line G3 on the substrate.

[0131] For example, the first voltage switching unit 402 sequentially crosses the third scan line G3 of the pixel circuit 40, the initial signal line 401 of the pixel circuit 40, the third scan line G3 of the pixel circuit 50, and the initial signal line 401 of the pixel circuit 50.

[0132] In some embodiments of this disclosure, such as Figure 2A As shown, the light-emitting control circuit may include a fifth transistor, and the control terminal of the light-emitting control circuit may be the gate of the fifth transistor T5.

[0133] For example, such as Figure 4 and Figure 2A As shown, the gate of the fifth transistor T5 is connected to the control signal line EM to receive the light emission control signal. The control signal line EM is parallel to the first voltage crossing line 305, and the control signal line EM is located on the side of the third scan line G3 away from the first voltage crossing line 305.

[0134] In some embodiments of this disclosure, the control signal line EM and the third scan line G3 are located on opposite sides of the orthographic projection of the driving circuit onto the substrate.

[0135] For example, such as Figure 2A As shown, the driving circuit includes a second transistor T2. Figure 4 As shown, the control signal line EM and the third scan line G3 are located on opposite sides of the orthogonal projection of the second transistor T2 onto the substrate.

[0136] In some embodiments of this disclosure, such as Figure 4 , Figure 5B and Figure 5G As shown, the storage circuit Cst includes a first capacitor plate Cst-1 and a second capacitor plate Cst-2. The orthographic projection of the first capacitor plate Cst-1 on the substrate lies between the orthographic projection of the third scan line G3 on the substrate and the orthographic projection of the control signal line EM on the substrate. The orthographic projection of the first capacitor plate Cst-1 on the substrate at least partially overlaps with the orthographic projection of the second capacitor plate Cst-2 on the substrate. The driving circuit includes a second transistor T2, which includes a gate. The first capacitor plate Cst-1 serves as the gate of the second transistor T2.

[0137] In this article, "at least partial coverage" can refer to partial coverage or full coverage. As long as there is overlap, it can be considered as at least partial coverage.

[0138] For example, the first capacitor plate Cst-1 and the second capacitor plate Cst-2 are stacked in a direction perpendicular to the substrate, and the orthogonal projection of the first capacitor plate Cst-1 on the substrate at least partially overlaps with the orthogonal projection of the active layer of the second transistor T2 on the substrate.

[0139] In some embodiments of this disclosure, the first capacitor substrate Cst-1 may be disposed on the first conductive layer 420, and the second capacitor plate Cst-2 may be disposed on the second conductive layer 440.

[0140] In some embodiments of this disclosure, the data writing circuit includes a control terminal. For example, the data writing signal includes a third transistor T3, and the gate of the third transistor T3 serves as the control terminal of the data writing circuit. Figure 2A As shown, the gate of the third transistor T3 is connected to the first scan line G1 to receive the first scan signal. Figure 4 and Figure 5B As shown, the first scan line G1 is parallel to the first voltage crossing line 305, and the first scan line G1 is located on the side of the control signal line EM away from the first voltage crossing line.

[0141] like Figure 4 As shown, in some embodiments of this disclosure, the third transistor T3 includes an active layer, and the orthographic projection of the active layer of the third transistor T3 onto the substrate is located between the orthographic projection of the first scan line G1 onto the substrate and the orthographic projection of the control signal line EM onto the substrate.

[0142] In some embodiments of this disclosure, the first control circuit includes a control terminal. For example, such as... Figure 4 As shown, the first control circuit is the fourth transistor T4, and the gate of the fourth transistor T4 serves as the control terminal of the first control circuit. The fourth transistor T4 is connected to the second scan line G2 to receive the second scan signal. The second scan line G2 is parallel to the first voltage crossing line 305, and the second scan line G2 is located on the side of the first scan line G1 away from the first voltage crossing line 305.

[0143] In some embodiments of this disclosure, the fourth transistor T4 includes an active layer, the orthographic projection of the active layer of the fourth transistor T4 onto the substrate being located between the orthographic projection of the first scan signal line G1 onto the substrate and the orthographic projection of the second scan signal line G2 onto the substrate.

[0144] In some embodiments of this disclosure, the first control circuit further includes a first terminal and a second terminal. The first terminal of the first control circuit is connected to a reference voltage line to receive a reference voltage, and the second terminal of the first control circuit is connected to the control terminal of the drive circuit.

[0145] For example, such as Figure 4 and Figure 2A As shown, the first terminal of the fourth transistor T4 is connected to the reference voltage line Vref to receive the reference voltage Vref, and the second terminal of the fourth transistor T4 is connected to the control terminal of the drive circuit (e.g., the gate of the second transistor T2).

[0146] like Figure 4 , Figure 5A and Figure 5E As shown, in some embodiments of this disclosure, the reference voltage line Vref includes a reference voltage main line 405 and a reference voltage cross line 406. The reference voltage main line 405 extends along the second direction Y and is parallel to the first voltage main line 304. The reference voltage cross line 406 extends along the first direction X. The reference voltage cross line 406 is connected to the reference voltage main line 406 through a third via 415. The reference voltage cross line 406 is connected to a first control circuit of a plurality of sub-pixels located in the same row and is configured to provide a reference voltage Vref to the first control circuit of the plurality of sub-pixels located in the same row.

[0147] Providing a reference voltage Vref for multiple sub-pixels in the same row by crossing a reference voltage line can simplify the circuit structure, reduce the number of traces, and save the space occupied by the traces.

[0148] In some embodiments of this disclosure, multiple sub-pixels located in the same row have a center line extending along a second direction Y, and a reference voltage main line overlaps with the center line.

[0149] For example, such as Figure 3 and Figure 4 As shown, each row in the pixel array may include 6 sub-pixels, and the 6 sub-pixels in the same row have a center line 39 extending along the second direction Y, and the reference voltage main line Vref overlaps with the center line 39.

[0150] For example, the reference voltage across line configuration provides a reference voltage to the first control circuitry of six sub-pixels located in the same row.

[0151] In some embodiments of this disclosure, the reference voltage cross line 406 is located on the side of the second scan line G2 away from the first voltage cross line 305.

[0152] In some embodiments of this disclosure, the second terminal of the first control circuit and the first capacitor plate are connected to the second terminal of the data writing circuit via a first bridging portion. The first bridging portion extends along the second direction Y and is connected to the second terminal of the data writing circuit via a fourth via. The orthographic projection of the first bridging portion on the substrate overlaps with the orthographic projection of the first scan line and the orthographic projection of the control signal line on the substrate. The first bridging portion includes a first terminal and a second terminal. The first terminal of the first bridging portion is located on the side of the first scan line away from the control signal line and is connected to the second terminal of the first control circuit. The second terminal of the first bridging portion is located on the side of the control signal line away from the first scan line and is connected to the first capacitor plate.

[0153] like Figure 4 , Figure 5D and Figure 5EAs shown, the first control circuit may be a fourth transistor T4. The second terminal 414 of the fourth transistor T4 and the first capacitor substrate Cst are connected to the second terminal of the data writing circuit (i.e., the third transistor T3) through a first bridging portion 407. The first bridging portion 407 extends along the second direction Y and is connected to the second terminal of the third transistor T3 through a fourth via 416. The orthographic projection of the first bridging portion 407 on the substrate overlaps with the orthographic projection of the first scan line G1 and the orthographic projection of the control signal line EM on the substrate.

[0154] In some embodiments of this disclosure, for example, the orthographic projection of the first bridging portion 407 on the substrate is perpendicular to the orthographic projection of the first scan line G1 on the substrate and the orthographic projection of the control signal line EM on the substrate.

[0155] like Figure 4 As shown, the first end of the first bridging portion 407 is located between the first scan line G1 and the second scan line G2, and the second end of the first bridging portion 407 is located on the side of the control signal line EM away from the first scan line G1 and is connected to point G on the first capacitor plate.

[0156] In some embodiments of this disclosure, the extension line of the first bridging portion 407 along the second direction Y overlaps with the extension line of the first voltage switching portion 402 along the second direction Y.

[0157] like Figure 4 and Figure 5E As shown, the first bridging portion 407 and the first voltage transfer portion 402 overlap along the extension of the second direction Y.

[0158] In some embodiments of this disclosure, for example, such as Figure 4 As shown, the orthographic projections of pixel circuits 40 and 50, located in the same column and adjacent sub-pixels, on the substrate are mirror-symmetrical about the first symmetry line. When the first voltage crossing line 305 is located between two adjacent sub-pixels in the same column, the first symmetry line overlaps with the first voltage crossing line. For example, for two sub-pixels corresponding to pixel circuits 40 and 50, the first voltage crossing line 305 is located between these two sub-pixels. In this case, the orthographic projections of pixel circuits 40 and 50 on the substrate are mirror-symmetrical about the first symmetry line, and the first symmetry line overlaps with the first voltage crossing line 503. That is, the orthographic projections of pixel circuits 40 and 50 on the substrate are mirror-symmetrical about the first voltage crossing line 503. When the first voltage crossing line is not located between two adjacent sub-pixels in the same column, the first symmetry line is the center line of the first voltage crossing line connected to the two adjacent sub-pixels in the same column. For example, for pixel circuit 50 and the pixel circuit below pixel circuit 50 (… Figure 4The first voltage crossing line 305 is not located between the two sub-pixels (there is no first voltage crossing line 305 between these two sub-pixels). There is a first voltage crossing line 305 connected to the pixel circuit 50 above it, and there is a first voltage crossing line connected to the pixel circuit below the pixel circuit 50 below it. At this time, the first symmetry line is the center line of these two first voltage crossing lines, and the orthographic projection of the two pixel circuits on the substrate is mirror symmetrical about the first symmetry line.

[0159] For example, the distribution of the reference voltage line 305, the initial signal line 401, the second scan line G2, the first scan line G1, the control signal line EM, and the third scan line G3 in two adjacent sub-pixels located in the same column is mirror-symmetrical about the first symmetry line.

[0160] In some embodiments of this disclosure, such as Figure 4 As shown, multiple sub-pixels are divided into multiple pixel units. Each pixel unit includes three adjacent sub-pixels located in the same row. Multiple first voltage main lines are arranged at intervals on the display substrate, and a pixel unit is arranged between every two adjacent first voltage main lines.

[0161] In some embodiments of this disclosure, the light-emitting control circuit includes a fifth transistor. For example, such as... Figure 4 , Figure 5D and Figure 5E As shown, the second end of the fifth transistor is connected to the first adapter line via the fifth via 431 and the sixth via 432 in sequence. The first adapter line is connected to the first end of the second control circuit (i.e., the first transistor T1) via the seventh via 433 and the eighth via 434 in sequence. The orthographic projections of the fifth via 431 and the sixth via 432 on the substrate are adjacent to each other. The fifth via 431 and the sixth via 432 are distributed along the first direction X. The orthographic projections of the seventh via 433 and the eighth via 434 on the substrate are adjacent to each other. The seventh via 433 and the eighth via 434 are distributed along the second direction Y.

[0162] like Figure 4 and Figure 5D As shown, the orthogonal projections of the fifth via 431 and the sixth via 432 on the substrate are located between the orthogonal projection of the third transistor T3 on the substrate and the light emission control line EM, and the orthogonal projections of the seventh via 433 and the eighth via 434 on the substrate are located between the third scan line G3 and the initial signal line 401.

[0163] In some embodiments of this disclosure, the light-emitting control circuit includes a fifth transistor. The first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor each include an active layer. The orthographic projection of the active layers of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor onto the substrate forms a transistor pattern. The transistor patterns of every two adjacent sub-pixels in the same row are mirror-symmetrical.

[0164] like Figure 5A As shown, the orthographic projection of the active layer 421 of the fourth transistor, the active layer 422 of the third transistor, the active layer 423 of the fifth transistor, the active layer 424 of the second transistor, and the active layer 425 of the first transistor onto the substrate forms a transistor pattern, and the transistor patterns of every two adjacent sub-pixels in the same row are mirror-symmetrical.

[0165] The following is combined with Figure 4 and Figures 5A to 5Q The embodiments of this disclosure will be further described.

[0166] For example, such as Figure 4 As shown, the reference voltage cross line Vref, the second scan line G2, the first scan line G1, the control signal line EM, and the third scan line G3 extend along the first direction X and are arranged along the second direction Y, which is not parallel to the first direction X.

[0167] For example, the first direction X and the second direction Y are perpendicular to each other. For example, the first direction X is parallel to the row direction of the pixel array, and the second direction Y is parallel to the column direction of the pixel array.

[0168] For example, such as Figure 4 As shown, in the second direction Y, the fourth transistor T4 is located between the first scan line G1 and the second scan line G2, and the projection of the active layer of the fourth transistor T4 onto the substrate is parallel to the first direction X. The third transistor T3 is located between the first scan line G1 and the control signal line EM, and the projection of the active layer of the third transistor T3 onto the substrate is parallel to the first direction X.

[0169] For example, such as Figure 4 As shown, the orthographic projection of the storage capacitor Cst on the substrate lies between the orthographic projection of the control signal line EM on the substrate and the orthographic projection of the third scan line G3 on the substrate.

[0170] For example, Figure 5C The diagram shows the overlapping portions of the first conductive layer 420 and the active semiconductor layer 410. The reference voltage cross-line Vref is located in the active semiconductor layer 410, while the second scan line G2, the first scan line G1, the control signal line EM, and the third scan line G3 are all located in the first conductive layer 420. Figure 5A ,5B As shown in Figure 5C, for example, the second scan line G2 overlaps with the active semiconductor layer 410 to define the active layer 421 of the fourth transistor T4, the first scan line G1 overlaps with the active semiconductor layer 410 to define the active layer 422 of the third transistor T3, the control signal line EM overlaps with the active semiconductor layer 410 to define the active layer 423 of the fifth transistor, the first capacitor plate Cst-1 overlaps with the active semiconductor layer 410 to define the active layer 424 of the second transistor, and the third scan line G3 overlaps with the active semiconductor layer 410 to define the active layer 425 of the first transistor T1.

[0171] For example, such as Figure 4 and Figure 5A As shown, the active layer 424 of the second transistor T2 and the active layer 423 of the light-emitting control transistor T5 are integrally formed.

[0172] Figure 5A The diagram illustrates an active semiconductor layer 410 for the plurality of pixel circuits. The active semiconductor layer 410 can be patterned on a substrate using semiconductor material. The active semiconductor layer 410 can be used to fabricate the active layers of the first transistor T1 to the fifth transistor T5. Each active layer may include a source region, a drain region, and a channel region between the source and drain regions. The channel region is used to form the channel of the transistor.

[0173] For example, such as Figure 5A As shown, the active layers of each transistor T1-T5 are set on the same layer, and the fifth transistor T5 and the second transistor T2 are integrated into one.

[0174] For example, such as Figure 5A As shown, in the second direction Y, the active layer 421 of the fourth transistor T4, the active layer 422 of the third transistor T3, and the active layer 423 of the fifth transistor T5 are located on the first side of the active layer 424 of the second transistor T2, and the active layer 425 of the first transistor T1 is located on the second side of the active layer 424 of the second transistor T2. For example, the active semiconductor layer 410 can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the aforementioned source region and drain region can be regions doped with n-type impurities or p-type impurities. In the embodiments of this disclosure, the doped source region corresponds to the source of the transistor (e.g., the first electrode of the transistor), and the doped drain region corresponds to the drain of the transistor (e.g., the second electrode of the transistor).

[0175] For example, a first insulating layer (not shown) is formed on the side of the active semiconductor layer 410 away from the substrate to protect the active semiconductor layer 410.

[0176] Figure 5BA first conductive layer 420 of the pixel circuit is shown. The first conductive layer 420 is disposed on the side of the first insulating layer away from the active semiconductor layer 410, thereby being insulated from the active semiconductor layer 410.

[0177] For example, the first scan line G1 to the third scan line G3, the control signal line EM, and the first voltage crossing line 305 are all located in the first conductive layer 420. In addition, the first conductive layer 420 may also include the first electrode plate Cst-1 of the storage capacitor Cst and the gates of the first transistor T1 to the fifth transistor T5.

[0178] For example, such as Figure 5B As shown, the first scan line G1, the second scan line G2, the control signal line EM, the third scan signal line G3, and the first voltage crossing line 305 all extend generally along the first direction X. In the second direction Y, the second scan line G2, the first scan line G1, the control signal line EM, the third scan signal line G3, and the first voltage crossing line 305 are arranged sequentially.

[0179] For example, such as Figure 5B As shown, the first scan line G1, the second scan line G2, the control signal line EM, the third scan signal line G3, and the first voltage crossing line 305 corresponding to each pixel circuit in each row of sub-pixels are continuous straight lines.

[0180] For example, the second scan line G2 is electrically connected to the gate of the fourth transistor T4 to control the fourth transistor T4 to be turned on or off; the first scan line G1 is electrically connected to the gate of the third transistor T3 to control the third transistor T3 to be turned on or off.

[0181] Figure 5C This is a schematic diagram showing the stacking position relationship between the active semiconductor layer 410 and the first conductive layer 420.

[0182] For example, such as Figure 5C As shown, in the direction perpendicular to the substrate, the portion of the active semiconductor layer 410 covered by the first electrode plate Cst-1 of the storage capacitor Cst of the first conductive layer 420 is the active layer 424 of the second transistor T2.

[0183] For example, the first transistor T1 includes an active layer 425, which includes a first channel 4251 and a second channel 4252. For example, as... Figure 5C As shown, the direction of the first channel 4251 is parallel to the second direction Y, and the direction of the second channel 4252 is parallel to the first direction X.

[0184] Figure 5D This is a schematic diagram showing the stacking position relationship of the active semiconductor layer 410, the first conductive layer 420, and the second insulating layer.

[0185] For example, a second insulating layer is formed on the side of the first conductive layer 420 away from the first insulating layer to protect the first conductive layer 420.

[0186] like Figure 5D As shown, the second insulating layer includes multiple vias. For example, vias 4342 and 4341 are connected via a first connecting line to connect the fourth transistor T4 to the reference voltage jumper Vref. Via 4348 is connected to the via corresponding to point G via the first jumper 407 and the fourth via 416. Via 4343 is connected to a data signal line (e.g., Data_R). The second terminal of the fifth transistor T5 is connected to the first adapter line via the fifth via 431 and the sixth via 432 in sequence. The first adapter line is connected to the first terminal of the first transistor T1 via the seventh via 433 and the eighth via 434 in sequence. The orthographic projections of the fifth via 431 and the sixth via 432 on the substrate are adjacent to each other and are distributed along the first direction X. The orthographic projections of the seventh via 433 and the eighth via 434 on the substrate are adjacent to each other and are distributed along the first direction X. Vias 4345 and 4346 are used to connect the second terminal of the first transistor T1 to the initial signal line 401. Via 4347 is connected to the second via 403 on the first voltage crossing 305 to receive the first voltage from the first voltage crossing 305.

[0187] Figure 5E The first source / drain metal layer is 490.

[0188] like Figure 5E As shown, the first voltage main line VDD, the reference voltage main line 405, the first bridging part 407, and the first voltage transition part 402 are all distributed on the first source-drain metal layer 490.

[0189] Figure 5F This is a schematic diagram showing the stacking position relationship of the active semiconductor layer 410, the first conductive layer 420, and the first source / drain metal layer 490.

[0190] For example, a second insulating layer (not shown) is formed on the side of the first conductive layer 420 away from the first insulating layer to protect the first conductive layer 420. A first source-drain metal layer 490 is formed on the side of the second insulating layer away from the first conductive layer 420.

[0191] Figure 5G This is a schematic diagram of the second conductive layer 440.

[0192] The second conductive layer 440 can be located between the first source / drain metal layer 490 and the third insulating layer 460. Figure 5H (as shown) between.

[0193] like Figure 5G As shown, the second conductive layer 440 includes the second electrode plate Cst-2 of the storage capacitor Cst and the initial signal line 401. Figure 5F As shown, the initial signal line 401 extends along the first direction X and is arranged along the second direction Y. In the direction perpendicular to the substrate, the first electrode plate Cst-1 of the storage capacitor Cst and the second electrode plate Cst-2 of the storage capacitor Cst at least partially overlap to form the storage capacitor Cst.

[0194] Figure 5H This is a schematic diagram of the third insulating layer 460.

[0195] The third insulating layer 460 may be located between the first source-drain metal layer 490 and the second conductive layer 440, thereby insulating the second conductive layer from the first source-drain metal layer 490.

[0196] like Figure 5H As shown, a plurality of vias 455 are distributed on the third insulating layer, and these vias 455 are used to connect the OLED. The third insulating layer may be made of, for example, a resin material.

[0197] Figure 5I This is a schematic diagram showing the stacking position relationship of the active semiconductor layer 410, the first conductive layer 420, the first source / drain metal layer 490, and the third insulating layer.

[0198] Figure 5J A schematic diagram of the second source / drain metal layer 470 is shown.

[0199] like Figure 5J As shown, the second source / drain metal layer 45 has an anode connection portion 471 distributed thereon.

[0200] Figure 5K A schematic diagram showing the stacking position relationship of the active semiconductor layer 410, the first conductive layer 420, the first source-drain metal layer 490, the third insulating layer, and the second source-drain metal layer 470 is shown.

[0201] For example, the first electrode of the light-emitting element 20 is connected to the first terminal of the second control circuit (i.e., the first transistor T1) through the anode connection portion 471. For example, the first electrode of the light-emitting element 20 can be an anode, and the second electrode of the light-emitting element 20 can be a cathode.

[0202] like Figure 5KAs shown, the anode connection portion 471 extends along the second direction Y. The anode connection portion 471 includes a first end and a second end. The first end of the anode connection portion 471 is located on the side of the third scan line G3 near the first capacitor plate Cst-1. The second end of the anode connection portion 471 is located on the side of the third scan line G3 away from the first capacitor plate Cst-1. The first end of the anode connection portion 471 is connected to the first end of the second control circuit (i.e., the first transistor T1) through the ninth via. The orthographic projection of the anode connection portion 471 on the substrate overlaps with the orthographic projection of the third scan line G3 on the substrate.

[0203] Figure 5L A schematic diagram of the distribution of the ninth via 4350 on the substrate is shown.

[0204] Figure 5M A schematic diagram showing the positional relationship of the active semiconductor layer 410, the first conductive layer 420, the first source-drain metal layer 490, the third insulating layer, the second source-drain metal layer 470, and the ninth via 4350 is shown.

[0205] Figure 5N The anode layer 480 of the pixel circuit is shown, which includes a first electrode (i.e., anode) 481 of the light-emitting element.

[0206] Figure 5O A schematic diagram showing the stacking position relationship of the active semiconductor layer 410, the first conductive layer 420, the first source-drain metal layer 490, the third insulating layer, the second source-drain metal layer 470, and the anode layer 480 is shown.

[0207] like Figure 5O As shown, the first electrode 481 of the light-emitting element covers the corresponding sub-pixel.

[0208] In some embodiments of this disclosure, the display substrate may further include a pixel definition layer (PDL) in addition to the foregoing embodiments.

[0209] Figure 5P A schematic diagram of the distribution of PDL 491 on the substrate is shown.

[0210] Figure 5Q A schematic diagram showing the stacking position relationship of the active semiconductor layer 410, the first conductive layer 420, the first source-drain metal layer 490, the third insulating layer, the second source-drain metal layer 470, the anode layer 480, and the PDL 491 is shown.

[0211] The pixel defining layer can be located on the side of the anode layer 480 away from the second source / drain metal layer 470. The pixel defining layer can prevent color mixing between the anode layers of adjacent light-emitting elements, resulting in high controllability over the area, shape, and arrangement of sub-pixels. For example, the pattern defined by the pixel defining layer corresponding to each sub-pixel can be an ellipse, rectangle, square, or other arbitrary shape, such as a shape composed of two straight lines and two semicircles (e.g.,...). Figure 5P and Figure 5Q As shown in the figure, each semicircle is connected to a straight line at both ends, thus forming a closed pattern that resembles the shape of a runway.

[0212] It should be noted that in the embodiments of this disclosure, the display substrate may include more layers, not limited to the layers described above, and the positional relationship of the layers in the display substrate is not limited, which can be determined according to actual needs.

[0213] At least one embodiment of this disclosure also provides a display panel. Figure 6 This is a schematic diagram of a display panel provided for at least one embodiment of the present disclosure. Figure 6 As shown, the display panel 800 includes a display substrate 810 provided in any embodiment of this disclosure. The display substrate 810 may be, for example, a... Figure 1A , Figures 3 to 5Q The display substrate 100 or 300 shown is illustrated.

[0214] For example, the display panel 800 can be an organic light-emitting diode (OLED) display panel, etc. When the display panel 800 is an organic light-emitting diode display panel, the display substrate 810 can be an array substrate.

[0215] For example, the display panel 800 can be a rectangular panel, a circular panel, an elliptical panel, or a polygonal panel. In addition, the display panel 800 can be not only a flat panel, but also a curved panel, or even a spherical panel.

[0216] For example, the display panel 800 can also have a touch function, that is, the display panel 800 can be a touch display panel.

[0217] For example, the display panel 800 can be used in any product or component with display function, such as mobile phones, tablets, televisions, monitors, laptops, digital photo frames, and navigators.

[0218] For example, the display panel 800 can be a flexible display panel, thereby meeting various practical application needs. For instance, the display panel 800 can be applied to curved screens, etc.

[0219] It should be noted that the display panel 800 may also include other components, such as data driving circuits and timing controllers, and the embodiments of this disclosure do not limit this. For clarity and brevity, the embodiments of this disclosure do not show all the constituent units of the display panel 800. To achieve the basic functions of the display panel 800, those skilled in the art can provide and set other structures (not shown) according to specific needs, and the embodiments of this disclosure do not limit this.

[0220] For the technical effects of the display panel 800 provided in the above embodiments, please refer to the technical effects of the display substrate provided in the embodiments of this disclosure, which will not be repeated here.

[0221] The following points should be noted regarding this disclosure:

[0222] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0223] (2) For clarity, the thickness and dimensions of layers or structures are enlarged in the drawings used to describe embodiments of the invention. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0224] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0225] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A display substrate, comprising: Substrate; Multiple sub-pixels are disposed on the substrate; The plurality of sub-pixels are arranged in multiple rows and columns, and each sub-pixel includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light. The light-emitting element is configured to emit light according to the received driving current. The pixel circuit includes a driving circuit, a data writing circuit, a storage circuit, a first control circuit, a second control circuit, and a light emission control circuit. The driving circuit includes a control terminal, a first terminal, and a second terminal, and is configured to control the driving current flowing through the light-emitting element. The first terminal of the driving circuit receives a first voltage from a first voltage line, and the second terminal of the driving circuit is connected to the light-emitting control circuit. The data writing circuit is connected to the control terminal of the driving circuit and is configured to write a data signal to the control terminal of the driving circuit in response to a first scan signal. The first terminal of the light-emitting control circuit is connected to the second terminal of the driving circuit, and the second terminal of the light-emitting control circuit is connected to the first electrode of the light-emitting element. The light-emitting control circuit is configured to apply the driving current to the light-emitting element in response to the light-emitting control signal. The first end of the storage circuit is connected to the control end of the driving circuit, and the second end of the storage circuit is connected to the second end of the light-emitting control circuit. The storage circuit is configured to store the data signal written by the data writing circuit. The first control circuit is connected to the control terminal of the drive circuit and is configured to write a reference voltage to the control terminal of the drive circuit in response to a second scan signal. The second control circuit is connected to the first electrode of the light-emitting element and is configured to write an initial voltage into the first electrode of the light-emitting element in response to a third scan signal; At least a portion of the pixel circuitry of every two adjacent sub-pixels in the same row is mirror-symmetrical in its orthographic projection onto the substrate. The plurality of sub-pixels are divided into a plurality of pixel units, each pixel unit including three adjacent sub-pixels located in the same row, and each pixel unit including a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along a first direction. The data writing circuit in the pixel circuit of the first sub-pixel is connected to the first data line to receive the corresponding data signal; The data writing circuit in the pixel circuit of the second sub-pixel is connected to the second data line to receive the corresponding data signal; The data writing circuit in the pixel circuit of the third sub-pixel is connected to the third data line to receive the corresponding data signal; The first voltage line includes a first voltage main line and a first voltage crossover line. The first voltage main line extends along the second direction and is parallel to the first data line, the second data line, and the third data line. The first voltage cross line extends along a first direction, the first voltage cross line is connected to the first voltage main line through a first via, and the first voltage cross line is configured to provide the first voltage to two rows of sub-pixels located on both sides of the first voltage cross line and adjacent to the first voltage cross line. The second control circuit includes a first terminal and a second terminal. The first terminal of the second control circuit is connected to the first electrode of the light-emitting element, and the second terminal of the second control circuit is connected to the initial signal line to receive the initial voltage. For the initial signal line and the first voltage cross line that are adjacent to each other in the second direction, the initial signal line is parallel to the first voltage cross line and is located between the orthographic projection of the first voltage cross line on the substrate and the orthographic projection of the second control circuit on the substrate.

2. The display substrate according to claim 1, wherein, The first data line, the second data line, and the third data line are parallel to each other and extend along a second direction, which is perpendicular to the first direction. The orthographic projections of the pixel circuits of the first sub-pixel and the second sub-pixel on the substrate are mirror-symmetrical about the center line between the first data line and the second data line. The orthographic projections of the pixel circuits of the second sub-pixel and the third sub-pixel on the substrate are mirror-symmetrical about the center line between the second data line and the third data line.

3. The display substrate according to claim 2, wherein, The first data line is located on the side of the first sub-pixel away from the second sub-pixel, and the second data line and the third data line are located between the second sub-pixel and the third sub-pixel; or The first data line and the second data line are located between the first sub-pixel and the second sub-pixel, and the third data line is located on the side of the third sub-pixel away from the second sub-pixel.

4. The display substrate according to claim 2, wherein, For two adjacent pixel units in the same row, the distribution positions of the multi-line pattern formed by the first data line, the second data line, and the third data line in the two pixel units are mirror symmetrical.

5. The display substrate according to claim 1, wherein, The second control circuit includes a first transistor, the first transistor including a gate, the gate of the first transistor being connected to a third scan line to receive the third scan signal. The third scan line is parallel to the first voltage crossing line and is located on the side of the initial signal line away from the first voltage crossing line. The first transistor includes an active layer, and at least a portion of the active layer of the first transistor is projected onto the substrate between the orthographic projections of the third scan line and the initial signal line onto the substrate.

6. The display substrate according to claim 5, wherein, The first voltage line further includes a plurality of first voltage transition sections, each of which is configured to provide the first voltage to two sub-pixels located in the same column, on both sides of the first voltage line, and adjacent to the first voltage line. Each first voltage adapter extends along the second direction and is connected to the first voltage crossover line through a second via. The first voltage adapter includes a first end and a second end. The first end and the second end of the first voltage adapter are respectively located on both sides of the first voltage crossover line. The first end of the first voltage adapter is connected to a sub-pixel located on one side of the first voltage crossover line, and the second end of the first voltage adapter is connected to a sub-pixel located on the other side of the first voltage crossover line.

7. The display substrate according to claim 6, wherein, The orthographic projection of the first voltage transfer section on the substrate overlaps with the orthographic projection of the initial signal line on the substrate and the orthographic projection of the third scan line on the substrate.

8. The display substrate according to claim 6, wherein, The light-emitting control circuit includes a control terminal, which is connected to a control signal line to receive the light-emitting control signal. The control signal line is parallel to the first voltage crossover line, and the control signal line is located on the side of the third scan line away from the first voltage crossover line.

9. The display substrate according to claim 8, wherein, The control signal line and the third scan line are located on opposite sides of the orthogonal projection of the driving circuit onto the substrate.

10. The display substrate according to claim 8, wherein, The storage circuit includes a first capacitor plate and a second capacitor plate. The orthographic projection of the first capacitor plate on the substrate lies between the orthographic projection of the third scan line on the substrate and the orthographic projection of the control signal line on the substrate. The orthographic projection of the first capacitor plate on the substrate at least partially overlaps with the orthographic projection of the second capacitor plate on the substrate. The driving circuit includes a second transistor, which has a gate, and the first capacitor plate serves as the gate of the second transistor.

11. The display substrate according to claim 10, wherein, The data writing circuit includes a control terminal, which is connected to the first scan line to receive the first scan signal. The first scan line is parallel to the first voltage crossover line, and the first scan line is located on the side of the control signal line away from the first voltage crossover line.

12. The display substrate according to claim 11, wherein, The data writing circuit includes a third transistor, which includes an active layer. The orthographic projection of the active layer of the third transistor onto the substrate is located between the orthographic projection of the first scan line onto the substrate and the orthographic projection of the control signal line onto the substrate.

13. The display substrate according to claim 12, wherein, The first control circuit includes a control terminal, which is connected to the second scan line to receive the second scan signal. The second scan line is parallel to the first voltage crossover line, and the second scan line is located on the side of the first scan line away from the first voltage crossover line.

14. The display substrate according to claim 13, wherein, The first control circuit includes a fourth transistor, the fourth transistor including an active layer, the orthographic projection of the active layer of the fourth transistor on the substrate being located between the orthographic projection of the first scan line on the substrate and the orthographic projection of the second scan line on the substrate.

15. The display substrate according to claim 13, wherein, The first control circuit further includes a first terminal and a second terminal. The first terminal of the first control circuit is connected to a reference voltage line to receive the reference voltage, and the second terminal of the first control circuit is connected to the control terminal of the drive circuit. The reference voltage line includes a main reference voltage line and a reference voltage crossover line. The reference voltage main line extends along the second direction and is parallel to the first voltage main line. The reference voltage crossover extends along a first direction, and the reference voltage crossover is connected to the reference voltage main line through a third via. The reference voltage crossover is connected to a first control circuit of a plurality of sub-pixels located in the same row, and is configured to provide the reference voltage to the first control circuit of the plurality of sub-pixels located in the same row.

16. The display substrate according to claim 15, wherein, The multiple sub-pixels located in the same row have a center line extending along the second direction, and the reference voltage main line overlaps with the center line.

17. The display substrate according to claim 16, wherein, The reference voltage is configured to provide the reference voltage to the first control circuit of each of the six sub-pixels located in the same row.

18. The display substrate according to claim 15, wherein, The reference voltage crossover is located on the side of the second scan line away from the first voltage crossover.

19. The display substrate according to claim 11, wherein, The second terminal of the first control circuit and the first capacitor plate are connected to the second terminal of the data writing circuit through a first bridging portion. The first bridging portion extends along the second direction and is connected to the second end of the data writing circuit through the fourth via. The orthographic projection of the first bridging portion on the substrate overlaps with the orthographic projection of the first scan line and the orthographic projection of the control signal line on the substrate. The first bridging portion includes a first end and a second end. The first end of the first bridging portion is located on the side of the first scan line away from the control signal line and is connected to the second end of the first control circuit. The second end of the first bridging portion is located on the side of the control signal line away from the first scan line and is connected to the first capacitor plate.

20. The display substrate according to claim 19, wherein, The extension line of the first bridging portion along the second direction overlaps with the extension line of the first voltage switching portion along the second direction.

21. The display substrate according to claim 15, wherein, The pixel circuits of two adjacent sub-pixels located in the same column are mirror-symmetrical about the first line of symmetry when projected onto the substrate. The distribution of the reference voltage cross line, the initial signal line, the second scan line, the first scan line, the control signal line, and the third scan line in two adjacent sub-pixels located in the same column is mirror-symmetrical about the first symmetry line. When the first voltage cross line is located between two adjacent sub-pixels in the same column, the first symmetry line overlaps with the first voltage cross line; or when the first voltage cross line is not located between two adjacent sub-pixels in the same column, the first symmetry line is the center line of the first voltage cross line that is connected to the two adjacent sub-pixels in the same column respectively.

22. The display substrate according to claim 1, wherein, The multiple sub-pixels are divided into multiple pixel units, each pixel unit including three adjacent sub-pixels located in the same row. The display substrate is provided with multiple spaced first voltage main lines, and a pixel unit is provided between every two adjacent first voltage main lines.

23. The display substrate according to claim 1, wherein, The second terminal of the light-emitting control circuit is connected to the first adapter cable via the fifth and sixth vias in sequence, and the first adapter cable is connected to the first terminal of the second control circuit via the seventh and eighth vias in sequence. The fifth via and the sixth via are adjacent to each other on the substrate, and the fifth via and the sixth via are distributed along a first direction. The seventh via and the eighth via are adjacent to each other on the substrate, and the seventh via and the eighth via are distributed along the second direction.

24. The display substrate according to claim 14, wherein, The light-emitting control circuit includes a fifth transistor, and the first transistor, second transistor, third transistor, fourth transistor, and fifth transistor each include an active layer. The active layers of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are projected onto the substrate to form a transistor pattern. The transistor patterns of every two adjacent sub-pixels in the same row are mirror-symmetric.

25. The display substrate according to claim 10, wherein, The first electrode of the light-emitting element covers the corresponding sub-pixel.

26. The display substrate according to claim 25, wherein, The first electrode of the light-emitting element is connected to the first end of the second control circuit through an anode connection portion. The anode connection portion extends along a second direction and includes a first end and a second end. The first end of the anode connection portion is located on the side of the third scan line close to the first capacitor plate, and the second end of the anode connection portion is located on the side of the third scan line away from the first capacitor plate. The first end of the anode connection portion is connected to the first end of the second control circuit through a ninth via. The orthographic projection of the anode connection portion on the substrate overlaps with the orthographic projection of the third scan line on the substrate.

27. A display panel comprising a display substrate as described in any one of claims 1-26.

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