A method and circuit for aging training of a high-precision variable constant temperature voltage chip assembly

Abstract

This invention discloses an aging training method and circuit for a high-precision variable temperature voltage (VTV) chip assembly. The method stabilizes the output voltage of the VTV chip within a specified technical characteristic range in a short time, shortening the out-of-range aging time of the VTV chip. This is achieved by applying a specific voltage to the VTV chip assembly through a special temperature control component for a specific time, thereby controlling the chip temperature to accelerate chip aging. The control component includes an electronic circuit that controls the temperature of the VTV chip during aging training. Furthermore, this invention also discloses a dedicated electronic circuit for implementing the above-mentioned aging training method, which subjects the high-precision VTV chip assembly to a specific temperature and maintains it at each temperature for a specific time, thereby eliminating or reducing the internal stress of the chip in a short time, thus achieving the purpose of chip aging.

Description

Technical Field

[0001] This invention relates to the field of variable temperature voltage chip aging training, and particularly to a high-precision variable temperature voltage chip assembly aging training method and circuit. Background Technology

[0002] High-precision variable temperature voltage chips serve as the internal voltage reference standard for high-precision instruments such as high-precision digital multimeters, high-precision multifunctional calibrators, and solid-state voltage transfer standards. The basic internal structure of these chips is based on Zener diodes or composite Zener diodes and corresponding temperature control and conditioning circuits.

[0003] To achieve higher accuracy, these chips are typically operated under controlled temperatures. This reduces additional errors caused by temperature variations and protects the chip from permanent or semi-permanent voltage drift due to operation at abnormal temperatures. Because the stability requirements for these chips are extremely high, a stability of 1×10⁻⁶ is typically required. -6 / year ~2×10 -6 / year. However, due to various mechanical stresses during chip manufacturing and installation on circuit boards, as well as thermal stresses generated by various thermal processes, high stability is achieved. Before use, chips need to be powered on and aged in actual circuits for several months or even more than a year to help them overcome their aging period.

[0004] For users, the power-on aging process takes too long. Moreover, not every chip that has undergone power-on aging can achieve the stability claimed by its manufacturer, requiring screening, which inevitably delays the application of the chips.

[0005] The existing aging technology is provided by the chip manufacturer Linear Technology. In Linear Technology's technical document "Application Note 82 Understanding and Applying Voltage References", it is mentioned that "When long-term stability is guaranteed, it is done by means of a 4-week burn-in, during which multiple output voltage measurements are made. Even with this elaborate, costly procedure, the guaranteed limit is about three to four times the typical drift." The existing technology is very time-consuming and expensive, requiring a 4-week power-on aging annealing process, and even after 4 weeks, it can only guarantee that the drift is reduced by (3 to 4) times the specified drift index, so the aging effect is not good. Summary of the Invention

[0006] The purpose of this invention is to shorten the off-domain aging time of chip components and achieve accelerated chip aging.

[0007] Therefore, this invention provides an aging training method for high-precision variable temperature voltage chips. An additional control circuit controls the chip's temperature, subjecting the chip's interior to specific temperatures and maintaining each temperature for a specific time. This eliminates or reduces internal stress in the chip within a shorter time, thereby achieving the purpose of chip aging.

[0008] The present invention also relates to an electronic circuit specifically for implementing the above-described aging training method.

[0009] The objective of this invention is achieved by at least one of the following technical solutions.

[0010] A high-precision aging training method for a variable thermoelectric voltage chip assembly is disclosed. This method enables the output voltage of the variable thermoelectric voltage chip to stabilize within a specified technical characteristic range in a short time, thereby shortening the out-of-range aging time of the variable thermoelectric voltage chip. This is achieved by applying a specific voltage to the variable thermoelectric voltage chip assembly through a special temperature control component for a specific period of time, thereby controlling the chip temperature to accelerate chip aging. The control component includes an electronic circuit that controls the temperature of the variable thermoelectric voltage chip during the aging training process.

[0011] Its characteristic is that it includes the following steps:

[0012] S1. The temperature of the variable constant temperature voltage chip is gradually increased from room temperature, and reaches the highest temperature after going through multiple steps.

[0013] S2. Control the temperature of the variable constant temperature voltage chip to maintain the highest temperature for a period of time, so that the variable constant temperature voltage chip is annealed at high temperature, and the internal temperature of the chip is maintained at a specific high temperature for a certain period of time to achieve the purpose of chip aging.

[0014] S3. Based on the multiple steps experienced in step S1, the temperature of the variable constant temperature voltage chip is controlled to gradually decrease to room temperature by changing back and forth between room temperature and a certain value above room temperature, so as to avoid generating new thermal stress during the cooling process.

[0015] Furthermore, in step S1, the temperature of the variable temperature voltage chip gradually increases from room temperature, reaching its maximum temperature T after passing through n steps. max The temperature rises by T between each step, and the duration of the temperature rise of the variable thermostatic voltage chip at each step is t.

[0016] Furthermore, in step S3, based on the n steps experienced in step S1, the temperature reduction process of the variable constant temperature voltage chip includes n stages, as detailed below:

[0017] In the first stage, the temperature of the variable temperature voltage chip is changed from the highest temperature T. max The temperature is lowered to room temperature and maintained for a period of time, then the temperature of the variable thermostatic voltage chip is raised from room temperature to the (n-1)th step temperature and maintained for a period of time.

[0018] In the second stage, the temperature of the variable thermostatic voltage chip drops from the temperature of the (n-1)th step to room temperature and is maintained for a period of time. Then, the temperature of the variable thermostatic voltage chip rises from room temperature to the temperature of the (n-2)th step and is maintained for a period of time.

[0019] Similarly, in the (n-1)th stage, the temperature of the variable thermostatic voltage chip drops from the temperature of the second step to room temperature and is maintained for a period of time, and then the temperature of the variable thermostatic voltage chip rises from room temperature to the temperature of the first step and is maintained for a period of time.

[0020] In the nth stage, the temperature of the variable constant-temperature voltage chip drops from the temperature of the first step to room temperature.

[0021] Furthermore, by applying a voltage set by the variable thermostatic voltage chip, the heating power of the variable thermostatic voltage chip is controlled, thereby controlling the temperature of the variable thermostatic voltage chip and the duration of the variable thermostatic voltage chip at that temperature.

[0022] An aging training circuit for a high-precision variable constant temperature voltage chip assembly includes a microcontroller unit (MCU), a parallel digital-to-analog converter (DAC), a voltage reference standard, and four operational amplifier units.

[0023] The data port and signal control pin of the parallel digital-to-analog converter (DAC) are connected to the I / O ports of the microcontroller unit (MCU);

[0024] The analog voltage value output by the parallel digital-to-analog converter (DAC) is written to the parallel port of the parallel digital-to-analog converter (DAC) by the program in the microcontroller unit (MCU). The parallel digital-to-analog converter (DAC), together with the first operational amplifier B and the second operational amplifier C, forms a two-quadrant unipolar output DAC to realize the voltage output between 0V and VREF.

[0025] The first operational amplifier B and the second operational amplifier C convert the output of the 16-bit parallel digital-to-analog converter (DAC) from current to voltage;

[0026] The output of the parallel digital-to-analog converter (DAC) is output to the signal input terminal of the variable temperature voltage chip after passing through a composite emitter follower consisting of the third operational amplifier D and the fourth operational amplifier E and a current-limiting resistor F. This controls the voltage at the base of the temperature sensing transistor in the variable temperature voltage chip, thereby controlling the internal temperature of the variable temperature voltage chip and realizing the aging training of the variable temperature voltage chip assembly.

[0027] Furthermore, a 16-bit parallel digital-to-analog converter (DAC) is used, with the voltage output pin of the voltage reference standard connected to the R1 pin of the 16-bit parallel digital-to-analog converter (DAC), and the R1 pin of the 16-bit parallel digital-to-analog converter (DAC) connected to ground along with a bypass capacitor.

[0028] The inverting input of the first operational amplifier B is connected to R of the 16-bit parallel digital-to-analog converter (DAC). COM The pins are connected, the non-inverting input of the first operational amplifier B is connected to ground, and the output of the first operational amplifier B is connected to the REF pin of the 16-bit parallel digital-to-analog converter (DAC).

[0029] The inverting input of the second operational amplifier C is connected to the I of the 16-bit parallel digital-to-analog converter (DAC). OUT1 The pins are connected, and the non-inverting input of the second operational amplifier C is connected to the AGND and DGND pins of the 16-bit parallel digital-to-analog converter (DAC) and then grounded. The output of the second operational amplifier C is connected to the R... OFS Pins and R FBThe pins are connected, and a filter capacitor is connected between the output terminal of the second operational amplifier C and the inverting input terminal of the second operational amplifier C.

[0030] The output of the second operational amplifier C is connected to the non-inverting input of the third operational amplifier D. The output of the third operational amplifier D is connected to the input of the fourth operational amplifier E. The output of the fourth operational amplifier E is connected in series with a 10kΩ resistor and then connected to the inverting input of the third operational amplifier D. A filter capacitor is connected between the output of the third operational amplifier D and its inverting input. The output of the fourth operational amplifier E is connected in series with a current-limiting resistor F and then externally connected to the signal input of the variable temperature voltage chip. This controls the voltage at the base of the temperature sensing transistor in the variable temperature voltage chip, thereby controlling the internal temperature of the variable temperature voltage chip and achieving the aging training of the variable temperature voltage chip assembly.

[0031] Furthermore, the value output by the parallel digital-to-analog converter (DAC) is written to the parallel port of the parallel digital-to-analog converter (DAC) by the program in the microcontroller unit (MCU). The parallel digital-to-analog converter (DAC), together with the first operational amplifier B and the second operational amplifier C, forms a two-quadrant unipolar output DAC to realize voltage output between 0V and VREF.

[0032] The first operational amplifier B and the second operational amplifier C convert the output of the parallel digital-to-analog converter (DAC) from current to voltage;

[0033] The output of the parallel digital-to-analog converter (DAC) is fed to the signal input terminal of the variable temperature voltage chip after passing through a composite emitter follower consisting of the third operational amplifier D and the fourth operational amplifier E, and a current-limiting resistor F.

[0034] Furthermore, by using the program written in the microcontroller unit (MCU) and the timer in the MCU, the aging training circuit outputs a set timing voltage waveform, thereby controlling the rise and fall of the internal temperature of the variable constant temperature voltage chip, completing the stress elimination and accelerated aging process.

[0035] Furthermore, the specific timing voltage waveform is as follows:

[0036] The voltage gradually decreases from the highest value in the set range through multiple steps to the lowest value. The voltage decrease is equal between each step, and the voltage is maintained at the lowest value for a set time. Finally, following the order of the decreasing steps, the voltage value changes back and forth between the highest value and each step until it passes through all the steps from low to high.

[0037] Furthermore, VREF is provided with a standard voltage by a voltage standard that uses a 10V bandgap standard voltage chip.

[0038] Furthermore, the fourth operational amplifier E is used to improve the driving capability of the operational amplifier by using a power buffer LT1010, which enables its startup capability to reach up to 150mA; the current-limiting resistor F is used to limit the voltage at the signal input terminal of the variable temperature voltage chip to the range of Vbe-90mV to Vbe+120mV.

[0039] Compared with the prior art, the advantages of this invention are:

[0040] (1) It can effectively shorten the off-domain aging time of chip components and improve the efficiency of screening qualified and stable chip components;

[0041] (2) The aging effect is significantly better than the existing methods, enabling the chip components to basically reach within (1 to 2) times the specified drift index. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of a high-precision variable constant temperature voltage chip and its peripheral circuit, used to control the voltage chip at a stable temperature under a certain temperature to achieve stable voltage output.

[0043] Figure 2 It is used to illustrate an application according to the present invention. Figure 1 The waveform of the actual control voltage at the connection of voltage divider resistors 8 and 9 in the circuit.

[0044] Figure 3 This is a circuit schematic diagram of a programmable microcontroller precision temperature modulation circuit, based on the present invention. Figure 2 It is used to set and control the internal temperature of the chip and generate a specific control voltage waveform. It is a programmable temperature and time control circuit.

[0045] Figure 4 yes Figure 3 The voltage waveform at point A in the diagram shows the circuit during its operation.

[0046] Figure 5 This is a flowchart illustrating the steps of an aging training method for a high-precision variable constant temperature voltage chip assembly according to an embodiment of the present invention. Detailed Implementation

[0047] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings, but the embodiments of the present invention are not limited thereto.

[0048] Example 1:

[0049] In this embodiment, the LTZ1000 is a reference voltage standard with a built-in on-chip heater. It can maintain the internal temperature of the chip at a certain temperature value through the setting of external circuitry and output a highly stable constant voltage. Figure 1 This is a typical application example circuit of the high-precision variable temperature voltage chip LTZ1000 / LTZ1000A, which is based on the chip datasheet of Analog Devices (ADI).

[0050] The above-described application example circuit of a high-precision typical variable temperature constant voltage chip is characterized by the following: components 1, 2, 3, and 4 are all located inside the chip and integrated within a very narrow area of ​​the substrate. Furthermore, because silicon itself is an excellent thermal conductor, the temperature difference between them is very small. Component 1 is a Zener diode, and component 2 is a compensation transistor. Both have similar temperature coefficients, with the Zener diode having a positive temperature coefficient and the compensation transistor's base-emitter junction having a negative temperature coefficient. The combination of components 1 and 2 cannot completely compensate for the temperature coefficient to zero.

[0051] The above is an example circuit of a typical high-precision variable temperature voltage chip, such as... Figure 1 As shown, it includes Zener diode 1, compensation transistor 2, temperature sensing transistor 3, heater 4, bias resistor 5, fifth operational amplifier 6, first resistor 7, first voltage divider resistor 8, second voltage divider resistor 9, second resistor 10, sixth operational amplifier 11, and control signal pin 12.

[0052] Bias resistor 5 sets the operating current of the Zener diode, and the first resistor 7 sets the collector operating current of the compensation transistor 2. The sum of the emitter voltage drops of the Zener diode 1 and the compensation transistor 2 serves as the chip's voltage output. The fifth operational amplifier 6 provides current by maintaining the collector voltage of the compensation transistor 2 at a constant value close to zero. The temperature coefficients of the Zener diode 1 and the compensation transistor 2 do not completely cancel each other out; in fact, they exhibit a very small positive temperature coefficient overall, allowing the chip to maintain a constant temperature using heater 4 and temperature sensing transistor 3. In this circuit, the first voltage divider resistor 8 and the second voltage divider resistor 9 provide a bias voltage of approximately 0.5 volts to transistor 3. This bias voltage is the base-emitter voltage of the temperature sensing transistor 3 at its operating temperature (typically 80°C). The collector current of the temperature sensing transistor 3 is determined by the second resistor 10. Based on the characteristics set in the diagram, the temperature coefficient of the base-emitter pn junction of the temperature sensing transistor 3 is predictable, approximately -2 mV / °C. Therefore, when the chip temperature rises, the temperature sensing transistor 3 will increase its conduction, thus increasing the voltage drop across the collector load resistor and lowering its collector voltage. This voltage is then amplified by the sixth operational amplifier 11, reducing the current through the heater 4, lowering the heating power, and consequently lowering the chip temperature. However, the specifications stated by the manufacturer in the technical specifications are not achievable with a new chip that has not undergone aging treatment; they require aging or a relatively long initial power-on period. This aging process is often very time-consuming and troublesome. The instability of chip performance is mainly due to the thermal and mechanical stresses during chip manufacturing. Of course, subsequent soldering and processing will further introduce new stresses. If these stresses are not effectively eliminated, the chip will experience output voltage variations of up to 10 ppm in the first few months of use, and it may take 1 to 2 years or more of normal power-on operation for the chip to fully stabilize.

[0053] To eliminate chip stress and improve its technical performance, this invention uses a specific aging training circuit to regulate the chip temperature, achieving an "annealing" process. The hardware circuitry includes the following implementation:

[0054] (1) In order to achieve the purpose of chip aging training, it is necessary to additionally control the internal constant temperature of the chip;

[0055] (2) The internal constant temperature of the additional control chip is achieved by controlling the heating power of the variable constant temperature voltage chip;

[0056] (3) The method for controlling the heating power of the chip is to apply an additional rated voltage. Figure 1 At pin 12 of the control signal, forced intervention in chip temperature control is achieved. Figure 2This is a voltage curve at the applied point, which is formed by the superposition of the conditioning voltage and the voltage division of the first voltage divider resistor 8 and the second voltage divider resistor 9. When no conditioning signal is applied, the chip temperature is determined by the bias voltage (Vbe) set by the first voltage divider resistor 8 and the second voltage divider resistor 9. Under normal circumstances, the chip temperature is set to 80°C.

[0057] (4) This additional rated voltage is generated by using an external aging training circuit. Figure 3 The provided schematic is a circuit designed to implement the aforementioned bias voltage conditioning. The current example utilizes a microcontroller, digital-to-analog converter, and voltage drive circuitry composed of operational amplifiers. Other examples may include circuits using electronic logic chips and corresponding operational amplifiers to achieve similar functionality. Figure 3 The circuit does not indicate the power connection or some unimportant components and auxiliary electronic devices.

[0058] In this embodiment,

[0059] A high-precision aging training method for a variable thermoelectric voltage chip assembly is disclosed. This method enables the output voltage of the variable thermoelectric voltage chip to stabilize within a specified technical characteristic range in a short time, thereby shortening the out-of-range aging time of the variable thermoelectric voltage chip. This is achieved by applying a specific voltage to the variable thermoelectric voltage chip assembly through a special temperature control component for a specific period of time, thereby controlling the chip temperature to accelerate chip aging. The control component includes an electronic circuit that controls the temperature of the variable thermoelectric voltage chip during the aging training process.

[0060] Its characteristic is that it includes the following steps:

[0061] S1. The temperature of the variable constant temperature voltage chip is gradually increased from room temperature, and reaches the highest temperature after going through multiple steps.

[0062] The temperature of the variable temperature voltage chip gradually increases from room temperature, reaching its maximum temperature T after passing through n steps. max The temperature rises by T between each step, and the duration of the temperature rise of the variable thermostatic voltage chip at each step is t.

[0063] S2. Control the temperature of the variable constant temperature voltage chip to maintain the highest temperature for a period of time, so that the variable constant temperature voltage chip is annealed at high temperature, and the internal temperature of the chip is maintained at a specific high temperature for a certain period of time to achieve the purpose of chip aging.

[0064] S3. Based on the multiple steps experienced in step S1, the temperature of the variable constant temperature voltage chip is controlled to gradually decrease to room temperature by changing back and forth between room temperature and a certain value above room temperature, so as to avoid generating new thermal stress during the cooling process.

[0065] Based on the n steps experienced in step S1, the temperature reduction process of the variable temperature voltage chip includes n stages, as detailed below:

[0066] In the first stage, the temperature of the variable temperature voltage chip is changed from the highest temperature T. max The temperature is lowered to room temperature and maintained for a period of time, then the temperature of the variable thermostatic voltage chip is raised from room temperature to the (n-1)th step temperature and maintained for a period of time.

[0067] In the second stage, the temperature of the variable thermostatic voltage chip drops from the temperature of the (n-1)th step to room temperature and is maintained for a period of time. Then, the temperature of the variable thermostatic voltage chip rises from room temperature to the temperature of the (n-2)th step and is maintained for a period of time.

[0068] Similarly, in the (n-1)th stage, the temperature of the variable thermostatic voltage chip drops from the temperature of the second step to room temperature and is maintained for a period of time, and then the temperature of the variable thermostatic voltage chip rises from room temperature to the temperature of the first step and is maintained for a period of time.

[0069] In the nth stage, the temperature of the variable constant-temperature voltage chip drops from the temperature of the first step to room temperature.

[0070] By applying a voltage set by the variable thermostatic voltage chip, the heating power of the variable thermostatic voltage chip is controlled, thereby controlling the temperature of the variable thermostatic voltage chip and the duration of the variable thermostatic voltage chip at that temperature.

[0071] An aging training circuit for a high-precision variable constant-temperature voltage chip assembly, such as... Figure 3 As shown, it includes a microcontroller unit (MCU), a 16-bit parallel digital-to-analog converter (DAC), a voltage reference standard, and four operational amplifier units;

[0072] The 16-bit data port and signal control pin of the 16-bit parallel digital-to-analog converter (DAC) are connected to the I / O ports of the microcontroller unit (MCU).

[0073] The voltage output pin of the voltage reference standard is connected to the R1 pin of the 16-bit parallel digital-to-analog converter (DAC), and the R1 pin of the 16-bit parallel digital-to-analog converter (DAC) is connected to ground along with a bypass capacitor.

[0074] The inverting input of the first operational amplifier B is connected to R of the 16-bit parallel digital-to-analog converter (DAC). COM The pins are connected, the non-inverting input of the first operational amplifier B is connected to ground, and the output of the first operational amplifier B is connected to the REF pin of the 16-bit parallel digital-to-analog converter (DAC).

[0075] The inverting input of the second operational amplifier C is connected to the I of the 16-bit parallel digital-to-analog converter (DAC). OUT1 The pins are connected, and the non-inverting input of the second operational amplifier C is connected to the AGND and DGND pins of the 16-bit parallel digital-to-analog converter (DAC) and then grounded. The output of the second operational amplifier C is connected to the R... OFS Pins and R FB The pins are connected, and a filter capacitor is connected between the output terminal of the second operational amplifier C and the inverting input terminal of the second operational amplifier C.

[0076] The output of the second operational amplifier C is connected to the non-inverting input of the third operational amplifier D. The output of the third operational amplifier D is connected to the input of the fourth operational amplifier E. The output of the fourth operational amplifier E is connected in series with a 10kΩ resistor and then connected to the inverting input of the third operational amplifier D. A filter capacitor is connected between the output of the third operational amplifier D and its inverting input. The output of the fourth operational amplifier E is connected in series with a current-limiting resistor F and then externally connected to the signal input of the variable temperature voltage chip. This controls the voltage at the base of the temperature sensing transistor in the variable temperature voltage chip, thereby controlling the internal temperature of the variable temperature voltage chip and achieving the aging training of the variable temperature voltage chip assembly.

[0077] The output value of the 16-bit parallel digital-to-analog converter (DAC) is written to the parallel port of the 16-bit parallel digital-to-analog converter (DAC) by the program in the microcontroller unit (MCU). The 16-bit parallel digital-to-analog converter (DAC), together with the first operational amplifier B and the second operational amplifier C, forms a two-quadrant unipolar output DAC to realize voltage output between 0V and VREF.

[0078] The first operational amplifier B and the second operational amplifier C convert the output of the 16-bit parallel digital-to-analog converter (DAC) from current to voltage;

[0079] The output of the 16-bit parallel digital-to-analog converter (DAC) is output to the signal input terminal of the variable temperature voltage chip after passing through a composite emitter follower consisting of the third operational amplifier D and the fourth operational amplifier E and a current-limiting resistor F.

[0080] The program written in the microcontroller unit (MCU) uses the timer in the MCU to control the output of the aging training circuit to set the timing voltage waveform, thereby controlling the rise and fall of the internal temperature of the variable constant temperature voltage chip, and completing the stress elimination and accelerated aging process.

[0081] With the cooperation of the above circuits and software, it is possible to Figure 3The circuit outputs a modulated voltage of 0.152V to 0.992V at point A, and its output resolution can reach up to 0.0002V.

[0082] like Figure 4 As shown, the specific timing voltage waveform is as follows:

[0083] The voltage gradually decreases from the highest value in the set range through multiple steps to the lowest value. The voltage decrease is equal between each step, and the voltage is maintained at the lowest value for a set time. Finally, following the order of the decreasing steps, the voltage value changes back and forth between the highest value and each step until it passes through all the steps from low to high.

[0084] The preceding description is intended only as a reference and guide, outlining the basic principles and simplifying some technical details. Other analog or digital control circuits may also achieve similar functionality. This modulation circuit can function as a standalone circuit, independent of the original high-precision variable temperature constant voltage chip assembly, used to age the chip. After aging, it can be separated from the high-precision variable temperature constant voltage chip assembly.

[0085] (5) The externally applied voltage ultimately acts on Figure 1 V on medium temperature sensing transistor 3 be Voltage.

[0086] To achieve the temperature and duration required for aging training, it is necessary to... Figure 1 The first voltage divider resistor 8 and the second voltage divider resistor 9 are connected in the circuit. Figure 2 Waveform diagram. (e.g.) Figure 2 As shown, the entire aging training is divided into three stages. The first stage is mainly to eliminate the mechanical stress of the chip and circuit board, which corresponds to 21 cycles of slow heating. The second stage is mainly to eliminate the thermal stress of the chip, which needs to be maintained for 168 hours. After the second stage, the chip has basically completed the off-domain aging and entered the quantitative stability stage. The third stage is to allow the chip to cool down slowly and return to normal room temperature. In order to prevent the cooling process from generating new stress, a treatment method similar to the metal demagnetization process is adopted during the cooling process, and the chip temperature is gradually reduced periodically to avoid generating new stress during the cooling process.

[0087] The waveform diagram includes the following steps:

[0088] (1) At the start of aging training, an external electronic circuit and a high-precision variable thermostatic voltage chip are powered on. The internal temperature of the high-precision variable thermostatic voltage chip is room temperature. At this time, an external circuit is applied to the chip. Figure 1 The voltage across the temperature sensing transistor 3 is V. be+120mV; At this point, the internal temperature of the high-precision variable constant temperature voltage chip remains at room temperature, and this state is maintained for 60s.

[0089] (2) to be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +110mV. At this point, the internal temperature of the chip rises to approximately room temperature +5°C, and this state is maintained for 60 seconds.

[0090] (3) to be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +100mV. At this point, the internal temperature of the chip rises to approximately room temperature +10°C, and this state is maintained for 60 seconds.

[0091] (4) to be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be At +90mV, the internal temperature of the chip rises to approximately room temperature +15°C, and this state is maintained for 60 seconds.

[0092] (5) to be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be At +80mV, the internal temperature of the chip rises to approximately room temperature +20°C, and this state is maintained for 60 seconds.

[0093] (6) to be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be At +70mV, the internal temperature of the chip rises to approximately room temperature +25℃, and this state is maintained for 60 seconds.

[0094] (7) to be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be At +60mV, the internal temperature of the chip rises to approximately room temperature +30℃, and this state is maintained for 60 seconds.

[0095] (8) to be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be At +50mV, the internal temperature of the chip rises to approximately room temperature +35℃, and this state is maintained for 60 seconds.

[0096] (9) to be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +40mV. At this point, the internal temperature of the chip rises to approximately room temperature +40℃, and this state is maintained for 60 seconds.

[0097] (10) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V beAt +30mV, the internal temperature of the chip rises to approximately room temperature +45℃, and this state is maintained for 60 seconds.

[0098] (11) to be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be At +20mV, the internal temperature of the chip rises to approximately room temperature +50℃, and this state is maintained for 60 seconds.

[0099] (12) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +10mV, at which point the internal temperature of the chip rises to approximately room temperature +55℃, and this state is maintained for 60 seconds.

[0100] (13) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be At this point, the internal temperature of the chip rises to approximately room temperature + 60°C, and this state is maintained for 60 seconds.

[0101] (14) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be -10mV. At this point, the internal temperature of the chip rises to approximately room temperature +65℃, and this state is maintained for 60 seconds.

[0102] (15) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be -20mV. At this point, the internal temperature of the chip rises to approximately room temperature +70°C, and this state is maintained for 60 seconds.

[0103] (16) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be -30mV. At this point, the internal temperature of the chip rises to approximately room temperature +75℃, and this state is maintained for 60 seconds.

[0104] (17) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be -40mV. At this point, the internal temperature of the chip rises to approximately room temperature +80℃, and this state is maintained for 60 seconds.

[0105] (18) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be -50mV. At this point, the internal temperature of the chip rises to approximately room temperature +85℃, and this state is maintained for 60 seconds.

[0106] (19) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be-60mV. At this point, the internal temperature of the chip rises to approximately room temperature +90℃, and this state is maintained for 60 seconds.

[0107] (20) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be -70mV. At this point, the internal temperature of the chip rises to approximately room temperature +95℃, and this state is maintained for 60 seconds.

[0108] (21) to be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be -80mV. At this point, the internal temperature of the chip rises to approximately room temperature +100℃, and this state is maintained for 60 seconds.

[0109] (22) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be -90mV. At this point, the internal temperature of the chip rises to approximately room temperature +105℃, and this state is maintained for 168 hours.

[0110] (23) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0111] (24) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be -80mV. At this point, the internal temperature of the chip rises to approximately room temperature +100℃, and this state is maintained for 300s.

[0112] (25) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0113] (26) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be -70mV. At this point, the internal temperature of the chip rises to approximately room temperature +95℃, and this state is maintained for 300s.

[0114] (27) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0115] (28) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be-60mV. At this point, the internal temperature of the chip rises to approximately room temperature +90℃, and this state is maintained for 300s.

[0116] (29) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0117] (30) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be -50mV. At this point, the internal temperature of the chip rises to approximately room temperature +85℃, and this state is maintained for 300s.

[0118] (31) to be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0119] (32) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be -40mV. At this point, the internal temperature of the chip rises to approximately room temperature +80℃, and this state is maintained for 300s.

[0120] (33) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0121] (34) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be -30mV. At this point, the internal temperature of the chip rises to approximately room temperature +75℃, and this state is maintained for 300s.

[0122] (35) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0123] (36) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be -20mV. At this point, the internal temperature of the chip rises to approximately room temperature +70°C, and this state is maintained for 300 seconds.

[0124] (37) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be+120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0125] (38) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be -10mV. At this point, the internal temperature of the chip rises to approximately room temperature +65℃, and this state is maintained for 300s.

[0126] (39) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0127] (40) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be At this point, the internal temperature of the chip rises to approximately room temperature + 60°C, and this state is maintained for 300 seconds.

[0128] (41) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0129] (42) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +10mV, at which point the internal temperature of the chip rises to approximately room temperature +55℃, and this state is maintained for 300s.

[0130] (43) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0131] (44) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be At +20mV, the internal temperature of the chip rises to approximately room temperature +50℃, and this state is maintained for 300s.

[0132] (45) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0133] (46) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be+30mV, at which point the internal temperature of the chip rises to approximately room temperature +45℃, and this state is maintained for 300s.

[0134] (47) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0135] (48) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +40mV. At this point, the internal temperature of the chip rises to approximately room temperature +40℃, and this state is maintained for 300s.

[0136] (49) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0137] (50) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be At +50mV, the internal temperature of the chip rises to approximately room temperature +35℃, and this state is maintained for 300s.

[0138] (51) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0139] (52) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be At +60mV, the internal temperature of the chip rises to approximately room temperature +30℃, and this state is maintained for 300s.

[0140] (53) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0141] (54) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be At +70mV, the internal temperature of the chip rises to approximately room temperature +25℃, and this state is maintained for 300s.

[0142] (55) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be+120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0143] (56) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be At +80mV, the internal temperature of the chip rises to approximately room temperature +20℃, and this state is maintained for 300s.

[0144] (57) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0145] (58) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be At +90mV, the internal temperature of the chip rises to approximately room temperature +15°C, and this state is maintained for 300 seconds.

[0146] (59) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0147] (60) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +100mV, at which point the internal temperature of the chip rises to approximately room temperature +10℃, and this state is maintained for 300s.

[0148] (61) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0149] (62) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +110mV. At this point, the internal temperature of the chip rises to approximately room temperature +5°C, and this state is maintained for 300 seconds.

[0150] (63) will be applied to Figure 1 The voltage across temperature sensing transistor 3 in the middle is V be +120mV, at which point the internal temperature of the chip drops to approximately room temperature, and this state is maintained for 300 seconds.

[0151] Compared with existing technologies, the advantages of this invention are that it can effectively shorten the off-domain aging time of chip components and improve the efficiency of screening qualified and stable chip components.

[0152]

[0153]

[0154] Example 2:

[0155] In this embodiment, the same aging training circuit and a similar aging training method as in Embodiment 1 are used. The difference from the aging training method in Embodiment 1 is that the dwell time for each temperature step during the 21 cycles of slow heating in the first stage is extended from 60s to 120s.

[0156] In this embodiment, the time required for the entire aging process is slightly longer, but the aging effect remains consistent.

[0157] Example 3:

[0158] In this embodiment, the same aging training circuit and similar aging training method as in Embodiment 1 are used. The difference from the aging training method in Embodiment 1 is that the dwell time of each temperature step in the 21-cycle slow cooling process of the third stage is shortened from 300s to 240s (that is, the holding time of waveform steps (23) to (63) in Embodiment 1 is shortened to 240s).

[0159] In this embodiment, the time required for the entire aging process is shortened, while the aging effect remains basically the same. However, due to the shortened maintenance time, the temperature stability of the LTZ1000A reference voltage standard component, which has an internal heat-insulating substrate and good external heat insulation, may be affected. There is a risk that the internal temperature of the chip may not be fully stable before entering the next temperature step.

[0160] The above descriptions are merely some embodiments of the present invention. Those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. A method for aging training of a high-precision variable constant-temperature voltage chip assembly, characterized in that, Includes the following steps: S1. The temperature of the variable thermostatic voltage chip is gradually increased from room temperature, passing through multiple steps before reaching the maximum temperature; wherein, the temperature of the variable thermostatic voltage chip gradually increases from room temperature, passing through n steps before reaching the maximum temperature. T max The temperature rises between each step to T The duration of temperature change of the variable thermostatic voltage chip at each step is t; S2. Control the temperature of the variable constant temperature voltage chip to maintain the highest temperature for a period of time, so that the variable constant temperature voltage chip is annealed at high temperature, and the internal temperature of the chip is maintained at a specific high temperature for a certain period of time to achieve the purpose of chip aging. S3. Based on the multiple steps experienced in step S1, the temperature of the variable constant temperature voltage chip is controlled to gradually decrease to room temperature by changing back and forth between room temperature and a certain value above room temperature, so as to avoid generating new thermal stress during the cooling process. In step S3, based on the n steps experienced in step S1, the temperature reduction process of the variable constant temperature voltage chip includes n stages, as detailed below: In the first stage, the temperature of the variable temperature voltage chip is reduced from the highest temperature. T max The temperature is lowered to room temperature and maintained for a period of time, then the temperature of the variable thermostatic voltage chip is raised from room temperature to the (n-1)th step temperature and maintained for a period of time. In the second stage, the temperature of the variable thermostatic voltage chip drops from the temperature of the (n-1)th step to room temperature and is maintained for a period of time. Then, the temperature of the variable thermostatic voltage chip rises from room temperature to the temperature of the (n-2)th step and is maintained for a period of time. Similarly, in the (n-1)th stage, the temperature of the variable thermostatic voltage chip drops from the temperature of the second step to room temperature and is maintained for a period of time, and then the temperature of the variable thermostatic voltage chip rises from room temperature to the temperature of the first step and is maintained for a period of time. In the nth stage, the temperature of the variable constant temperature voltage chip drops from the temperature of the first step to room temperature; By applying a voltage set by the variable thermostatic voltage chip, the heating power of the variable thermostatic voltage chip is controlled, thereby controlling the temperature of the variable thermostatic voltage chip and the duration of the variable thermostatic voltage chip at that temperature.

2. An aging training circuit for a high-precision variable constant-temperature voltage chip assembly, used to implement the aging training method as described in claim 1, characterized in that, It includes a microcontroller unit (MCU), a parallel digital-to-analog converter (DAC), a voltage reference standard, and four operational amplifier units; The data port and signal control pin of the parallel digital-to-analog converter (DAC) are connected to the I / O ports of the microcontroller unit (MCU); The analog voltage value output by the parallel digital-to-analog converter (DAC) is written to the parallel port of the parallel digital-to-analog converter (DAC) by the program in the microcontroller unit (MCU). The parallel digital-to-analog converter (DAC), together with the first operational amplifier B and the second operational amplifier C, forms a two-quadrant unipolar output DAC to realize the voltage output between 0V and VREF. The first operational amplifier B and the second operational amplifier C convert the output of the parallel digital-to-analog converter (DAC) from current to voltage; The output of the parallel digital-to-analog converter (DAC) is output to the signal input terminal of the variable temperature voltage chip after passing through a composite emitter follower composed of the third operational amplifier D and the fourth operational amplifier E and a current-limiting resistor F. This controls the voltage of the base of the temperature sensing transistor in the variable temperature voltage chip, thereby controlling the internal temperature of the variable temperature voltage chip and realizing the aging training of the variable temperature voltage chip assembly. A 16-bit parallel digital-to-analog converter (DAC) is used. The voltage output pin of the voltage reference standard is connected to the R1 pin of the 16-bit parallel digital-to-analog converter (DAC), and the R1 pin of the 16-bit parallel digital-to-analog converter (DAC) is connected to ground along with a bypass capacitor. The inverting input of the first operational amplifier B is connected to R of the 16-bit parallel digital-to-analog converter (DAC). COM The pins are connected, the non-inverting input of the first operational amplifier B is connected to ground, and the output of the first operational amplifier B is connected to the REF pin of the 16-bit parallel digital-to-analog converter (DAC). The inverting input of the second operational amplifier C is connected to the I of the 16-bit parallel digital-to-analog converter (DAC). OUT1 The pins are connected, and the non-inverting input of the second operational amplifier C is connected to the AGND and DGND pins of the 16-bit parallel digital-to-analog converter (DAC) and then grounded. The output of the second operational amplifier C is connected to the R... OFS Pins and R FB The pins are connected, and a filter capacitor is connected between the output terminal of the second operational amplifier C and the inverting input terminal of the second operational amplifier C. The output of the second operational amplifier C is connected to the non-inverting input of the third operational amplifier D. The output of the third operational amplifier D is connected to the input of the fourth operational amplifier E. The output of the fourth operational amplifier E is connected in series with a 10kΩ resistor and then connected to the inverting input of the third operational amplifier D. A filter capacitor is connected between the output of the third operational amplifier D and its inverting input. The output of the fourth operational amplifier E is connected in series with a current-limiting resistor F and externally connected to the signal input of the variable temperature voltage chip. This controls the voltage at the base of the temperature sensing transistor in the variable temperature voltage chip, thereby controlling the internal temperature of the variable temperature voltage chip and realizing the aging training of the variable temperature voltage chip assembly. VREF is provided with a standard voltage by a voltage standard, which uses a 10V bandgap standard voltage chip; the fourth operational amplifier E is used to improve the driving capability of the operational amplifier, using a power buffer LT1010; the current-limiting resistor F is used to limit the voltage at the signal input terminal of the variable temperature voltage chip to V. be -90mV~V be Within the range of +120mV; The program written in the microcontroller unit (MCU) uses the timer in the MCU to control the output of the aging training circuit to set the timing voltage waveform, thereby controlling the rise and fall of the internal temperature of the variable constant temperature voltage chip, and completing the stress elimination and accelerated aging process. The specific timing voltage waveform is as follows: The voltage gradually decreases from the highest value in the set range through multiple steps to the lowest value. The voltage decrease is equal between each step, and the voltage is maintained at the lowest value for a set time. Finally, following the order of the decreasing steps, the voltage value changes back and forth between the highest value and each step until it passes through all the steps from low to high.

3. The aging training circuit for a high-precision variable constant-temperature voltage chip assembly according to claim 2, characterized in that: The program written in the microcontroller unit (MCU) uses the timer in the MCU to control the output of the aging training circuit to set the timing voltage waveform, thereby controlling the rise and fall of the internal temperature of the variable constant temperature voltage chip, and completing the stress elimination and accelerated aging process.

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