Integrated circuits and methods

Abstract

The present invention discloses a method for integrated circuit, comprising: providing a non-volatile memory circuit to cryptographically, permanently record and protect a key data content having Y bits; providing a programmable memory circuit to store a user configuration data content having X bits which is greater than Y bits; converting the user configuration data content having X bits to a user configuration key content having Y bits; comparing the user configuration key content having Y bits with the key data content having Y bits; selecting a fallback configuration data content having X bits as an output data when the contents do not match; selecting the user configuration data content having X bits as the output data when the contents match; and performing a corresponding capability operation according to the output data. The present invention also discloses an integrated circuit. The present invention can effectively reduce the time for assembly, testing and manufacturing, and the overall cost for manufacturing the circuit device.

Description

Technical Field

[0001] This application relates to a mechanism of an integrated circuit, and more particularly to an integrated circuit and a corresponding method. Background Technology

[0002] Generally, existing one-time programmable memories (electronic fuses) are implemented with multiple physical one-time programmable bits (or configuration bits), each storing exactly one capability bit of information. However, this necessitates the use of larger circuitry for implementation. Summary of the Invention

[0003] Therefore, one of the purposes of this application is to disclose an integrated circuit to solve the aforementioned problems.

[0004] According to an embodiment of this application, an integrated circuit is disclosed. The integrated circuit includes a non-volatile memory circuit, a programmable memory circuit, a decision circuit, and a processing circuit. The non-volatile memory circuit is used to cryptographically and permanently record and protect key data content having Y bits. The programmable memory circuit is used to store user configuration data content having X bits, where the number of X bits is greater than the number of Y bits. The decision circuit is coupled to the non-volatile memory circuit and the programmable memory circuit, and is used to: receive the key data content having Y bits and the user configuration data content having X bits; convert the user configuration data content having X bits into user configuration key content having Y bits; compare the user configuration key content having Y bits with the key data content having Y bits; when the user configuration key content does not match the key data content, select fallback configuration data content having X bits as output data; and when the user configuration key content matches the key data content, select the user configuration data content having X bits as the output data. The processing circuit is coupled to the decision circuit and is used to receive the output data of the decision circuit and to perform corresponding capability operations based on the output data.

[0005] According to an embodiment of this application, a method for integrating an integrated circuit is disclosed. The method includes: providing and using a non-volatile memory circuit to cryptographically and permanently record and protect key data content having Y bits; providing and using a programmable memory circuit to store user configuration data content having X bits, which is greater than Y bits; converting the user configuration data content having X bits into user configuration key content having Y bits; comparing the user configuration key content having Y bits with the key data content having Y bits; when the user configuration key content does not match the key data content, selecting fallback configuration data content having X bits as output data; when the user configuration key content matches the key data content, selecting the user configuration data content having X bits as the output data; and receiving the output data and performing corresponding capability operations based on the output data. Attached Figure Description

[0006] Figure 1 This is a block diagram of an integrated circuit according to an embodiment of this application.

[0007] Figure 2 According to an embodiment of this application Figure 1 The diagram shows a flowchart of the method for integrating an integrated circuit.

[0008] The reference numerals in the attached figures are explained as follows:

[0009] 100 Integrated Circuits

[0010] 105 Non-volatile memory circuit

[0011] 110 Programmable Memory Circuit

[0012] 115 Decision Circuit

[0013] 120 processing circuit

[0014] 125 Data Compression Circuit

[0015] 130 comparator circuit

[0016] 135 Rollback Mechanism Block Detailed Implementation

[0017] This application aims to disclose a technical solution and circuit device that can effectively provide multiple identical or similar configurations for multiple operations / functions of multiple functional blocks or circuits included in the circuit device by using fewer configuration bits, data slagging / encoding operations, and data comparison operations. This minimizes the circuit area of ​​a non-volatile memory circuit (e.g., an array of one-time programmable memories (E-Fuse)) while retaining or maintaining the identical or similar configurations for the operations / functions of the functional blocks or circuits. Furthermore, the disclosed technical solution and circuit device can increase the space of the entire addressable memory used to store information in the E-Fuse array and / or reduce the silicon area used by the E-Fuse array, thus effectively reducing assembly, testing, and manufacturing time and the overall cost of manufacturing the circuit device (e.g., a circuit chip).

[0018] One-time programmable memory (E-Fuse) is a component in modern integrated circuit design used to store multiple configuration bits that collectively define various operational capabilities of the end product. Within the E-Fuse block, each system capability is assigned a dedicated bit. For example, multiple system capabilities require multiple bits to represent different supported feature operations. If a particular system has many operational capabilities, then more bits need to be implemented in the E-Fuse within the silicon region. As the array size of the E-Fuse increases and the added silicon region is affected, it negatively impacts E-Fuse programming and verification operations during chip manufacturing. Therefore, when designing the appropriate size of the E-Fuse array during the chip design phase, a compromise must typically be reached between manufacturing costs and the market flexibility of configuring multiple SKUs.

[0019] To overcome the aforementioned problems, the disclosed technical solution and circuit arrangement enable a larger number of post-fabrication system capabilities to be independently configured, requiring only a relatively small E-Fuse array to be implemented on the chip. Thus, the one-time programmable bit of each entity used in the disclosed technical solution and circuit arrangement can effectively store more than one capability bit of information.

[0020] Figure 1 This is a block diagram of an integrated circuit 100, such as an integrated circuit chip or a system-on-a-chip device, according to an embodiment of this application. Figure 1The integrated circuit 100 includes a non-volatile memory circuit 105, a programmable memory circuit 110, a decision circuit 115, and a processing circuit 120. The decision circuit 115 includes a data compression circuit 125, a comparator circuit 130, and a fallback mechanism block 135. The system of the integrated circuit 100 includes multiple functional blocks within the processing circuit 120, and multiple configuration bits are used to provide multiple corresponding configuration settings to these functional blocks, enabling or disabling at least one part of these functional blocks. For example, each configuration bit is initially set to '0', and a configuration bit can be set to '1' according to different needs.

[0021] The non-volatile memory circuit 105 is used to cryptographically and permanently record and protect a key data content of Y bits. The implementation of the non-volatile memory circuit 105 only requires... Figure 1 If the key data content, represented by the signal fuse_key[Y-1:0], has Y bits, can be permanently set by a chip manufacturer and electronically protected from being erased or modified by an unauthorized party, its hardware implementation can include or utilize one or more actual one-time programmable memory arrays, one-time programmable read-only memory (OTP ROM), electrically erasable programmable read-only memory (EEPROM), flash memory, or other technologies. The key data content fuse_key[Y-1:0] is, for example, a compressed or encoded data content generated from the X capability bits of the user configuration data content set by the chip manufacturer. Once set, the key data content fuse_key[Y-1:0] cannot be modified by the user.

[0022] The programmable memory circuit 110 is used to store a user configuration data content with X bits, where the number of X bits is greater than the number of Y bits. The programmable memory circuit 110 can be implemented by including or using a user-programmable memory, a set of multiple flip-flops, a set of multiple latches, a register file, a static random access memory (SRAM), or a dynamic random access memory (DRAM), provided that the programmable memory circuit 110 is user-programmable and the programmed value can be accessed by multiple other logic blocks of the system. The programmed value, i.e., the X capability bits of the user configuration data content, is represented by the signal user_config[X-1:0]. The programmed value will be transmitted to two functional blocks, namely the data compression circuit 125 and the fallback mechanism block 135 in the decision circuit 115.

[0023] The decision circuit 115 is coupled to the non-volatile memory circuit 105 and the programmable memory circuit 110. It receives the key data content fuse_key[Y-1:0] with Y bits, receives the user configuration data content user_config[X-1:0] with X bits, converts the user configuration data content user_config[X-1:0] with X bits into a user configuration key content user_key[Y-1:0] with Y bits, and compares the user configuration key content user_key[Y-1:0] with the data content user_key[Y-1:0] with Y bits. The key data content fuse_key[Y-1:0] is selected as output data when the user configuration key content user_key[Y-1:0] does not match the key data content fuse_key[Y-1:0], and when the user configuration key content user_key[Y-1:0] matches the key data content fuse_key[Y-1:0], the user configuration key content user_key[Y-1:0] is selected as output data.

[0024] In other words, the decision circuit 115 is used to generate a larger number of result configuration bits for the functional blocks based on a smaller number of initial configuration bits stored in the non-volatile memory circuit 105 and information stored in the user-programmable memory circuit 110. This allows the circuit area occupied by the non-volatile memory circuit 105 to be reduced or minimized, while increasing the storage space of the user-programmable memory circuit 110.

[0025] In practice, the data compression circuit 125 is, for example, a compression / encoder logic (or circuit) that can employ various operations or algorithms, such as Hamming codes, checksums, cyclic redundancy check (CRC), hash algorithms, and other data compression algorithms. These algorithms can process a large amount of data to generate or create a smaller amount of data / key / signature. For example, the Hamming code operation can be used to generate a 6-bit parity signature from a 26-bit input and an 8-bit parity signature from a 120-bit input, effectively reducing the size requirement of the E-Fuse array, for example, by 77% and 93% respectively; however, this is not a limitation of this application. Figure 1As shown, the data compression circuit 125 performs a data compression / encoding operation on the X bits of user_config[X-1:0] of the user configuration data content stored in the programmable memory circuit 110, compressing the X bits of user configuration data content to produce the user configuration key content (i.e., the signal user_key[Y-1:0]) with fewer than X bits.

[0026] Next, the comparator circuit 130 receives the bits of the signal user_key[Y-1:0] from the data compression circuit 125, receives the bits of the signal fuse_key[Y-1:0] from the non-volatile memory circuit 105, compares the bits / values ​​of the signal user_key[Y-1:0] with the bits / values ​​of the signal fuse_key[Y-1:0] to generate a comparison signal, and reports the information of the comparison signal to the fallback mechanism block 135, wherein the comparison signal indicates whether the information of the signal user_key[Y-1:0] matches the information of the signal fuse_key[Y-1:0]. If the bits / values ​​of the signal user_key[Y-1:0] match the bits / values ​​of the signal fuse_key[Y-1:0], that is, the user configuration matches the configuration set by the chip manufacturer for the integrated circuit 110, then the content of the report signal transmitted from the comparator circuit 130 to the multiplexer MUX can be set to '1', and the multiplexer MUX will select the signal user_config[X-1:0] as its output signal based on the bit '1' of the report signal. Conversely, if the bit / value of the signal user_key[Y-1:0] does not match the bit / value of the signal fuse_key[Y-1:0], that is, if the user configuration does not match the expected configuration set by the chip manufacturer, the content of the report signal transmitted from the comparator circuit 130 to the multiplexer MUX will be set to '0', and the multiplexer MUX will select a fallback configuration signal with X bits (represented by the signal fallback_config[X-1:0]) as its output based on the bit '0' of the report signal.

[0027] Figure 1The fallback mechanism block 135 shown includes the multiplexer MUX, which can be implemented by an array of multiple multiplexers. In this embodiment, the fallback configuration signal has X bits represented by the signal fallback_config[X-1:0], for example, an interleaved configuration pattern signal set by the chip manufacturer. It can be used to prevent the system from operating, partially disable or malfunction multiple system capabilities, enter a specific operating mode to notify the user of mismatch information, or allow the user to troubleshoot and correct specific problems. That is, when the fallback configuration data fallback_config[X-1:0] is received by the processing circuit 120, the processing circuit 120 can perform at least one of the following operations: prevent the system from operating, partially disable or malfunction multiple system capabilities, enter a specific operating mode to notify the user of mismatch information, or allow the user to troubleshoot and correct specific problems. Once the problem has been corrected, the final configuration signal, consisting of X bits (represented by the signal final_config[X-1:0]), is generated from the output of the multiplexer MUX and output to the processing circuit 120. If the return signal bit is '1', the final configuration signal is selected from the signal user_config[X-1:0]. In this case, the full operational capabilities defined / specified by the chip manufacturer become available for the functional blocks contained in the processing circuit 120.

[0028] The processing circuit 120 is coupled to the decision circuit 115 and is used to receive the output data (i.e., the signal final_config[X-1:0]) of the decision circuit 115 and to perform at least one corresponding capability operation based on the output data. For example, one or more functional blocks included in the processing circuit 120 may perform one or more corresponding functions and operations based on the configuration information indicated by the multiple configuration bits carried by the signal final_config[X-1:0].

[0029] By doing so, the disclosed integrated circuit, employing data compression and comparison operations and storing configuration / entity bits in one or more E-Fuse arrays, can effectively achieve multiple operational capabilities of the corresponding functional blocks with more configuration / entity bits. This significantly reduces the circuit silicon area of ​​one or more E-Fuse arrays.

[0030] Furthermore, the number X, the number Y, and the relationship between X and Y can be determined by the type of data compression or encoding algorithm used by the system according to integrated circuit 100, or it can be a specific data compression or encoding algorithm used. For example, the number X can be designed to be larger than the number Y to provide more practical technical advantages.

[0031] Furthermore, it should be noted that in other embodiments, Figure 1 The integrated circuit 100 shown can be synthesized as a netlist circuit or implemented as an application-specific integrated circuit (ASIC). In one embodiment, the integrated circuit 100 can be emulated by a programmable hardware circuit. Furthermore, in one embodiment, the integrated circuit 100 can be implemented using multiple discrete, independent hardware components. Still further, in one embodiment, portions of the integrated circuit 100 are implemented using multiple software components.

[0032] To make the process of this application clearer to readers, the following information has been disclosed. Figure 2 . Figure 2 According to an embodiment of this application Figure 1 The flowchart illustrates the method of the integrated circuit 100 shown. Detailed explanations of the steps are as follows:

[0033] Step S200: Begin;

[0034] Step S205: Receive a key data content with Y bits stored in a non-volatile memory circuit, wherein the non-volatile memory circuit securely and permanently records and protects the key data content with Y bits.

[0035] Step S210: Receive a user configuration data content with X bits from a programmable memory circuit, where the number of X bits is greater than the number of Y bits;

[0036] Step S215: Compress or encode the user configuration data content having X bits to generate a user configuration key content having Y bits, which is less than the X bits;

[0037] Step S220: Compare the user configuration key content with Y bits with the key data content with Y bits to determine if the contents match; if the contents do not match, proceed to step S225, otherwise proceed to step S230.

[0038] Step S225: Select a rollback configuration data content with X bits as the output data;

[0039] Step S230: Select the user configuration data content with X bits as the output data;

[0040] Step S235: Perform at least one corresponding capability operation based on the output data; and

[0041] Step S240: End.

[0042] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An integrated circuit, characterized in that, Include: A non-volatile memory circuit is used to cryptographically and permanently record and protect key data content with Y bits; A programmable memory circuit is used to store user configuration data with X bits, where the number of X bits is greater than the number of Y bits. A decision circuit, coupled to the non-volatile memory circuit and the programmable memory circuit, is used to: Receive the key data content with Y bits and the user configuration data content with X bits; Convert the user configuration data content with X bits into user configuration key content with Y bits; Compare the user configuration key content with Y bits to the key data content with Y bits; When the user's configured key content does not match the key data content, select the fallback configuration data content with X bits as the output data; as well as When the user's configured key content matches the key data content, select the user's configured data content with X bits as the output data; as well as A processing circuit, coupled to the decision circuit, is used to receive the output data of the decision circuit and to perform corresponding capability operations based on the output data.

2. The integrated circuit as described in claim 1, characterized in that, The decision circuit includes: A data compression circuit is used to compress the user configuration data content with X bits to produce the user configuration key content with Y bits, which is less than X bits. A comparator circuit, coupled to the data compression circuit, is used to compare the user configuration key content with Y bits and the key data content with Y bits to generate a comparison signal. as well as A multiplexer, coupled to the programmable memory circuit and the comparator circuit, is used to: When the comparison signal indicates that the user-configured key content does not match the key data content, the rollback configuration data content with X bits is selected as the output data of the decision circuit; and When the comparison signal indicates that the user-configured key content matches the key data content, the user-configured data content with X bits is selected as the output data.

3. The integrated circuit as described in claim 2, characterized in that, The data compression circuit employs Hamming code operations, checksum operations, cyclic redundancy check operations, or hash algorithms.

4. The integrated circuit as described in claim 1, characterized in that, When the rollback configuration data is received, the corresponding capability operation performed by the processing circuit includes at least one of the following operations: denying the system from operating, causing partial or no functionality of multiple system capabilities, entering a specific operating mode to notify the user of mismatch information, or allowing the user to troubleshoot and fix specific problems.

5. The integrated circuit as described in claim 4, characterized in that, After the specific problem is corrected, the decision circuit will select the user configuration data content with X bits as the output data.

6. The integrated circuit as claimed in claim 1, characterized in that, The integrated circuit is either synthesized as a netlist circuit or implemented as an application-specific integrated circuit (ASIC).

7. The integrated circuit as claimed in claim 1, characterized in that, The integrated circuit is simulated using programmable hardware circuits.

8. The integrated circuit as claimed in claim 1, characterized in that, This integrated circuit is implemented using multiple discrete and independent hardware components.

9. The integrated circuit as claimed in claim 1, characterized in that, Part of this integrated circuit is implemented using multiple software components.

10. The integrated circuit as claimed in claim 1, characterized in that, The non-volatile memory circuit includes a read-only memory that can only be programmed once, an electrically erasable programmable read-only memory, or flash memory.

11. The integrated circuit as claimed in claim 1, characterized in that, The programmable memory circuit includes a set of multiple flip-flops, a set of multiple latches, a register file, static random access memory, or dynamic random access memory.

12. A method for integrating an integrated circuit, characterized in that, Include: Provides and uses non-volatile memory circuitry to cryptographically and permanently record and protect key data content with Y bits; Provides and uses programmable memory circuitry to store user configuration data content of X bits with more than Y bits; Convert the user configuration data content with X bits into user configuration key content with Y bits; Compare the user configuration key content with Y bits to the key data content with Y bits; When the user's configured key content does not match the key data content, select the fallback configuration data content with X bits as the output data; as well as When the user's configured key content matches the key data content, select the user's configured data content with X bits as the output data; as well as Receive the output data and perform the corresponding capability operations based on the output data.

13. The method as described in claim 12, characterized in that, The steps to convert the user configuration data content with X bits into the user configuration key content with Y bits include: The user configuration data content, consisting of X bits, is compressed to produce the user configuration key content, consisting of Y bits, which is less than X bits; and The steps for comparing the user configuration key content with the key data content with Y bits include: A comparator circuit is used to compare the Y-bit content of the user configuration key with the Y-bit content of the key data to generate a comparison signal.

14. The method as described in claim 13, characterized in that, The steps to compress the user configuration data content with X bits are to use Hamming code operation, checksum operation, cyclic redundancy check operation or hash algorithm.

15. The method as described in claim 12, characterized in that, When the rollback configuration data is received, the method further includes at least one of the following operations: refusing system operation, partially disabling or malfunctioning multiple system capabilities, entering a specific operating mode to notify the user of mismatch information, or allowing the user to troubleshoot and fix specific problems.

16. The method as described in claim 15, characterized in that, The method also includes: After the specific issue is fixed, the user configuration data content with X bits is selected as the output data.

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