A method for improving cache utilization using SIMD instructions

Abstract

The application provides a method for improving cache utilization using SIMD instructions, a method for quickly solving square root reciprocal using SIMD instructions to improve cache utilization, an SIMD instruction set capable of loading 512-bit data in an integer multiple at a time, using at least one register to complete the loading, performing the same operation on 512-bit data at a time during calculation, and subtracting the result of directly logically right shifting 1 bit of the data in the register from the hexadecimal magic number 0x5f3759df to obtain the first approximation value of the square root reciprocal of the input floating point number; then reusing the first approximation value as a floating point number to repeatedly iterate by using the Newton iteration method until the approximate value meeting the matching accuracy requirement is obtained and stored in the register, and finally storing the data in the register into the memory. The method can improve cache utilization, load multiple data at a time, reduce the interaction time of hard disk and memory data, greatly improve the operation speed, occupy a small amount of resources, and efficiently operate in the case of limited hardware resources.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to a method for improving cache utilization using SIMD instructions. Background Technology

[0002] In existing technologies, vector calculations often require taking the reciprocal of the square root, for example, to normalize the vector. While the square root reciprocal method in the C mathematical function library offers high precision, it may not meet the demands of fast computation. The Fast Inverse Square Root algorithm is a fast algorithm for calculating the reciprocal of the square root (the input data must be a 32-bit single-precision floating-point number conforming to the IEEE 754 standard format). This algorithm improves computational speed while maintaining sufficient precision. This algorithm was initially attributed to John Carmack, but later investigations revealed that it had already been used in computer graphics hardware and software before that. Not only is the original author unknown, but the origin of the special constants used in the algorithm remains unclear; these special constants are known as "magic numbers."

[0003] Furthermore, current fast algorithms for calculating the reciprocal of the square root are generally implemented in C language. This involves first receiving a 32-bit single-precision floating-point number conforming to the IEEE 754 standard format, treating it as a 32-bit integer, then performing a logical right shift and halving the result. The halved result is then subtracted from the hexadecimal "magic number" 0x5f3759df to obtain an initial approximation of the reciprocal of the square root of the input floating-point number. This is then repeated using Newton's method to find a more accurate approximation, until the required precision is achieved. This algorithm is four times faster than direct floating-point division when calculating the approximation of the reciprocal of the square root of a floating-point number with the same precision.

[0004] However, in the process of data processing, C language programming is often used. The quick calculation method for square root reciprocals can only process one data point at a time, which causes cache waste and long data interaction time, resulting in slow calculation speed. It cannot run on some platforms or chips with limited hardware resources. In particular, for many chip manufacturers, different chips are used for different needs. For example, on the chips of Beijing Junzheng Integrated Circuit Co., Ltd. (hereinafter referred to as Beijing Junzheng), using C language will greatly limit the chip speed and cause cache waste.

[0005] The following are commonly used terms in the prior art:

[0006] 1. SIMD stands for Single Instruction Multiple Data, which is a set of instructions that can process multiple operands at once and pack them into a large register.

[0007] 2. The Newton-Raphson method, also known as the Newton-Raphson method, is a method proposed by Newton in the 17th century for approximately solving equations in the real and complex number fields.

[0008] Let r be a root of f(x) = 0. Choose x0 as the initial approximation of r. Draw a tangent line L to the curve y = f(x) through the point (x0, f(x0)), where L: y = f(x0) + f'(x0)(x - x0). The x-coordinate of the intersection point of L and the x-axis is x1 = x0 - f(x0) / f'(x0), and x1 is called the first-order approximation of r. Draw another tangent line to the curve y = f(x) through the point (x1, f(x1)), and find the x-coordinate of the intersection point of this tangent line and the x-axis, x2 = x1 - f(x1) / f'(x1), and x2 is called the second-order approximation of r. Repeat the above process to obtain a sequence of approximations of r, where x(n+1) = xn - f(xn) / f'(xn), called the (n+1)th order approximation of r. This formula is called Newton's iteration formula. Summary of the Invention

[0009] To address the aforementioned issues, this method aims to achieve rapid calculation of the reciprocal of the square root using SIMD instructions. This improves cache utilization, allows for the loading of multiple data sets at once, reduces the interaction time between hard disk and memory data, thereby significantly increasing computational speed while consuming minimal resources and enabling efficient operation even with limited hardware resources.

[0010] Specifically, this invention provides a method for improving cache utilization using SIMD instructions. The method uses SIMD instructions to quickly calculate the reciprocal of the square root to improve cache utilization. The SIMD instruction set used can load bits of data that are multiples of 512 at a time, using at least one register to complete the loading. During calculation, the same operation is performed on 512 bits of data at a time. The result of a direct logical right shift of the data in the register is subtracted from the hexadecimal magic number 0x5f3759df to obtain the first approximation of the reciprocal of the square root of the input floating-point number. This is then treated as a floating-point number and iterated repeatedly using Newton's method until an approximation matching the required accuracy is obtained and stored in a register. Finally, the data in the register is stored in memory.

[0011] There are a total of 32 registers that have been loaded and can be reused.

[0012] The SIMD instruction set includes arithmetic operations such as addition, subtraction, multiplication, taking absolute value, maximum value, and minimum value; logical operations such as AND, OR, NOT, XOR, and shift; and comparison operations such as less than, equal to, and less than or equal to. Complex calculation requirements are achieved by combining multiple instructions.

[0013] The method includes the following steps:

[0014] S1. Data is loaded in multiples of 32 bits, with a maximum of 512 bits of data loaded into one register;

[0015] Register 1, denoted as Register1, is used to store the calculation results;

[0016] Using a single SIMD instruction to load data, it can be represented as:

[0017] Register1=Ingenic_simd512_load((float)data),

[0018] Where (float)data is the input of 16 32-bit single-precision floating-point numbers;

[0019] S2. Perform a direct logical right shift of 1 bit on the data in Register1.

[0020] Using a single SIMD instruction that logically shifts right by 1 bit, it can be represented as:

[0021] Register2 = Ingenic_simd512_logical_shift_right_1_bit(Register1) Register1 is the operand. The 16 32-bit single-precision floating-point numbers in Register1 are simultaneously logically shifted right by 1 bit, and the result is stored in register2, which is represented as Register2.

[0022] S3. Subtract the result of step S2 from the 32-bit hexadecimal magic number 0x5f3759df to obtain the first approximation of the reciprocal of the square root.

[0023] Using a single SIMD instruction to load an immediate value, it can be represented as:

[0024] Register3=Ingenic_simd512_load_immediate(0x5f3759df),

[0025] Load 0x5f3759df into Register3. This instruction can copy a 32-bit data into 16 32-bit data and load them into a 512-bit register.

[0026] Using a single SIMD instruction for integer subtraction, it can be represented as:

[0027] Register2=Ingenic_simd512_int_sub(Register3,Register2),

[0028] Subtract the 16 32-bit data in Register3 from the result of step S2. This instruction can perform 16 subtraction operations at the same time. Since both operands of the subtraction are integers, the integer subtraction instruction is used. The result of the subtraction is still stored in Register2.

[0029] S4. Use a single SIMD instruction for floating-point multiplication, that is, multiply the 16 floating-point numbers in Register1 with the corresponding 16 floating-point numbers in Register3, as follows:

[0030] Register4=Ingenic_simd512_float_mul(Register1, Register3),

[0031] To multiply the data in Register1 by the floating-point number 0.5, 0.5 needs to be loaded into Register3 first. Since 0.5 is a floating-point number, the immediate load instruction cannot be used; only a normal load instruction can be used, represented as:

[0032] Register3=Ingenic_simd512_load(0.5),

[0033] After loading a 0.5, a repeat instruction is used to copy the data, represented as: Register3 = Ingenic_simd512_repeat(Register3),

[0034] Copy the 32-bit floating-point number 0.5 into 16 32-bit floating-point numbers and store them in Register3;

[0035] At this point, both operands of the multiplication instruction are floating-point numbers, so the floating-point multiplication instruction is used, and the result is stored in Register4;

[0036] Then, load the 32-bit floating-point number 1.5 into Register5 using the same method, as follows:

[0037] Register5=Ingenic_simd512_load(1.5),

[0038] Register5=Ingenic_simd512_repeat(Register5);

[0039] The Register4 and Register5 results obtained in this step prepare for the Newton-Raphson iteration method in the following steps;

[0040] S5. Perform the first Newton-Raphson iteration method:

[0041] The SIMD instruction for floating-point multiplication, Ingenic_simd512_float_mul, multiplies the data in Register2 from step S3 with the data in Register2 to obtain the square result. This step involves squaring the 16 32-bit data in Register2, storing the result in Register6, and then multiplying it with the data in Register4, with the result still stored in Register6. Then, the floating-point subtraction instruction is used, that is, the 16 floating-point numbers in Register5 are subtracted from the corresponding 16 floating-point numbers in Register6. This is represented as the Ingenic_simd512_float_sub instruction, which subtracts the data in Register6 from the data in Register5. Since both operands of this instruction are floating-point numbers, the floating-point subtraction instruction is used, and the result is stored in Register6. Finally, the data in Register6 is multiplied with the data in Register2, and the result is stored in Register2.

[0042] The registers here store 16 single-precision floating-point numbers, each 32-bit, and each instruction operates on 16 floating-point numbers simultaneously; represented as:

[0043] Register6=Ingenic_simd512_float_mul(Register2, Register2);

[0044] Register6=Ingenic_simd512_float_mul(Register4, Register6);

[0045] Register6=Ingenic_simd512_float_sub(Register5,Register6);

[0046] Register2=Ingenic_simd512_float_mul(Register2, Register6);

[0047] S6. In order to achieve the accuracy requirements of practical applications, it is necessary to perform n Newton iterations as needed, that is, to repeat step S5 (n-1) times.

[0048] S7. Data from the register is stored in memory in multiples of 32 bits, with a maximum storage capacity of 512 bits, or 16 32-bit single-precision floating-point numbers. *ptr is the memory address, stored using a single SIMD instruction, represented as:

[0049] *ptr=Ingenic_simd512_store(Register2),

[0050] Register2 contains 512 bits of data that need to be stored, which is also the final calculation result.

[0051] Step S6 further includes: enabling three Newton iterations, repeating step S5 twice more, as follows:

[0052] Second Newton iteration:

[0053] Register6=Ingenic_simd512_float_mul(Register2, Register2);

[0054] Register6=Ingenic_simd512_float_mul(Register4, Register6);

[0055] Register6=Ingenic_simd512_float_sub(Register5,Register6);

[0056] Register2=Ingenic_simd512_float_mul(Register2, Register6);

[0057] The third Newton iteration:

[0058] Register6=Ingenic_simd512_float_mul(Register2, Register2);

[0059] Register6=Ingenic_simd512_float_mul(Register4, Register6);

[0060] Register6=Ingenic_simd512_float_sub(Register5,Register6);

[0061] Register2=Ingenic_simd512_float_mul(Register2, Register6).

[0062] Therefore, the advantages of this application are: using the SIMD instruction set, especially the Ingenic_simd512 instruction set in the chip developed by Beijing Junzheng, to optimize and improve the reciprocal square root algorithm, improve cache utilization, consume less resources, and achieve a calculation speed 50 times faster than the C language reciprocal square root algorithm, and can run efficiently on platforms with limited hardware resources. Attached Figure Description

[0063] The accompanying drawings, which are provided to further illustrate the invention and form part of this application, are not intended to limit the scope of the invention.

[0064] Figure 1 This is a flowchart illustrating the method of the present invention.

[0065] Figure 2 This is a diagram of the C language code for a quick algorithm to calculate the reciprocal of the square root. Detailed Implementation

[0066] To better understand the technical content and advantages of the present invention, the present invention will now be described in further detail with reference to the accompanying drawings.

[0067] like Figure 1 As shown, the present invention relates to a method for improving cache utilization using SIMD instructions, the method comprising the following steps:

[0068] S1. Data is loaded in multiples of 32 bits, with a maximum of 512 bits of data loaded into one register;

[0069] Register 1, denoted as Register1, is used to store the calculation results;

[0070] Using a single SIMD instruction to load data, it can be represented as:

[0071] Register1=Ingenic_simd512_load((float)data),

[0072] Where (float)data is the input of 16 32-bit single-precision floating-point numbers;

[0073] S2. Perform a direct logical right shift of 1 bit on the data in Register1.

[0074] Using a single SIMD instruction that logically shifts right by 1 bit, it can be represented as:

[0075] Register2 = Ingenic_simd512_logical_shift_right_1_bit(Register1), where Register1 is the operand. The 16 32-bit single-precision floating-point numbers in Register1 are simultaneously logically shifted right by 1 bit, and the result is stored in register2, which is represented as Register2.

[0076] S3. Subtract the result of step S2 from the 32-bit hexadecimal magic number 0x5f3759df to obtain the first approximation of the reciprocal of the square root. This is represented by a single SIMD instruction that loads an immediate value:

[0077] Register3=Ingenic_simd512_load_immediate(0x5f3759df),

[0078] Load 0x5f3759df into Register3. This instruction can copy a 32-bit data into 16 32-bit data and load them into a 512-bit register.

[0079] Using a single SIMD instruction for integer subtraction, it can be represented as:

[0080] Register2 = Ingenic_simd512_int_sub(Register3,Register2) subtracts the result of step S2 from the 16 32-bit data in Register3. This instruction can perform 16 subtraction operations at the same time. Since both operands of the subtraction are integers, the integer subtraction instruction is used. The result of the subtraction is still stored in Register2.

[0081] S4. Use a single SIMD instruction for floating-point multiplication, that is, multiply the 16 floating-point numbers in Register1 with the corresponding 16 floating-point numbers in Register3, as follows:

[0082] Register4=Ingenic_simd512_float_mul(Register1, Register3),

[0083] To multiply the data in Register1 by the floating-point number 0.5, 0.5 needs to be loaded into Register3 first. Since 0.5 is a floating-point number, the immediate load instruction cannot be used; only a normal load instruction can be used, represented as:

[0084] Register3=Ingenic_simd512_load(0.5),

[0085] After loading 0.5, a repeat instruction is used. The repeat instruction is a data copy instruction, represented as:

[0086] Register3=Ingenic_simd512_repeat(Register3),

[0087] Copy the 32-bit floating-point number 0.5 into 16 32-bit floating-point numbers and store them in Register3;

[0088] At this point, both operands of the multiplication instruction are floating-point numbers, so the floating-point multiplication instruction is used, and the result is stored in Register4;

[0089] Then, load the 32-bit floating-point number 1.5 into Register5 using the same method, as follows:

[0090] Register5=Ingenic_simd512_load(1.5),

[0091] Register5=Ingenic_simd512_repeat(Register5);

[0092] The Register4 and Register5 results obtained in this step prepare for the Newton-Raphson iteration method in the following steps;

[0093] S5. Perform the first Newton-Raphson iteration method:

[0094] The SIMD instruction for floating-point multiplication, Ingenic_simd512_float_mul, multiplies the data in Register2 from step S3 by the data in Register2 to obtain the square result, which is stored in Register6. Then, it multiplies the data in Register4, and the result is still stored in Register6. Then, the floating-point subtraction instruction is used, that is, the 16 floating-point numbers in Register5 are subtracted from the corresponding 16 floating-point numbers in Register6. This is represented as: Ingenic_simd512_float_sub, which subtracts the data in Register6 from the data in Register5. Since both operands of this instruction are floating-point numbers, the floating-point subtraction instruction is used, and the result is stored in Register6. Then, the data in Register6 is multiplied by the data in Register2, and the result is stored in Register2.

[0095] The registers here store 16 single-precision floating-point numbers, each 32-bit, and each instruction operates on 16 floating-point numbers simultaneously; represented as:

[0096] Register6=Ingenic_simd512_float_mul(Register2, Register2);

[0097] Register6=Ingenic_simd512_float_mul(Register4, Register6);

[0098] Register6=Ingenic_simd512_float_sub(Register5,Register6);

[0099] Register2=Ingenic_simd512_float_mul(Register2, Register6);

[0100] S6. In order to achieve the accuracy requirements of practical applications, it is necessary to perform n Newton iterations as needed, that is, to repeat step S5 (n-1) times.

[0101] S7. Data from the register is stored in memory in multiples of 32 bits, with a maximum storage capacity of 512 bits, or 16 32-bit single-precision floating-point numbers. *ptr is the memory address, stored using a single SIMD instruction, represented as:

[0102] *ptr=Ingenic_simd512_store(Register2),

[0103] Register2 contains 512 bits of data that need to be stored, which is also the final calculation result.

[0104] Specifically, for ease of understanding, embodiments of the present invention can also be described as follows:

[0105] This method uses the Ingenic_simd512 SIMD instruction set, which can load 512 bits of data into a 512-bit register at once. For cases with large caches, it can load multiples of 512 bits of data at a time, requiring the use of multiple registers. A total of 32 registers are available and can be reused. During computation, the same operation can be performed on 512 bits of data simultaneously. This instruction set includes arithmetic operations such as addition, subtraction, multiplication, absolute value, maximum value, and minimum value; logical operations such as AND, OR, NOT, XOR, and shift operations; and comparison operations such as less than, equal to, and less than or equal to, satisfying general computational needs. Complex computational requirements can be achieved by combining multiple instructions.

[0106] Therefore, the method for quickly calculating the reciprocal of the square root using SIMD instructions includes the following steps:

[0107] S1. Loading data is done in multiples of 32 bits, with a maximum of 512 bits per register. Single-precision floating-point numbers are 32 bits, and a register can hold 16 floating-point numbers, so a single SIMD instruction can perform calculations on 16 floating-point numbers simultaneously. Register1 is register 1, storing the calculation result; Ingenic_simd512_load is a SIMD instruction for loading data; (float)data represents the 16 input 32-bit single-precision floating-point numbers.

[0108] Register1=Ingenic_simd512_load((float)data);

[0109] S2. Perform a direct logical right shift of 1 bit on the data in Register1. This achieves the result of converting the floating-point number to an integer and then performing a logical right shift of 1 bit, as is done in C language. Ingenic_simd512_logical_shift_right_1_bit is a SIMD instruction for logical right shift of 1 bit. Register1 is the operand. The 16 32-bit single-precision floating-point numbers in Register1 are simultaneously logically shifted right by 1 bit, and the result is stored in Register2.

[0110] Register2=Ingenic_simd512_logical_shift_right_1_bit(Register1);

[0111] S3. Subtracting the result of step 2 from the 32-bit hexadecimal "magic number" 0x5f3759df yields the first approximation of the reciprocal of the square root. `Ingenic_simd512_load_immediate` is a SIMD instruction that loads an immediate value, placing 0x5f3759df into Register3 (0x5f3759df is an integer, so immediate loading instructions can be used; floating-point numbers cannot). This instruction can copy a 32-bit data into 16 32-bit data values ​​and load them into a 512-bit register. `Ingenic_simd512_int_sub` is a SIMD instruction for integer subtraction, subtracting 0x5f3759df from the result of step 2. This instruction can perform 16 subtraction operations simultaneously. Since both operands in this subtraction step are integers, an integer subtraction instruction is used, and the result is still stored in Register2.

[0112] Register3=Ingenic_simd512_load_immediate(0x5f3759df);

[0113] Register2=Ingenic_simd512_int_sub(Register3,Register2);

[0114] S4. Use the `Ingenic_simd512_float_mul` instruction to multiply the data in Register1 with the floating-point number 0.5. First, load 0.5 into Register3 (registers can be reused). Since 0.5 is a floating-point number, immediate loading instructions cannot be used; only ordinary loading instructions can be used. After loading 0.5, use the `Ingenic_simd512_repeat` instruction to copy the 32-bit floating-point number 0.5 into 16 32-bit floating-point numbers and store them in Register3. Since both operands of the multiplication instruction are floating-point numbers, a floating-point multiplication instruction is used, and the result is stored in Register4. Then, load the 32-bit floating-point number 1.5 into Register5 using the same method. The results in Register4 and Register5 obtained in this step prepare for the Newton-Raphson iteration method.

[0115] Register3=Ingenic_simd512_load(0.5);

[0116] Register3=Ingenic_simd512_repeat(Register3);

[0117] Register4=Ingenic_simd512_float_mul(Register1, Register3);

[0118] Register5=Ingenic_simd512_load(1.5);

[0119] Register5=Ingenic_simd512_repeat(Register5);

[0120] S5. Perform the first Newton-Raphson iteration. Use the `Ingenic_simd512_float_mul` instruction to multiply the data in `Register2` from step 3 by the data in `Register2`, obtaining the squared result, and store the result in `Register6`. Then multiply this result by the data in `Register4`, and store the result in `Register6` as well. Use the `Ingenic_simd512_float_sub` instruction to subtract the data in `Register6` from the data in `Register5`. Since both operands of this instruction are floating-point numbers, a floating-point subtraction instruction is used, and the result is stored in `Register6`. Finally, multiply the data in `Register6` by the data in `Register2`, and store the result in `Register2`. Each register here stores 16 32-bit single-precision floating-point numbers, and each instruction operates on 16 floating-point numbers simultaneously.

[0121] Register6=Ingenic_simd512_float_mul(Register2, Register2);

[0122] Register6=Ingenic_simd512_float_mul(Register4, Register6);

[0123] Register6=Ingenic_simd512_float_sub(Register5,Register6);

[0124] Register2=Ingenic_simd512_float_mul(Register2, Register6);

[0125] S6. In order to achieve the accuracy requirements of practical applications, multiple Newton iterations are required. This method performs three Newton iterations and repeats step 5 twice.

[0126] Second Newton iteration:

[0127] Register6=Ingenic_simd512_float_mul(Register2, Register2);

[0128] Register6=Ingenic_simd512_float_mul(Register4, Register6);

[0129] Register6=Ingenic_simd512_float_sub(Register5,Register6);

[0130] Register2=Ingenic_simd512_float_mul(Register2, Register6);

[0131] The third Newton iteration:

[0132] Register6=Ingenic_simd512_float_mul(Register2, Register2);

[0133] Register6=Ingenic_simd512_float_mul(Register4, Register6);

[0134] Register6=Ingenic_simd512_float_sub(Register5,Register6);

[0135] Register2=Ingenic_simd512_float_mul(Register2, Register6);

[0136] S7. Data in the register is stored in memory in multiples of 32 bits, with a maximum of 512 bits of data stored at a time, which is 16 32-bit single-precision floating-point numbers. *ptr is the memory address, Ingenic_simd512_store is a SIMD instruction for storing data, and Register2 is the 512 bits of data to be stored, which is also the final calculation result;

[0137] *ptr=Ingenic_simd512_store(Register2).

[0138] Explanation of the accuracy and speed of this method:

[0139] Using the square root reciprocal method from the C math function library as a reference, such as... Figure 2 The image shown is a schematic of the C language code for a quick algorithm to calculate the reciprocal of the square root. It includes the following code:

[0140] int i = *((int*)&x); means: read x as an integer.

[0141] i = 0x5f3759df - (i >> 1); This means obtaining the first approximation of the reciprocal of the square root.

[0142] x = *((float*)&i); means: read i in floating-point mode.

[0143] x = x * (1.5 - (half_x * x * x)); This means that Newton's iteration improves accuracy.

[0144] Under the same input data, the following formula (1) is used to obtain the accuracy loss between the calculation result of this method and the calculation result of the C mathematical function library method. The accuracy loss is on the order of 1e-7, which meets the accuracy requirements of practical applications. If you want to achieve higher accuracy, you can repeat step 5 to perform multiple Newton iterations. The calculation speed of this method is 200 times that of the C language mathematical function library. The accuracy of this method is consistent with the C language square root reciprocal algorithm using three Newton iterations, but the calculation speed is 50 times that of the C language square root reciprocal algorithm.

[0145] Precision_loss=(C_result-SIMD_result) / C_result formula (1)

[0146] In formula (1), Precision_loss represents the result of precision loss calculation, C_result is the result of square root reciprocal method in C mathematical function library, and SIMD_result is the result of this method.

[0147] This application uses the SIMD instruction set of Ingenic_simd512 to optimize and improve the fast algorithm for the reciprocal of square roots, thereby increasing cache utilization, reducing resource consumption, and achieving a calculation speed 50 times faster than the fast algorithm for the reciprocal of square roots in C language. It can run efficiently on platforms with limited hardware resources.

[0148] In this embodiment of the method, after comparison and calculation with the square root reciprocal method in the C mathematical function library, it is found that when the accuracy loss requirement is on the order of 1e-7, three Newton iterations are required.

[0149] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for improving cache utilization using SIMD instructions, characterized in that, The method uses SIMD instructions to quickly calculate the reciprocal of the square root to improve cache utilization. The SIMD instruction set used can load bits of data that are multiples of 512 at a time, using at least one register for loading, and performing the same operation on 512 bits of data at a time during calculation; and uses hexadecimal magic numbers. Subtracting the result of a direct logical right shift of 1 bit from the data in the register yields the first approximation of the reciprocal of the square root of the input floating-point number. This is then treated as a floating-point number and iterated repeatedly using Newton's method until an approximation matching the required precision is obtained and stored in the register. Finally, the data in the register is stored in memory. The SIMD instruction set includes arithmetic operations such as addition, subtraction, multiplication, absolute value, maximum value, and minimum value; logical operations such as AND, OR, NOT, XOR, and shift; and comparison operations such as less than, equal to, and less than or equal to. Complex computational requirements are achieved through a combination of multiple instructions. The method includes the following steps: S1. Data is loaded in multiples of 32 bits, with a maximum of 512 bits of data loaded into one register; Register 1, denoted as Register1, is used to store the calculation results; Using a single SIMD instruction to load data, it can be represented as: ， Where (float)data is the input of 16 32-bit single-precision floating-point numbers; S2. Perform a direct logical right shift of 1 bit on the data in Register1. Using a single SIMD instruction that logically shifts right by 1 bit, it can be represented as: ， Register1 is the operand. The 16 32-bit single-precision floating-point numbers in Register1 are simultaneously logically shifted right by 1 bit, and the result is stored in Register2, which is represented as Register2. S3. Using 32-bit hexadecimal magic numbers Subtracting the result from step S2, we obtain the first approximation of the reciprocal of the square root. Using a single SIMD instruction to load an immediate value, it can be represented as: ， Will Load into Register3. This instruction can copy a 32-bit data into 16 32-bit data and load them into a 512-bit register. Using a single SIMD instruction for integer subtraction, it can be represented as: ， Subtract the 16 32-bit data in Register3 from the result of step S2. This instruction can perform 16 subtraction operations at the same time. Since both operands of the subtraction are integers, the integer subtraction instruction is used. The result of the subtraction is still stored in Register2. S4. Use a single SIMD instruction for floating-point multiplication, that is, multiply the 16 floating-point numbers in Register1 with the corresponding 16 floating-point numbers in Register3, as follows: ， To multiply the data in Register1 by the floating-point number 0.5, 0.5 needs to be loaded into Register3 first. Since 0.5 is a floating-point number, the immediate load instruction cannot be used; only a normal load instruction can be used, represented as: ， After loading 0.5, a repeat instruction is used. The repeat instruction is a data copy instruction, represented as: ， Copy the 32-bit floating-point number 0.5 into 16 32-bit floating-point numbers and store them in Register3; At this point, both operands of the multiplication instruction are floating-point numbers, so the floating-point multiplication instruction is used, and the result is stored in Register4; Then, load the 32-bit floating-point number 1.5 into Register5 using the same method, as follows: ； ； The Register4 and Register5 results obtained in this step prepare for the Newton-Raphson iteration method in the following steps; S5. Perform the first Newton-Raphson iteration method: SIMD instructions for floating-point multiplication: The instruction multiplies the data in Register2 from step S3 by the data in Register4, obtains the square result, stores the result in Register6, multiplies it by the data in Register4, and stores the result in Register6 again. Then, it uses a floating-point subtraction instruction, that is, subtracts the corresponding 16 floating-point numbers in Register6 from the 16 floating-point numbers in Register5, which is expressed as: The instruction subtracts the data in Register6 from the data in Register5. Since both operands of this instruction are floating-point numbers, a floating-point subtraction instruction is used. The result is stored in Register6. Then, the data in Register6 is multiplied by the data in Register2, and the result is stored in Register2. The registers here store 16 single-precision floating-point numbers, each 32-bit, and each instruction operates on 16 floating-point numbers simultaneously; represented as: ； ； ； ； S6. To achieve the required accuracy for practical applications, n Newton iterations are needed, which means repeating step S5. Second-rate; S7. Data in the register is stored in memory in multiples of 32 bits. A maximum of 512 bits of data can be stored at a time, which is 16 32-bit single-precision floating-point numbers. It is a memory address, represented by a single SIMD instruction for storing data: ， Register2 contains 512 bits of data that need to be stored, which is also the final calculation result.

2. The method for improving cache utilization using SIMD instructions according to claim 1, characterized in that, There are a total of 32 registers that have been loaded and can be reused.

3. The method for improving cache utilization using SIMD instructions according to claim 1, characterized in that, In step S1, a single-precision floating-point number is 32 bits, and a register loads 16 floating-point numbers, so a single SIMD instruction can perform calculations on 16 floating-point numbers simultaneously.

4. The method for improving cache utilization using SIMD instructions according to claim 1, characterized in that, In step S2, performing a direct logical right shift of 1 bit on the data in Register1 achieves the result of first converting the floating-point number to an integer and then performing a logical right shift of 1 bit, as is done in C language.

5. A method for improving cache utilization using SIMD instructions according to claim 1, characterized in that, In step S3, the Integers can use the load immediate instruction; Register 3 can be reused.

6. A method for improving cache utilization using SIMD instructions according to claim 1, characterized in that, Step S6 further includes: enabling three Newton iterations, repeating step S5 twice more, as follows: Second Newton iteration: ； ； ； ； The third Newton iteration: ； ； ； 。

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