Graph task scheduling method, execution device, storage medium and program product

Abstract

Embodiments of the present application provide a kind of graph task scheduling method, execution equipment, storage medium and program product, by determining the required computing resource number of each subgraph in graph task, then according to the dependency between each subgraph and the required computing resource number of each subgraph, for the graph task scheduling computing resource, to solve the problem of large time cost in the scheduling process of existing graph task scheduling mode, and the task processing efficiency is lower.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a graph task scheduling method, execution device, storage medium and program product. Background Technology

[0002] Graph tasks are tasks represented using a graph structure. Each node in the graph structure represents a task, and the directed edges between nodes represent the dependencies between tasks. When processing graph tasks, the host device typically distributes the tasks from each subgraph sequentially to the execution device, which then allocates sufficient computing resources to execute the graph tasks.

[0003] However, in the existing resource scheduling method, since the resources required by each subgraph in the graph task are scheduled relatively independently by the execution device, for two subgraphs with dependencies in the graph task, they may be allocated to different computing resource units for computation. This makes it necessary for the data obtained by the successor subgraph to be transmitted through computing resource units to reach the computing resource unit where the current subgraph is located for computation processing.

[0004] Clearly, this task scheduling method results in a significant time cost for data transmission, severely impacting the overall task processing efficiency. Summary of the Invention

[0005] This invention provides a graph task scheduling method, execution device, storage medium, and program product to solve the problems of high time cost and low task processing efficiency in existing graph task scheduling methods.

[0006] In a first aspect, embodiments of the present invention provide a method for scheduling graph tasks, comprising:

[0007] Determine the number of computational resources required for each subgraph in the graph task;

[0008] Based on the dependencies between subgraphs and the number of computing resources required for each subgraph, computing resources are scheduled for the graph task.

[0009] In an optional implementation, the determination of the number of computational resources required for each subgraph in the graph task includes:

[0010] For any subgraph, determine the task duration and number of computing resources for each task in the subgraph;

[0011] Based on the task duration and computing resources of each task, multiple task execution sequences are determined for the subgraph; wherein each task execution sequence includes all tasks in the subgraph and the execution relationships between the tasks.

[0012] The number of computing resources required for the subgraph is determined based on the number of schedulable computing resources, the total number of computing resources required to execute each task execution sequence, and the total task duration.

[0013] In an optional implementation, determining the various task execution sequences of the subgraph based on the task duration and computing resource requirements of each task includes:

[0014] The task priorities of each task are sorted according to the task duration and computing resources required for each task.

[0015] Based on the priority ranking of each task, various task execution sequences of the subgraph are determined.

[0016] In an optional implementation, the task priority is directly proportional to the number of computing resources for the task and also directly proportional to the task duration.

[0017] In an optional implementation, determining the number of computing resources required for the subgraph based on the number of schedulable computing resources, the total number of computing resources required to execute each task execution sequence, and the total task duration includes:

[0018] Determine the product between the total number of computational resources for each task execution sequence and the total task duration;

[0019] In each task execution sequence, the task execution sequence with the smallest total number of computing resources and the smallest product is determined, and the total number of computing resources of the task execution sequence is taken as the number of computing resources of the subgraph.

[0020] In an optional implementation, the method further includes:

[0021] Calculate the total number of computing resources required to execute each task sequence and the total task duration.

[0022] In an optional implementation, the calculation of the total number of computing resources and the total task duration required to execute each task execution sequence includes:

[0023] For any task execution sequence, based on the execution relationship between the tasks in the task execution sequence and the task duration and number of computing resources of each task, determine the maximum number of parallel computing resources required for the task execution sequence to complete each task under its corresponding execution relationship, and use the maximum number of parallel computing resources as the total number of computing resources of the task execution sequence.

[0024] Based on the execution relationship between tasks in the task execution sequence and the task duration of each task, the estimated execution time until the task execution sequence is completed is taken as the total task duration of the task execution sequence.

[0025] In an optional implementation, scheduling computing resources for the graph task based on the dependencies between subgraphs and the number of computing resources required for each subgraph includes:

[0026] Based on the dependencies between subgraphs and the number of computing resources required for each subgraph, the computing resources required for the graph task are determined, and the corresponding computing resources are scheduled for the graph task.

[0027] In an optional implementation, the computational resources required for determining the graph task include:

[0028] The maximum number of computing resources required by each subgraph is the computing resources required for the graph task.

[0029] In an optional implementation, scheduling corresponding computing resources for the image task includes:

[0030] Determine the quadrant number of computational resources required for the graph task and the quadrant constraint relationships between the subgraphs of the graph task;

[0031] Based on the number of quadrants and the quadrant constraints, computational resources are scheduled for the image task.

[0032] Secondly, embodiments of the present invention provide a computer system, including: a host terminal and a device terminal; wherein,

[0033] On the host side, the number of computing resources required for each subgraph in the graph task is determined; based on the dependencies between subgraphs and the number of computing resources required for each subgraph, the task scheduling graph of the graph task is determined, wherein the task scheduling graph is used to describe the number of quadrants of computing resources required by the graph task and the quadrant constraint relationships;

[0034] On the device side, it is used to schedule computing resources for the task based on the task scheduling graph issued by the host.

[0035] Thirdly, embodiments of this application provide an execution device, including: a memory and a processor;

[0036] Memory; memory for storing executable instructions of the processor;

[0037] The processor is configured as follows:

[0038] Determine the number of computational resources required for each subgraph in the graph task;

[0039] Based on the dependencies between subgraphs and the number of computing resources required for each subgraph, computing resources are scheduled for the graph task.

[0040] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the graph task scheduling method as described in any of the first aspects.

[0041] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the graph task scheduling method as described in any of the first aspects.

[0042] This invention provides a graph task scheduling method, execution device, storage medium, and program product. By determining the number of computing resources required for each subgraph in a graph task, and then scheduling computing resources for the graph task based on the dependencies between subgraphs and the number of computing resources required for each subgraph, the invention solves the problems of high time cost and low task processing efficiency in existing graph task scheduling methods. Attached Figure Description

[0043] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0044] Figure 1 This diagram shows a structural schematic of a board 10 according to an embodiment of the present disclosure;

[0045] Figure 2 This diagram shows a structural diagram of the combined processing device in chip 101 of this embodiment;

[0046] Figure 3 A schematic diagram of the internal structure of the computing device 201 as a single-core processor is shown.

[0047] Figure 4 A schematic diagram of the internal structure of the computing device 201 as a multi-core processor is shown.

[0048] Figure 5 This diagram illustrates the internal structure of a processor core according to an embodiment of the present disclosure;

[0049] Figure 6 A schematic diagram of a graph structure for a graph task;

[0050] Figure 7 This is a schematic diagram of the structure of schedulable resources in the execution phase;

[0051] Figure 8 This is a schematic diagram of scheduling resources for graph tasks provided by existing technology;

[0052] Figure 9 This is a flowchart illustrating a graph task scheduling method provided in this application;

[0053] Figure 10 This diagram illustrates the resource scheduling during the execution of a task execution sequence.

[0054] Figure 11 A schematic diagram of quadrant distribution provided for an embodiment of this application;

[0055] Figure 12 This is a schematic diagram of the hardware structure of a computer system provided in this application.

[0056] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0057] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0058] In existing graph tasks, the resources required by each subgraph are scheduled relatively independently by the execution device. This means that two dependent subgraphs may be assigned to different computing resource units for computation. This necessitates data transfer between computing resource units for the preceding subgraph to reach the current subgraph for processing. Clearly, this task scheduling method incurs significant time costs for data transfer, severely impacting overall task processing efficiency. This application addresses this issue by providing a graph task scheduling method, execution device, storage medium, and program product.

[0059] The graph task scheduling method, execution device, storage medium, and program product provided in this invention determine the number of computing resources required for each subgraph in a graph task, and then schedule computing resources for the graph task according to the dependencies between subgraphs and the number of computing resources required for each subgraph, thereby solving the problems of high time cost and low task processing efficiency in existing graph task scheduling methods.

[0060] The method and apparatus are based on the same concept of the application. Since the methods and apparatus solve problems in similar ways, the implementation of the apparatus and methods can refer to each other, and the repeated parts will not be described again.

[0061] For ease of explanation, the computer hardware structure involved in this application will be described first:

[0062] Figure 1 A schematic diagram of the structure of a board 10 according to an embodiment of this disclosure is shown. This board can serve as the aforementioned execution device. Figure 1 As shown, board 10 includes chip 101, which is a system-on-chip (SoC) integrating one or more combined processing units. These combined processing units are artificial intelligence computing units used to support various deep learning and machine learning algorithms, meeting the intelligent processing needs of complex scenarios in fields such as computer vision, speech, natural language processing, and data mining. In particular, deep learning technology is widely used in cloud intelligence. A significant characteristic of cloud intelligence applications is the large volume of input data, placing high demands on the platform's storage and computing capabilities. Board 10 in this embodiment is suitable for cloud intelligence applications, possessing massive off-chip storage, on-chip storage, and powerful computing capabilities.

[0063] Chip 101 is connected to external device 103 via external interface device 102. External device 103 may be, for example, a server, computer, camera, monitor, mouse, keyboard, network card, or Wi-Fi interface. Data to be processed can be transmitted from external device 103 to chip 101 via external interface device 102. The calculation results from chip 101 can be transmitted back to external device 103 via external interface device 102. Depending on the application scenario, external interface device 102 may have different interface forms, such as a PCIe interface.

[0064] The board 10 also includes a storage device 104 for storing data, which includes one or more memory cells 105. The storage device 104 is connected to and transmits data with the controller 106 and the chip 101 via a bus. The controller 106 in the board 10 is configured to regulate the state of the chip 101. Therefore, in one application scenario, the controller 106 may include a microcontroller (MCU).

[0065] Figure 2 This is a structural diagram illustrating the combined processing device in chip 101 of this embodiment. (As shown) Figure 2 As shown, the combined processing device 20 includes a computing device 201, an interface device 202, a processing device 203, and a storage device 204.

[0066] The computing device 201 is configured to perform user-specified operations. It is mainly implemented as a single-core intelligent processor or a multi-core intelligent processor to perform deep learning or machine learning calculations. It can interact with the processing device 203 through the interface device 202 to jointly complete the user-specified operations.

[0067] Interface device 202 is used to transmit data and control commands between computing device 201 and processing device 203. For example, computing device 201 can obtain input data from processing device 203 via interface device 202 and write it to on-chip storage device of computing device 201. Further, computing device 201 can obtain control commands from processing device 203 via interface device 202 and write them to on-chip control cache of computing device 201. Alternatively or optionally, interface device 202 can also read data from storage device of computing device 201 and transmit it to processing device 203.

[0068] Processing device 203, as a general-purpose processing device, performs basic controls including but not limited to data transfer, and starting and / or stopping computing device 201. Depending on the implementation, processing device 203 may be one or more types of processors, including but not limited to digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, computing device 201 disclosed herein can be considered as having a single-core structure or a homogeneous multi-core structure. However, when computing device 201 and processing device 203 are considered together, they are considered to form a heterogeneous multi-core structure.

[0069] Storage device 204 is used to store data to be processed. It may be DRAM or DDR memory, typically 16G or larger in size, and is used to store data of computing device 201 and / or processing device 203.

[0070] Figure 3The diagram shows the internal structure of the single-core computing device 201. The single-core computing device 301 is used to process input data such as computer vision, speech, natural language, and data mining. The single-core computing device 301 includes three main modules: a control module 31, a processing module 32, and a storage module 33.

[0071] The control module 31 coordinates and controls the operation of the computation module 32 and the storage module 33 to complete the deep learning task. It includes an instruction fetch unit (IFU) 311 and an instruction decode unit (IDU) 312. The instruction fetch unit 311 fetches instructions from the processing device 203, and the instruction decode unit 312 decodes the fetched instructions and sends the decoding result as control information to the computation module 32 and the storage module 33.

[0072] The computation module 32 includes a vector operation unit 321 and a matrix operation unit 322. The vector operation unit 321 is used to perform vector operations and can support complex operations such as vector multiplication, addition, and nonlinear transformations; the matrix operation unit 322 is responsible for the core computations of deep learning algorithms, namely matrix multiplication and convolution.

[0073] Storage module 33 is used to store or move relevant data, including neuron RAM (NRAM) 331, weight RAM (WRAM) 332, and direct memory access (DMA) module 333. NRAM 331 is used to store input neurons, output neurons, and intermediate results after computation; WRAM 332 is used to store the convolution kernels of the deep learning network, i.e., the weights; DMA 333 is connected to DRAM through bus 34 and is responsible for data transfer between the single-core computing device 301 and DRAM.

[0074] Figure 4 A schematic diagram of the internal structure of the computing device 201 as a multi-core is shown. The multi-core computing device 41 adopts a hierarchical structure design. As a system-on-a-chip, the multi-core computing device 41 includes at least one cluster, and each cluster includes multiple processor cores. In other words, the multi-core computing device 41 is constructed in a hierarchy of system-on-a-chip - cluster - processor core.

[0075] From the perspective of system-on-a-chip hierarchy, such as Figure 4 As shown, the multi-core computing device 41 includes an external storage controller 401, a peripheral communication module 402, an on-chip interconnect module 403, a synchronization module 404, and multiple clusters 405.

[0076] There can be multiple external storage controllers 401; two are shown as an example in the figure. These controllers are used to access external storage devices, such as those issued by the processor core, in response to access requests from the processor core. Figure 4 The DRAM 304 in the chip allows data to be read from or written to external devices. The peripheral communication module 402 receives control signals from the processing device 203 via the interface device 202, initiating the computing device 201 to execute tasks. The on-chip interconnect module 403 connects the external storage controller 401, the peripheral communication module 402, and multiple clusters 405 to transmit data and control signals between modules. The synchronization module 404 is a global barrier controller (GBC) used to coordinate the working progress of each cluster and ensure information synchronization. The multiple clusters 405 are the computing cores of the multi-core computing device 41. Four are shown exemplarily in the figure; however, with hardware development, the multi-core computing device 41 disclosed herein may also include 8, 16, 64, or even more clusters 405. The clusters 405 are used to efficiently execute deep learning algorithms.

[0077] From the perspective of cluster hierarchy, such as Figure 4 As shown, each cluster 405 includes multiple processor cores (IPU cores) 406 and one memory core (MEM core) 407.

[0078] Four processor cores 406 are shown in the figure as an example; this disclosure does not limit the number of processor cores 406. Its internal architecture is as follows: Figure 5 As shown. Each processor core 406 is similar to Figure 3 The single-core computing device 301 also includes three main modules: a control module 51, an arithmetic module 52, and a storage module 53. The functions and structures of the control module 51, arithmetic module 52, and storage module 53 are largely the same as those of the control module 31, arithmetic module 32, and storage module 33, and will not be described again. It should be noted that the storage module 53 includes an input / output direct memory access (IODMA) module 533 and a move direct memory access (MVDMA) module 534. The IODMA 533 controls the memory access of NRAM 531 / WRAM 532 and DRAM 304 via the broadcast bus 409; the MVDMA 534 controls the memory access of NRAM 531 / WRAM 532 and SRAM 408.

[0079] Back Figure 4The storage core 407 is primarily used for storage and communication, namely storing shared data or intermediate results among processor cores 406, and performing communication between cluster 405 and DRAM 304, communication between clusters 405, and communication between processor cores 406. In other embodiments, the storage core 407 has scalar operation capabilities and is used to perform scalar operations.

[0080] The storage core 407 includes an SRAM 408, a broadcast bus 409, a cluster direct memory access (CDMA) module 410, and a global direct memory access (GDMA) module 411. The SRAM 408 acts as a high-performance data relay station. Data multiplexed between different processor cores 406 within the same cluster 405 does not need to be obtained from the DRAM 304 by each processor core 406. Instead, it is relayed between processor cores 406 via the SRAM 408. The storage core 407 only needs to quickly distribute the multiplexed data from the SRAM 408 to multiple processor cores 406 to improve inter-core communication efficiency and greatly reduce on-chip and off-chip input / output access.

[0081] Broadcast bus 409, CDMA 410, and GDMA 411 are used to perform communication between processor cores 406, communication between clusters 405, and data transfer between cluster 405 and DRAM 304, respectively. These will be explained below.

[0082] The broadcast bus 409 is used to complete high-speed communication between the processor cores 406 within the cluster 405. In this embodiment, the broadcast bus 409 supports inter-core communication methods including unicast, multicast, and broadcast. Unicast refers to point-to-point (e.g., data transmission from one processor core to another) data transmission. Multicast is a communication method that transmits a piece of data from SRAM 408 to several specific processor cores 406. Broadcast is a communication method that transmits a piece of data from SRAM 408 to all processor cores 406, and is a special case of multicast.

[0083] CDMA 410 is used to control SRAM 408 access between different clusters 405 within the same computing device 201.

[0084] GDMA 411 works in conjunction with external memory controller 401 to control memory access from SRAM 408 to DRAM 304 in cluster 405, or to read data from DRAM 304 into SRAM 408. As previously described, communication between DRAM 304 and NRAM 531 or WRAM 532 can be achieved through two channels. The first channel is a direct connection between DRAM 304 and NRAM 531 or WRAM 532 via IODMA 533; the second channel involves first transmitting data between DRAM 304 and SRAM 408 via GDMA 411, and then transmitting data between SRAM 408 and NRAM 531 or WRAM 532 via MVDMA 534. Although the second channel appears to require more components and has a longer data flow, in some embodiments, the bandwidth of the second channel is significantly greater than that of the first channel. Therefore, communication between DRAM 304 and NRAM 531 or WRAM 532 may be more efficient via the second channel. The embodiments disclosed herein allow for the selection of data transmission channels based on the hardware capabilities available.

[0085] In other embodiments, the functions of GDMA 411 and IODMA 533 can be integrated into the same component. For ease of description, this disclosure treats GDMA 411 and IODMA 533 as different components. For those skilled in the art, any component that performs similar functions and achieves similar technical effects to this disclosure falls within its scope of protection. Furthermore, the functions of GDMA 411, IODMA 533, CDMA 410, and MVDMA 534 can also be implemented by the same component.

[0086] The scheduling method for graph tasks provided in this application is executed in... Figure 1 The graph task shown in board 10 can include various deep learning and machine learning tasks, such as neural network tasks with multiple task nodes. This graph task can be applied to complex scenarios in fields such as computer vision, speech, natural language processing, and data mining.

[0087] Based on the hardware structure of the aforementioned execution device, in order to better understand the technical solution of this application, the scheduling scheme of graph tasks in the prior art will be described in detail below.

[0088] Graph tasks refer to tasks that use a graph structure to represent multiple consecutive tasks. Each node in the graph structure represents a task, and the directed edges between nodes represent the dependencies between tasks. Graph tasks can be neural network tasks, and each task node in a graph task can be an operator (such as convolution, fully connected layers, activation, etc.) in the neural network task.

[0089] Figure 6 This is a schematic diagram of a graph structure for a graph task, such as... Figure 6 As shown, the graph structure includes five nodes: A, B, C, D, and E. Each node represents a task. A is connected to B, C, and D by directed edges, while B, C, and D are connected to E by directed edges. Based on this graph structure, it can be seen that A has dependencies on B, C, and D; that is, B, C, and D can only perform their operations after A has completed its operation. Similarly, B, C, and D have dependencies on E; that is, E can only perform its operation after B, C, and D have all completed their operations.

[0090] In the existing resource scheduling method, since the resources required by each subgraph in the graph task are scheduled relatively independently by the execution device, the execution device adopts a dynamic scheduling execution method during scheduling.

[0091] When processing graph tasks, the host first sends the task to the execution end, and then the processing unit in the execution end executes the task. The execution end can be a multi-core processor such as an artificial intelligence processor, which can include multiple processing units. Figure 7 This is a schematic diagram of the structure of schedulable resources in the execution phase, such as... Figure 7 As shown, multiple processing units can be configured according to the NUMA architecture. These multiple processing units can be divided into four quadrants, each quadrant including at least one computing unit and at least one storage unit.

[0092] like Figure 7 As shown, each quadrant's processing unit includes four arithmetic units and one storage unit. Specifically, the first quadrant includes storage unit 1 and arithmetic units 11-14; the second quadrant includes storage unit 2 and arithmetic units 21-24; the third quadrant includes storage unit 3 and arithmetic units 31-34; and the fourth quadrant includes storage unit 4 and arithmetic units 41-44. It should be clear that... Figure 7 The example of an execution processor containing 16 arithmetic units is provided only and is not intended to limit the specific structure of the execution processor or the number of arithmetic units it contains. Of course, in other alternative embodiments, the execution processor may contain 8 or 32 arithmetic units, etc., in which case the number of arithmetic units in each quadrant is not limited to 4.

[0093] Figure 8 This is a schematic diagram of scheduling resources for graph tasks provided by existing technology; such as Figure 8 As shown, for the graph structure described above, after the execution end receives the graph task, it will schedule resources for each subgraph according to the computing resources required by each task of each subgraph recorded in the graph task.

[0094] First, dynamic resource scheduling will be performed for A. For example, if the execution end knows that A needs 4 computing units of computing resources, and when determining computing resources for A, it is found that the computing resources in the first quadrant are free (i.e., computing units 11-14 are free), then the computing resources in the first quadrant can be allocated to A to perform computing processing. Correspondingly, the data obtained by A's computing is also stored in the storage resources in the first quadrant (i.e., storage unit 1).

[0095] After A completes its operation, the execution end will begin dynamic resource scheduling for B, C, and D. If the execution end knows that B and C each require 2 units of computing resources and D requires 4 units of computing resources, then the execution end will determine the currently available computing resources. For example, if the execution end finds that the computing resources in the second and third quadrants are available, then the execution end will allocate the computing resources in the second quadrant to B and C, and the computing resources in the third quadrant to D.

[0096] At this point, since there is a dependency between A and BCD, in order to perform the operation on BCD, the computing resources in the second quadrant need to read the operation result on A from the storage resources in the first quadrant and perform the operation on BC based on the operation result; similarly, the computing resources in the third quadrant also need to read the operation result on A from the storage resources in the first quadrant and perform the operation on D based on the operation result.

[0097] Finally, after the execution end has completed the calculations of BCD, it will begin to dynamically schedule resources for E. If the execution end knows that E needs 4 units of computing resources, it will then determine the currently available computing resources. For example, if the execution end finds that the computing resources in the first quadrant are available, it will allocate the computing resources in the first quadrant to E.

[0098] Similarly, since there is a dependency between E and BCD, in order to perform operations on E, the computing resources in the first quadrant need to read the operation results of BC from the storage resources in the second quadrant, and the computing resources in the first quadrant also need to read the operation results of D from the storage resources in the third quadrant. Then, the computing resources in the first quadrant can use the read operation results of BCD to perform the operation on E and obtain the final graph task operation result.

[0099] Clearly, in the resource scheduling process for graph tasks described above, the dynamic scheduling method used by the execution end only schedules tasks based on the current availability of computing resources, without considering the dependencies between tasks. This means that during task execution, two dependent subgraphs within a graph task may be assigned to different computing resource units for computation. This necessitates data transfer between computing resource units for the predecessor subgraph to reach the current subgraph for processing. This task scheduling method obviously incurs significant time costs for data transfer, severely impacting the overall task processing efficiency.

[0100] To address the aforementioned issues, the host side of this embodiment determines the number of computing resources required for each subgraph in the graph task. Based on the dependencies between subgraphs and the number of computing resources required for each subgraph, a task scheduling graph for the graph task is determined. This task scheduling graph represents the number of quadrants of computing resources required by the graph task and the quadrant constraints. Then, the execution side schedules computing resources for the graph task according to the task scheduling graph issued by the host side. This processing method clusters dependent tasks in the same or similar computing resources, effectively improving the overall computing efficiency of the task.

[0101] The embodiments of this application will now be described in detail with reference to the accompanying drawings and the steps provided above.

[0102] Figure 9 This is a flowchart illustrating a graph task scheduling method provided in this application, which can be applied to... Figure 1 In the computer hardware structure shown, the execution entity of this scheduling method can be the host device, which can be the aforementioned external device 103. Through the implementation method provided in this application, the host device can generate graph tasks and send the graph tasks and the corresponding scheduling graph to the execution device in a whole form through the external interface device 102, so that the execution device can execute the graph tasks based on the scheduling graph.

[0103] like Figure 9 As shown, the scheduling method for the graph tasks includes:

[0104] Step 901: Determine the number of computing resources required for each subgraph in the graph task;

[0105] Step 902: Based on the dependencies between subgraphs and the number of computing resources required for each subgraph, schedule computing resources for the graph task.

[0106] In this embodiment, before the host device sends the graph task to the execution device, it will also use the scheduling method provided in this embodiment to schedule computing resources for the graph task. Subsequently, the host device will schedule each subgraph in the graph task and the corresponding task for the graph task. Figure 1 The data is then sent to the execution device. After receiving the graph task and the task scheduling graph, the execution device will perform corresponding resource scheduling processing for each subgraph in the graph task based on the number of quadrants of computing resources required by the graph task as described in the task scheduling graph and the quadrant constraint relationships.

[0107] For the host device, in order to generate a task scheduling graph for a graph task, the host device first determines the number of computing resources required for each subgraph in the graph task. Then, the host device schedules computing resources for the graph task based on the dependencies between the subgraphs, such as predecessor and successor tasks, and in conjunction with the aforementioned number of computing resources required for each subgraph.

[0108] Specifically, as mentioned earlier, a subgraph may contain multiple tasks, and the number of computing resources required for a subgraph refers to the amount of computing resources needed to execute these tasks. Computing resources can be understood as modules or units, including IPUs, that can be used for data processing. Generally, the number of computing resources for each task is determined when the task is created. However, for the number of computing resources for a subgraph, due to differences in the execution order or relationship of the tasks, different execution orders or relationships result in different task sequences requiring different numbers of computing resources. These different numbers of computing resources will affect subsequent resource scheduling and processing.

[0109] Steps 9011 to 9013 describe how to determine the number of computational resources required for any subgraph:

[0110] Step 9011: Determine the task duration and computing resources for each task in the subgraph;

[0111] Step 9012: Based on the task duration and computing resources of each task, determine multiple task execution sequences of the subgraph; wherein each task execution sequence includes all tasks in the subgraph and the execution relationships between the tasks;

[0112] Step 9013: Determine the number of computing resources required for the subgraph based on the number of schedulable computing resources, the total number of computing resources required to execute each task execution sequence, and the total task duration.

[0113] As mentioned above Figure 6 Taking the graph task shown as an example, in Figure 6In the graph task shown, the graph is divided into subgraphs based on the dependencies between tasks. The subgraph can be divided in various ways, such as depth-first or breadth-first partitioning.

[0114] Taking breadth-first partitioning as an example, the task in this graph can be divided into three subgraphs: subgraph A; subgraphs B, C, and D; and subgraph E. For subgraphs A and E, since each subgraph contains only one unique task, the computational resources required for each subgraph are the same as the resource requirements for that unique task within that subgraph.

[0115] For the subgraph BCD, since it contains three tasks, there are multiple possible task execution sequences and a total number of computational resources required for each sequence. Therefore, when determining the number of computational resources required for the subgraph BCD, we can first identify the possible task execution sequences corresponding to the subgraph.

[0116] For example, for BCD, the possible task execution sequences can be shown in Table 1 below.

[0117] Table 1

[0118]

[0119] Table 1 shows all possible task execution sequences of subgraph BCD, where the task execution order is used to represent the execution priority of each task. For example, BCD is used to indicate that the priority of B is greater than that of C, and the priority of C is greater than that of D.

[0120] Under the same task execution priority order, different execution relationships between tasks will present different task execution sequences. For example, under the BCD task priority, there are multiple task execution sequences including: "B serial C serial D", "B parallel C parallel D", "B serial (C parallel D)", "(B serial C) parallel D", and "(B parallel C) serial D".

[0121] The terms "serial" and "parallel" are used to describe the task execution relationship, which can be understood as "executed sequentially" and "executed in parallel." It should be noted that in a "serial" task execution relationship, the two tasks generally utilize all or part of the same computing resources and are executed sequentially; in a "parallel" task execution relationship, the two tasks generally utilize different computing resources and are executed concurrently.

[0122] Taking "B serial C serial D" as an example, it means that BCD is executed sequentially using all or part of the same computing resources.

[0123] "(B serial C) parallel D" means that BC is executed sequentially using all or part of the same computing resources, and D is executed using completely different computing resources while BC is being executed.

[0124] "B serial (C parallel D)" means that the computing resources for executing B are partially or entirely the same as those for executing C and D, and B is executed first, and C and D will only begin to be executed after B is executed. The computing resources for executing C and D are different computing resources, and they are executed synchronously.

[0125] In determining multiple task execution sequences for the subgraph based on the task duration and computing resources of each task, the number of possible task execution sequences will increase exponentially with the increase in the number of tasks. To reduce the workload in determining the task execution sequence, in an optional implementation, the task priority of each task in the subgraph can be determined first, and then the optimal multiple task execution sequences can be determined based on the task priority ranking result.

[0126] Specifically, task priority is generally related to the amount of computing resources a task requires and its duration. The more computing resources a task requires, the higher its urgency; similarly, the longer a task takes, the higher its computational complexity. In other words, task priority is directly proportional to the amount of computing resources a task has and also directly proportional to its duration.

[0127] Taking the aforementioned subgraph BCD as an example, assume that: the task duration of task B is 40ms and the number of computing resources is 4; the task duration of task C is 20ms and the number of computing resources is 2 IPU; and the task duration of task D is 40ms and the number of computing resources is 2.

[0128] Following the aforementioned method, BCD can be sorted first based on the number of computing resources to obtain BD and C; then, based on the task duration of BD, they can be sorted again to finally obtain the task priority of BDC.

[0129] Based on the priority ranking of this task, different execution relationships can be reused as mentioned above to obtain different task execution sequences, as shown in Table 2.

[0130] Table 2

[0131]

[0132] This method will greatly reduce the number of task execution sequences, which is beneficial to improving the overall scheduling efficiency.

[0133] Subsequently, the number of computing resources required for each subgraph in the graph task will depend on the task execution sequence mentioned above. Different task execution sequences generally have different numbers of computing resources and total task durations. Therefore, when determining the number of computing resources required for a subgraph, it is necessary to consider, on the one hand, the number of schedulable computing resources on the execution device, such as the number of IPUs included in the execution device, and on the other hand, the total number of computing resources required by the task execution sequence and the total task duration. Based on these two factors, the optimal task execution sequence is selected from multiple task execution sequences to serve as the task execution sequence for that subgraph in the task scheduling graph. The total number of computing resources for the final task execution sequence will then be considered as the number of computing resources required for that subgraph.

[0134] Based on this, in an optional implementation, the product between the total number of computing resources and the total duration of each task execution sequence can be determined first; then, among each task execution sequence, the task execution sequence with the smallest product whose total number of computing resources is not greater than the number of schedulable computing resources is determined, and the total number of computing resources of the task execution sequence is taken as the number of computing resources of the subgraph.

[0135] To determine the total number of computing resources and the total task duration required for each task execution sequence, embodiments of this application also provide a method for calculating the total number of computing resources and the total task duration required for executing each task execution sequence:

[0136] Specifically, for any task execution sequence corresponding to a subgraph, the following steps can be performed:

[0137] Step 901: Based on the execution relationship between tasks in the task execution sequence and the task duration and number of computing resources for each task, determine the maximum number of parallel computing resources required for the task execution sequence to complete each task under its corresponding execution relationship, and use the maximum number of parallel computing resources as the total number of computing resources for the task execution sequence.

[0138] Step 902: Based on the execution relationship between each task in the task execution sequence and the task duration of each task, the estimated execution time until the task execution sequence is completed is taken as the total task duration of the task execution sequence.

[0139] Taking the task execution sequence "B parallel (D serial C)" as an example, Figure 10 This diagram illustrates the resource scheduling during the execution of a task execution sequence.

[0140] It should be noted that, in Figure 10 In the structure shown, IPU refers to the Intelligence Processing Unit (IPU). IPU is one specific unit type among the aforementioned computing units.

[0141] like Figure 10 As shown, based on the aforementioned assumptions, task B has a duration of 40ms and requires 4 IPUs of computational resources; task C has a duration of 20ms and requires 2 IPUs of computational resources; and task D has a duration of 40ms and requires 2 IPUs of computational resources. Furthermore, it is assumed that the schedulable resources are 8 IPUs, i.e., as... Figure 10 The IPU1, IPU2, IPU3, IPU4, IPU5, IPU6, IPU7, and IPU8 are shown. IPU1-IPU4 belong to the same quadrant, such as the first quadrant; IPU5-IPU8 belong to the same quadrant, such as the second quadrant.

[0142] According to the task execution sequence of "B parallel (D serial C)", from 0ms to 40ms, IPU1, IPU2, IPU3, and IPU4 are all assigned to task B for computation. From 0ms to 40ms, any two IPUs among IPU5, IPU6, IPU7, and IPU8, such as IPU5 and IPU6, are assigned to task D for computation. From 41ms to 60ms, task C continues to use the computing resources of task D for computation, that is, IPU5 and IPU6 are assigned to task C for computation.

[0143] At this point, it is known that the maximum number of parallel computing resources for the "B parallel (D serial C)" task execution sequence is 6 IPUs, meaning that all 6 IPUs are performing operations from 0 to 40ms; and the estimated execution time for the "B parallel (D serial C)" task execution sequence is 60ms, meaning that all tasks will be completed by 60ms.

[0144] The total task duration and total computing resources for all task execution sequences corresponding to the subgraph can be determined using the above method. Taking the task execution sequences listed in Table 2 as an example, the total computing resources and total task duration, as well as their product, can be obtained as shown in Table 3.

[0145] Table 3

[0146]

[0147] Based on the above, it can be seen that when the schedulable computing resources are less than 8 IPUs, "B serial (D parallel C)" will be the optimal task execution sequence, and the corresponding 4 IPUs will be the total computing resources of subgraph BCD.

[0148] When the schedulable computing resources are greater than or equal to 8 IPUs, both "B-serial (D-parallel C)" and "B-parallel D-parallel C" satisfy the condition that the total number of computing resources is less than the number of schedulable computing resources. In this case, the optimal task execution sequence can be determined according to the actual situation. That is, if you want to complete the task execution of the entire subgraph quickly, you can choose the task execution order of "B-parallel D-parallel C" and use 8 IPUs as the total number of computing resources for the subgraph; if there are other subgraphs that need to be run in the entire graph task, and the processing urgency of this subgraph is not very high, you can use "B-serial (D-parallel C)" as the task execution order and use 4 IPUs as the total number of computing resources for the subgraph.

[0149] The above method can determine the total number of computing resources required for each subgraph in the graph generation task.

[0150] Next, it is necessary to schedule computing resources for the graph task based on the dependencies between subgraphs and the number of computing resources required for each subgraph. Specifically, the computing resources required for the graph task can be determined based on the dependencies between subgraphs and the number of computing resources required for each subgraph, and the corresponding computing resources can be scheduled for the graph task.

[0151] In determining the computational resources required for a graph task, the maximum number of computational resources required by each subgraph can be used as the computational resources required for the graph task.

[0152] For example, assuming that subgraph A requires 4 IPUs, subgraphs BCD require 8 IPUs, and subgraph E requires 8 IPUs, then the computational resources required for this graph task are 8 IPUs.

[0153] Based on this, when scheduling corresponding computing resources for the image task, the number of quadrants of computing resources required by the graph task and the quadrant constraint relationship between each subgraph of the graph task will be determined first; and computing resources will be scheduled for the image task according to the number of quadrants and the quadrant constraint relationship.

[0154] Figure 11 A schematic diagram of quadrant distribution provided for an embodiment of this application, such as... Figure 11 As shown, when allocating scheduling graphs for the aforementioned graph tasks, the quadrant distribution can be considered.

[0155] Since each quadrant contains 4 IPUs, and the computational resources required for a graph task are 8 IPUs, it is sufficient to allocate 2 quadrants for the graph task. Furthermore, since the dependency relationship between subgraphs is A-BCD-E, the allocation can be as follows: subgraph A is allocated to the first quadrant (4 IPUs); subgraph BCD (e.g., using a task execution sequence where B, D, and C are parallel) has B allocated to the first quadrant (4 IPUs), and DC is allocated to the second quadrant (4 IPUs); subgraph E is allocated to both the first and second quadrants (a total of 8 IPUs).

[0156] Thus, this resource scheduling method allows the computational resources of the entire graph task to be concentrated in two quadrants, reducing data transmission across multiple quadrants and improving the overall operating efficiency of the graph task.

[0157] This invention provides a graph task scheduling method. By determining the number of computing resources required for each subgraph in a graph task, and then scheduling computing resources for the graph task based on the dependencies between subgraphs and the number of computing resources required for each subgraph, the method solves the problems of high time cost and low task processing efficiency in existing graph task scheduling methods.

[0158] Example 2

[0159] Figure 12 This is a schematic diagram of the hardware structure of a computer system provided in this application. Figure 12 As shown, the computer system includes: a host terminal 1210 and a device terminal 1220; wherein,

[0160] The host 1210 is used to determine the number of computing resources required for each subgraph in the graph task; and to determine the task scheduling graph of the graph task based on the dependencies between the subgraphs and the number of computing resources required for each subgraph, wherein the task scheduling graph is used to describe the number of quadrants of computing resources required by the graph task and the quadrant constraint relationships.

[0161] Device 1220 is used to schedule computing resources for the task based on the task scheduling graph issued by the host.

[0162] The device 1220 in the computer system can be used to execute the method described in the aforementioned embodiment 1.

[0163] Example 3

[0164] This application also provides an execution device, including: a memory and a processor;

[0165] Memory; memory for storing executable instructions of the processor;

[0166] The processor is configured as follows:

[0167] Determine the number of computational resources required for each subgraph in the graph task;

[0168] Based on the dependencies between subgraphs and the number of computing resources required for each subgraph, computing resources are scheduled for the graph task.

[0169] Furthermore, the processor is also configured to perform the method described in the first embodiment described above.

[0170] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the graph task scheduling method as described in any one of Embodiment 1.

[0171] The computer-readable storage medium can be any available medium or data storage device that a computer can access, including but not limited to magnetic storage (e.g., floppy disks, hard disks, magnetic tapes, magneto-optical disks (MOs), etc.), optical storage (e.g., CDs, DVDs, BDs, HVDs, etc.), and semiconductor storage (e.g., ROMs, EPROMs, EEPROMs, non-volatile memory (NAND flash), solid-state drives (SSDs)).

[0172] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the graph task scheduling method described in any one of the embodiments.

[0173] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0174] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-executable instructions. These computer-executable instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0175] These computer-executable instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0176] These computer-executable instructions can also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

Claims

1. A scheduling method for graph tasks, characterized in that, Applications to systems comprising host-side devices and execution-side devices include: The host device determines the number of computing resources required for each subgraph in the graph task; wherein, the number of computing resources required for each subgraph is determined based on the number of computing resources required for each task in the subgraph and the execution relationship of each task; the host device schedules computing resources for the graph task based on the dependencies between subgraphs and the number of computing resources required for each subgraph, and determines the task scheduling graph of the graph task; The host device sends the graph task and the task scheduling graph of the graph task to the execution device; The number of computational resources required for each subgraph in the graph determination task includes: For any subgraph, determine the task duration and number of computing resources for each task in the subgraph; Based on the task duration and computing resources of each task, multiple task execution sequences of the subgraph are determined; wherein each task execution sequence includes all tasks in the subgraph and the execution relationships between the tasks; The number of computing resources required for the subgraph is determined based on the number of schedulable computing resources, the total number of computing resources required to execute each task execution sequence, and the total task duration.

2. The scheduling method according to claim 1, characterized in that, The process of determining multiple task execution sequences for the subgraph based on the task duration and computing resource requirements of each task includes: The task priorities of each task are sorted according to the task duration and computing resources required for each task. Based on the priority ranking of each task, various task execution sequences of the subgraph are determined.

3. The scheduling method according to claim 2, characterized in that, The task priority is directly proportional to the number of computing resources available for the task and also directly proportional to the task duration.

4. The scheduling method according to claim 1, characterized in that, The step of determining the number of computing resources required for the subgraph based on the number of schedulable computing resources, the total number of computing resources required to execute each task execution sequence, and the total task duration includes: Determine the product between the total number of computational resources for each task execution sequence and the total task duration; In each task execution sequence, the task execution sequence with the smallest total number of computing resources and the smallest product is determined, and the total number of computing resources of the task execution sequence is taken as the number of computing resources of the subgraph.

5. The scheduling method according to claim 1, characterized in that, The method further includes: Calculate the total number of computing resources required to execute each task sequence and the total task duration.

6. The scheduling method according to claim 5, characterized in that, The calculation of the total number of computing resources required to execute each task execution sequence and the total task duration includes: For any task execution sequence, based on the execution relationship between the tasks in the task execution sequence and the task duration and number of computing resources of each task, determine the maximum number of parallel computing resources required for the task execution sequence to complete each task under its corresponding execution relationship, and use the maximum number of parallel computing resources as the total number of computing resources of the task execution sequence. Based on the execution relationship between tasks in the task execution sequence and the task duration of each task, the estimated execution time until the task execution sequence is completed is taken as the total task duration of the task execution sequence.

7. The scheduling method according to any one of claims 1-6, characterized in that, The step of scheduling computational resources for the graph task based on the dependencies between subgraphs and the number of computational resources required by each subgraph includes: Based on the dependencies between subgraphs and the number of computing resources required for each subgraph, the computing resources required for the graph task are determined, and the corresponding computing resources are scheduled for the graph task.

8. The scheduling method according to claim 7, characterized in that, The computational resources required for the graph determination task include: The maximum number of computing resources required by each subgraph is the computing resources required for the graph task.

9. The scheduling method according to claim 7, characterized in that, The scheduling of corresponding computing resources for the graph task includes: Determine the quadrant number of computational resources required for the graph task and the quadrant constraint relationships between the subgraphs of the graph task; Based on the number of quadrants and the quadrant constraints, computational resources are scheduled for the graph task.

10. A computer system, characterized in that, include: Host side and device side; among them, On the host side, the system determines the number of computing resources required for each subgraph in the graph task. The number of computing resources required for each subgraph is determined based on the number of computing resources required for each task in the subgraph and the execution relationships between the tasks. Based on the dependencies between subgraphs and the number of computing resources required for each subgraph, a task scheduling graph for the graph task is determined. This task scheduling graph represents the number of quadrants of computing resources required by the graph task and the quadrant constraints. The number of computing resources required for each subgraph is determined as follows: for any subgraph, the task duration and number of computing resources for each task in the subgraph are determined; based on the task duration and number of computing resources for each task, multiple task execution sequences for the subgraph are determined; each task execution sequence includes all tasks in the subgraph and the execution relationships between them; and based on the number of schedulable computing resources, the total number of computing resources required to execute each task execution sequence, and the total task duration, the number of computing resources required for the subgraph is determined. On the device side, it is used to schedule computing resources for the task based on the task scheduling graph issued by the host.

11. An execution device, comprising: Memory, processor; Memory; Memory used to store the processor's executable instructions; The processor is configured as follows: Determine the number of computational resources required for each subgraph in the graph task; Based on the dependencies between subgraphs and the number of computing resources required for each subgraph, computing resources are scheduled for the graph task. The processor is specifically configured to: for any subgraph, determine the task duration and number of computing resources for each task in the subgraph; determine multiple task execution sequences for the subgraph based on the task duration and number of computing resources for each task; wherein each task execution sequence includes all tasks in the subgraph and the execution relationships between the tasks; and determine the number of computing resources required for the subgraph based on the number of schedulable computing resources, the total number of computing resources required to execute each task execution sequence, and the total task duration.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the graph task scheduling method as described in any one of claims 1 to 9.

13. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the graph task scheduling method according to any one of claims 1 to 9.

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