A method and system for satellite computer initialization monitoring and maintenance

Abstract

The application relates to the technical field of satellite computer software, and provides a satellite computer initialization monitoring and maintenance method, which comprises the following steps: S1: initializing a processor of a satellite computer in a power-on starting process of a programmable memory (PROM); S2: after the processor of the satellite computer is initialized, initializing a memory SDRAM; and S3: after the memory SDRAM is initialized, entering a judgment process comprising a remote control privilege mode, a serial port privilege mode and a normal starting mode. The satellite computer can detect and maintain the memory state in the starting process, and the reliability of a satellite is ensured.

Description

Technical Field

[0001] This invention relates to the technical field of spaceborne computer software, and in particular to a method and system for initialization monitoring and maintenance of a spaceborne computer. Background Technology

[0002] Artificial satellites operate in the harsh environment of space. During their operation in orbit, the onboard electronic systems can malfunction due to factors such as space radiation, which can alter their operating system images and application software files. Therefore, the initialization process of the onboard electronic systems' software requires testing and maintenance to assess their operational status and ensure the reliability of the satellite's operation. Summary of the Invention

[0003] To address the aforementioned problems, the present invention aims to provide a method and system for monitoring and maintaining the initialization of a spaceborne computer, thereby enabling the detection and maintenance of the memory status of the spaceborne computer during startup and ensuring the reliability of the satellite's operation.

[0004] The above-mentioned objective of this invention is achieved through the following technical solutions:

[0005] A method for initial monitoring and maintenance of a spaceborne computer includes the following steps:

[0006] S1: During the power-on startup process of the programmable memory (PROM), the processor of the onboard computer is initialized;

[0007] S2: After the processor of the onboard computer is initialized, the SDRAM memory is initialized;

[0008] S3: After the SDRAM initialization is completed, the system enters a judgment process that includes remote control privilege mode, serial port privilege mode and normal startup mode.

[0009] Further, in step S1, during the power-on startup process of the programmable memory (PROM), the processor of the onboard computer is initialized, specifically as follows:

[0010] During the initialization process of the programmable memory PROM, registers including the MSR register and the floating-point register are cleared.

[0011] After the programmable memory (PROM) is initialized, the pointer is set to point to the SDRAM memory.

[0012] Further, in step S2, the SDRAM memory is initialized, specifically as follows:

[0013] The SDRAM memory is refreshed to all zeros, the instruction cache (I Cache) and data cache (D Cache) are disabled, the instruction register (I BAT) and data register (DBAT) are cleared, and the TLB cache is cleared.

[0014] Initialize the instruction register I BAT and the data register DBAT, and set the SP pointer;

[0015] Copy the Text segment (containing code) and the Data segment (containing data) from the programmable memory (PROM) to the main memory (SDRAM), and clear the BSS segment.

[0016] Further, in step S3, a judgment process including the remote control privileged mode, the serial port privileged mode, and the normal startup mode is entered, specifically as follows:

[0017] S31: Use a watchdog reset counter to count, and read the watchdog reset counter;

[0018] S32: If the watchdog reset counter count is 0, proceed to step S38;

[0019] S33: If the watchdog reset counter counts to 1, record the current time as T1, store it in the ADDR1 address in the static random access memory (SRAM), and proceed to step S38.

[0020] S34: If the watchdog reset counter counts to 2, record the current time as T2, store it in the ADDR2 address in the static random access memory (SRAM), and proceed to step S38.

[0021] S35: If the watchdog reset counter counts to 3, record the current time as T3, store it in the ADDR3 address in the static random access memory (SRAM), and proceed to step S37.

[0022] S36: If the watchdog reset counter counts to 4, record the current time as T4, obtain T3 and T2 from the ADDR3 address and the ADDR2 address, and store T4, T3 and T2 in the ADDR3 address, the ADDR2 address and the ADDR1 address in sequence;

[0023] S37: Obtain T3 and T1 from the ADDR3 address and the ADDR1 address. If the time difference between T3 and T1 is greater than the preset time interval, proceed to step S38; otherwise, proceed to the remote control privilege mode.

[0024] S38: Enter the serial port privilege judgment program. If the time difference between T3 and T1 is less than the preset time interval, and there is a privileged instruction on the communication serial port within 100ms, then enter the serial port privilege mode; otherwise, enter the normal startup mode.

[0025] Furthermore, the preset time interval is 9 minutes.

[0026] Furthermore, T1, T2, T3 and T4 are timed using an FPGA master clock.

[0027] Furthermore, in the remote control privileged mode, the satellite's attitude is not controlled, and uplink commands from the ground station are received; in the serial port privileged mode, remote control commands from the satellite are received and forwarded through the serial port, and the satellite's attitude is controlled normally; in the normal startup mode, the onboard computer is loaded and started normally.

[0028] An onboard computer initialization monitoring and maintenance system for performing the onboard computer initialization monitoring and maintenance method as described above includes:

[0029] The processor initialization module is used to initialize the processor of the onboard computer during the power-on startup process of the programmable memory (PROM).

[0030] The memory initialization module is used to initialize the SD RAM after the processor of the onboard computer is initialized.

[0031] The mode determination module is used to enter a determination process including remote control privileged mode, serial port privileged mode and normal startup mode after the SDRAM initialization is completed.

[0032] A computer device includes a memory and one or more processors, the memory storing computer code that, when executed by the one or more processors, causes the one or more processors to perform the method described above.

[0033] A computer-readable storage medium storing computer code that, when executed, performs the method described above.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] A method for initializing, monitoring, and maintaining an onboard computer is provided, comprising the following steps: S1: During the power-on startup process of the programmable memory (PROM), the processor of the onboard computer is initialized; S2: After the processor of the onboard computer is initialized, the SDRAM memory is initialized; S3: After the SDRAM memory initialization is completed, a judgment process including remote control privileged mode, serial port privileged mode, and normal startup mode is entered. This technical solution enables the detection and maintenance of the memory status of the onboard computer during startup, ensuring the reliability of the satellite's operation. Attached Figure Description

[0036] Figure 1 This is an overall flowchart of a method for initializing, monitoring, and maintaining a spaceborne computer according to the present invention;

[0037] Figure 2 This is a detailed flowchart of a method for initializing, monitoring, and maintaining a spaceborne computer according to the present invention;

[0038] Figure 3 This is a flowchart illustrating the determination process for remote control privileged mode, serial port privileged mode, and normal startup mode in this invention.

[0039] Figure 4 This is an overall structural diagram of a spaceborne computer initialization monitoring and maintenance system according to the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0042] First Embodiment

[0043] like Figure 1 and 2 As shown, a method for initial monitoring and maintenance of a spaceborne computer is characterized by comprising the following steps:

[0044] S1: During the power-on startup process of the programmable memory (PROM), the processor of the onboard computer is initialized.

[0045] Specifically, the onboard computer in this embodiment uses a PowerPC 750 processor (a high-performance 32-bit and 64-bit RI SC microprocessor series jointly developed by Motorola and Apple) for initialization. The PowerPC 750 processor initialization operation is performed during the power-on startup process of the programmable memory (PROM).

[0046] The specific process for processor initialization is as follows: during the initialization of the programmable memory PROM, registers including the MSR register (Mode 1 Special Register, a set of 64-bit registers of the CPU) and floating-point registers are cleared; after the programmable memory PROM is initialized, the pointer is pointed to the memory SDRAM (synchronous dynamic random-access memory).

[0047] S2: After the processor of the onboard computer is initialized, the SDRAM memory is initialized, specifically as follows:

[0048] The process involves clearing the SDRAM to all zeros, disabling the instruction cache (I Cache, used to cache instructions) and data cache (D Cache, used to cache data), clearing the instruction register (IBAT) and data register (DBAT), and clearing the TLB (Translation Lookaside Buffer, a memory management unit used to improve the speed of virtual address to physical address translation. The TLB is a small, virtual addressing cache where each line stores a block of single PTEs (Page Table Entry). Without a TLB, each data retrieval requires two memory accesses: looking up the page table to obtain the physical address and retrieving the data.)

[0049] Initialize the instruction register IBAT and the data register DBAT, and set the SP pointer (Stack Pointer, also a general-purpose register used for push and pop operations);

[0050] Copy the Text segment (containing code) and the Data segment (containing data) from the programmable memory (PROM) to the main memory (SDRAM). Clear the BSS segment (which contains global and static variables that are defined but not initialized; it usually only records the variable name and size, acting as a placeholder) to zero.

[0051] S3: After the SDRAM initialization is completed, as follows Figure 3 As shown, the judgment process for entering remote privileged mode, serial port privileged mode, and normal startup mode is as follows:

[0052] S31: Use a watchdog reset counter (WDT, Watch Dog Timer is a component of a microcontroller, it is actually a counter) to count and read the watchdog reset counter;

[0053] S32: If the watchdog reset counter count is 0, proceed to step S38;

[0054] S33: If the watchdog reset counter counts to 1, record the current time as T1, store it in the ADDR1 address in the static random-access memory (SRAM), and proceed to step S38;

[0055] S34: If the watchdog reset counter counts to 2, record the current time as T2, store it in the ADDR2 address in the static random access memory (SRAM), and proceed to step S38.

[0056] S35: If the watchdog reset counter counts to 3, record the current time as T3, store it in the ADDR3 address in the static random access memory (SRAM), and proceed to step S37.

[0057] S36: If the watchdog reset counter counts to 4, record the current time as T4, obtain T3 and T2 from the ADDR3 address and the ADDR2 address, and store T4, T3 and T2 in the ADDR3 address, the ADDR2 address and the ADDR1 address in sequence;

[0058] S37: Obtain T3 and T1 from the ADDR3 address and the ADDR1 address. If the time difference between T3 and T1 is greater than the preset time interval, proceed to step S38; otherwise, proceed to the remote control privilege mode.

[0059] S38: Enter the serial port privilege judgment program. If the time difference between T3 and T1 is less than the preset time interval, and there is a privileged instruction on the communication serial port within 100ms, then enter the serial port privilege mode; otherwise, enter the normal startup mode.

[0060] Furthermore, the preset time interval is 9 minutes.

[0061] Furthermore, T1, T2, T3 and T4 are timed using an FPGA master clock.

[0062] Furthermore, in the remote control privileged mode, the satellite's attitude is not controlled, and uplink commands from the ground station are received; in the serial port privileged mode, remote control commands from the satellite are received and forwarded through the serial port, and the satellite's attitude is controlled normally; in the normal startup mode, the onboard computer is loaded and started normally.

[0063] Second Embodiment

[0064] like Figure 4 As shown, this embodiment provides a spaceborne computer initialization monitoring and maintenance system for executing the spaceborne computer initialization monitoring and maintenance method as described in the first embodiment, comprising:

[0065] Processor initialization module 1 is used to initialize the processor of the onboard computer during the power-on startup process of the programmable memory PROM;

[0066] The memory initialization module 2 is used to initialize the SDRAM memory after the processor of the onboard computer is initialized.

[0067] The mode determination module 3 is used to enter a determination process including remote control privilege mode, serial port privilege mode and normal startup mode after the SDRAM initialization is completed.

[0068] A computer-readable storage medium stores computer code that, when executed, performs the methods described above. Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. This program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk, etc.

[0069] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

[0070] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0071] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for initialization monitoring and maintenance of a spaceborne computer, characterized in that, Includes the following steps: S1: During the power-on startup process of the programmable memory (PROM), the processor of the onboard computer is initialized; S2: After the processor of the onboard computer is initialized, the SDRAM memory is initialized; S3: After the SDRAM initialization is completed, the process of judging remote privilege mode, serial port privilege mode and normal startup mode is entered; In step S3, a judgment process is initiated, including the remote control privileged mode, the serial port privileged mode, and the normal startup mode, specifically as follows: S31: Use a watchdog reset counter to count, and read the watchdog reset counter; S32: If the watchdog reset counter count is 0, proceed to step S38; S33: If the watchdog reset counter counts to 1, record the current time as T1, store it in the ADDR1 address in the static random access memory (SRAM), and proceed to step S38. S34: If the watchdog reset counter counts to 2, record the current time as T2, store it in the ADDR2 address in the static random access memory (SRAM), and proceed to step S38. S35: If the watchdog reset counter counts to 3, record the current time as T3, store it in the ADDR3 address in the static random access memory (SRAM), and proceed to step S37. S36: If the watchdog reset counter counts to 4, record the current time as T4, obtain T3 and T2 from the ADDR3 address and the ADDR2 address, and store T4, T3 and T2 in the ADDR3 address, the ADDR2 address and the ADDR1 address in sequence; S37: Obtain T3 and T1 from the ADDR3 address and the ADDR1 address. If the time difference between T3 and T1 is greater than the preset time interval, proceed to step S38; otherwise, proceed to the remote control privilege mode. S38: Enter the serial port privilege judgment program. If the time difference between T3 and T1 is less than the preset time interval, and there is a privileged instruction on the communication serial port within 100ms, then enter the serial port privilege mode; otherwise, enter the normal startup mode.

2. The method for initial monitoring and maintenance of a spaceborne computer according to claim 1, characterized in that, In step S1, during the power-on startup process of the programmable memory (PROM), the processor of the onboard computer is initialized, specifically as follows: During the initialization process of the programmable memory PROM, registers including the MSR register and the floating-point register are cleared. After the programmable memory (PROM) is initialized, the pointer is set to point to the SDRAM memory.

3. The method for initial monitoring and maintenance of a spaceborne computer according to claim 1, characterized in that, In step S2, the SDRAM memory is initialized, specifically as follows: The SDRAM memory is refreshed to all zeros, the instruction cache (ICache) and data cache (DCache) are disabled, the instruction register (IBAT) and data register (DBAT) are cleared, and the TLB cache is cleared. Initialize the instruction register IBAT and the data register DBAT, and set the SP pointer; Copy the Text segment (containing code) and the Data segment (containing data) from the programmable memory (PROM) to the main memory (SDRAM), and clear the BSS segment.

4. The method for initial monitoring and maintenance of a spaceborne computer according to claim 1, characterized in that, The preset time interval is 9 minutes.

5. The method for initial monitoring and maintenance of a spaceborne computer according to claim 1, characterized in that, T1, T2, T3 and T4 are timed using the FPGA master clock.

6. The method for initial monitoring and maintenance of a spaceborne computer according to claim 1, characterized in that, Also includes: In the remote control privileged mode, the satellite's attitude is not controlled, and uplink commands are received from the ground station; In the privileged serial port mode, remote control commands from the satellite are received and forwarded via the serial port, and the satellite's attitude is controlled normally. In the normal startup mode, the onboard computer loads and starts normally.

7. A spaceborne computer initialization monitoring and maintenance system for performing the spaceborne computer initialization monitoring and maintenance method as described in any one of claims 1-6, characterized in that, include: The processor initialization module is used to initialize the processor of the onboard computer during the power-on startup process of the programmable memory (PROM). The memory initialization module is used to initialize the SDRAM memory after the processor of the onboard computer is initialized. The mode determination module is used to enter a determination process including remote control privileged mode, serial port privileged mode and normal startup mode after the SDRAM initialization is completed.

8. A computer device comprising a memory and one or more processors, the memory storing computer code that, when executed by the one or more processors, causes the one or more processors to perform the method as described in any one of claims 1 to 6.

9. A computer-readable storage medium storing computer code, wherein when the computer code is executed, the method of any one of claims 1 to 6 is performed.

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