Flash memory protection method and apparatus, electronic device, and storage medium

Abstract

The application provides a flash memory protection method and device, electronic equipment and a storage medium. The method comprises the following steps: a processor acquires a first instruction; the processor acquires first indication information corresponding to the first flash memory area from the register, and the first indication information is used for indicating the erasing and writing permission of the first flash memory area, wherein the first indication information is pre-configured into the register; when the first indication information indicates that the erasing and writing permission of the first flash memory area is erasable and writable, the processor executes the instruction to erase information in the first flash memory area or write information into the first flash memory area; and when the first indication information indicates that the erasing and writing permission of the first flash memory area is not erasable and writable, the processor feeds back an abnormal operation.

Description

Technical Field

[0001] This application relates to the field of automotive chips, and more particularly to a flash memory protection method, apparatus, electronic device, and storage medium. Background Technology

[0002] Flash memory in automotive devices employs various data protection mechanisms, each with its own advantages in read, write, and erase protection. However, current methods protect the flash memory as a whole. This means that when erasing or writing information stored in a portion of the flash memory, some unalterable information may be accidentally erased or modified, leading to unforeseen errors in the flash memory information stored in the automotive device and causing malfunctions in the chip. Therefore, how to achieve refined protection of the information stored in the flash memory of automotive devices is a pressing technical problem that needs to be solved. Summary of the Invention

[0003] This application provides a flash memory protection method, apparatus, electronic device, and storage medium. First, the flash memory is divided into regions to prevent unintended erasure and modification of data in the flash memory, which could lead to abnormal chip operation.

[0004] In a first aspect, embodiments of this application provide a flash memory data protection method applied to an in-vehicle device, wherein the in-vehicle device includes a processor, flash memory, and registers, and the method includes:

[0005] The processor acquires a first instruction, wherein the first instruction is used to erase information in a first flash memory area or write information to the first flash memory area, the first flash memory area being any one of a plurality of flash memory areas obtained by partitioning the flash memory, the plurality of flash memory areas including at least one flash memory area for storing data and at least one flash memory area for storing programs;

[0006] The processor obtains first indication information corresponding to the first flash memory region from the register. The first indication information is used to indicate the erase / write permission of the first flash memory region. The first indication information is pre-configured in the register.

[0007] When the first indication information indicates that the erase / write permission of the first flash memory area is erasable and writable, the processor executes the instruction to erase information in the first flash memory area or write information to the first flash memory area;

[0008] When the first indication information indicates that the erase / write permission for the first flash memory area is non-erasable, the processor reports an abnormal operation.

[0009] A second aspect provides an in-vehicle device, the device including a processor, flash memory, and registers;

[0010] The processor is configured to acquire a first instruction, wherein the first instruction is configured to erase information stored in a first flash memory region or write information to the first flash memory region, wherein the first flash memory region is any one of a plurality of flash memory regions obtained by partitioning the flash memory, and the plurality of flash memory regions include at least one flash memory region for storing data and at least one flash memory region for storing programs.

[0011] The processor is configured to obtain first indication information corresponding to the first flash memory region from the register, the first indication information being used to indicate the erase / write permission of the first flash memory region, wherein the first indication information is pre-configured in the register;

[0012] The processor is configured to execute the instruction to erase information in the first flash memory area or write information to the first flash memory area when the first indication information indicates that the erase / write permission of the first flash memory area is erasable / writable.

[0013] The processor is configured to report an abnormal operation when the first indication information indicates that the erase / write permission for the first flash memory area is non-erasable.

[0014] Thirdly, embodiments of this application provide an electronic device, including: a processor connected to a memory for storing a computer program, and the processor for executing the computer program stored in the memory to cause the electronic device to perform the method as described in the first aspect.

[0015] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that causes a computer to perform the method as described in the first aspect.

[0016] Fifthly, embodiments of this application provide a computer program product, the computer program product including a non-transitory computer-readable storage medium storing a computer program, and a computer operable to perform the method as described in the first aspect.

[0017] The above-mentioned solution in this application includes at least the following beneficial effects:

[0018] In this embodiment, the processor first obtains a first instruction, which is used to erase information stored in a first flash memory region or write information to the first flash memory region. The first flash memory region is any one of multiple flash memory regions obtained by dividing the flash memory. Then, the processor obtains first indication information corresponding to the first flash memory region from a register. The first indication information is used to indicate the erase / write permissions of the first flash memory region, and is pre-configured in the register. Furthermore, when the first indication information indicates that there is permission to erase / write the first flash memory region, the processor executes the instruction. When the first indication information indicates that there is no permission to erase / write the first flash memory region, the processor reports an operation error. This application divides the flash memory into regions, providing fine-grained protection for information in each region. Using indication information to represent erase / write permissions prevents unintended erasure and modification of information in the flash memory, thus improving the flash memory protection mechanism and preventing abnormal chip operation. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A system architecture diagram of a flash memory protection method provided in this application embodiment;

[0021] Figure 2 A schematic flowchart illustrating a flash memory protection method provided in an embodiment of this application;

[0022] Figure 3 A schematic diagram illustrating the partitioning of a program flash memory region as provided in an embodiment of this application;

[0023] Figure 4 A schematic diagram illustrating the partitioning of a data flash memory region provided in an embodiment of this application;

[0024] Figure 5 This application provides a schematic diagram of a process for configuring indication information for a flash memory region.

[0025] Figure 6 This is a schematic diagram illustrating how multiple input data from multiple flash memory regions in each flash memory combination are spliced ​​together, as provided in an embodiment of this application.

[0026] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0028] The terms "comprising" and "having," and any variations thereof, appearing in this specification, claims, and drawings, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. Furthermore, the terms "first," "second," and "third," etc., are used to distinguish different objects and are not used to describe a specific order.

[0029] See Figure 1 , Figure 1 A system architecture for an in-vehicle device is provided in this application embodiment. The system architecture diagram includes flash memory 10, registers 20, and processor 30. The flash memory 10, registers 20, and processor 30 are connected via a bus.

[0030] First, the processor 30 divides the flash memory 10 into multiple flash memory regions based on the flash memory partition information. For example... Figure 1 As shown, the flash memory can be set as flash memory region 1, flash memory region 2, flash memory region 3, ..., flash memory region n. Then, the corresponding fields are set in register 20 for each flash memory region, such as... Figure 1 The fields 1, 2, 3, ..., n are shown; then, the processor 30 configures indication information in the register 20 in the vertical direction for each flash memory region, and the indication information for each flash memory region is used to indicate the erase and write permissions of that flash memory region;

[0031] When the processor 30 receives a first instruction, wherein the first instruction is used to erase information in a first flash memory region or write information to a first flash memory region, the first flash memory region being any one of the plurality of flash memory regions; in response to the first instruction, the processor 30 obtains first indication information corresponding to the first flash memory region from the register 20, wherein the first indication information is used for the erase / write permission of the first flash memory region; when the first indication information indicates that the erase / write permission of the first flash memory region is erasable / writable, the processor executes the instruction to erase information stored in the first flash memory region or write information to the first flash memory region; when the first indication information indicates that the erase / write permission of the first flash memory region is not erasable / writable, the processor reports an abnormal operation.

[0032] As can be seen, in this embodiment, the flash memory is divided into regions to provide more refined protection for the information in each region. Indicator information is used to represent write / erase permissions, preventing unintended erasure and modification of information in the flash memory. This improves the flash memory protection mechanism and prevents abnormal chip operation.

[0033] Please see Figure 2 , Figure 2 This is a flowchart illustrating a flash memory protection method provided in an embodiment of this application. The method is applied to in-vehicle devices, such as... Figure 2 As shown, steps 201-204 are included:

[0034] 201: The processor fetches its first instruction.

[0035] First, the processor acquires flash memory partitioning information, which divides the flash memory into multiple flash memory regions. These regions include at least one flash memory region for storing data and at least one flash memory region for storing programs. In this embodiment, the flash memory region for storing data can be referred to as the data flash memory region, and the flash memory region for storing programs can be referred to as the program flash memory region. Then, the processor configures corresponding indication information in registers for each flash memory region. The process of configuring the indication information will be described in detail later and will not be elaborated upon here.

[0036] like Figure 3 As shown, the flash memory can be divided into 44 program flash memory regions, and the size of each program flash memory region is set to 16kb; correspondingly, 44 bits of indicator information are set in the register, that is, one bit of indicator information is set for each program flash memory region.

[0037] like Figure 4As shown, the flash memory can be divided into 8 data flash memory regions, and the size of each data flash memory region is set to 16kb; correspondingly, 8 bits of indicator information are set in the register, that is, one bit of indicator information is set for each data flash memory region.

[0038] Furthermore, the processor acquires a first instruction, which is received by the on-board device and forwarded to the processor for processing. This first instruction is used to erase information in a first flash memory region or write information to a first flash memory region, which is any one of multiple flash memory regions obtained by dividing the flash memory.

[0039] 202: The processor retrieves the first indication information corresponding to the first flash memory region from the register.

[0040] In this embodiment, the first indication information is used to indicate the erase / write permissions of the first flash memory region, wherein the first indication information is pre-configured in a register. The erase / write permissions of the first flash memory region are either erasable / writable or non-erasable / writable, wherein erasable / writable means that information in the first flash memory region can be erased or information can be written to the first flash memory region; non-erasable / writable means that information in the first flash memory region cannot be erased or information can be written to the first flash memory region.

[0041] The first instruction includes a serial number of the first flash memory region and an erase / write instruction. Specifically, the processor can parse the first instruction and, based on the erase / write instruction and the serial number, determine that the first instruction is used to erase or write the first flash memory region. Further, after receiving the first instruction, the processor can retrieve the first indication information of the first flash memory region from a register.

[0042] Specifically, the processor can obtain the address range of the first flash memory region based on its serial number. Then, based on the mapping relationship between the address range and the fields, and the address range of the first flash memory region, the processor determines the field corresponding to the first flash memory region in the register; and obtains the first indication information from the field. Specifically, the processor can send an I2C command timing sequence via the bus, that is, the processor sends an I2C command timing sequence to the bus to address the register; then, the processor sends the address and read indication of the first flash memory region to the bus. Correspondingly, after the register obtains the address and read indication of the first flash memory region, it can read the indication information of the field corresponding to the address of the first flash memory region, that is, the first indication information, to the processor.

[0043] Furthermore, the erase / write permissions for the first flash memory area are indicated according to the value of the first indication information. Specifically, when the value of the first indication information is 1, it indicates that there is no permission to erase / write the first flash memory area. When the value of the first indication information is 0, it indicates that there is permission to erase / write the first flash memory area.

[0044] 203: When the first instruction indicates that the processor has permission to erase and write to the first flash memory area, the processor executes the instruction.

[0045] For example, when the processor determines that it has erase / write permissions for the first flash memory area based on the first instruction information, it will erase / write the first flash memory area when it is necessary to do so.

[0046] 204: When the first indication information indicates that there is no permission to erase or write to the first flash memory area, the processor reports an operation error.

[0047] For example, when the first instruction is sent to the in-vehicle device by a third-party device, the processor can send a feedback message indicating an operational error to the third-party device via the in-vehicle device's network card. When the first instruction is sent to the processor by the user through the in-vehicle device's input-output device, an operational error message is displayed on the in-vehicle device's screen.

[0048] As can be seen, in this embodiment, after obtaining the indication information of the first flash memory area, the processor can determine whether permission is granted based on the indication information. The indication information can be 1 or 0. If the indication information is 1, the corresponding flash memory area is unprotected. If the indication information is 0, the corresponding flash memory area is protected. When the indication information is 0, the processor reports an operation error. When the indication information is 1, the processor executes a first instruction to erase or rewrite the data in the first flash memory area.

[0049] See Figure 5 , Figure 5 This is a schematic diagram illustrating a process for configuring indication information for a flash memory region, as provided in an embodiment of this application. The process includes, but is not limited to, the following steps:

[0050] 501: The processor obtains the flash memory partition information of the flash memory, the flash memory partition information including the starting address of each flash memory region, the size of each flash memory region, and the attributes of each flash memory region, the attributes of each flash memory region indicating that the flash memory region is used to store programs or data.

[0051] Optionally, the flash memory partition information can be sent to the processor of the vehicle-mounted device by other devices, or it can be pre-configured to the processor; this application does not limit this. The attributes of each flash memory region indicate whether the flash memory region is used to store programs or data, that is, whether each flash memory region is program flash memory or data flash memory.

[0052] 502: The processor loads the system program and system data of the vehicle-mounted device.

[0053] 503: The processor determines the address range of each flash memory region based on the starting address of each flash memory region and the size of each flash memory region.

[0054] For example, the processor can determine the ending address of each flash memory region based on the starting address of each flash memory region and the size of each flash memory region, and thus determine the address range of each flash memory region.

[0055] 504: The processor determines the erase / write permissions for each flash memory region based on the address range of each flash memory region, the attributes of each flash memory region, the system program, and the system data.

[0056] Optionally, based on the size and attributes of each flash memory region, multiple allocation operations are performed on the plurality of flash memory regions to obtain multiple flash memory combinations. Each allocation operation includes allocating at least one first target flash memory region from the plurality of flash memory regions for storing system programs, the size of which is greater than or equal to the size of the system programs; and allocating at least one second target flash memory region for storing system data, the size of which is greater than or equal to the size of the system data.

[0057] In other words, during each allocation, at least one first target flash memory region needs to be selected from the flash memory regions designated for storing programs, and the size of this at least one first target flash memory region must be greater than or equal to the size of the system program, so that the system program can be subsequently written to this at least one first target flash memory region. Similarly, system data is written to at least one second target flash memory region.

[0058] It should be understood that, because this application divides the flash memory into multiple flash memory regions for storing data and multiple flash memory regions for storing programs, the first target flash memory and the second target flash memory selected each time an allocation is made may not be exactly the same.

[0059] Further, based on the attributes of each flash region in the plurality of flash regions, a target attribute for each flash region in each flash combination is determined, wherein the target attribute of the first target flash region in each flash combination is for storing system programs, the target attribute of the second target flash region is for storing system data, and the target attribute of the remaining flash regions is for storing non-system programs or non-system data. The remaining flash regions are the flash regions in each flash combination other than at least one target flash region and at least one second target flash region.

[0060] It should be understood that, for each flash memory combination, after selecting the first and second target flash memory regions, the target attribute of each first target flash memory region can be set to store system programs, and the target attribute of each second target flash memory region can be set to store system data. For the remaining flash memory regions, if the attribute of the remaining flash memory region is for storing programs, then the attribute of the remaining flash memory region is set to store non-system programs (i.e., for storing user programs); if the attribute of the remaining flash memory region is for storing data, then the attribute of the remaining flash memory region is set to store non-system data (i.e., for storing user data). It can be seen that the target attribute of each flash memory region in each flash memory combination can be set based on the attribute of each flash memory region.

[0061] Then, based on the address range of each flash region in each flash memory combination and the target attributes of each flash region, the bad block rate of each flash region in each flash memory combination is determined.

[0062] like Figure 6 As shown, based on the size, address range, and target attributes of each flash region in each flash memory combination, the input data for each flash region in each flash memory combination is determined. Optionally, the target of each flash region in each flash memory combination is encoded to obtain the attribute encoding value of each flash region. For example, attribute encoding value 00 indicates that the target attribute is for storing system programs, 11 indicates that the target attribute is for storing system data; 01 indicates that the target attribute is for storing non-system programs, and 10 indicates that the target attribute is for storing non-system data. Then, the address range, size, and attribute encoding value of each flash region in each flash memory combination are sequentially combined to obtain the input data for each flash region in each flash memory combination; further, as shown... Figure 6 As shown, multiple input data from multiple flash regions in each flash memory combination are concatenated to obtain the data to be processed for each flash memory combination; the data to be processed for each flash memory combination is then input into a pre-trained bad block prediction model to obtain the bad block rate for each flash region in each flash memory combination.

[0063] The training process for the bad block prediction model is described below. This training process can be performed on other devices and then configured onto the vehicle-mounted device, or it can be trained by the vehicle-mounted device itself; this application does not limit this to either method.

[0064] For example, firstly, multiple training samples are obtained, where each training sample represents the partition information of a flash memory, including the number of partitions in the flash memory, the size of each flash memory partition, the starting address, and the target attributes of each flash memory region. Each training sample is labeled as whether each flash memory region contains bad blocks.

[0065] Therefore, based on the partition information of each training sample, the target attribute of each flash memory region in each training sample can be encoded to obtain the attribute encoding value of each flash memory region. Similarly, based on the attribute encoding value, the training data corresponding to each training sample can be obtained. Then, the initial model is trained using the training data corresponding to each training sample to predict the bad block rate of each flash memory region in each training sample, that is, the probability that the flash memory region will become a bad block when it is used later. Then, based on the predicted bad block rate of each flash memory region and the actual bad block rate (i.e., label) of each flash memory region, the loss corresponding to each training sample is determined. Based on the loss corresponding to each training sample, the target loss is determined. The model parameters of the initial model are adjusted according to the target loss to obtain the bad block prediction model mentioned above. Among them, the model parameters of the initial model can be adjusted based on the gradient descent method until the initial model converges to obtain the bad block prediction model.

[0066] For example, the loss of the i-th training sample can be expressed by formula (1):

[0067]

[0068] Among them, Loss i M is the loss for the i-th training sample. j Let p(j) be the number of flash memory regions in the i-th training sample, and p(j) be the true bad block rate of the j-th flash memory region in the i-th training sample. Let be the predicted bad block rate of the j-th flash memory region.

[0069] For example, the target loss can be expressed by formula (2):

[0070]

[0071] Among them, Loss g The target loss is N, where N is the number of training samples.

[0072] Furthermore, the loss cost for each flash memory combination is calculated based on the bad block probability of each flash memory region within each flash memory combination and the target attribute of each flash memory region. Specifically, a weight coefficient for each flash memory region is determined based on its target attribute. For example, a relatively large weight coefficient can be set for a flash memory region whose target attribute is to store system programs or system data. Therefore, for automotive devices, anomalies in system programs or system data are intolerable errors that will lead to operational failures; hence, a relatively large weight coefficient can be set for such flash memory regions. Finally, the bad block rate of each flash memory region is weighted according to the weight coefficient of each flash memory region in each flash memory combination to obtain the loss cost for each flash memory combination.

[0073] Finally, the flash memory combination with the lowest cost of loss is selected as the target flash memory combination. For the target flash memory combination, the erase / write permissions of the first and second target flash memory regions within the target flash memory combination can be set to non-erasable, meaning that information in the first and second target flash memory regions cannot be erased or written. Then, the permissions of the remaining flash memory regions are set to erasable, thus obtaining the erase / write permissions of each flash memory region in the target flash memory combination, and consequently, the erase / write permissions of each of the multiple flash memory regions divided in this application.

[0074] 505: The processor configures indication information for each flash memory region in the field corresponding to the address range of each flash memory region in the register according to the erase / write permissions of each flash memory region.

[0075] For example, the processor configures the indication information for each flash memory region in a field in the register corresponding to the address range of each flash memory region, based on the erase / write permissions of each flash memory region. In other words, the erase / write permissions of each flash memory region are indicated by the indication information.

[0076] In one embodiment of this application, after dividing the flash memory area into multiple flash memory areas and configuring indication information for each flash memory area based on the erase / write permissions of each flash memory area, when the processor receives a second instruction, wherein the second instruction is used to erase and rewrite the indication information of the second flash memory area among the multiple flash memory areas; the processor determines the field in the register corresponding to the second flash memory area according to the address range of the second flash memory area; the processor erases the indication information configured in the field and rewrites the indication information.

[0077] For example, the processor can erase the indication information in the second flash memory area from 1 and rewrite it to 0. This second instruction can be an FTFC command. It should be noted that when obtaining the second instruction to adjust the indication information in the second flash memory area, the flash memory configuration fields must be correctly rewritten before the on-board equipment is powered on again or woken from standby; otherwise, the flash memory will be permanently locked and the debugger cannot be connected again.

[0078] According to one embodiment of this application, Figure 1The various units of the vehicle-mounted device shown can be individually or entirely combined into one or more other units, or some of the units can be further divided into multiple functionally smaller units. This achieves the same operation without affecting the technical effects of the embodiments of this application. The above-mentioned units are based on logical function division. In practical applications, the function of one unit can also be implemented by multiple units, or the function of multiple units can be implemented by one unit. In other embodiments of this application, the vehicle-mounted device may also include other units. In practical applications, these functions can also be implemented with the assistance of other units, and can be implemented collaboratively by multiple units.

[0079] According to another embodiment of this application, the following can be achieved by running on a general-purpose computing device, such as a computer, which includes processing elements and storage elements such as a central processing unit (CPU), random access memory (RAM), and read-only memory (ROM), a device capable of performing operations such as... Figure 1 The computer program (including program code) for each step involved in the corresponding method shown, to construct such... Figure 1 The vehicle-mounted device shown herein, and the flash memory protection method for implementing embodiments of this application, are described. A computer program may be recorded on, for example, a computer-readable recording medium, loaded onto the aforementioned computing device via the computer-readable recording medium, and executed therein.

[0080] Based on the description of the method and apparatus embodiments above, this application also provides an electronic device. Please refer to... Figure 7 The electronic device includes at least a processor 701, a register 702, a flash memory 703, and a memory 704. The processor 701, register 702, flash memory 703, and memory 704 within the electronic device can be connected via a bus or other means.

[0081] The memory 704 can be stored in the memory of the electronic device. The memory 704 is used to store computer programs, which include program instructions. The processor 701 is used to execute the program instructions stored in the memory 704. The processor 701 (or CPU (Central Processing Unit)) is the computing and control core of the electronic device. It is suitable for implementing one or more instructions, specifically for loading and executing one or more instructions to achieve the corresponding method flow or corresponding function.

[0082] In one embodiment, the processor 701 of the electronic device provided in this application can be used to perform the following steps:

[0083] Obtain a first instruction, wherein the first instruction is used to erase information in a first flash memory area or write information to the first flash memory area, the first flash memory area being any one of a plurality of flash memory areas obtained by partitioning the flash memory, the plurality of flash memory areas including at least one flash memory area for storing data and at least one flash memory area for storing programs;

[0084] Obtain first indication information corresponding to the first flash memory region from the register. The first indication information is used to indicate the erase / write permission of the first flash memory region. The first indication information is pre-configured in the register.

[0085] When the first indication information indicates that the erase / write permission of the first flash memory area is erasable and writable, the instruction is executed to erase the information in the first flash memory area or write information to the first flash memory area;

[0086] When the first indication information indicates that the erase / write permission for the first flash memory area is not erase / write, an abnormal operation is reported.

[0087] In some possible implementations, in retrieving the first indication information corresponding to the first flash memory region from the register, the processor 701 is specifically configured to:

[0088] Obtain the address range of the first flash memory region;

[0089] Based on the mapping relationship between address range and field, and the address range of the first flash memory region, determine the field corresponding to the first flash memory region in the register;

[0090] The first indication information is obtained from the field.

[0091] In some possible implementations, the value of the first indication information is used to indicate the erase / write permissions of the first flash memory area;

[0092] When the value of the first indication information is 1, it indicates that the erase / write permission of the first flash memory area is non-erasable; when the value of the first indication information is 0, it indicates that the erase / write permission of the first flash memory area is erasable.

[0093] In some possible implementations, processor 701 is further configured to:

[0094] Obtain a second instruction, wherein the second instruction is used to erase and rewrite the indication information of the second flash memory region in the plurality of flash memory regions;

[0095] Based on the address range of the second flash memory region, determine the field in the register corresponding to the second flash memory region;

[0096] The instruction information configured in the field is erased and then rewritten.

[0097] In some possible implementations, processor 701 is further configured to:

[0098] Obtain the flash memory partition information of the flash memory, which includes the starting address of each flash memory region, the size of each flash memory region, and the attributes of each flash memory region. The attributes of each flash memory region are for storing programs or data.

[0099] Load the system program and system data of the vehicle-mounted equipment;

[0100] The address range of each flash memory region is determined based on its starting address and size.

[0101] The erase / write permissions for each flash memory region are determined based on the address range of each flash memory region, the attributes of each flash memory region, the system program, and the system data.

[0102] Based on the erase / write permissions of each flash memory region, the field in the register corresponding to the address range of each flash memory region is configured with indication information for each flash memory region.

[0103] In some possible implementations, in determining the erase / write permissions of each flash memory region based on the address range of each flash memory region, the attributes of each flash memory region, the system program, and the system data, processor 701 is specifically configured to:

[0104] Based on the size and attributes of each flash memory region, multiple allocation operations are performed on the multiple flash memory regions to obtain various flash memory combinations; wherein each allocation operation includes: allocating at least one first target flash memory region for storing the system program from the multiple flash memory regions and allocating at least one or more second target flash memory regions for storing the data, and the total size of at least one first target flash memory region is greater than or equal to the size of the system program, and the total size of at least one second target flash memory region is greater than the size of the system data;

[0105] Based on the attributes of each flash region in the plurality of flash regions, and at least one first target flash region and at least one second target flash region in each flash combination, the target attributes of each flash region in each flash combination are determined, wherein the target attribute of the first target flash region in each flash combination is for storing system programs, the target attribute of the second target flash region is for storing system data, and the target attribute of the remaining flash regions is for storing non-system programs or non-system data, wherein the remaining flash regions are the flash regions in each flash combination other than at least one target flash region and at least one second target flash region;

[0106] The bad block rate of each flash region in each flash region is determined based on the address range of each flash region in each flash combination and the target attributes of each flash region;

[0107] Calculate the loss cost for each flash memory combination based on the bad block probability of each flash memory region in each flash memory combination and the target attributes of each flash memory region;

[0108] Determine the target flash memory combination based on the loss cost of each flash memory combination;

[0109] The erase / write permissions of at least one first target flash memory region for storing system data and at least one second target flash memory region for storing system programs in the target flash memory assembly are set to non-erasable / writable, and the permissions of the remaining flash memory regions in the target flash memory assembly are set to erasable / writable, thereby obtaining the erase / write permissions of each flash memory region in the plurality of flash memory regions.

[0110] In some possible implementations, in determining the bad block rate of each flash region in each flash memory combination based on the address range of each flash region in each flash memory combination and the target attributes of each flash region, the processor 701 is specifically configured to:

[0111] Based on the size, address range, and target attributes of each flash region in each flash memory combination, determine the input data for each flash region in each flash memory combination;

[0112] Multiple input data from multiple flash memory regions in each flash memory combination are concatenated to obtain the data to be processed for each flash memory combination;

[0113] The data to be processed for each flash memory combination is input into a pre-trained bad block prediction model to obtain the bad block rate of each flash memory region in each flash memory combination.

[0114] The aforementioned electronic device can be the aforementioned vehicle-mounted device, and the electronic device includes, but is not limited to, processor 701, register 702, flash memory 703, and memory 704. Those skilled in the art will understand that the schematic diagram is merely an example of an electronic device and does not constitute a limitation on the electronic device; it may include more or fewer components than illustrated, or combine certain components, or use different components.

[0115] It should be noted that since the processor 701 of the electronic device implements the steps in the above-described flash memory protection method when executing the computer program, the embodiments of the above-described flash memory protection method are all applicable to the electronic device and can achieve the same or similar beneficial effects.

[0116] This application embodiment also provides a computer storage medium (Memory), which is a memory device in an electronic device used to store programs and data. It is understood that the computer storage medium here can include the built-in storage medium in a terminal, or it can include an extended storage medium supported by the terminal. The computer storage medium provides storage space, which stores the terminal's operating system. Furthermore, this storage space also stores one or more instructions suitable for loading and execution by the processor 701. These instructions can be one or more computer programs (including program code). It should be noted that the computer storage medium here can be a high-speed RAM memory, or a non-volatile memory, such as at least one disk storage device; optionally, it can also be at least one computer storage medium located remotely from the aforementioned processor 701. In one embodiment, the processor 701 can load and execute one or more instructions stored in the computer storage medium to implement the corresponding steps of the aforementioned flash memory protection method.

[0117] For example, a computer program on a computer storage medium includes computer program code, which may be in the form of source code, object code, executable file, or some intermediate form. Computer-readable media may include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

[0118] It should be noted that since the computer program on the computer storage medium implements the steps in the above-described flash memory protection method when executed by the processor, all embodiments of the above-described flash memory protection method are applicable to the computer storage medium and can achieve the same or similar beneficial effects.

[0119] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A flash memory protection method, characterized in that, Applied to in-vehicle devices, wherein the in-vehicle devices include a processor, flash memory, and registers, the method includes: The processor obtains the flash memory partition information of the flash memory, which includes the starting address of each flash memory region that divides the flash memory into multiple flash memory regions, the size of each flash memory region, and the attributes of each flash memory region. The attributes of each flash memory region are for storing programs or data. The processor loads the system program and system data of the vehicle-mounted device; The processor determines the address range of each flash memory region based on the starting address of each flash memory region and the size of each flash memory region; The processor determines the erase / write permissions for each flash memory region based on the address range of each flash memory region, the attributes of each flash memory region, the system program, and the system data, including: Based on the size and attributes of each flash memory region in the plurality of flash memory regions, multiple allocation operations are performed on the plurality of flash memory regions to obtain multiple flash memory combinations; based on the address range and target attributes of each flash memory region in each flash memory combination, the bad block rate of each flash memory region in each flash memory combination is determined; based on the bad block probability of each flash memory region in each flash memory combination and the target attributes, the loss cost of each flash memory combination is calculated; based on the loss cost of each flash memory combination, a target flash memory combination is determined; the erase / write permissions of at least one first target flash memory region used to store the system data and at least one second target flash memory region used to store the system program in the target flash memory combination are set to non-erasable, and the permissions of the remaining flash memory regions in the target flash memory combination are set to erasable, thereby obtaining the erase / write permissions of each flash memory region in the plurality of flash memory regions; The processor configures indication information for each flash memory region in the field corresponding to the address range of each flash memory region in the register according to the erase / write permissions of each flash memory region. The processor acquires a first instruction, wherein the first instruction is used to erase information in a first flash memory area or write information to the first flash memory area, the first flash memory area being any one of a plurality of flash memory areas obtained by partitioning the flash memory, the plurality of flash memory areas including at least one flash memory area for storing data and at least one flash memory area for storing programs; The processor obtains first indication information corresponding to the first flash memory region from the register. The first indication information is used to indicate the erase / write permission of the first flash memory region. The first indication information is pre-configured in the register. When the first indication information indicates that the erase / write permission of the first flash memory area is erasable and writable, the processor executes the instruction to erase information in the first flash memory area or write information to the first flash memory area; When the first indication information indicates that the erase / write permission for the first flash memory area is non-erasable, the processor reports an abnormal operation.

2. The method according to claim 1, characterized in that, The processor obtains first indication information corresponding to the first flash memory region from the register, including: The processor obtains the address range of the first flash memory region; The processor determines the field corresponding to the first flash memory region in the register based on the mapping relationship between the address range and the field, and the address range of the first flash memory region; The processor obtains the first indication information from the field.

3. The method according to claim 1 or 2, characterized in that, The value of the first indication information is used to indicate the erase / write permissions of the first flash memory area; When the value of the first indication information is 1, it indicates that the erase / write permission of the first flash memory area is non-erasable; when the value of the first indication information is 0, it indicates that the erase / write permission of the first flash memory area is erasable.

4. The method according to claim 1, characterized in that, The method further includes: The processor acquires a second instruction, wherein the second instruction is used to erase and rewrite the indication information of the second flash memory region in the plurality of flash memory regions; The processor determines the field in the register corresponding to the second flash memory region based on the address range of the second flash memory region; The processor erases the instruction information configured in the field and rewrites the instruction information.

5. The method according to claim 1, characterized in that, in, Each allocation operation includes: allocating at least one first target flash memory region from the plurality of flash memory regions for storing the system program and allocating at least one or more second target flash memory regions for storing the data, wherein the total size of at least one first target flash memory region is greater than or equal to the size of the system program, and the total size of at least one second target flash memory region is greater than the size of the system data; The method further includes: Based on the attributes of each flash region in the plurality of flash regions, and at least one first target flash region and at least one second target flash region in each flash combination, the target attributes of each flash region in each flash combination are determined, wherein the target attribute of the first target flash region in each flash combination is for storing system programs, the target attribute of the second target flash region is for storing system data, and the target attribute of the remaining flash regions is for storing non-system programs or non-system data, wherein the remaining flash regions are the flash regions in each flash combination other than at least one target flash region and at least one second target flash region.

6. The method according to claim 5, characterized in that, The step of determining the bad block rate of each flash region in each flash memory combination based on the address range of each flash region in each flash memory combination and the target attributes of each flash region includes: Based on the size, address range, and target attributes of each flash region in each flash memory combination, determine the input data for each flash region in each flash memory combination; Multiple input data from multiple flash memory regions in each flash memory combination are concatenated to obtain the data to be processed for each flash memory combination; The data to be processed for each flash memory combination is input into a pre-trained bad block prediction model to obtain the bad block rate of each flash memory region in each flash memory combination; The bad block prediction model is trained through the following steps: Multiple training samples are obtained, where each training sample is the partition information of a flash memory. The partition information includes the number of partitions in the flash memory, the size of each flash memory partition, the starting address, and the target attributes of each flash memory region. The label of each training sample is whether each flash memory region is a bad block. Based on the partition information of each training sample, the target attribute of each flash memory region in each training sample is encoded to obtain the attribute encoding value of each flash memory region in each training sample; based on the attribute encoding value, the training data corresponding to each training sample is obtained. The initial model is trained using the training data corresponding to each training sample, and the bad block rate of each flash memory region in each training sample is predicted. Based on the predicted bad block rate of each flash memory region in each training sample and the label of each flash memory region, the loss corresponding to each training sample is determined. Based on the loss corresponding to each training sample, the target loss is determined; the model parameters of the initial model are adjusted according to the target loss to obtain the bad block prediction model.

7. The method according to claim 5 or 6, characterized in that, The calculation of the loss cost for each flash memory combination based on the bad block probability of each flash memory region in each flash memory combination and the target attributes of each flash memory region includes: The weighting coefficient for each flash region is determined based on the target attributes of each flash region in each flash memory combination; The bad block rate of each flash memory region is weighted according to the weight coefficient of each flash memory region in each flash memory combination to obtain the loss cost of each flash memory combination.

8. A vehicle-mounted device, characterized in that, The vehicle-mounted device is used to implement the method according to any one of claims 1-7, and the vehicle-mounted device includes a processor, flash memory, and registers; The processor is configured to acquire a first instruction, wherein the first instruction is configured to erase information stored in a first flash memory region or write information to the first flash memory region, wherein the first flash memory region is any one of a plurality of flash memory regions obtained by partitioning the flash memory, and the plurality of flash memory regions include at least one flash memory region for storing data and at least one flash memory region for storing programs. The processor is configured to obtain first indication information corresponding to the first flash memory region from the register, the first indication information being used to indicate the erase / write permission of the first flash memory region, wherein the first indication information is pre-configured in the register; The processor is configured to execute the instruction to erase information in the first flash memory area or write information to the first flash memory area when the first indication information indicates that the erase / write permission of the first flash memory area is erasable / writable. The processor is configured to report an abnormal operation when the first indication information indicates that the erase / write permission for the first flash memory area is non-erasable.

9. An electronic device, characterized in that, include: A processor and a memory, the processor being connected to the memory, the memory being used to store a computer program, and the processor being used to execute the computer program stored in the memory to cause the electronic device to perform the method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, A computer-readable storage medium stores a computer program that is executed by a processor to implement the method as described in any one of claims 1-7.

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