Direct memory access controller, data transfer method and system

Abstract

The application provides a direct memory access controller, a data transmission method and a data transmission system. The direct memory access controller comprises a read control channel module, a data format conversion module and a write control channel module. The read control channel module is configured to obtain to-be-transmitted data from a source end according to configuration information of a processor. The data format conversion module is configured to process the to-be-transmitted data according to target format information in the configuration information to obtain target data. The write control channel module is configured to transmit the target data to a destination end according to the configuration information. Therefore, in the process of data transmission using the direct memory access controller, the problem that other devices and the direct memory access controller contend for a system bus due to data format conversion does not occur, and thus the efficiency of data transmission can be improved.

Description

Technical Field

[0001] This application relates to the field of data transmission technology, and in particular to a direct memory access controller, data transmission method, and system. Background Technology

[0002] Because Direct Memory Access (DMA) controllers allow hardware devices of different speeds to communicate without relying on a large interrupt load from the processor, they offer higher transfer efficiency compared to processor polling or interrupt-based methods. Therefore, DMA controllers are widely used in data transfer processes.

[0003] However, traditional Direct Memory Access (DMI) controllers only support copying data from the source to the destination. When the data format required by the destination differs from that of the source, the traditional DMI controller cannot achieve this in a single transfer. Therefore, additional hardware or software processing is required in either the source or destination devices, or the memory address needs to be modified at the destination. Either approach leads to contention for system bus space between various devices and the DMI controller. This is especially problematic when transmitting large amounts of data, severely impacting the DMI controller's scheduling of the system bus and consequently affecting data transmission efficiency. Summary of the Invention

[0004] This application provides a direct memory access controller, a data transmission method, and a data transmission system, which can improve data transmission efficiency when the data format required at the destination is different from that at the source.

[0005] In a first aspect, embodiments of this application provide a direct memory access controller (DMC), which is connected to a system bus and is used to transmit data from a source end to a destination end according to processor configuration information, wherein the configuration information further includes target format information. The DMC includes:

[0006] The read control channel module is used to obtain the data to be transmitted from the source end according to the configuration information.

[0007] The data format conversion module is used to process the data to be transmitted according to the target format information to obtain the target data;

[0008] The write control channel module is used to transmit the target data to the destination terminal according to the configuration information.

[0009] Secondly, embodiments of this application provide a data transmission method applied to the direct memory access controller described in the first aspect above, the data transmission method comprising:

[0010] The read control channel module obtains the data to be transmitted from the source end according to the configuration information;

[0011] The data format conversion module processes the data to be transmitted according to the target format information to obtain the target data;

[0012] The write control channel module transmits the target data to the destination terminal according to the configuration information.

[0013] Thirdly, embodiments of this application provide a data transmission system, including the direct memory access controller as described in the first aspect above.

[0014] This application provides a direct memory access controller, a data transmission method, and a data transmission system. The direct memory access controller includes a read control channel module, a data format conversion module, and a write control channel module. The read control channel module acquires the data to be transmitted from the source based on the processor's configuration information. The data format conversion module processes the data to be transmitted according to the target format information in the configuration information to obtain the target data. The write control channel module transmits the target data to the destination based on the configuration information. This direct memory access controller integrates data transfer and data format conversion into one process. Therefore, when data transmission occurs in scenarios where the data format required at the destination differs from that at the source, the problem of other devices competing with the direct memory access controller for system bus access due to data format conversion will not occur, thereby improving data transmission efficiency.

[0015] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit the disclosure of the embodiments of this application. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of a data transmission system to which the direct memory access controller provided in this application is applicable;

[0018] Figure 2 An exemplary structural diagram of a direct memory access controller provided in an embodiment of this application;

[0019] Figure 3A schematic diagram of the data arrangement format of the source and destination ends provided in the embodiments of this application;

[0020] Figure 4 Another exemplary structural diagram of the direct memory access controller provided in the embodiments of this application;

[0021] Figure 5 An exemplary structural diagram of a data format conversion module provided in an embodiment of this application;

[0022] Figure 6 An exemplary structural diagram of another data format conversion module provided in an embodiment of this application;

[0023] Figure 7 An exemplary structural diagram of a write data format conversion module provided in an embodiment of this application;

[0024] Figure 8 This is an exemplary structural diagram of another write data format conversion module mentioned in the embodiments of this application;

[0025] Figure 9 Another exemplary structural diagram of the direct memory access controller provided in the embodiments of this application;

[0026] Figure 10 Another exemplary structural diagram of the direct memory access controller provided in the embodiments of this application;

[0027] Figure 11 An exemplary structural diagram of another data format conversion module provided in an embodiment of this application;

[0028] Figure 12 An exemplary structural diagram of another write data format conversion module provided in an embodiment of this application;

[0029] Figure 13 Another exemplary structural diagram of the direct memory access controller provided in the embodiments of this application;

[0030] Figure 14 This is a flowchart illustrating a data transmission method provided in an embodiment of this application;

[0031] Figure 15 This is a flowchart illustrating another data transmission method for embodiments of this application. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0034] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0035] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0036] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0037] It should be noted that, in the following specific embodiments of this application, the direct memory access controller may be referred to as the DMA controller.

[0038] DMA controller transfer is the process of copying data from one address space to another, enabling high-speed data transfer between peripherals and memory, or between memory and memory, or between peripherals. The peripherals refer to external devices connected to the system bus.

[0039] In practical applications, when data transfer is performed based on a DMA controller, there may be scenarios where the data formats at the source and destination ends differ. Specifically, the source data may be in a first format, while the destination requires a second format. These two formats differ in that the data format can be a data arrangement, data combination method, or data structure. When the second format of the data required by the destination differs from the first format of the data stored at the source, existing DMA controllers need to rely on other software or hardware to complete the data transfer. These other software or hardware are generally designed into the source or destination devices. Therefore, during the data transfer process from source to destination using DMA control, data format conversion is also required. This can lead to other devices competing with the DMA controller for system bus space, thus reducing data transfer efficiency.

[0040] It should be noted that in the embodiments of this application, other devices can be source or destination, or other external devices connected to the system bus, and are not limited here.

[0041] For example, taking data format as the data arrangement format, if the DMA controller needs to transfer 256 bytes of data from the source's contiguous memory address space (0 to 255) to the destination, but the destination requires these 256 bytes of data to be stored in a different format than the source's contiguous memory address format. Assume the destination requires storing 128 bytes of data from address 500 to address 627, and the remaining 128 bytes from address 800 to address 927. Clearly, existing DMA controllers cannot directly complete this data transfer. They need to use appropriate software or hardware to perform data segmentation at either the source or destination. Therefore, during data transfer, this can lead to system bus scheduling issues between other devices (source or destination) and the DMA controller, resulting in bus contention and affecting data transfer efficiency.

[0042] When the source and destination data formats differ, traditional DMA controllers clearly cannot achieve a single transfer. Data processing is required, either before or after the DMA transfer. This often necessitates multiple transfers, increasing data transmission overhead and potentially leading to bus contention. For instance, to achieve a single transfer with different data layout formats, the upper-layer application needs to handle the destination address, or dedicated hardware logic needs to be added to handle data changes. Both of these methods increase design complexity, especially with more complex data layouts, such as in high-volume datasets where there are specific requirements for data format arrangement and a strong emphasis on timeliness. In such cases, relying on upper-layer applications or adding dedicated hardware logic is clearly not a reasonable choice.

[0043] It should be noted that the upper-layer application can specifically be a management program for the data transmission system, or it can be used to manage hardware devices connected to the system bus.

[0044] Furthermore, since the data objects transferred by DMA controllers are typically large in volume and required by specialized fields, such as artificial intelligence, the data processing, including data format conversion at the source or destination, becomes more complex when dealing with large volumes of data with specific format requirements, such as data matrices processed by convolutional neural networks. Therefore, in existing technologies using DMA controllers for data transfer, especially for current artificial intelligence needs, how to avoid bus scheduling problems caused by other external software or hardware and ensure the timeliness of data transfer by the DMA controller is a pressing technical problem that needs to be solved.

[0045] Therefore, the data transfer process based on the DMA controller requires a new type of DMA controller to avoid additional software or hardware overhead when the data formats at the source and destination are different, which would lead to bus scheduling problems during data transfer by the DMA controller and reduce the efficiency of data transfer.

[0046] To address the aforementioned technical problems, embodiments of this application provide a direct memory access controller, a data transmission method, and a data transmission system. The data transmission method is applied to the direct memory access controller, and the data transmission system includes the direct memory access controller. This improves data transmission efficiency in scenarios where the data formats at the source and destination ends differ, and is particularly suitable for current big data applications such as artificial intelligence.

[0047] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described herein are for illustration and explanation only and are not intended to limit the application. Furthermore, the embodiments and features described herein can be combined with each other unless otherwise specified.

[0048] Please see Figure 1 , Figure 1 This is a schematic diagram of a data transmission system applicable to the DMA controller provided in the embodiments of this application. Figure 1 As shown, the data transmission system 10 includes a DMA controller 12, a system bus 14, and a processor 16. The DMA controller 12 is connected to the system bus 14, and the processor 16 is also connected to the system bus 14. In specific implementations, the data transmission system 10 can be a system-on-a-chip (SOC), a field-programmable gate array (FPGA) system, or an application-specific integrated circuit (ASIC) system—any chip system that includes a DMA controller.

[0049] The following description uses a System-on-a-Chip (SoC) as an example to illustrate the data transmission system, specifically the DMA controller provided in this embodiment, which is applied within an SoC. Correspondingly, the system bus can also be referred to as an on-chip bus.

[0050] The processor 16 can be a central processing unit (CPU). During the data transfer process, the DMA controller 12 does not require the intervention of the CPU, and the CPU can perform other tasks, thereby greatly improving the operating efficiency of the CPU.

[0051] In practical implementation, the data transfer system 10 may include a CPU, a DMA controller, and a storage device, such as on-chip RAM, on-chip Flash memory, off-chip memory, or I / O devices. This storage device is connected to the system bus 14. If data transfer is to be performed via the DMA controller, the processor 16 (e.g., the CPU) initiates a data transfer command to the DMA controller via the system bus 14. After gaining access to the system bus 14, the DMA controller controls the data transfer based on the configuration information issued by the CPU and returns the bus access after the transfer is complete. The DMA controller does not require CPU involvement during data transfer, which not only saves on CPU overhead but also improves data transfer efficiency.

[0052] like Figure 1As shown, the data transmission system 10 may also include a source end 11 and a destination end 13. The DMA controller 12 is used to move the data to be transmitted from the source end 11 to the destination end 13 according to the processor's configuration information. Of course, it can be understood that the source end 11 and the destination end 13 may not be considered devices in the data transmission system 10, but may be external devices of the data transmission system 10, connected to the system bus 14 of the data transmission system 10 through I / O interfaces, etc.

[0053] In this embodiment, the source end 11 and the destination end 13 can be storage devices connected to the system bus 14, respectively. Specifically, the source end 11 and the destination end 13 can be at least one of flash memory, static random-access memory (SRAM), peripheral SRAM, peripheral clock enable register (RCC_APB1ENR, APB1), or peripheral clock enable register (RCC_APB2ENR, APB2). Alternatively, the source end 11 and the destination end 13 can also be at least one of flash memory, static random-access memory (SRAM), peripheral SRAM, peripheral clock enable register (RCC_APB1ENR, APB1), or peripheral clock enable register (RCC_APB2ENR, APB2).

[0054] It should be noted that the DMA controller 12 of the data transmission system 10 can be any of the DMA controllers provided in the embodiments of this application. The DMA controllers provided in the embodiments of this application are described in detail below.

[0055] Please see Figure 2 , Figure 2 This is an exemplary structural diagram of a DMA controller provided in an embodiment of this application. The DMA controller is mainly used in scenarios where the data format requirements of the destination and the source are different, but it can also be used in scenarios where the data format requirements of the destination and the source are the same.

[0056] like Figure 2 As shown, the DMA controller 12 includes a read control channel module 121, a data format conversion module 122, and a write control channel module 123.

[0057] The DMA controller 12 is connected to the system bus 14 and is used to receive configuration information sent by the processor 16. According to the configuration information, the data to be transmitted from the source end 11 is transmitted to the destination end 13. The difference is that the configuration information also includes target format information.

[0058] The configuration information is used by the DMA controller 12 to read the data to be transferred from the source end 11 and to write the data to the destination end 13, thereby completing the data transfer. The target format information is used by the DMA controller 12 to process the data to be transferred to obtain data that meets the format requirements of the destination end 13, i.e., the target data.

[0059] In this system, source device 11 stores the data to be transmitted, while destination device 13 needs to receive and store the target data transmitted by the DMA controller. It should be noted that source device 11 and destination device 13 can be of the same type of storage device or different types of storage devices.

[0060] The data to be transmitted stored at the source end 11 has a first format, and the target data required by the destination end 13 has a second format. Specifically, the first format and the second format can be different. The first format and the second format can refer to the data arrangement format, the data file format, the data storage format, the data structure, or the data type, etc.

[0061] For example, both the first and second formats are data arrangement formats. The first format can be stored at contiguous addresses, while the second format can be stored at non-contiguous addresses; that is, the first and second formats are different. Of course, it is understandable that different data arrangement formats can also include many other cases. For example, both the first and second formats can be stored non-contiguously, but the specific arrangement methods are different.

[0062] It should also be noted that the first format and the second format can be the same, meaning the DMA controller provided in this application embodiment can also be used to transmit data with the same format. When transmitting data with the same format, the processor's configuration information does not need to include target format information; that is, the DMA controller is not required to perform format conversion on the data to be transmitted, but is only used to transmit the data from the source to the destination. The DMA controller provided in this application embodiment is mainly used to improve the data transmission efficiency when the first format and the second format are different.

[0063] System bus 14 can be a high-performance system bus AHB (Advanced High-performance Bus), ASB (Advanced System Bus), APB (Advanced Peripheral Bus), on-chip system IP core interconnection Wishbone bus, Avalon bus, CoreConnect bus, CoreFrame bus, or FISPbus bus, etc.

[0064] In practical implementation, the processor 16, acting as the main controller of the data transmission system 10, can send configuration information to the DMA controller 12 via the system bus 14, so that the DMA controller 12 can transmit the data to be transmitted from the source end 11 to the destination end 13 according to the configuration information. When the data format at the source end and the data format required at the destination end are different, the processor also needs to configure the target format information in the configuration information.

[0065] Specifically, the processor 16, acting as the main controller, is a data processing module independent of the DMA controller. For example, the main controller can be a CPU. In the embodiments of this application, the main controller, acting as a central processing unit, can send configuration information to the DMA controller 12 through a preset configuration interface. The DMA controller 12 stores the configuration information in its registers and then reads the configuration information to perform data transmission based on the configuration information.

[0066] When the DMA controller 12 transmits data to be transmitted from the source end 11 to the destination end 13 according to the configuration information, specifically: the read control channel module 121 obtains the data to be transmitted from the source end 11 according to the configuration information; the data format conversion module 122 processes the data to be transmitted according to the target format information in the configuration information to obtain the target data, the data format of the target data being adapted to the required data format of the destination end 13; and the write control channel module 123 transmits the target data to the destination end 13 according to the configuration information. This achieves data format conversion during data transfer, avoids the problem of preemption of the system bus, and thus improves the efficiency of data transmission.

[0067] In the embodiments of this application, the target format information can be understood as information such as the data conversion logic corresponding to the second format of the target data required by the destination 13 from the first format of the data to be transmitted from the source 11, thereby facilitating the data format conversion module 122 to convert the data to be transmitted from the first format to the second format according to the target format information to obtain the target data. It should be understood that the data conversion logic corresponding to different data formats is different, and the target format information that needs to be configured is also different.

[0068] For example, if both the first format of the data to be transmitted and the second format of the target data are data layout formats, such as the data to be transmitted in the source 11 including six data items, namely D1, D2, D3, D4, D5, and D6, where D1, D2, and D3 are stored with consecutive addresses, and D4, D5, and D6 are also stored with consecutive addresses, but D3 and D4 are not stored with consecutive addresses, this can be specifically called layout a; while the data transmitted to the destination 13 is expected to have D1 and D2 stored with consecutive addresses, D3 and D4 stored with consecutive addresses, and D5 and D6 stored with consecutive addresses, but D2 and D3 are not stored with consecutive addresses, and D4 and D5 are not stored with consecutive addresses, this can be specifically called layout b. For details on layout a and layout b, please refer to... Figure 3 Understood. The target format information can be the data conversion logic information corresponding to the conversion of the data to be transmitted from arrangement a to arrangement b, which can be achieved through methods such as shifting and splicing.

[0069] For example, if the first format of the data to be transmitted and the second format of the target data are both data structures, for example, the first data structure is assumed to be a 5HD structure and the target data is assumed to be an NZ structure, then the corresponding configured target format information can be: conversion method information for converting the 5HD structure to the NZ structure.

[0070] It should also be noted that, in the embodiments of this application, the read control channel module 121 and the write control channel module 123 can be connected to the system bus 14 through a data transmission interface 141, or they can be connected to the system bus 14 through two data transmission interfaces 141 respectively. The number of data transmission interfaces 141 is not limited here. The read control channel module 121 reads the data to be transmitted from the source end 11 through the data transmission interface 141 and the system bus 14. Similarly, the write control channel module 123 can write the target data to the destination end 13 through the data transmission interface 141 and the system bus 14. Therefore, there may be a problem of preemption of the system bus within it.

[0071] The DMA controller provided in this application can acquire data to be transmitted from the source end through the read control channel module. The data format conversion module processes the data acquired from the source end by the read control channel module based on the target format information in the processor's configuration information to obtain target data that meets the requirements of the destination end. Then, the target data is directly transmitted to the destination end through the write control channel module. This eliminates the need for additional software or hardware at the source and destination ends for data conversion, thus avoiding the problem of other software or hardware preempting the system bus during data transmission using the DMA controller, thereby improving data transmission efficiency.

[0072] In some embodiments, to improve the flexibility of reading data from the source end and writing data to the destination end, the configuration information may further include read data information and write data information. Specifically, the read control channel module 121 is used to read the data to be transmitted from the source end 11 according to the read data information, and the write control channel module 123 is used to write the target data to the destination end 13 according to the write data information.

[0073] For example, the data information to be read may include the starting address of the data to be transmitted and the length of the data to be transmitted, so that the read control channel module 121 can read the data to be transmitted from the source end 11 according to the starting address of the data to be transmitted and the length of the data to be transmitted.

[0074] For example, the data information to be read may include: the starting address of the data to be transmitted, the length of the data to be transmitted each time, and the number of times the data to be transmitted is read, so that the read control channel module 121 can read the data to be transmitted from the source 11 according to the starting address of the data to be transmitted, the length of the data to be transmitted each time, and the number of times the data to be transmitted is read.

[0075] For example, the read data information may also include: the starting address of the data to be transmitted, the length of the data to be transmitted each time it is read, the address interval for reading the data to be transmitted, and the number of times the data to be transmitted is read. This allows the read control channel module 121 to read the data to be transmitted from the source 11 based on the starting address of the data to be transmitted, the length of the data to be transmitted each time it is read, the address interval for reading the data to be transmitted, and the number of times the data to be transmitted is read. By configuring the read data information to include the starting address of the data to be transmitted, the length of the data to be transmitted each time it is read, the address interval for reading the data to be transmitted, and the number of times the data to be transmitted is read, the read control channel module 121 can read valid data from the source 11. The valid data is the data that needs to be transmitted, that is, the valid data is the data that actually needs to be transferred, thereby further improving the efficiency of data transmission.

[0076] It should be noted that the starting address of the data to be transferred corresponds to the starting address of the DMA controller when performing a read operation; the length of the data to be transferred each time corresponds to the amount of data read by the DMA controller each time; the address interval for reading the data to be transferred corresponds to the address jump interval for the DMA controller when performing a read operation; and the number of times the data to be transferred is read specifically refers to the number of reads.

[0077] For valid data: For example, the consecutive storage addresses 0-9 of source 11 store data D1, D2, D3, X1, X2, D4, D5, D6, X3, and X4 respectively. Among them, D1, D2, D3, D4, D5, and D6 are the data that needs to be moved, that is, D1, D2, D3, D4, D5, and D6 are valid data, while X1, X2, X3, and X4 are invalid data.

[0078] Regarding how to extract valid data so that it can be transferred to the destination 11, embodiments of this application provide at least two processing methods. It should be noted that the conversion of valid data to target data is implemented by the data format conversion module 122. Extracting valid data from the data to be transmitted can be achieved by the data format conversion module 122 based on data processing information, i.e., the data processing information includes valid data information; alternatively, it can be achieved by the read control channel module 121 based on read data information.

[0079] Method 1: Valid data can be directly read from the source end 11 as data to be transmitted by reading the read data information configured in the read control channel module 121. For example, by configuring the starting address of the data to be transmitted, the length of the data to be transmitted each time, the address interval for reading the data to be transmitted, and the number of times the data to be transmitted is read, all the data to be transmitted can be obtained from the source end 11 as valid data.

[0080] Method 2: Alternatively, the data format conversion module 122 can be used to process data based on the configuration information. This data processing information includes valid data information, where the valid data is the data to be transmitted, and the valid data information itself contains related information such as storage addresses. The read control channel module 121 obtains all the data to be transmitted from the source 11 according to the configuration information. This data includes both valid and invalid data. The data format conversion module 122 can extract data from the data to be transmitted based on the valid data information to obtain the valid data, which is then used as the processed data to be transmitted.

[0081] For example, the data information to be written may include the starting address of the target data and the length of the target data, so that the write control channel module 123 can write the target data to the destination 13 according to the starting address of the target data and the length of the target data.

[0082] For example, the data writing information may include: the starting address of the target data, the length of the target data written each time, and the number of times the target data is written, so that the write control channel module 123 can write the target data to the destination 13 according to the starting address of the target data, the length of the target data written each time, and the number of times the target data is written.

[0083] For example, the data writing information may include: the starting address of the target data, the length of the target data written each time, the address interval for writing the target data, and the number of times the target data is written. This allows the write control channel module 123 to write the target data to the destination terminal 13 according to the starting address of the target data, the length of the target data written each time, the address interval for writing the target data, and the number of times the target data is written. This enables the target data to be written to the desired storage address.

[0084] Therefore, by configuring read data information and write data information, the flexibility of the DMA controller in reading data from the source and writing data to the destination 13 can be improved. With reasonable information configuration and in conjunction with the data format conversion module, the efficiency of data transmission can be further improved.

[0085] The above embodiments are merely exemplary descriptions of the DMA controller provided in this application. In other embodiments of this application, the DMA controller may have different structures.

[0086] Please see Figure 4 , Figure 4 This is yet another exemplary structural diagram of the DMA controller provided in an embodiment of this application. For example... Figure 4 As shown, the data format conversion module 122 may include a read data format conversion module 1221 and a write data format conversion module 1222. The read data format conversion module 1221 receives the data to be transmitted read from the source end 11 by the read control channel module 121, and processes the data to be transmitted according to the processor's configuration information to obtain the processed data to be transmitted. The write data format conversion module 1222 processes the processed data to be transmitted according to the target format information in the configuration information to obtain target data that meets the requirements of the destination end 13. The write control channel module 123 writes the target data to the destination end 13.

[0087] The read control channel module 121 and write control channel module 123 can read the data to be transmitted from the source end 11 and write the target data to the destination end 13 according to the read data information and write data information configured by the processor, respectively. By setting read data format conversion modules and write data format conversion modules inside the DMA controller, the read data process and the write data process are effectively separated, which can effectively prevent the bus contention problem caused by the read data process and the write data process running simultaneously, thereby effectively improving the efficiency of data transmission.

[0088] In some embodiments, the processor configuration information may also include data processing information, such as valid data information and data splicing information, so that the read data format conversion module 1221 can process the data to be transmitted according to the data processing information to obtain the processed data to be transmitted.

[0089] For example, if the data processing information includes valid data information, the data format conversion module 12121 can be used to extract data from the data to be transmitted based on the valid data information to obtain valid data, which serves as the processed data to be transmitted. Specifically, the valid data information is used to identify valid data in the data to be transmitted, thereby facilitating the extraction of valid data by the data format conversion module.

[0090] For example, if the data processing information includes data splicing information, the data format conversion module 12121 can be used to splice the data to be transmitted according to the data splicing information to obtain spliced ​​data, which is used as the processed data to be transmitted.

[0091] It should be noted that, in order to further improve the efficiency of data transmission, the data to be transmitted can be processed by the read data format conversion module 1221 according to the pre-configured data processing information. It is understood that the read data format conversion module 1221 can also be omitted from processing the data to be transmitted; for example, if the data read from the source is all valid data, then the read data format conversion module 1221 is not required to process it.

[0092] The following describes the specific circuit structure design of the read data format conversion module 1221 provided in the embodiments of this application, and also describes the specific circuit structure design of the write data format conversion module 1222 provided in the embodiments of this application.

[0093] In some embodiments, such as Figure 5 As shown, the read data format conversion module 1221 may include a first bit width processing circuit 12211 and a first counting circuit 12212. The first counting circuit 12212 is used to count the number of data to be transmitted that are input into the read data format conversion module 1221. The first bit width processing circuit 12211 is used to perform bit width processing on the data to be transmitted under the control of the first counting circuit 12212 to obtain the processed data to be transmitted.

[0094] For example, such as Figure 6As shown, the first-bit width processing circuit 12211 may include a first shift circuit and a first splicing circuit. The first shift circuit is used to shift the data to be transmitted, and the first splicing circuit splices the data after the shifting process to obtain the processed data to be transmitted. Correspondingly, the first counting circuit 12212 may also include a first read data counter and a first valid data counter. Both the first read data counter and the first valid data counter are connected to the first-bit width processing circuit. Specifically, the first read data counter and the first valid data counter are both connected to the first shift circuit and the first splicing circuit. The first read data counter is used to count the number of data to be transmitted to the read data format conversion module 1221, and the first valid data counter is used to count the number of valid data in the data to be transmitted. Thus, under the control of the first read data counter and the first valid data counter, the first shift circuit and the first splicing circuit can extract valid data from the data to be transmitted. By processing the valid data in the transmitted data, the efficiency of data transmission can be further improved.

[0095] It should be noted that the first wide processing circuit 12211 may include not only the first shift circuit and the first splicing circuit, but also other circuits, such as multiple shift circuits or multiple splicing circuits, which are not limited here; the first counting circuit 12212 may include not only the first read data counter and the first valid data counter, but also more counters, which are not limited here.

[0096] The first read data counter is used to count the data to be transmitted sent by the read control channel module. For example, if the width of the data to be transmitted sent by the read control channel module is 128 bits (16 bytes), and the DMA controller reads 10 data items at a time, the total amount of data to be transmitted counted by the first read data counter is 160 bytes. The first valid data counter is used to count the valid data in the data to be transmitted sent by the read control channel module. For example, if the width of the data to be transmitted sent by the read control channel module is 128 bits (16 bytes), but only 96 bits (12 bytes) of each data item are valid, and the DMA controller reads 10 data items at a time, the total amount of valid data counted by the first valid data counter is 120 bytes. The first shift circuit is used to shift each incoming data item to the left or right, or it can be left unshifted. The first concatenation circuit combines the valid parts of two sequentially incoming data items. Shifting and concatenation are used in conjunction.

[0097] The splicing process of the first splicing circuit includes sequential splicing, but it can also be spliced ​​according to other preset rules. Alternatively, it can splice at least two valid data points before the shifting process, or splice the valid data before the shifting process and the data obtained after the shifting process. Specifically, the splicing process should be determined based on the data processing information in the configuration information, and no limitations are made here.

[0098] It should be understood that the first read data counter, the first valid data counter, the first shift circuit, and the first splicing circuit need to be used in conjunction. The first shift circuit can realize the process of shortening long data, and the first splicing circuit can realize the process of lengthening short data. In other words, both the first shift circuit and the first splicing circuit can realize the change of data bit width.

[0099] For example, if the data to be transmitted via the read control channel module 121 is 'ab', and we want to obtain two data points, 'bx' and 'ay' (where x and y represent invalid values), we need to use the first shift circuit to first shift 'b' of 'ab' to the left to obtain a new data point 'bx'. At this point, we can avoid shifting the position of 'a' and directly concatenate 'y' to obtain 'ay'. Both the first shift circuit and the first concatenation circuit operate under the control of two counters (the first read data counter and the first valid data counter), specifically determining how each data point should be shifted and concatenated based on real-time counting.

[0100] For example, two data sets to be transmitted, Gb and cK, are transmitted through the read control channel module 121. The first read data counter counts Gb and cK based on the read data information, and the first valid data counter counts Gb and cK based on the valid data information, determining b and c as valid data. The first read data counter and the first valid data counter generate a series of control signals based on the statistical results to control the first shift circuit and the first splicing circuit. The first shift circuit moves the valid data b in data Gb to the left to obtain a new data set bx, and moves the valid data c in data cK to the right to obtain a new data set yc. The first splicing circuit splices bx and yc based on the control signals to obtain the valid data set bc. Here, x and y represent invalid data.

[0101] For example, if the read control channel module 121 receives two data to be transmitted, namely a and b, and both data are valid, then according to the control signal generated by the first read data counter and the first valid data counter based on the statistical results, the first shift circuit can be controlled to not shift the two data, but the first splicing circuit can be controlled to splice the two data to obtain a single data ab.

[0102] Therefore, as can be seen from the two examples above, if it is necessary to process the data to be transmitted, it is only necessary to configure the data processing information of the configuration information, and the specific circuit of the read data format conversion module can be used to achieve this.

[0103] It should be noted that the first shift circuit and the first splicing circuit can operate under the control of either of the two counters, or can be controlled by both counters simultaneously. The number of counters is not specifically limited here.

[0104] It should be noted that the functions of the first read data counter and the first valid data counter can be performed independently by one counter or by multiple counters working together. That is, in this embodiment, the first counting circuit of the read data format conversion module 1221 may include at least one first counter. This embodiment only uses the first read data counter and the first valid data counter as examples to illustrate the process by which the read data format conversion module 1221 obtains valid data, and does not constitute a limitation on the internal structure of the read data format conversion module 1221. This embodiment, through the real-time counting results and configuration information of the first read data counter and the first valid data counter, can accurately determine whether bit-width processing of each valid data point is required. By controlling the first bit-width processing circuit, bit-width processing of at least one valid data point is achieved. After obtaining valid data, the write data control channel can directly acquire the required valid data, thereby improving data transmission efficiency.

[0105] It should be noted that the first read data counter and the first valid data counter each include different operational logic circuits. These operational logic circuits are composed of different counting units and control gates to achieve their respective functions. Specifically, no limitations are made here regarding the specific composition of the operational logic circuits included in the first read data counter and the first valid data counter.

[0106] It should also be noted that, under the control of the two counters, the first shift circuit and the first splicing circuit can not only extract valid data, but also obtain data in other desired data arrangement formats.

[0107] In some embodiments, such as Figure 7As shown, the write data format conversion module 1222 includes a second bit-width processing circuit 12221 and a second counting circuit 12222. The second counting circuit 12222 counts the amount of data to be transmitted or processed data to be transmitted that enters the write data format conversion module 1222. The second bit-width processing circuit 12221, under the control of the second counting circuit 12221, performs bit-width processing on the data to be transmitted or processed data to be transmitted to obtain the target data. This allows for format conversion of the data to be transmitted to meet the format requirements of the destination. The write data format conversion module 1222, used in conjunction with the aforementioned read data format conversion module 1221, improves data processing flexibility and further enhances data transmission efficiency.

[0108] In some embodiments, such as Figure 8 As shown, the second bit-width processing circuit 12221 may include a second shift circuit and a second splicing circuit; wherein, the second shift circuit is used to shift the data to be transmitted or the processed data to be transmitted; the second splicing circuit is used to splice the data after the shifting process of the second shift circuit to obtain the target data. Correspondingly, the second counting circuit 12222 includes a second write data counter and a second valid data counter; wherein, the second write data counter and the second valid data counter are both connected to the second bit-width processing circuit, specifically they can be connected to the second shift circuit and the second splicing circuit respectively. The second write data counter is used to count the number of data input to the write data format conversion module, and the second valid data counter is used to count the number of valid data in the data input to the write data format conversion module.

[0109] The second write data counter counts the amount of data received from the read data format conversion module or other devices and inputs to the write data format conversion module. The second valid data counter counts the amount of valid data among the data input to the write data format conversion module; this valid data is the data that actually needs to be transmitted to the destination via the write control channel module. For example, if the data width of the write control channel module is 128 bits (16 bytes), and the DMA controller writes 10 data items at a time, the total amount of data counted by the second write data counter is 160 bytes. However, only 96 bits (12 bytes) of each data item are valid. If the DMA controller writes 10 data items at a time, the total amount of valid data counted by the second valid data counter is 120 bytes. The shift circuit is used to shift each incoming data item to the left or right, or it can be left unshifted. The concatenation circuit combines the valid portions of two sequentially input data items. Shifting and concatenation are used in conjunction.

[0110] For example, if the first data input to the data format conversion module is "ab" and the second data is "cd", and the target format information in the configuration is used to obtain a new data "bc" that meets the format requirements of the destination, then the second shift circuit is used to first shift the "b" of "ab" to the left (called left shift) to obtain a new data "bx", and then shift the "c" of "cd" to the right (called right shift) to obtain a new data "yc". Here, "x" and "y" are invalid data. Then, the second concatenation circuit is used to concatenate "bx" and "yc" to form "bc". The second shift circuit and the second concatenation circuit perform the above shifting / concatenation under the control of two counters (the second write data counter and the second valid data counter). This means that the real-time count determines how each data should be shifted and concatenated. Based on these two counters, it can be determined whether the final new data has been generated.

[0111] For example, the first data passed to the data format conversion module is arranged in the format of D1, D2, D3, and the second data is arranged in the format of D4, D5, D6, where D3 and D4 are not consecutive. If the destination 13 requires data arranged in the format of D1, D2, D3, D4, D5, D6, where D1 and D2 are consecutive, D2 and D3 are not consecutive, D3 and D4 are consecutive, D4 ​​and D5 are not consecutive, and D5 and D6 are consecutive, the specific details can be found in [reference needed]. Figure 3 It is understood that both of these methods can be implemented using a second shift circuit and a second splicing circuit under the control of two counters.

[0112] It should be noted that the second write data counter and the second valid data counter each include different operational logic circuits, which are composed of different counting units and control gates to achieve their respective functions. Specifically, no limitations are made on the specific composition of the operational logic circuits included in the second write data counter and the second valid data counter.

[0113] In practical implementation, the functions of the second write data counter and the second valid data counter 1 can be completed independently by one data counter, or they can be completed in cooperation by multiple small data counters. That is to say, in this embodiment, the write data format conversion module may include at least one data counter. This embodiment only uses the second write data counter and the second valid data counter as an example to illustrate the process of the write data format conversion module obtaining the target data, and does not constitute a limitation on the internal structure of the write data format conversion module. This embodiment uses the real-time counting results of the second write data counter and the second valid data counter to control the second shift circuit and the second splicing circuit to perform bit-width processing on the data input to the write data format conversion module, thereby obtaining the target data. This can effectively avoid data processing with the help of external software or hardware, prevent bus contention, and aims to improve data transmission efficiency.

[0114] It should be noted that the read data format conversion module 1221 and the write data format conversion module 1222 can be used independently or in combination. For example, the read data format conversion module 1221 can choose not to process the data to be transmitted from the read control channel module, but instead directly send the data to be transmitted to the write data format conversion module 1222, which will then process the data.

[0115] In some embodiments, such as Figure 9 As shown, the data format conversion module 122 may also include a memory 124, which can store the intermediate data processed by the data format conversion module 122 and the final target data, so that the write control channel module 123 can read the corresponding target data from the memory after the data format conversion module 122 completes the data format conversion, which can effectively prevent the bus preemption problem and improve the data transmission efficiency.

[0116] During data transfer using a DMA controller, if the amount of data to be transferred is large, the DMA controller may face the challenge of simultaneously transferring a large amount of target data while performing data format conversion through the data format conversion module. This could lead to bus contention between the data format conversion module, read control channel module, and write control channel module, resulting in bus scheduling anomalies. Therefore, when the amount of data to be transferred is large, a memory can be incorporated into the DMA controller. This allows the data format conversion module to convert the data received by the read control channel module and store the resulting target data in the memory. The write control channel module can then read the required target data from the memory after the data format conversion is complete. This effectively avoids bus contention and improves data transfer efficiency.

[0117] The memory 124 can be located on the data format conversion module 122. Of course, in practical applications, the memory 124 can also be connected to the data format conversion module 122. The memory 124 includes, but is not limited to, random access memory (RAM) or first-in-first-out memory (FIFO).

[0118] Specifically, FIFO memory can output data instantly when it is stored. RAM memory, on the other hand, needs to be filled with a sufficient amount of data before outputting, thus preventing bus malfunctions and enhancing protocol compatibility. The amount of data stored in RAM memory depends on the data transmission protocol; provided the data transmission protocol is not violated, the FIFO mode is more efficient.

[0119] In some embodiments, such as Figure 10 As shown, to further improve data transmission efficiency, the memory 124 can be divided into a first memory 1241 and a second memory 1242. The first memory 1241 is used to store the data to be transmitted after being processed by the read data format conversion module 1221; the second memory 1242 is used to store the target data obtained by the write data format conversion module 1222 after converting the data to be processed. Alternatively, the read data format conversion module 1221 can be understood as including the first memory 1241, and the write data format conversion module 1222 includes the second memory 1242.

[0120] To accelerate data processing efficiency and improve data transmission efficiency, the first memory 1241 can be located within the read data format conversion module 1221, and the second memory 1242 can be located within the write data format conversion module 1242. This allows the read data format conversion module 1221 to conveniently store valid data into the first memory 1241, and the write data format conversion module 1222 to conveniently read target data from the second memory 1242, thereby improving data transmission efficiency.

[0121] It should be noted that the first memory 1241 can also be configured to be connected to the read data format conversion module 1221, and the second memory 1232 can also be configured to be connected to the write data format conversion module 1222. Specific details are not limited here.

[0122] In other words, in the embodiments of this application, the first memory 1241 can be disposed within the read data format conversion module 1221 or connected to the read data format conversion module 1221; the second memory 1242 can be disposed within the write data format conversion module 1222 or connected to the write data format conversion module 1222. Furthermore, the positional relationship between the first memory 1241 and the second memory 1242 does not affect each other. The first memory 1241 includes, but is not limited to, FIFO or RAM. The second memory 1242 includes, but is not limited to, FIFO or RAM.

[0123] Specifically, when the amount of data to be transmitted is large, the read data format conversion module 1221 can process the data to be transmitted and store each processed data in sequence into the first memory 1241. When the first memory 1241 contains data and receives a read request from a downstream module, such as the write control channel module of the DMA controller or other devices, it stops storing valid data into the first memory 1241. That is, the DMA controller stops reading data before the write operation can begin. Data can be output from the first memory 1241 to the write data format conversion module 1222 so that data can be written to other devices through the write control channel module, thereby effectively preventing bus scheduling problems.

[0124] When a read request from the write control channel module of the DMA controller or other devices requires reading a large amount of target data, the write data format conversion module 1222 needs to process multiple data stored in the first memory based on the configured target format information to obtain multiple target data that meet the requirements of the destination. Correspondingly, to prevent the write control channel module 123 from causing bus contention, the write data format conversion module 1222 stores the generated target data into the second memory 1242 after each generation. The second memory 1242 stores the target data, and the write data format conversion module 1222 stops storing data into the second memory 1242 after receiving permission from the bus to output data from the second memory 1242. This also effectively prevents bus scheduling problems and improves data transmission efficiency.

[0125] In some embodiments, such as Figure 11 As shown, the read data format conversion module 1221 includes a first shift circuit, a first splicing circuit, a first read data counting circuit, a first valid data counting circuit, a read / write control module, and a first memory. The first read data counting circuit and the first valid data counting circuit are connected to the first shift circuit and the first splicing circuit, and also connect to the read / write control module. The read / write control module controls the first shift circuit and the first splicing circuit to process the data input to the read data format conversion module 1221, and simultaneously stores the processed data in the first memory. This allows for more efficient processing of the data to be transmitted acquired by the read control channel module, thereby improving data transmission efficiency.

[0126] Specifically, once new data is generated by the first shift circuit and the first concatenation circuit, and the first memory is not full, the new data can be stored in the first memory. If the read / write module wants to read data from the first memory, the first memory must contain data, and the data can only be output after receiving a request from a downstream module (such as a read request from the DMA write direction or other devices). Therefore, this design can further avoid the problem of preemption of the system bus by internal modules of the DMA controller, thereby improving data transfer efficiency.

[0127] In some embodiments, such as Figure 12As shown, the write data format conversion module 1222 includes a second shift circuit, a second splicing circuit, a second write data counting circuit, a second valid data counting circuit, a read / write control module, and a second memory. The second write data counting circuit and the second valid data counting circuit are connected to the second shift circuit and the second splicing circuit, and are also connected to the read / write control module to control the second shift circuit and the second splicing circuit to process the data input to the write data format conversion module 1222. Simultaneously, the read / write control module stores the processed data in the second memory.

[0128] Specifically, the second write data counter and the second valid data counter indicate whether the final new data, i.e., the target data, has been generated. Once final new data is generated and the second memory is not full, a write signal is generated for the second memory through the read / write control module, storing the generated new data into the second memory. The memory read / write module can only read data from the second memory if it confirms that the second memory contains data and that the on-chip bus allows writing. Therefore, this design further avoids the problem of preemption of the system bus by internal modules of the DMA controller, thereby improving data transfer efficiency.

[0129] In some embodiments, such as Figure 13 As shown, the DMA controller 12 can send processor configuration information to the configuration module 15 through the configuration interface 142. Specifically, the DMA controller may also include the configuration interface 142 and the configuration module 15. The configuration module 15 is connected to the system bus 14 through the configuration interface 142 and is used to receive the configuration information sent by the processor 16, and to send the configuration information to other modules within the DMA controller 12. Specifically, the configuration information can be written into the registers of each module of the DMA controller 12, so that the other modules within the DMA controller 12 can complete the processing and transmission of the data to be transmitted according to the corresponding configuration information.

[0130] It should be noted that other configuration methods can also be used. For example, the DMA controller 12 may not have a separate configuration module; instead, the implementation logic of the configuration module can be designed in other modules to achieve configuration. Alternatively, a configuration module may be provided, but it can be connected to the system bus through other interfaces. In the embodiments of this application, the configuration interface 142 can be referred to as the first interface, and the data transmission interface 141 can be referred to as the second interface. Of course, the DMA controller may include other interfaces, which are not limited here.

[0131] The DMA controllers provided in the above embodiments integrate data transfer and data format conversion, meaning that data format conversion is performed during data transmission, meeting the needs of scenarios where the data format required by the destination differs from that of the source, thus reducing the complexity of hardware and software design. More importantly, during data transmission using this direct memory access controller, there is no issue of other devices competing with the DMA controller for the system bus, thereby improving data transmission efficiency.

[0132] Please see Figure 14 , Figure 14 This is a flowchart illustrating a data transmission method provided in an embodiment of this application. This data transmission method can be applied to any of the DMA controllers provided in the above embodiments to transmit data to be transmitted from the source to the destination based on the processor's configuration information.

[0133] like Figure 14 As shown, the data transmission method specifically includes steps S101 to S103:

[0134] S101, The read control channel module obtains the data to be transmitted from the source end according to the configuration information.

[0135] Specifically, the DMA controller can receive configuration information sent by the processor through the configuration interface, and then distribute the corresponding configuration information to other modules within the DMA controller, so that the other modules within the DMA controller can complete the data transmission according to the corresponding configuration information.

[0136] In addition, the configuration interface can also be connected to the configuration module, which can be connected to the system bus through the configuration interface to receive configuration information issued by the processor such as the CPU, and then issue the configuration information to other modules inside the DMA controller so that the other modules inside the DMA controller can complete the data transmission according to the corresponding configuration information.

[0137] In addition to information for reading data to be transmitted and information for writing target data to the destination, the configuration information also includes target format information, which is used to convert the data format of the data to be transmitted into target data that is compatible with the destination.

[0138] In some embodiments, the configuration information of the processor configuration may further include read data information and write data information. The read data information is used by the read control channel module to read data to be transmitted from the source, and the write data information is used by the write control channel module to write target data to the destination.

[0139] For example, the read data information can be configured to include the starting address of the data to be transmitted and the length of the data to be transmitted, so that the read control channel module can read the data to be transmitted from the source based on the starting address of the data to be transmitted and the length of the data to be transmitted.

[0140] For example, the read data information can also be configured to include the starting address of the data to be transmitted, the length of the data to be transmitted each time, and the number of times the data to be transmitted is read, so that the read control channel module can read the data to be transmitted from the source end according to the starting address of the data to be transmitted, the length of the data to be transmitted each time, and the number of times the data to be transmitted is read.

[0141] For example, the read data information can be configured to include the starting address of the data to be transmitted, the length of the data to be transmitted each time, the address interval for reading the data to be transmitted, and the number of times the data to be transmitted is read. This allows the read control channel module to read the data to be transmitted from the source based on the starting address of the data to be transmitted, the length of the data to be transmitted each time, the address interval for reading the data to be transmitted, and the number of times the data to be transmitted is read. By configuring the read data information to include the starting address of the data to be transmitted, the length of the data to be transmitted each time, the address interval for reading the data to be transmitted, and the number of times the data to be transmitted is read, the read control channel module can read valid data from the source. Valid data is the data that needs to be transmitted; that is, valid data is the data that actually needs to be transferred.

[0142] It should be noted that the starting address of the data to be transferred corresponds to the starting address of the DMA controller when performing a read operation; the length of the data to be transferred each time corresponds to the amount of data read by the DMA controller each time; the address interval for reading the data to be transferred corresponds to the address jump interval for the DMA controller when performing a read operation; and the number of times the data to be transferred is read specifically refers to the number of reads.

[0143] For writing data information, you can configure the writing data information to include: the starting address of the target data and the length of the target data, so that the write control channel module can write the target data to the destination end according to the starting address of the target data and the length of the target data.

[0144] For example, the write data information can be configured to include: the starting address of the target data, the length of the target data written each time, and the number of times the target data is written, so that the write control channel module can write the target data to the destination end according to the starting address of the target data, the length of the target data written each time, and the number of times the target data is written.

[0145] For example, the write data information can be configured to include: the starting address of the target data, the length of the target data written each time, the address interval for writing the target data, and the number of times the target data is written. This allows the write control channel module to write the target data to the destination based on the starting address of the target data, the length of the target data written each time, the address interval for writing the target data, and the number of times the target data is written. This enables the target data to be written to the desired storage address.

[0146] Therefore, by configuring read and write data information, the flexibility of the DMA controller in reading data from the source and writing data to the destination can be improved. With proper information configuration, the efficiency of data transmission can be further improved.

[0147] S102. The data format conversion module processes the data to be transmitted according to the target format information to obtain the target data.

[0148] In the embodiments of this application, the target format information can be understood as information such as the conversion logic corresponding to the transformation from the first format of the data to be transmitted at the source end to the second format of the target data required at the destination end. Therefore, the data format conversion module can convert the data to be transmitted from the first format to the second format according to the target format information to obtain the target data. It should be understood that the data conversion logic corresponding to different data formats is different, and the target format information that needs to be configured is also different.

[0149] For example, please also refer to Figure 3Assume that the data to be transmitted stored in source terminal 11 starts from address 0 and is arranged in rows from left to right according to the preset address width and ascending address order. Each address is assumed to hold one piece of data, and the preset address width is assumed to be 5 addresses. In this embodiment, source terminal 11 is assumed to store 6 data items D1, D2, D3, D4, D5, and D6. Since the preset address width is 5 addresses, they are arranged in rows of 5 addresses each, forming two rows of data to be transmitted from top to bottom. Specifically, addresses 0 to 4 constitute the first row of data to be transmitted, with address 0 storing data D1, address 1 storing data D2, address 2 storing data D3, and addresses 3 and 4 either not storing data or storing other data; addresses 5 to 9 constitute the second row of data to be transmitted, with address 5 storing data D4, address 6 storing data D5, address 7 storing data D6, and addresses 8 to 9 either not storing data or storing other data. In other words, each row in source 11 stores three valid data entries, and each row contains two addresses for storing invalid data. The data arrangement format in destination 13 differs from that in source 11. Assuming that D1 needs to be stored at address 0, D2 at address 1, D3 at address 5, D4 at address 6, D5 at address 10, and D6 at address 11, then in this embodiment, destination 13 stores two valid data entries per row. The six data entries from source 11 need to be converted in the corresponding order to form three rows of data, with each row containing two valid data entries. The data format conversion module can then convert the arrangement of the data to be transmitted in source 11 into the arrangement of the target data in destination 13 based on the target format information.

[0150] In some embodiments, the data format conversion module may include a read data format conversion module and a write data format conversion module. The read data format conversion module receives data to be transmitted from the source end by the read control channel module and processes the data according to the processor's configuration information to obtain processed data to be transmitted. The write data format conversion module processes the processed data according to the target format information in the configuration information to obtain target data that meets the requirements of the destination end. The write control channel module then writes the target data to the destination end.

[0151] The read control channel module and write control channel module can read the data to be transmitted from the source end and write the target data to the destination end, respectively, based on the read data information and write data information configured by the processor. By setting up separate read data format conversion modules and write data format conversion modules inside the DMA controller, the read data process and the write data process are effectively separated, which can prevent bus contention problems caused by the read data process and the write data process running simultaneously, thereby effectively improving the efficiency of data transmission.

[0152] In some embodiments, the processor configuration information may also include data processing information, such as valid data information and data splicing information, so that the read data format conversion module can process the data to be transmitted according to the data processing information to obtain the processed data to be transmitted.

[0153] For example, the data processing information includes valid data information and a data format conversion module, which can be used to extract data from the data to be transmitted based on the valid data information to obtain valid data, which is then used as the processed data to be transmitted.

[0154] For example, data processing information includes data splicing information and a data format conversion module, which can be used to splice the data to be transmitted according to the data splicing information to obtain spliced ​​data, which is then used as the processed data to be transmitted.

[0155] It should be noted that the specific circuit structure of the read data format conversion module and the write data format conversion module, as well as the processing method of the data to be transmitted, can be referred to the above-described DMA controller embodiment, and will not be described in detail here.

[0156] In some embodiments, the intermediate data processed by the data format conversion module and the final target data can also be stored in a memory. This memory can be located inside the data format conversion module or connected to the data format conversion module, so that the write control channel module can read the corresponding target data from the memory after the data format conversion module completes the data format conversion. This can effectively prevent bus preemption issues and improve data transmission efficiency.

[0157] For example, during data transfer using a DMA controller, if the amount of data to be transferred is large, the DMA controller may face the challenge of simultaneously transferring a large amount of target data while performing data format conversion through the data format conversion module. This could lead to bus contention between the data format conversion module, the read control channel module, and the write control channel module, resulting in bus scheduling anomalies. Therefore, when the amount of data to be transferred is large, a memory can be incorporated into the DMA controller. This allows the data format conversion module to convert the data received by the read control channel module and store the resulting target data in the memory. The write control channel module can then read the required target data from the memory after the data format conversion is complete, effectively avoiding bus contention and improving data transfer efficiency.

[0158] In some embodiments, the data to be transmitted processed by the read data format conversion module can be stored in a first memory; the target data obtained by the write data format conversion module after converting the processed data can be stored in a second memory. The first memory can be located within the read data format conversion module, and the second memory can be located within the write data format conversion module, so that the read data format conversion module can conveniently store valid data into the first memory, and the write data format conversion module can conveniently read the target data from the second memory, thereby improving data transmission efficiency.

[0159] In practical applications, when the amount of data to be transmitted is large, the read data format conversion module can process the data to be transmitted, storing each processed data piece sequentially into the first memory. When the first memory contains data and a read request is received from a downstream module, such as the write control channel module of the DMA controller or other devices, the module stops storing valid data into the first memory. In other words, the controller stops reading data before the write operation can begin. Data can be output from the first memory to the write data format conversion module so that data can be written to other devices through the write control channel module, thereby effectively preventing bus scheduling problems.

[0160] In practical applications, when a write control channel module from the DMA controller or other devices requires reading a large amount of target data, the write data format conversion module needs to process multiple data stored in the first memory based on the configured target format information to obtain multiple target data that meet the requirements of the destination. Correspondingly, to prevent the write control channel module from preempting the bus, the write data format conversion module stores each generated target data into the second memory. Once the second memory contains the target data and the write data format conversion module receives permission from the bus to output data from the second memory, it stops storing data into the second memory. This effectively prevents bus scheduling problems and improves data transmission efficiency.

[0161] S103, The write control channel module transmits the target data to the destination terminal according to the configuration information.

[0162] For example, the configured write data information includes: the starting address of the target data, the length of each write of the target data, the address interval for writing the target data, and the number of writes of the target data; the write control channel module can transmit the write data to the destination end and transmit the target data to the destination end according to the write data information in the configuration information.

[0163] It should be understood that the detailed implementation process of each of the above steps can be found in the corresponding references. Figures 1 to 13 The descriptions of the corresponding parts are not repeated here.

[0164] The data transmission method based on the DMA controller provided in the above embodiments also realizes data format conversion during data transmission. It is suitable for scenarios where the data format required by the destination is different from that of the source. It will not cause other devices and the direct memory access controller to compete for the system bus due to data format conversion, thereby improving the efficiency of data transmission.

[0165] Please see Figure 15 , Figure 15 This is a schematic flowchart illustrating another data transmission method provided in an embodiment of this application. This data transmission method can be applied to the data transmission system provided in the above embodiments to transmit data to be transmitted from a source to a destination.

[0166] like Figure 15 As shown, the data transmission method specifically includes steps S201 to S208:

[0167] S201. The processor sends configuration information to the configuration module of the DMA controller via the system bus.

[0168] S202. The configuration module configures each module of the DMA controller according to the configuration information.

[0169] Specifically, the DMA controller modules may include a read control channel module, a write control channel module, a read data format conversion module, and a write data format conversion module; the configuration information may include read data information, write data information, data processing information, and target format information.

[0170] S203, Start the DMA controller.

[0171] S204. The read control channel module initiates a DMA read request based on the configuration information to obtain the data to be transmitted from the source end connected to the system bus.

[0172] Specifically, the read control channel module can initiate a DMA read request or continuously initiate DMA read requests based on the read data information in the configuration information.

[0173] S205. The data format conversion module processes the data to be transmitted according to the data processing information in the configuration information, obtains the processed data to be transmitted, and stores it in the first memory.

[0174] S206. The write control channel module initiates a DMA write request based on the write data information in the configuration information in order to prepare to send data to the destination connected to the system bus.

[0175] S207. The write data format conversion module converts the processed data to be transmitted according to the target format information in the configuration information to obtain the target data, which is then stored in the second memory.

[0176] S208: The write data format conversion module reads the target data from the second memory according to the DMA write request and sends it to the destination on the system bus through the write control channel module.

[0177] By using the above data transmission method, when the data format required at the destination is different from that at the source, the data format can be converted during the data transfer process. This allows the data at the source to be transferred to the destination in one go, thus avoiding the problem of other devices and the DMA controller competing for the system bus due to different data formats. This improves the efficiency of data transmission.

[0178] It should be noted that steps S201 to S208 of the data transmission method are not described in detail in this embodiment of the application. For a better understanding, please refer to the above-described embodiments regarding the DMA controller. This data transmission method can achieve the same or similar technical effects as the embodiments of the DMA controller, and therefore will not be described in detail here.

[0179] It should be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application.

[0180] It should also be understood that the term “and / or” as used in this application and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0181] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A direct memory access controller, characterized in that, The direct memory access controller is connected to the system bus and is used to transmit data from the source end to the destination end according to the processor's configuration information, the configuration information including target format information. The direct memory access controller includes: The read control channel module is used to obtain the data to be transmitted from the source end according to the configuration information. The data format conversion module is used to process the data to be transmitted according to the target format information to obtain the target data; The write control channel module is used to transmit the target data to the destination terminal according to the configuration information; The data format conversion module includes a first bit width processing circuit and a first counting circuit, a second bit width processing circuit and a second counting circuit; the first counting circuit is used to count the number of data to be transmitted; the first bit width processing circuit is used to perform bit width processing on the data to be transmitted under the control of the first counting circuit to obtain processed data to be transmitted; the second counting circuit is used to count the number of processed data to be transmitted; the second bit width processing circuit is used to perform bit width processing on the processed data to be transmitted under the control of the second counting circuit to obtain the target data.

2. The direct memory access controller according to claim 1, characterized in that, The data format conversion module includes a read data format conversion module and a write data format conversion module; the configuration information also includes data processing information. The read data format conversion module is used to process the data to be transmitted according to the data processing information to obtain the processed data to be transmitted. The write data format conversion module is used to process the processed data to be transmitted according to the target format information to obtain the target data.

3. The direct memory access controller according to claim 2, characterized in that, The data processing information includes valid data information, and the valid data in the valid data information is the data that needs to be transmitted. The read data format conversion module is used to extract data from the data to be transmitted based on the valid data information to obtain valid data, which is then used as the processed data to be transmitted.

4. The direct memory access controller according to claim 1, characterized in that, The first bit-width processing circuit includes a first shift circuit and a first splicing circuit; and / or, the second bit-width processing circuit includes a second shift circuit and a second splicing circuit; The first shift circuit is used to shift the data to be transmitted; the first splicing circuit splices the data after the first shift circuit shifts to obtain the processed data to be transmitted. The second shift circuit is used to shift the data to be transmitted or the processed data to be transmitted. The second splicing circuit is used to splice the data after the shifting process of the second shifting circuit to obtain the target data.

5. The direct memory access controller according to claim 2, characterized in that, The first counting circuit includes a first read data counter and a first valid data counter. Both the first read data counter and the first valid data counter are connected to the first bit-width processing circuit. The first read data counter is used to count the number of data to be transmitted input to the read data format conversion module, and the first valid data counter is used to count the number of valid data items in the data to be transmitted; and / or, The second counting circuit includes a second write data counter and a second valid data counter. Both the second write data counter and the second valid data counter are connected to the second bit-width processing circuit. The second write data counter is used to count the number of data input to the write data format conversion module, and the second valid data counter is used to count the number of valid data in the data input to the write data format conversion module.

6. The direct memory access controller according to any one of claims 2, 3, or 5, characterized in that, The read data format conversion module includes a first memory; and / or, the write data format conversion module includes a second memory; The first memory is used to store the processed data to be transmitted; the second memory is used to store the target data.

7. The direct memory access controller according to claim 1, characterized in that, The configuration information includes read data information and write data information; The read data information includes the starting address of the data to be transmitted, the length of the data to be transmitted each time it is read, the address interval for reading the data to be transmitted, and the number of times the data to be transmitted is read. The write data information includes: the starting address of the target data, the length of each write of the target data, the address interval between writes of the target data, and the number of writes of the target data.

8. The direct memory access controller according to claim 1, characterized in that, The direct memory access controller includes a first interface and a second interface, and the direct memory access controller further includes: A configuration module, which is connected to the system bus through the first interface, is used to receive configuration information from the processor and write the configuration information into the register of the direct memory access controller; The read control channel module and the write control channel module are connected to the system bus through the second interface, and are used to obtain the data to be transmitted from the source end and send the target data to the destination end through the system bus.

9. A data transmission method, characterized in that, The direct memory access controller according to any one of claims 1-8 is used to transmit data from a source end to a destination end according to the processor's configuration information, the configuration information including target format information; The data transmission method includes: The read control channel module obtains the data to be transmitted from the source end according to the configuration information; The data format conversion module processes the data to be transmitted according to the target format information to obtain the target data; The write control channel module transmits the target data to the destination terminal according to the configuration information.

10. The method according to claim 9, characterized in that, The configuration information includes read data information and write data information; The read data information includes the starting address of the data to be transmitted, the length of the data to be transmitted each time it is read, the address interval for reading the data to be transmitted, and the number of times the data to be transmitted is read. The write data information includes: the starting address of the target data, the length of each write of the target data, the address interval between writes of the target data, and the number of writes of the target data.

11. The method according to claim 9, characterized in that, The data format conversion module includes a read data format conversion module and a write data format conversion module; the configuration information also includes data processing information. The read data format conversion module is used to process the data to be transmitted according to the data processing information to obtain the processed data to be transmitted. The write data format conversion module is used to process the processed data to be transmitted according to the target format information to obtain the target data.

12. The method according to claim 11, characterized in that, The read data format conversion module includes a first memory; and / or, the write data format conversion module includes a second memory; the method further includes: The data to be transmitted, processed by the read data format conversion module, is stored in the first memory; and / or the target data is stored in the second memory.

13. A data transmission system, characterized in that, Includes the direct memory access controller as described in any one of claims 1 to 8.

Images