A system, method, device and medium for dynamic switching of memory channel control

Abstract

The application provides a memory channel control right dynamic switching system, method, device and medium, the system comprises: CPU is connected with CPLD, BMC, BOIS respectively, data selector is connected with CPU, CPLD, BMC data through I3C bus respectively, the control signal output end of CPU is connected with the signal input end of data selector, the control signal output end GPIO0 of CPU is connected with the signal input end S0 of data selector, the control signal output end GPIO1 of CPU is connected with the signal input end S1 of data selector, the BIOS of CPU end can selectively dynamically switch the control right of I3C channel to other users after using the SPD information of memory.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to a system, method, apparatus, and medium for dynamically switching control of memory channels. Background Technology

[0002] In the current server field, with the development of information technology, high-capacity, high-bandwidth DDR5 memory is gradually replacing DDR4. This has led to the adoption of the faster I3C communication protocol for CPUs and other host devices to access SPD (Serial Presence Detect) information on memory. Simultaneously, new-generation BMCs (such as ASPEED and AST2600) also support the I3C communication protocol. Therefore, as long as there is a hardware connection, the BMC can also access the memory SPD via I3C. This has led to different application scenarios with varying SPD access permissions. One scenario requires that only the CPU has in-band access to the SPD, while the BMC has no out-of-band access. Another scenario allows the BMC to take over SPD access from the CPU for out-of-band access. A third scenario requires that after the CPU completes necessary memory initialization by accessing the SPD, neither the CPU nor the BMC is allowed to continue accessing the SPD. For a single boot process, the software behavior will inevitably be different for different application scenarios. Since only one master device can occupy the same memory I3C channel at a time, how to provide a method to dynamically switch control of the memory I3C channel during a boot process is an urgent problem to be solved.

[0003] In the prior art, invention patent application number CN202111154341.0 discloses a device management method, apparatus, device, and readable medium based on I3C. It provides a channel for the BMC to access DIMM devices via I3C, monitor device status, and obtain error information from the DIMM devices during debugging. First, the first master port of the first I3C connection node is connected to both the CPU and the BMC. The first slave port of the first I3C connection node is connected to the memory device according to the number of CPU channels. The BMC obtains the first monitoring information of the memory device through I3C communication. Then, the second master port of the second I3C connection node is connected to both the CPU and the BMC. The second slave port of the second I3C connection node is connected to several monitoring devices. The BMC obtains the second monitoring information of these monitoring devices through I3C communication. Finally, the third master port of the third I3C connection node is connected to both the BMC and a CPLD with PRF functionality. The third slave port of the third I3C connection node is connected to the platform controller. The BMC obtains the third monitoring information of the CPLD verifying the firmware via PRF through I3C communication.

[0004] However, this technical solution only provides one I3C channel for the BMC to access the memory's SPD information, without considering the issue of switching control of the memory I3C channel. Since only one master device can occupy this channel at a time, the CPU or BMC cannot acquire control of this channel at any time. Summary of the Invention

[0005] To address the above problems, the present invention aims to provide a system, method, device, and medium for dynamically switching memory channel control, enabling the CPU-side BIOS to selectively and dynamically switch I3C channel control to other users after using the memory's SPD information.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a dynamic switching system for memory channel control, comprising: a CPU, a CPLD, a BMC, a BIOS, a data selector, and a DIMM slot; the CPU is connected to the CPLD, BMC, and BIOS respectively, the data selector is connected to the CPU, CPLD, and BMC respectively via an I3C bus, and the control signal output terminal of the CPU is connected to the signal input terminal of the data selector.

[0007] Furthermore, the CPU's control signal output terminal GPIO0 is connected to the data selector's signal input terminal S0, and the CPU's control signal output terminal GPIO1 is connected to the data selector's signal input terminal S1.

[0008] Furthermore, the data selector is equipped with data transmission ports D0, D1, D2, and D3; data transmission port D0 is connected to the CPU via the I3C bus, data transmission port D1 is connected to the BMC via the I3C bus, data transmission port D2 is connected to the CPLD via the I3C bus, and data transmission port D3 is grounded.

[0009] Furthermore, the BMC is used to store JSON files in the H2B SRAM area of ​​memory. The JSON file records the Master value used to set the current memory I3C channel control. The CPU reads the Master value to generate corresponding control signals and sends them to the data selector through the control signal output terminals GPIO0 and GPIO1. The data selector switches between data transmission ports D0, D1, and D2 according to the control signals.

[0010] Accordingly, the present invention also discloses a method for dynamically switching memory channel control, comprising: the BMC storing the Master value representing the current memory I3C channel control in the H2B SRAM area of ​​memory in the form of a JSON file;

[0011] Users can adjust the Master value stored in the H2B SRAM area of ​​the memory as needed using out-of-band commands; during the startup phase, the CPU is used to initialize the memory through BIOS settings.

[0012] The BMC H2B device is initialized via BIOS, enabling access to its SRAM area, and the Master value is read by parsing the JSON file.

[0013] The master device with control over the current memory I3C channel is determined based on the Master value, and the corresponding control is switched, and access control is performed during the startup process.

[0014] Furthermore, the Master value is a combination of the GPIO0 and GPIO1 signals; when both GPIO0 and GPIO1 are 0, the Master value is 00, and the CPU is the master device with control over the current memory I3C channel; when both GPIO0 and GPIO1 are 1, the Master value is 01, and the BMC is the master device with control over the current memory I3C channel; when both GPIO0 and GPIO1 are 1, the Master value is 10, and the CPLD is the master device with control over the current memory I3C channel.

[0015] Furthermore, during the startup phase, the CPU completes memory initialization through BIOS settings, including: during the startup phase, the BIOS initializes the signal combination consisting of GPIO0 and GPIO1 signals to 00, giving the CPU control over the current memory I3C channel; on the CPU side, the BIOS reads the memory SPD information through the I3C bus to complete memory initialization.

[0016] Furthermore, based on the Master value, the master device with control over the current memory I3C channel is determined, and the corresponding controller switch is performed. Access control is also performed during the startup process, including:

[0017] When the Master value is 00, the BIOS maintains the signal combination of GPIO0 and GPIO1 at 00, and the CPU continues to have control over the I3C channel. During the subsequent boot process and after entering the system, the CPU continues to access and set the memory SPD information.

[0018] When the Master value is 01, the BIOS changes the combined value of the GPIO0 and GPIO1 signals to 01. After receiving the control signal, the data selector switches control of the I3C channel to the BMC. During the subsequent boot process and after entering the system, only the CPU has the permission to access and set the memory SPD information. When the Master value is 10, the BIOS changes the combined value of the GPIO0 and GPIO1 signals to 10. After receiving the control signal, the data selector switches control of the I3C channel to the CPLD. During the subsequent boot process and after entering the system, no device has the permission to access and set the memory SPD information.

[0019] Accordingly, the present invention discloses a dynamic switching device for memory channel control, comprising:

[0020] Memory, used to store dynamic switching programs for memory channel control;

[0021] A processor, when executing the dynamic switching procedure for memory channel control, implements the steps of the dynamic switching method for memory channel control as described in any of the above.

[0022] Accordingly, the present invention discloses a readable storage medium storing a dynamic switching program for memory channel control, wherein when the dynamic switching program for memory channel control is executed by a processor, it implements the steps of the dynamic switching method for memory channel control as described in any of the above claims.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention discloses a dynamic switching system, method, device and medium for memory channel control. By adding a switching circuit for memory I3C channel control and adding switching logic in the BIOS, the user's switching requirements are stored in the BMC H2B SRAM space. During the startup process, the user's requirements are parsed, and then the control of the memory I3C channel is dynamically switched to the CPU, BMC or CPLD. The switching method is flexible and efficient and can adapt to application scenarios with different requirements for memory SPD access permissions.

[0024] Therefore, it is evident that the present invention has outstanding substantive features and significant progress compared with the prior art, and the beneficial effects of its implementation are also obvious. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0026] Figure 1 This is a system structure diagram of a specific embodiment of the present invention.

[0027] Figure 2 This is the data structure of the Master value in a specific embodiment of the present invention.

[0028] Figure 3 This is a flowchart illustrating a specific embodiment of the present invention. Detailed Implementation

[0029] The core of this invention is to provide a dynamic switching system for memory channel control. In the prior art, only one I3C channel allows the BMC to access the memory's SPD information, without considering the issue of switching memory I3C channel control. Since only one master device can occupy this channel at a time, the CPU or BMC cannot acquire control of this channel at any time, and cannot achieve dynamic switching of memory I3C channel control during a single startup.

[0030] The dynamic switching system for memory channel control provided by this invention includes: a CPU, CPLD, BMC, BIOS, a data selector, and a DIMM slot. The CPU is connected to the CPLD, BMC, and BIOS respectively. The data selector is connected to the CPU, CPLD, and BMC via the I3C bus. The control signal output terminal of the CPU is connected to the signal input terminal of the data selector. Therefore, this invention enables the BIOS on the CPU side to selectively and dynamically switch control of the I3C channel to other users after using the memory's SPD information.

[0031] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] Example 1:

[0033] like Figure 1As shown, this embodiment provides a dynamic switching system for memory channel control, including: CPU, CPLD, BMC, BIOS, data selector (SEL) and DIMM slot; the CPU is connected to CPLD, BMC and BIOS respectively, the data selector is connected to CPU, CPLD and BMC via I3C bus respectively, and the control signal output terminal of the CPU is connected to the signal input terminal of the data selector.

[0034] The CPU's control signal output terminal GPIO0 is connected to the data selector's signal input terminal S0, and the CPU's control signal output terminal GPIO1 is connected to the data selector's signal input terminal S1. The data selector has data transmission ports D0, D1, D2, and D3. Data transmission port D0 is connected to the CPU via an I3C bus, data transmission port D1 is connected to the BMC via an I3C bus, data transmission port D2 is connected to the CPLD via an I3C bus, and data transmission port D3 is grounded.

[0035] It should be noted that the Master of the I3C channel of the memory DIMM is controlled by a 4-to-1 data selector, and the selection signals of S0 and S1 are controlled by the CPU's GPIO0 and GPIO1. When S0 and S1 inputs are 00, the CPU has control over the input of D0; when S0 and S1 inputs are 01, the BMC has control over the input of D1; when S0 and S1 inputs are 10, the CPLD has control over the input of D2; and the input of D3 is not grounded.

[0036] Users set the Master value to be adjusted in this storage area using out-of-band commands. The data structure of the Master value is as follows: Figure 2 As shown, when the Master needs to be the CPU, set S0S1 to 00, and GPIO0 and GPIO1 are 0 respectively; when the Master needs to be the BMC, set S0S1 to 01, and GPIO0 and GPIO1 are 1 respectively; when the Master needs to be the CPLD, set S0S1 to 10, and GPIO0 and GPIO1 are 0 respectively.

[0037] This embodiment provides a dynamic switching system for memory channel control. By adding a switching circuit for memory I3C channel control and adding switching logic in the BIOS, the system utilizes the BMC H2B SRAM space to store user switching requirements. During the startup process, the system parses the user's requirements and then dynamically switches the control of the memory I3C channel to the CPU, BMC, or CPLD. The switching method of this system is flexible and efficient and can adapt to application scenarios with different requirements for memory SPD access permissions.

[0038] Example 2:

[0039] Based on Example 1, such as Figure 3 As shown, the present invention also discloses a method for dynamically switching memory channel control, comprising the following steps:

[0040] S1: The BMC stores the Master value, representing the current control of the memory I3C channel, in the H2B SRAM area of ​​memory as a JSON file.

[0041] The Master value is a combination of the GPIO0 and GPIO1 signals. When both GPIO0 and GPIO1 are 0, the Master value is 00, and the CPU is the master device with control over the current memory I3C channel. When both GPIO0 and GPIO1 are 1, the Master value is 01, and the BMC is the master device with control over the current memory I3C channel. When both GPIO0 and GPIO1 are 1, the Master value is 10, and the CPLD is the master device with control over the current memory I3C channel.

[0042] This step enables the BMC to store the current memory I3C channel to be switched to the Master device in the H2B SRAM area as a JSON file.

[0043] S2: Users can adjust the Master value stored in the H2B SRAM area of ​​memory using out-of-band commands as needed.

[0044] Specifically, when the Master needs to be the CPU, set S0S1 to 00, and GPIO0 and GPIO1 are 0 respectively; when the Master needs to be the BMC, set S0S1 to 01, and GPIO0 and GPIO1 are 1 respectively; when the Master needs to be the CPLD, set S0S1 to 10, and GPIO0 and GPIO1 are 0 respectively.

[0045] S3: During the startup phase, the CPU is used to initialize the memory through BIOS settings.

[0046] Specifically, during the startup phase, the CPU initializes the memory through BIOS settings. This includes: initializing the GPIO0 and GPIO1 signal combination to 00 via the BIOS, granting the CPU control over the current memory I3C channel. Then, on the CPU side, the BIOS reads the memory SPD information via the I3C bus to complete the memory initialization.

[0047] S4: Initialize the BMC H2B device via BIOS, enabling access to its SRAM area, and read the Master value by parsing the JSON file.

[0048] S5: Determine the master device with control over the current memory I3C channel based on the Master value, perform the corresponding control switch, and perform access control during the startup process.

[0049] Specifically, based on the different Master values, there are three scenarios:

[0050] 1. When the Master value is 00, the BIOS keeps the signal combination consisting of GPIO0 and GPIO1 signals at 00, and the CPU continues to have control over the I3C channel. During the subsequent boot process and after entering the system, the CPU continues to access and set the memory SPD information.

[0051] It is important to note that in this scenario, the BIOS keeps the combination of GPIO0 and GPIO1 at 00, and the CPU continues to have control over the I3C channel. During the subsequent boot process and after entering the system, the CPU can continue to access the SPD to obtain information and set certain bits of the SPD to store information.

[0052] 2. When the Master value is 01, the BIOS changes the signal combination value of GPIO0 and GPIO1 to 01. After receiving the control signal, the data selector switches the control of the I3C channel to the BMC. In the subsequent boot process and after entering the system, only the CPU has the right to access and set the memory SPD information.

[0053] It is important to note that in this scenario, when IOS changes the combination of GPIO0 and GPIO1 to 0 and 1, the I3C channel is switched to BMC under the control of this GPIO combination. During the subsequent boot process and after entering the system, only BMC can access the memory SPD to obtain information and set certain bits of the SPD to store information.

[0054] 3. When the Master value is 10, the BIOS changes the signal combination value of GPIO0 and GPIO1 to 10. After receiving the control signal, the data selector switches the control of the I3C channel to the CPLD. During the subsequent boot process and after entering the system, no device has the permission to access and set the memory SPD information.

[0055] It is important to note that in this scenario, the BIOS changes the combination of GPIO0 and GPIO1 to 10. Under the control of this GPIO combination, the I3C channel is switched to the CPLD. Neither the CPU nor the BMC has the ability to access the memory SPD information. That is, neither in-band nor out-of-band methods can control the memory SPD. At this time, the security level is the highest, which can prevent the memory SPD information from being read or modified.

[0056] This embodiment provides a dynamic switching system for memory channel control. By adding a switching circuit for memory I3C channel control and adding switching logic in the BIOS, the system utilizes the BMC H2B SRAM space to store user switching requirements. During the startup process, the system parses the user's requirements and then dynamically switches the control of the memory I3C channel to the CPU, BMC, or CPLD. This method is flexible and efficient in the switching process and can adapt to application scenarios with different requirements for memory SPD access permissions.

[0057] Example 3:

[0058] This embodiment discloses a dynamic switching device for memory channel control, including a processor and a memory; wherein, when the processor executes the dynamic switching program for memory channel control stored in the memory, it performs the following steps:

[0059] 1. The BMC stores the Master value, representing the current control of the memory I3C channel, in the H2B SRAM area of ​​memory as a JSON file.

[0060] 2. Users can adjust the Master value stored in the H2B SRAM area of ​​memory using out-of-band commands as needed.

[0061] 3. During the startup phase, the CPU is used to initialize the memory through BIOS settings.

[0062] 4. Initialize the BMC H2B device through the BIOS to enable access to its SRAM area and read the Master value by parsing the JSON file.

[0063] 5. Determine the master device with control over the current memory I3C channel based on the Master value, perform the corresponding control switch, and implement access control during the startup process.

[0064] Furthermore, the dynamic switching device for memory channel control in this embodiment may further include:

[0065] The input interface is used to acquire a dynamic switching program for memory channel control imported from the outside, and save the acquired dynamic switching program for memory channel control to the memory. It can also be used to acquire various instructions and parameters transmitted from external terminal devices and transmit them to the processor, so that the processor can use these instructions and parameters to perform corresponding processing. In this embodiment, the input interface may specifically include, but is not limited to, a USB interface, a serial interface, a voice input interface, a fingerprint input interface, a hard disk read interface, etc.

[0066] An output interface is used to output various data generated by the processor to connected terminal devices, so that other terminal devices connected to the output interface can obtain the various data generated by the processor. In this embodiment, the output interface may include, but is not limited to, a USB interface, a serial interface, etc.

[0067] A communication unit is used to establish a remote communication connection between the dynamic switching device for memory channel control and an external server, so that the dynamic switching device for memory channel control can mount the image file to the external server. In this embodiment, the communication unit may specifically include, but is not limited to, a remote communication unit based on wireless communication technology or wired communication technology.

[0068] The keyboard is used to acquire various parameter data or commands input by the user through real-time keystrokes.

[0069] The monitor is used to display relevant information in real time regarding the process of locating a short circuit in the server's power supply line.

[0070] A mouse can be used to assist users in inputting data and simplifying user operations.

[0071] Example 4:

[0072] This embodiment also discloses a readable storage medium, which includes random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable hard disk, CD-ROM, or any other form of storage medium known in the art. The readable storage medium stores a dynamic switching program for memory channel control, which, when executed by a processor, performs the following steps:

[0073] 1. The BMC stores the Master value, representing the current control of the memory I3C channel, in the H2B SRAM area of ​​memory as a JSON file.

[0074] 2. Users can adjust the Master value stored in the H2B SRAM area of ​​memory using out-of-band commands as needed.

[0075] 3. During the startup phase, the CPU is used to initialize the memory through BIOS settings.

[0076] 4. Initialize the BMC H2B device through the BIOS to enable access to its SRAM area and read the Master value by parsing the JSON file.

[0077] 5. Determine the master device with control over the current memory I3C channel based on the Master value, perform the corresponding control switch, and implement access control during the startup process.

[0078] In summary, this invention enables the CPU-side BIOS to selectively and dynamically switch control of the I3C channel to other users after using the SPD information of the memory. For example, the CPU or BMC can continue to have read and write permissions to the SPD, or neither of them can continue to access the SPD, in order to adapt to application scenarios with different requirements for memory SPD access permissions.

[0079] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the systems disclosed in the embodiments; relevant details can be found in the method section.

[0080] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0081] In the embodiments provided by this invention, it should be understood that the disclosed systems, methods, and approaches can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between systems or units may be electrical, mechanical, or other forms.

[0082] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0083] In addition, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit.

[0084] Similarly, in the various embodiments of the present invention, each processing unit can be integrated into a functional module, or each processing unit can exist physically, or two or more processing units can be integrated into a functional module.

[0085] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0086] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0087] The present invention has provided a detailed description of the method, system, apparatus, and readable storage medium for dynamically switching memory channel control. Specific examples have been used to illustrate the principles and implementation methods of the invention. The descriptions of these embodiments are merely illustrative of the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to the invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims.

Claims

1. A method for dynamically switching control of a memory channel, characterized in that, The method employs a dynamic switching system for memory channel control, which includes: CPU, CPLD, BMC, BIOS, data selector, and DIMM slot; the CPU is connected to CPLD, BMC, and BIOS respectively, the data selector is connected to CPU, CPLD, and BMC via I3C bus respectively, and the control signal output terminal of the CPU is connected to the signal input terminal of the data selector. The CPU's control signal output terminal GPIO0 is connected to the signal input terminal S0 of the data selector, and the CPU's control signal output terminal GPIO1 is connected to the signal input terminal S1 of the data selector. The data selector has data transmission ports D0, D1, D2, and D3. Data transmission port D0 is connected to the CPU via an I3C bus, data transmission port D1 is connected to the BMC via an I3C bus, data transmission port D2 is connected to the CPLD via an I3C bus, and data transmission port D3 is grounded. The BMC is used to store JSON files in the H2B SRAM area of ​​memory. The JSON files record the Master value used to set the current memory I3C channel control. The CPU reads the Master value and generates corresponding control signals, which are sent to the data selector through control signal output terminals GPIO0 and GPIO1. The data selector switches between data transmission ports D0, D1, and D2 according to the control signals. The method includes: The BMC stores the Master value, representing the current control of the memory I3C channel, in the H2B SRAM area of ​​memory as a JSON file; Users can adjust the Master value stored in the H2B SRAM area of ​​memory using out-of-band commands as needed; During the startup phase, the CPU is used to initialize the memory through BIOS settings. The BMC H2B device is initialized via BIOS, enabling access to its SRAM area, and the Master value is read by parsing the JSON file. Based on the Master value, the master device with control over the current memory I3C channel is determined, and the corresponding control is switched. Access control is performed during the startup process, including: When the Master value is 00, the BIOS maintains the signal combination of GPIO0 and GPIO1 at 00, and the CPU continues to have control over the I3C channel. During the subsequent boot process and after entering the system, the CPU continues to access and set the memory SPD information. When the Master value is 01, the BIOS changes the signal combination value of GPIO0 and GPIO1 to 01. After receiving the control signal, the data selector switches the control of the I3C channel to the BMC. In the subsequent boot process and after entering the system, only the CPU has the right to access and set the memory SPD information. When the Master value is 10, the BIOS changes the signal combination value of GPIO0 and GPIO1 to 10. After receiving the control signal, the data selector switches the control of the I3C channel to the CPLD. During the subsequent boot process and after entering the system, no device has the permission to access and set the memory SPD information.

2. The method for dynamically switching memory channel control according to claim 1, characterized in that, The Master value is a combination of the GPIO0 and GPIO1 signals. When GPIO0 signal is 0 and GPIO1 signal is 0, the Master value is 00, and the CPU is the master device that has control over the current memory I3C channel; When GPIO0 signal is 0 and GPIO1 signal is 1, the Master value is 01, and BMC is the master device that has control over the current memory I3C channel; When GPIO0 signal is 1 and GPIO1 signal is 0, the Master value is 10, and CPLD is the master device that has control over the current memory I3C channel.

3. The method for dynamically switching memory channel control according to claim 2, characterized in that, During the startup phase, the CPU initializes the memory via BIOS settings, including: During the startup phase, the BIOS initializes the signal combination consisting of GPIO0 and GPIO1 signals to 00, giving the CPU control over the current memory I3C channel. On the CPU side, the BIOS uses the I3C bus to read the memory SPD information and complete the memory initialization.

4. A dynamic switching device for memory channel control, characterized in that, include: Memory, used to store dynamic switching programs for memory channel control; A processor, when executing the dynamic switching procedure for memory channel control, implements the steps of the dynamic switching method for memory channel control as described in any one of claims 1 to 3.

5. A readable storage medium, characterized in that: The readable storage medium stores a dynamic switching program for memory channel control, which, when executed by a processor, implements the steps of the dynamic switching method for memory channel control as described in any one of claims 1 to 3.

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