An electronic device and its PCIe topology configuration method and apparatus

Abstract

An electronic device and its PCIe topology configuration method and apparatus are disclosed, relating to the field of computer technology. The electronic device includes at least one main processor, multiple graphics processors (GPUs), and a management chip. Each main processor and the multiple GPUs are interconnected via peripheral components and connected to at least one switching device via a PCIe bus. Each switching device is communicatively connected to the management chip. The management chip generates switching information corresponding to a target application scenario based on first information, including type identification information and / or configuration information for each GPU. The switching devices switch the PCIe bus connections between the multiple GPUs and their corresponding main processors according to the switching information, adapting the configured topology to the current target application scenario and facilitating optimal application performance of the electronic device. This reduces manual intervention during topology configuration, significantly improving the efficiency of PCIe bus topology configuration in the electronic device.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an electronic device and a PCIe topology configuration method and apparatus thereof. Background Technology

[0002] GPU (graphics processing unit) servers offer a variety of GPU options, with different types typically suited for scenarios such as training, inference, and high-performance computing (HPC). Enterprise users often aim to leverage a single GPU server to cover as many scenarios as possible. However, each scenario requires a specific PCIe bus topology configuration within the GPU server to support GPU communication. Currently, configuring the PCIe bus topology is often done manually by professionals, which is inefficient. Summary of the Invention

[0003] This application provides an electronic device and its PCIe topology configuration method and apparatus, which can realize adaptive switching of PCIe topology in a server.

[0004] In a first aspect, this application provides an electronic device comprising at least one main processor, multiple graphics processors, and a management chip. Each main processor is interconnected with the multiple graphics processors via a peripheral component interconnection PCIe bus connected to at least one switching device. Each switching device is communicatively connected to the management chip. The management chip is used to generate switching information corresponding to a target application scenario based on first information, the first information including type identification information and / or configuration information for each graphics processor. The switching devices are used to switch the PCIe bus connection relationship between the multiple graphics processors and the corresponding main processor based on the switching information.

[0005] In this embodiment, the electronic device can be a workstation, a GPU server, or a super terminal, etc. The multiple graphics processors can be GPUs used for training / inference scenarios in deep learning, GPUs used for graphics rendering scenarios, or GPUs used for HPC scenarios, but are not limited to these. The multiple graphics processors are connected to a switching device via a PCIe bus, and the switching device can switch the communication path between the GPU and the corresponding main processor.

[0006] In a possible implementation of this embodiment, the management chip of the electronic device (such as a baseboard management controller, BMC) can monitor and obtain the type identification information or other configuration information of the graphics processors after they are connected to the electronic device. It then generates switching information corresponding to the target application scenario applicable to the current graphics processor, controlling the switching device to perform corresponding actions. This completes the configuration of the PCIe bus topology between multiple graphics processors and their corresponding main processor, ensuring the configured topology adapts to the current target application scenario and facilitating optimal application performance for the electronic device. Furthermore, the configuration process reduces manual intervention, significantly improving the efficiency of PCIe bus topology configuration in the electronic device.

[0007] In some possible implementations, the electronic device includes a firmware module that reads the type identification information of each graphics processor as the first piece of information to be reported to the management chip.

[0008] In this implementation, the firmware module can be the BIOS firmware stored in the electronic device's memory. The BIOS automatically reads the GPU's type identification information and reports it to the BMC, eliminating the need for manual input of configuration information. This forms a closed-loop control system from automatically collecting GPU-related information to the BMC automatically generating switching information, and finally, the switching device configures the GPU's topology based on the switching information, thus achieving automated configuration.

[0009] In some possible implementations, the management chip is specifically used to determine the target application scenario corresponding to the type identifier information in the first information based on the predefined mapping relationship between type identifier information and application scenario.

[0010] In this implementation, by utilizing the predefined mapping relationship between type identification information and application scenarios, the target application scenario to which the user wants the device to be applied can be quickly and efficiently determined after the management chip obtains the first information.

[0011] In some possible implementations, the management chip is also used to query a preset scenario dictionary based on the target application scenario, match the target PCIe bus topology corresponding to the target application scenario, and the scenario dictionary is used to record the mapping relationship between multiple application scenarios and multiple PCIe bus topologies, and generate corresponding switching information based on the target PCIe bus topology.

[0012] In this implementation, by using a predefined scenario dictionary, the PCIe bus topology that is adapted to the target application scenario can be determined quickly and efficiently after the management chip determines the target application scenario.

[0013] In some possible implementations, the configuration information may include target application scenario information and / or target PCIe bus topology information. Based on the user-input target application scenario information or target PCIe bus topology information, the management chip can generate corresponding switching information by querying a scenario dictionary or generating it directly. This satisfies the user's need to directly configure the PCIe bus topology, improving the compatibility of electronic devices.

[0014] In some possible implementations, there are multiple main processors, each connected to a switching device via a PCIe bus. Adjacent switching devices are connected via PCIe buses. Multiple graphics processors (GPUs) are connected to their respective switching devices via PCIe buses. Each switching device is specifically used to switch the PCIe bus connections between its connected GPUs, main processors, and / or adjacent switching devices based on switching information. This PCIe bus network formed by multiple main processors and multiple switching devices facilitates flexible configuration of the PCIe bus topology, allowing users to access corresponding GPUs according to different application scenarios.

[0015] Secondly, embodiments of this application provide a PCIe topology configuration method, which is applied to an electronic device. The electronic device includes at least one main processor, multiple graphics processors, and a management chip. Each main processor and multiple graphics processors are interconnected via peripheral components. At least one switching device is connected to the PCIe bus, and each switching device is communicatively connected to the management chip.

[0016] The method includes: a management chip acquiring first information, the first information including device information and / or configuration information of each graphics processor; the management chip generating switching information corresponding to the target application scenario based on the first information; and the management chip also transmitting the switching information to a switching device so that the switching device switches the PCIe bus connection relationship between multiple graphics processors and the corresponding master processor.

[0017] In some possible implementations, before the management chip obtains the first information, the method includes: the firmware module in the electronic device reads the type identification information of each graphics processor to report to the management chip as the first information.

[0018] In some possible implementations, the management chip generates switching information for the corresponding target application scenario based on the first information, including: determining the target application scenario corresponding to the type identifier information in the first information according to the predefined mapping relationship between type identifier information and application scenarios; querying a preset scenario dictionary according to the target application scenario to match the target PCIe bus topology corresponding to the target application scenario, wherein the scenario dictionary is used to record the mapping relationship between multiple application scenarios and multiple PCIe bus topologies; and generating corresponding switching information based on the target PCIe bus topology.

[0019] In some possible implementations, the configuration information includes target application scenario information and / or target PCIe bus topology information.

[0020] Thirdly, this application provides a computer-readable storage medium storing a computer program that, when run on a processor, causes the processor to perform the method described in the second aspect or any possible implementation thereof.

[0021] Fourthly, this application provides a computer program product, characterized in that, when the computer program product is run on a processor, it causes the processor to execute the method described in the second aspect or any possible implementation of the second aspect.

[0022] Fifthly, this application provides a chip, characterized in that it includes at least one processor and an interface; the at least one processor acquires program instructions or data through the interface; the at least one processor is used to execute program line instructions to implement the method described in the second aspect or any possible implementation of the second aspect.

[0023] It is understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application;

[0025] Figure 2 This is a schematic diagram of the hardware structure of an electronic device provided in a specific embodiment of this application;

[0026] Figure 3 This is a schematic diagram of the architecture of an electronic device provided in an embodiment of this application;

[0027] Figure 4 This is a flowchart illustrating a PCIe topology configuration method provided in an embodiment of this application;

[0028] Figure 5This is a flowchart illustrating a PCIe topology configuration method according to a specific embodiment of this application;

[0029] Figure 6 This is a schematic diagram of the structure of a PCIe topology configuration device provided in an embodiment of this application;

[0030] Figure 7 This is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation

[0031] In this article, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The symbol " / " in this article indicates that the related objects are in an "or" relationship; for example, A / B means A or B.

[0032] The terms "first" and "second," etc., used in the specification and claims herein are used to distinguish different objects, not to describe a specific order of objects. For example, "first information" and "second information," etc., are used to distinguish different information, not to describe a specific order of information.

[0033] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0034] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0035] To facilitate understanding of the technical solution of this application, the relevant terms used in this document are explained below.

[0036] GPU (graphics processing unit): Also known as a graphics core, visual processor, or display chip, it is a microprocessor specifically designed to perform image and graphics-related calculations on electronic devices (such as personal computers, workstations, servers, and some mobile devices).

[0037] GPU card: A board that carries a GPU, also known as a graphics card.

[0038] CPU (Central Processing Unit): As the core of a computer system for computation and control, it is the final execution unit for information processing and program execution.

[0039] PCIe (Peripheral Component Interconnect Express, PCI-Express): High-speed peripheral component interconnect is a high-speed serial computer expansion bus standard. PCIe is a high-speed serial point-to-point dual-channel high-bandwidth transmission. Connected devices are allocated dedicated channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot-plugging, and Quality of Service (QoS) functions.

[0040] P2P (peer to peer): a peer-to-peer network, an end-to-end transmission network.

[0041] BIOS (Basic Input Output System): Essentially, it's a set of programs embedded in a ROM (read-only memory) chip on the computer's motherboard, also known as "BIOS firmware." It stores the computer's most important basic input / output programs, power-on self-test (POST) programs, and system boot programs. It can read and write specific system settings from the CMOS RAM. The main function of the BIOS is to provide the lowest-level, most direct hardware settings and control for the computer. In addition, the BIOS also provides some system parameters to the operating system.

[0042] BMC (baseboard management controller): The baseboard management controller is a remote management controller that can perform operations such as firmware upgrades and monitoring of the machine when it is not powered on.

[0043] RAID (Redundant Arrays of Independent Disks): A system of redundant disk arrays.

[0044] GPU servers can be equipped with multiple GPU cards to perform graphics and intensive computing tasks, suitable for scenarios such as deep learning training, scientific computing, graphics and image processing, and video encoding and decoding. They can provide fast, stable, and flexible computing power support for image processing and edge AI acceleration in fields such as automatic optical inspection, assisted driving, and medical industries.

[0045] In a GPU server, the GPUs typically have different functional focuses depending on their type (or model). For example, some GPUs are focused on training / inference, some on graphics rendering, and others on high-density computing. Users select GPUs based on their scenario requirements, and after connecting the selected GPUs to the server, the PCIe topology of the GPUs needs to be adapted to achieve optimal performance. However, the traditional method of manually configuring the PCIe topology is inefficient and reduces operational efficiency.

[0046] To improve the configuration efficiency of PCIe topology in servers and reduce manual intervention, this application provides a PCIe topology configuration method, device, electronic device, computer storage medium, and computer program product. It mainly adapts the PCIe topology structure in the server according to the application scenario of the electronic device (such as a GPU server), thereby achieving efficient configuration of PCIe topology and improving the operational efficiency of the server.

[0047] To facilitate understanding of the technical solutions of this application, the electronic devices provided in the embodiments of this application will be described first below.

[0048] For example, Figure 1 A schematic diagram of the hardware structure of an electronic device is shown. The electronic device 100 can be a hardware device capable of providing data processing, computing, and storage functions, such as a workstation, GPU server, or hyperterminal, but is not limited to these. Figure 1 As shown, the electronic device 100 provided in this application embodiment may include a processor 101, a memory 102, a graphics processor 103, a management chip 104, and a communication interface 105. These components in the electronic device 200 may be integrated on the motherboard, and the components may be connected to each other via a bus 110 to complete mutual communication.

[0049] The processor 101 may include various processing devices, such as a central processing unit (CPU), a system-on-a-chip (SoC), a processor integrated on an SoC, a separate processor chip, or a controller. The processor 101 may also include special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and digital signal processors (DSPs). The processor 101 may be a processor group consisting of multiple processors, which are coupled to each other via one or more buses. For example... Figure 2 The schematic diagram of the hardware structure of the electronic device 100 shown in some specific examples includes a motherboard that may include two CPUs (101a, 101b). CPUs 101a and 101b are coupled via a triple-path interconnect (UPI) bus to enable high-speed communication between the two processors. Additionally, both CPUs 101a and 101b have multiple interfaces for connecting other components (such as hard drive 1021, GPU 10 card 103, PCIe standard card 120, etc.).

[0050] The memory 102 can be coupled to the processor 101. Specifically, the memory 102 can be coupled to the processor 101 through one or more memory controllers. The memory 102 can be used to store computer program instructions, including the computer operating system (OS), BIOS firmware, and various programs. The memory 102 can be non-volatile memory (NVM), such as an embedded multimedia card (EMMC), universal flash storage (UFS), or read-only memory (ROM), or other types of static storage devices capable of storing static information and instructions. It can also be volatile memory, such as random access memory (RAM), or other types of dynamic storage devices capable of storing information and instructions. Furthermore, it can be electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM), or other optical disc storage, disk storage media, or other storage devices, or any other computer-readable storage medium capable of carrying or storing program code having instruction or data structure forms and accessible by a computer, but is not limited thereto. The memory 102 can exist independently, or it can be integrated with the processor 101. In some examples, such as... Figure 2 As shown, each CPU (101a, 101b) can be connected to a hard disk 1021, a disk array (RAID) 1022 and other storage devices 102 via an interface to support the CPU (101a, 101b)'s calculation, processing and other operations.

[0051] The graphics processing unit (GPU) 103 may include various types of microprocessors for graphics and intensive computing, such as GPUs for deep learning training / inference, GPUs for graphics rendering, and GPUs for HPC computing, but is not limited thereto. Multiple GPUs 103 may be coupled to the processor (i.e., the main processor) 101 and perform corresponding tasks under the control of the processor 101. For example, multiple GPUs 103 may be coupled to the processor 101 and share the workload of the computationally intensive parts of the application when the processor 101 is running an application.

[0052] In some examples, processor 101 may include M (M≥2) CPUs, and multiple GPUs 103 are mounted on the M CPUs via N (N≥1) PCIe switches (PCIe SWs) 106. Both CPUs and GPUs 103 are connected to the switch 106 via a high-speed peripheral interconnect PCIe bus. When N≥2, adjacent switch 106 are also connected via a PCIe bus. It can be understood that the PCIe SW 106, as a switching device, provides expansion or aggregation capabilities and allows more devices (such as processor 101, GPU 103, etc.) to connect to a single PCIe port. The PCIe SW 106 can identify which path a given packet should take based on its address or other routing information, acting as a PCIe-to-PCIe bridge.

[0053] For example, see reference. Figure 2 As shown, two CPUs (101a, 101b) are connected to eight GPUs (103a-103h) via two switching chips (106a, 106b). The two switching chips (106a, 106b) are also connected to each other via a PCIe bus. Thus, by coordinating the switching between the two switching chips (106a, 106b), the PCIe connection between all GPUs (103a-103h) and the CPUs (101a, 101b) can be controlled, thereby enabling the configuration of the connection channels between GPUs 103a and CPUs (101a, 101b). For example, switching chip 106b can close its connection channel with CPU 101b, while opening its connection channels with switching chip 106a and to GPUs 103a-103h. This PCIe topology configuration allows eight GPUs (103a-103h) to be connected to CPU 101a.

[0054] For example, continue to refer to Figure 1 and Figure 2 As shown, the electronic device 100 also includes a management chip 104, which can be a baseboard management controller (BMC). The BMC 104 is used to monitor and control the hardware of the electronic device 100 (including various GPUs 103) and connected hardware devices (such as hard disks 10221, disk arrays 1022, PCIe cards 120, etc.). For example, it can monitor the temperature, voltage, and other information of the electronic device 100 and make corresponding adjustments to ensure that the electronic device 100 is in a normal operating state. The BMC 104 can also record information and logs of various hardware or nodes, provide event logs, recovery control, and configuration monitoring and management functions. It should be noted that the BMC 104 is an independent device; it does not depend on other hardware in the electronic device 100 (such as processors 101 or memory 102, etc.) nor on the OS, but the BMC 104 can interact with the OS.

[0055] In this example, refer to Figure 3 As shown, the BIOS 130 in the electronic device 100 can read the type identification information (such as model, identity ID, etc.) of each GPU (103a~103h) connected on the PCIe bus and report it to the BMC 104. Then, the BMC 104 can analyze the current target application scenario based on the information obtained, and control the switching chips (106a, 106b) to adapt to the target application scenario and perform the corresponding switching action to complete the PCIe topology configuration operation, thereby adapting to the target application scenario and mounting the connected GPU to the corresponding CPU so that the device can achieve the best performance.

[0056] For some specific examples, please refer to [link / reference]. Figure 3 As shown, a complex programmable logic device (CPLD) 107 is provided between the BMC104 and each switching chip (106a, 106b). The BMC104 can be connected to the input terminal of the CPLD 107 via a bus (such as a CPU bus localbus or a serial bus I2C), and the output terminal of the CPLD 107 is connected to each switching chip (106a, 106b) via a bus (such as a serial bus I2C). In this way, the BMC104 can transmit the switching information to the CPLD 107 for decoding and translation, generate control commands, and output them to the corresponding switching chips (106a, 106b) to execute the switching action.

[0057] The communication interface 105 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0058] In this embodiment, bus 110 includes a bus using one or more communication protocols. Furthermore, bus 110 includes hardware, software, or both, that couples components of electronic device 100 together. For example, and not limitingly, bus 110 may include the PCIe bus, UPI bus, localbus bus, I2C bus, etc., as described above, and may also include Accelerated Graphics Port (AGP) or other graphics buses, Enhanced Industry Standard Architecture (EISA) bus, Front Side Bus (FSB), HyperTransport (HT) interconnect, Industry Standard Architecture (ISA) bus, Infinite Bandwidth Interconnect, Low Pin Count (LPC) bus, memory bus, Microchannel Architecture (MCA) bus, Peripheral Component Interconnect (PCI) bus, Serial Advanced Technology Attachment (SATA) bus, Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. It should be understood that although specific buses are described and illustrated in the embodiments of this application, any suitable bus or interconnect is contemplated herein.

[0059] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0060] Furthermore, it is understood that, in this solution, exemplary embodiments of electronic device 100 include, but are not limited to, electronic devices running iOS, Android, Windows, Harmony OS, or other operating systems.

[0061] Next, based on the content described above, a PCIe topology configuration method provided by an embodiment of this application will be introduced. It is understood that this method is proposed based on the content described above, and some or all of the content of this method can be found in the description above.

[0062] Please see Figure 4 , Figure 4 This is a flowchart illustrating a PCIe topology configuration method provided in an embodiment of this application. It can be understood that this method can... Figure 1 , Figure 2 as well as Figure 3 The electronic device 100 shown can perform this action, but it can also be performed by other devices or equipment with computing and processing capabilities. For example... Figure 4 As shown, the PCIe topology configuration method may include S401 to S403:

[0063] S401, the management chip obtains first information, which includes type identification information and / or configuration information for each graphics processor.

[0064] In this embodiment, when configuring electronic devices such as GPU servers 100, the graphics processing unit (GPU) can be selected according to business needs. For example, if the user needs to use the device for deep learning training / inference scenarios, a GPU model that emphasizes training / inference functions, such as the NVIDIA A100 model, can be selected. If the user needs to use the device for graphics processing scenarios, a GPU model that emphasizes graphics rendering functions, such as the NVIDIA A40 model, can be selected. After the user selects the corresponding type of GPU 103 and mounts it under the processor (hereinafter referred to as "CPU") 101, the communication path between each GPU 103 and the CPU it is mounted on is adaptively switched by the switching chip 106. In other words, the PCIe bus topology of each GPU and CPU can be configured through the switching chip 106. When configuring the PCIe bus topology, the first information monitored by the management chip BMC 104 is analyzed to identify the application scenario required by the current user, thereby controlling the switching chip 106 accordingly to reduce manual intervention in the deployment of the PCIe bus topology.

[0065] For example, in combination Figure 5 As shown, the first information obtained by BMC104 can be information reported by BIOS130 via S1a, or configuration information entered by the user based on the management interface provided by BMC104 via S1b.

[0066] The following provides detailed examples of different sources of primary information.

[0067] For example, in S1a, the BIOS reads the type identification information of each graphics processor and reports it to BMC104 as the first piece of information.

[0068] In this example, continue to refer to Figures 1-3 As shown, after the user connects the selected GPU 103 to the motherboard of the electronic device 100 and connects the switching chip 106, when the entire system starts working, the BIOS 130 in the electronic device 100 can automatically read the model, identity ID, and other type identification information of each GPU 103 and report this type identification information to the management chip BMC 104. It can be understood that the information reported by the BIOS 130 to the management chip BMC 104 is the aforementioned first information. Thus, the management chip BMC 104 can subsequently perform steps S402 to S403 below to analyze and determine the scenario in which the user wants the device to be used based on the type identification information of each GPU 103, thereby adaptively generating switching information to indicate the PCIe bus topology configuration suitable for that scenario.

[0069] In some specific examples, multiple GPUs can be evenly connected to the switching chip 106 to which each CPU is connected, as shown in the reference. Figure 2 and Figure 3 As shown, CPUs 101a and 101b are connected to four GPUs 103 via switching chips 106a and 106b, respectively. In some other examples, when multiple GPUs are connected to multiple switching chips 106 connected to multiple CPUs, they can be deployed unevenly, such as connecting two GPUs to one CPU and four GPUs to another. This facilitates flexible GPU deployment.

[0070] For example, in S1b, the management chip obtains configuration information input by the user.

[0071] In this example, the user can also input corresponding configuration information based on some peripherals of electronic device 100 (such as a keyboard). This configuration information may include information about the target application scenario, or information about the target PCIe bus topology to be switched.

[0072] For example, a user can input configuration information describing a target application scenario (such as a graphics rendering scenario, training scenario, or HPC scenario) through an interface (such as the BMC management interface provided by BMC104). This configuration information can be transmitted to BMC104 as the first piece of information. It is understood that this interface can be displayed by hardware devices such as a monitor connected to electronic device 100.

[0073] Alternatively, each PCIe bus lane of each switching chip 106 has a unique channel identifier. Users can also directly input information about the PCIe bus lanes on the switching chip 106 through the interface, that is, information about which channels of each switching chip 106 are turned on and which channels are turned off, thereby generating configuration information describing the target PCIe bus topology to be switched. This configuration information can be transmitted to BMC104 as the first information.

[0074] In this embodiment, after BMC104 obtains the first information transmitted from BIOS130 or interface through the aforementioned S401, it can execute:

[0075] S402, the management chip generates switching information for the corresponding target application scenario based on the first information.

[0076] In this embodiment, BMC104 can analyze the first information obtained from the BIOS130 or management interface to generate switching information, thereby controlling the switching chip 106 connected to each GPU103 to switch the PCIe bus channel.

[0077] For example, if the first information is reported by BIOS 130, then when BMC 104 executes S402, it may specifically include S4021 to S4023:

[0078] S4021, the management chip determines the target application scenario corresponding to the type identifier information in the first information based on the predefined mapping relationship between type identifier information and application scenario.

[0079] In this embodiment, the mapping relationship between type identification information and application scenarios can be predefined. For example, a GPU with model number "A100" can be set to correspond to a training / inference scenario, and a GPU with model number "A40" can correspond to a graphics rendering scenario. In this way, when BMC104 obtains the first information, it can automatically identify the target application scenarios applicable to these GPUs based on the type identification information in the first information, that is, the scenarios in which the user wants the electronic device 100 to be used.

[0080] For example, the type identification information reported by BIOS130 includes information on the "A100" and "A30" models. If BMC104 determines the training / inference scenario corresponding to these two GPU models through the predefined mapping relationship between type identification information and application scenarios, then the training / inference scenario is determined as the target application scenario. In this way, BMC104 can analyze the user's needs (i.e. the target application scenario that the user wants to adapt to) without user intervention.

[0081] Similarly, if the type identification information reported by BIOS130 includes information on four models: "A40", "A30", "A10" and "A2", then BMC104 determines, through the predefined mapping relationship between type identification information and application scenarios, that the majority of these four GPU models are used for graphics rendering and virtual desktops. In other words, all currently connected GPUs focus on graphics rendering / virtual desktop scenarios, and the graphics rendering / virtual desktop scenario can be identified as the target application scenario.

[0082] S4022, the management chip queries the scenario dictionary based on the target application scenario to determine the target PCIe bus topology corresponding to the target application scenario.

[0083] In this embodiment, during the process of BMC104 generating switching information, application scenarios can be analyzed by calling a scenario dictionary. This scenario dictionary is a predefined dictionary that records the mapping relationship between various application scenarios and the PCIe bus topology. The PCIe bus topology includes the connection relationships between the CPU and the switching chip, between the various switching chips, and between the switching chip and the GPU via the PCIe bus.

[0084] For example, the scene dictionary can define the PCIe bus topology K1 corresponding to the training / inference scene, combined with... Figure 3 As shown, since the training scenario needs to support a single-root topology, meaning all GPUs are connected to a single CPU, in this topology K1, switching chip 106a can be configured to enable all PCIe bus channels it is connected to, while switching chip 106b can disable its connection to CPU 101b and enable its PCIe bus channels with switching chip 106a and to GPUs 103e-103h. Similarly, a PCIe bus topology K2 corresponding to the graphics rendering scenario can be defined in the scene dictionary. This topology K2 allows all GPUs to be evenly distributed across CPUs. Furthermore, a PCIe bus topology K3 adapted to HPC scenarios can also be defined in the scene dictionary, and so on. This embodiment does not impose specific limitations.

[0085] In this way, after BMC104 determines the target application scenario that the user wants to configure based on the first information, it can quickly and efficiently determine the target PCIe bus topology applicable to the target application scenario by querying the scenario dictionary and based on the mapping relationship between the scenario and the PCIe bus topology defined in the scenario dictionary.

[0086] The S4023 management chip generates switching information based on the target PCIe bus topology.

[0087] In this embodiment, after BMC104 determines the target PCIe bus topology, it can generate switching information based on the topology. This switching information can be used to indicate the communication state (such as on or off) of each PCIe bus channel of each switching chip 106.

[0088] For example, if the target PCIe bus topology is topology K1 as described above, the generated switching information instructs switching chip 106a to activate all PCIe bus channels connected to it, and switching chip 106b to deactivate the connection channel between itself and CPU 101b, while activating the PCIe bus channels between itself and switching chip 106a, as well as to GPUs 103e to 103h. Similarly, if the target PCIe bus topology is topology K2 or K3 as described above, the generated switching information instructs each switching chip 106 to configure the connection relationships set by topology K2 or K3.

[0089] In this embodiment, after BMC104 generates the handover information through the aforementioned S402, the following S403 can be executed:

[0090] In S403, the management chip transmits switching information to the corresponding switching device, so that the switching device switches the PCIe bus connection relationship between multiple graphics processors and the corresponding host processor.

[0091] In this embodiment, reference Figure 5 As shown, BMC104 generates switching information, which can be transmitted to the logic device CPLD107 through its interface. CPLD107 executes S2 to decode and translate the information into control instructions, and then executes S3 to transmit the information from the corresponding bus to the switching chip 106. The switching chip 106 then executes S4 to perform actions (or not actions) according to the instructions, turning on / off the GPU's PCIe bus channel, thus forming a PCIe bus topology that adapts to the user's needs.

[0092] For example, refer to Figure 3 As shown, if the target PCIe bus topology corresponding to the switching information is the aforementioned topology K1, the switching information is translated by CPLD107 and sent to switching chips 106a and 106b respectively. This causes switching chip 106a to activate all PCIe bus channels connected to it, and causes switching chip 106b to close the connection channel between itself and CPU101b, while activating the PCIe bus channels between itself and switching chip 106a, as well as to GPUs 103e to 103h. In this PCIe bus topology, GPUs (103a to 103d) and GPUs (103e to 103h) can communicate via P2P through the switching chips (106a, 106b), and all GPUs (103a to 103h) are connected to CPU101a.

[0093] Similarly, if the target PCIe bus topology corresponding to the switching information is the aforementioned topology K2, the switching information is translated by CPLD107 and sent to switching chips 106a and 106b respectively, so that switching chips 106a and 106b respectively connect the channels between their respective connected CPUs and GPUs, so that GPUs (103a to 103d) are mounted under CPU 101a, and GPUs (103e to 103h) are mounted under CPU 101b.

[0094] Thus, from the automatic acquisition of GPU 103 type identification information by BIOS 130, to the automatic identification of application scenarios and determination of switching information by BMC 104, then the translation and transmission via logic device 107, and finally the switching chip 106 executing the switching of the communication channel between GPU 103 and the GPU, a closed-loop control chain is formed: "GPU 103 → BMC 104 → CPLD 107 → PCIe SW 106 → GPU 103". Using GPU 103 as the input control point, different PCIe topologies are determined according to different scenarios in which the GPU is used. In other words, the method of this embodiment can automatically identify the GPU type, thereby automatically matching the high-speed PCIe topology, achieving adaptive control of the PCIe bus topology configuration, enabling the electronic device 100 to achieve optimal application performance, reducing manual intervention, improving machine deployment efficiency, and bringing operational efficiency improvements to customers.

[0095] In some other possible implementations, if the first information is configuration information obtained from the management interface to describe the application scenario, then the BMC104 can directly execute the aforementioned steps S4022 to S4023 and S403 based on the configuration information, adaptively generate a switching information and send it to the switching chip 106 to control the switching chip 106 to configure a PCIe bus topology suitable for the application scenario.

[0096] If the first information is configuration information obtained from the management interface that describes the PCIe bus topology information to be switched, then BMC104 can directly execute the aforementioned steps S4023 and S403 to generate a switching information and send it to the switching chip 106 to control the switching chip 106 to configure a PCIe bus topology suitable for the application scenario.

[0097] Based on the methods described in the above embodiments, this application provides a PCIe topology configuration device. Please refer to... Figure 6 , Figure 6 This is a schematic diagram of a PCIe topology configuration device provided in an embodiment of this application. It can be understood that this device can be deployed on the aforementioned... Figure 1 , Figure 2 as well as Figure 3 The electronic device 100 shown can also be deployed in other devices or equipment with computing and processing capabilities.

[0098] like Figure 6As shown, the PCIe topology configuration device 600 may include an acquisition module 601 and a processing module 602. The acquisition module 601 can acquire first information, which includes type identification information and / or configuration information for each graphics processor. The processing module 602 can generate switching information corresponding to a target application scenario based on the first information. Furthermore, the processing module 602 can also transmit the switching information to a corresponding switching device, enabling the switching device to switch the PCIe bus connection relationship between multiple graphics processors and their corresponding master processors.

[0099] In some embodiments, the processing module 602 can be specifically used to determine the target application scenario corresponding to the type identifier information in the first information according to the predefined mapping relationship between type identifier information and application scenario, query a preset scenario dictionary according to the target application scenario, and match the target PCIe bus topology corresponding to the target application scenario. The scenario dictionary is used to represent the mapping relationship between multiple application scenarios and multiple PCIe bus topologies, and generate corresponding switching information according to the target PCIe bus topology.

[0100] It should be understood that the above-described device is used to execute the methods in the above embodiments. The implementation principle and technical effect of the corresponding program modules in the device are similar to those described in the above methods. The working process of the device can be referred to the corresponding process in the above methods, and will not be repeated here.

[0101] Based on the methods in the above embodiments, this application provides a computer-readable storage medium storing a computer program that, when run on a processor, causes the processor to execute the methods in the above embodiments.

[0102] Based on the methods in the above embodiments, this application provides a computer program product, characterized in that, when the computer program product is run on a processor, the processor executes the methods in the above embodiments.

[0103] Based on the methods described in the above embodiments, this application also provides a chip. Please refer to... Figure 7 , Figure 7 This is a schematic diagram of a chip structure provided in an embodiment of this application. Figure 7 As shown, chip 700 includes one or more processors 701 and interface circuitry 702. Optionally, chip 700 may also include a bus 703. Wherein:

[0104] The processor 701 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed through integrated logic circuits in the hardware of the processor 701 or through software instructions. The processor 701 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods and steps disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor.

[0105] The interface circuit 702 can be used to send or receive data, instructions or information. The processor 701 can use the data, instructions or other information received by the interface circuit 702 to process the data, instructions or other information, and can send the processed information out through the interface circuit 702.

[0106] Optionally, chip 700 also includes memory, which may include read-only memory and random access memory, and provides operation instructions and data to the processor. A portion of the memory may also include non-volatile random access memory (NVRAM).

[0107] Optionally, the memory stores executable software modules or data structures, and the processor can execute corresponding operations by calling the operation instructions stored in the memory (which may be stored in the operating system).

[0108] Optionally, the interface circuit 702 can be used to output the execution results of the processor 701.

[0109] It should be noted that the functions of the processor 701 and the interface circuit 702 can be implemented through hardware design, software design, or a combination of hardware and software; no restrictions are imposed here.

[0110] It should be understood that each step of the above method embodiments can be completed by hardware logic circuits or software instructions in a processor.

[0111] It is understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. In addition, in some possible implementations, each step in the above embodiments may be selectively executed according to the actual situation, and may be partially or fully executed, which is not limited here.

[0112] The method steps in the embodiments of this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can reside in an ASIC.

[0113] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium.

[0114] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application.

Claims

1. An electronic device, characterized in that, The electronic device includes at least one main processor, multiple graphics processors, and a management chip. Each main processor and the multiple graphics processors are interconnected via a peripheral component interconnection PCIe bus and at least one switching device is connected. Each switching device is communicatively connected to the management chip. The management chip is used to generate switching information for a corresponding target application scenario based on the first information, wherein the first information includes type identification information for each graphics processor; The switching device is used to switch the PCIe bus connection relationship between the plurality of graphics processors and the corresponding main processor according to the switching information; The electronic device includes a firmware module. The firmware module is used to read the type identification information of each graphics processor, and report it to the management chip as the first information; The management chip is specifically used for: Based on the mapping relationship between preset type identification information and application scenarios, the target application scenario corresponding to the type identification information in the first information is determined; According to the target application scenario, a preset scenario dictionary is queried to match the target PCIe bus topology corresponding to the target application scenario. The scenario dictionary is used to record the mapping relationship between multiple application scenarios and multiple PCIe bus topologies. Based on the target PCIe bus topology, generate corresponding switching information.

2. The electronic device according to claim 1, characterized in that, The first information also includes configuration information for each of the graphics processors; the configuration information includes target application scenario information and / or target PCIe bus topology information.

3. The electronic device according to claim 1 or 2, characterized in that, There are multiple main processes, each of which is connected to a switching device via a PCIe bus. Adjacent switching devices are connected via a PCIe bus. The plurality of graphics processors are respectively connected to the corresponding switching devices via PCIe buses. Each of the switching devices is specifically used to switch the PCIe bus connection relationship between its connected graphics processor, main processor, and / or its adjacent switching devices according to the switching information.

4. A PCIe topology configuration method, characterized in that, The method is applied to an electronic device, which includes at least one main processor, multiple graphics processors, and a management chip. Each main processor and the multiple graphics processors are interconnected via a peripheral component interconnect PCIe bus and at least one switching device is connected. Each switching device is communicatively connected to the management chip. The method includes: The firmware module in the electronic device reads the type identification information of each graphics processor and reports it to the management chip as the first information. The management chip acquires first information, which includes device information for each graphics processor. Based on the preset mapping relationship between type identification information and application scenarios, the target application scenario corresponding to the type identification information in the first information is determined; According to the target application scenario, a preset scenario dictionary is queried to match the target PCIe bus topology corresponding to the target application scenario. The scenario dictionary is used to record the mapping relationship between multiple application scenarios and multiple PCIe bus topologies. Based on the target PCIe bus topology, generate corresponding switching information; The management chip transmits the switching information to the switching device, so that the switching device switches the PCIe bus connection relationship between the plurality of graphics processors and the corresponding main processor.

5. The method according to claim 4, characterized in that, The first information also includes configuration information for each of the graphics processors, which includes target application scenario information and / or target PCIe bus topology information.

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