Circuit verification method, device, equipment and storage medium

Abstract

This disclosure provides a circuit verification method, apparatus, device, and storage medium. The circuit verification method includes: acquiring a status verification file of a termination circuit module in the circuit under test; the status verification file includes standard output data of the signal to be checked of the termination circuit module; acquiring a simulation output file of the termination circuit module in the circuit under test; the simulation output file includes the actual output waveform of the signal to be checked of the termination circuit module; acquiring a mapping file of the termination circuit module in the circuit under test; the mapping file includes the mapping relationship between the status verification file and the signal to be checked in the simulation output file; and comparing the status verification file and the simulation output file according to the mapping file to check the status of the signal to be checked of the termination circuit module. In this disclosure, by comparing the status verification file and the simulation output file according to the mapping file, the status of the signal to be checked of the termination circuit module can be checked, and the status of the termination circuit module can be automatically verified to improve the efficiency of the simulation verification of the termination circuit module.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method, apparatus, device and storage medium for verifying circuits. Background Technology

[0002] Dynamic Random Access Memory (DRAM), as an important semiconductor memory in computer systems, exhibits different states in its internal on-die termination (ODT) circuitry during read, write, and idle states. To prevent errors in DRAM during read, write, and idle states, it is necessary to verify the proper functioning of the termination circuit module through simulation under different test conditions.

[0003] When verifying the status of the termination circuit module, testers need to manually analyze the simulation results, resulting in very low efficiency in the simulation verification of the termination circuit module. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a method, apparatus, device, and storage medium for verifying circuits.

[0006] According to a first aspect of the present disclosure, a method for verifying a circuit is provided, the method comprising:

[0007] Obtain the status verification file of the termination circuit module in the circuit under test; the status verification file includes the standard output data of the signal to be checked of the termination circuit module;

[0008] Obtain the simulation output file of the termination circuit module in the circuit under test; the simulation output file includes the actual output waveform of the signal to be checked by the termination circuit module;

[0009] Obtain the mapping file of the termination circuit module in the circuit under test; the mapping file includes the mapping relationship between the status verification file and the signal to be checked in the simulation output file;

[0010] Based on the mapping file, compare the state verification file and the simulation output file to check the state of the signal to be checked in the termination circuit module.

[0011] According to some embodiments of this disclosure, before obtaining the status verification file of the termination circuit module in the circuit under test, the circuit verification method further includes:

[0012] Obtain the check execution file of the termination circuit module; the check execution file includes the storage path information of the status verification file, the simulation output file, and the mapping file;

[0013] Based on the storage path information in the check execution file, locate the status verification file, the simulation output file, and the mapping file.

[0014] According to some embodiments of this disclosure, before obtaining the status verification file of the termination circuit module in the circuit under test, the circuit verification method further includes:

[0015] Obtain the functional check file of the termination circuit module; the functional check file includes simulation parameters and excitation information corresponding to the target function of the circuit under test.

[0016] Based on the functional check file, the circuit under test is functionally verified, the standard output data of the signal under test is obtained, and a status verification file corresponding to the termination circuit module when the target function is completed is formed.

[0017] According to some embodiments of this disclosure, the step of performing functional verification on the circuit under test based on the functional check file, obtaining standard output data of the signal under test, and forming a status verification file corresponding to the termination circuit module when the target function is completed includes:

[0018] Based on the functional check file, the circuit under test is functionally verified, and a functional verification result file of the circuit under test is generated.

[0019] Based on the functional check file, the standard output data of the signal to be checked is obtained from the functional result verification file to form the status verification file corresponding to the termination circuit module when the target function is completed.

[0020] According to some embodiments of this disclosure, the functional verification of the circuit under test is implemented using a functional verification platform that supports the Verilog language.

[0021] According to some embodiments of this disclosure, before obtaining the simulation output file of the termination circuit module in the circuit under test, the verification method of the circuit further includes:

[0022] Based on the functional check file, the simulation parameters of the termination circuit module are obtained; the simulation parameters include test frequency parameters and test process corner parameters.

[0023] The excitation information of the circuit under test is extracted from the functional test file to form a simulation excitation file;

[0024] Based on the simulation parameters and the simulation stimulus file, a simulation check file for the termination circuit module is generated;

[0025] Based on the simulation check file, the circuit under test with parasitic parameters is simulated to obtain the actual output waveform of the signal under test, and a simulation output file corresponding to the termination circuit module when the target function is completed is formed.

[0026] According to some embodiments of this disclosure, the step of performing simulation on the circuit under test with parasitic parameters loaded based on the simulation check file, obtaining the actual output waveform of the signal under test, and forming a simulation output file corresponding to the termination circuit module when the target function is completed includes:

[0027] Based on the simulation check file, the circuit under test with parasitic parameters loaded is simulated to generate a simulation verification result file corresponding to the circuit under test when the target function is completed.

[0028] Based on the simulation check file, the actual output waveform of the signal to be checked is obtained from the simulation result verification file to form the simulation output file corresponding to the termination circuit module when the target function is completed.

[0029] According to some embodiments of this disclosure, the simulation of the circuit under test with parasitic parameters is performed using Finesim simulation software, Hspice simulation software, Hsim simulation software, or Spectre simulation software.

[0030] According to some embodiments of this disclosure, the step of checking the state of the signal to be checked in the termination circuit module by comparing the state verification file and the simulation output file based on the mapping file includes:

[0031] The signal to be checked of the termination circuit module is determined according to the status verification file, and the standard output data of the signal to be checked in the status verification file is obtained.

[0032] Based on the mapping relationship between the signal to be checked in the state verification file and the signal to be checked in the mapping file, the actual output data of the signal to be checked is obtained from the actual output waveform of the simulation output file.

[0033] By comparing the standard output data and the actual output data of each signal to be checked, the state of the signal to be checked in the termination circuit module is verified.

[0034] According to some embodiments of this disclosure, verifying the state of the signal under test of the termination circuit module by comparing the standard output data and the actual output data of each signal under test includes:

[0035] Based on the aforementioned functional check file, determine the start and end times of each state in the termination circuit module;

[0036] During the start and end time of each state, determine whether the deviation between the actual output data and the standard output data of each signal to be inspected is within a preset range;

[0037] When the deviation between the actual output data and the standard output data of the signal to be inspected is within the preset range, the state of the signal to be inspected is determined to be normal.

[0038] When the deviation between the actual output data and the standard output data of the signal to be inspected is outside the preset range, the state of the signal to be inspected is determined to be abnormal.

[0039] According to some embodiments of this disclosure, after verifying the state of the signal to be checked in the termination circuit module by comparing the standard output data and the actual output data of each signal to be checked, the verification method of the circuit further includes:

[0040] The state of the termination circuit module is determined based on the state of each of the signals to be inspected;

[0041] A status check report is generated for the termination circuit module.

[0042] According to some embodiments of this disclosure, the functional check file includes multiple target functions; the status check report for forming the termination circuit module includes:

[0043] Multiple status check reports are generated for each of the target functions.

[0044] According to some embodiments of this disclosure, the functional check file includes multiple target functions; the status check report for forming the termination circuit module includes:

[0045] A status check report corresponding to the preset target function is generated.

[0046] According to some embodiments of this disclosure, the functional check file includes multiple simulation parameters; the status check report for forming the termination circuit module includes:

[0047] Multiple status check reports are generated for each of the simulation parameters.

[0048] According to some embodiments of this disclosure, the filenames of the state verification file, the simulation output file, the mapping file, and / or the state check report contain the simulation parameters.

[0049] A second aspect of this disclosure provides a circuit verification apparatus, the circuit verification apparatus comprising:

[0050] The first acquisition module is configured to acquire a status verification file of the termination circuit module in the circuit under test; the status verification file includes standard output data of the signal to be checked of the termination circuit module;

[0051] The second acquisition module is configured to acquire the simulation output file of the termination circuit module in the circuit under test; the simulation output file includes the actual output waveform of the signal to be checked by the termination circuit module;

[0052] The third acquisition module is configured to acquire the mapping file of the termination circuit module in the circuit under test; the mapping file includes the mapping relationship between the status verification file and the signal to be checked in the simulation output file;

[0053] The inspection module is configured to check the status of the signal to be inspected in the termination circuit module by comparing the status verification file and the simulation output file according to the mapping file.

[0054] A third aspect of this disclosure provides a circuit verification apparatus, the circuit verification apparatus comprising:

[0055] processor;

[0056] Memory used to store processor-executable instructions;

[0057] The processor is configured to execute:

[0058] Obtain the status verification file of the termination circuit module in the circuit under test; the status verification file includes the standard output data of the signal to be checked of the termination circuit module;

[0059] Obtain the simulation output file of the termination circuit module in the circuit under test; the simulation output file includes the actual output waveform of the signal to be checked by the termination circuit module;

[0060] Based on the mapping file, compare the state verification file and the simulation output file to check the state of the signal to be checked in the termination circuit module.

[0061] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium is provided, which, when instructions in the storage medium are executed by a processor of a circuit verification device, enables the circuit verification device to perform:

[0062] Obtain the status verification file of the termination circuit module in the circuit under test; the status verification file includes the standard output data of the signal to be checked of the termination circuit module;

[0063] Obtain the simulation output file of the termination circuit module in the circuit under test; the simulation output file includes the actual output waveform of the signal to be checked by the termination circuit module;

[0064] Obtain the mapping file of the termination circuit module in the circuit under test; the mapping file includes the mapping relationship between the status verification file and the signal to be checked in the simulation output file;

[0065] Based on the mapping file, compare the state verification file and the simulation output file to check the state of the signal to be checked in the termination circuit module.

[0066] The circuit verification method, apparatus, device, and storage medium provided in this disclosure acquire a state verification file of the termination circuit module in the circuit under test. Since the state verification file includes standard output data of the signal to be checked from the termination circuit module, it can serve as a file for determining the ideal state of the termination circuit module. A simulation output file of the termination circuit module in the circuit under test is also acquired. Since the simulation output file includes the actual output waveform of the signal to be checked from the termination circuit module, it can serve as a file for determining the actual state of the termination circuit module. Because there are differences between the signal to be checked in the state verification file and the simulation output file, a mapping file of the termination circuit module in the circuit under test is acquired to ensure that the signal to be checked corresponds in both the state verification file and the simulation output file. By comparing the state verification file and the simulation output file according to the mapping file, the state of the signal to be checked from the termination circuit module can be checked, automatically verifying the state of the termination circuit module to improve the efficiency of the termination circuit module simulation verification.

[0067] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0068] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0069] Figure 1 This is a flowchart illustrating a circuit verification method according to an exemplary embodiment;

[0070] Figure 2 This is a flowchart illustrating a circuit verification method according to an exemplary embodiment;

[0071] Figure 3This is a flowchart illustrating a circuit verification method according to an exemplary embodiment;

[0072] Figure 4 This is a flowchart illustrating a circuit verification method according to an exemplary embodiment;

[0073] Figure 5 This is a flowchart illustrating a circuit verification method according to an exemplary embodiment;

[0074] Figure 6 This is a flowchart illustrating a circuit verification method according to an exemplary embodiment;

[0075] Figure 7 This is a flowchart illustrating a circuit verification method according to an exemplary embodiment;

[0076] Figure 8 This is a flowchart illustrating a circuit verification method according to an exemplary embodiment;

[0077] Figure 9 This is a flowchart illustrating a circuit verification method according to an exemplary embodiment;

[0078] Figure 10 This is a flowchart illustrating a circuit verification method according to an exemplary embodiment;

[0079] Figure 11 This is a block diagram illustrating a circuit verification apparatus according to an exemplary embodiment;

[0080] Figure 12 This is a block diagram illustrating a circuit verification device according to an exemplary embodiment. Detailed Implementation

[0081] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0082] Dynamic Random Access Memory (DRAM), as a type of semiconductor memory, enables data reading and writing. When writing data, a signal is sent from the DRAM controller to the DRAM. Due to interference in the connection lines between the DRAM controller and the DRAM, data writing causes a change in the impedance at the DRAM's termination point, resulting in signal reflection. Therefore, the termination impedance needs to be adjusted to eliminate signal reflection. A common method is to use a termination circuit module, which includes multiple termination sub-modules, each corresponding to a pin. Each termination sub-module includes one or more termination resistors connected in series and / or parallel. By using termination resistors, the change in impedance at the termination point is reduced, eliminating reflection and improving signal quality. When reading data, one or more termination resistors need to be disconnected due to power consumption. When the DRAM is idle, one or more termination resistors also need to be disconnected due to power consumption. By connecting termination resistors in series / parallel with switching elements, the switching elements are closed / opened when the termination resistors are needed, and opened / closed when the termination resistors are not needed. Therefore, by checking the control signals of the switching elements, it is determined whether the terminating resistors controlled by the corresponding switching elements are connected, thus determining the status of the termination submodule and the termination circuit module. Since each termination submodule corresponds to one pin, and each termination submodule includes multiple terminating resistors, each pin corresponds to the control signal of a switching element for multiple terminating resistors.

[0083] To prevent errors in dynamic random access memory (DRAM) during read, write, and idle states, it is necessary to verify the normal operation of the termination circuit module through simulation under different test conditions. When determining the state of the termination circuit module using the actual output waveform from the simulation software, testers need to observe and analyze the actual output waveform. During observation and analysis, it is necessary to first locate the control signals of the switching elements of the multiple termination resistors in each pin and find the control signal voltage of each switching element. Then, determine the start and end times of each state in the termination circuit module. Finally, compare the simulated voltage and ideal voltage of each control signal within each start and end time, and determine the control signal and the state of the termination circuit module based on the comparison results. Since DRAM contains multiple termination circuit modules, each containing multiple termination resistors and their corresponding switching elements, the number of control signals to be located is large. Especially for fifth-generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), compared to fourth- and third-generation DDR SDRAM, the sheer number of internal termination circuit modules leads to a dramatic increase in the number of control signals that need to be located. Furthermore, the state of these termination circuit modules changes multiple times within a short period, with numerous determined start and end times. Therefore, testers need to spend a significant amount of time observing and analyzing the actual output waveforms, resulting in low efficiency in the simulation verification of the termination circuit modules.

[0084] Based on this, this disclosure provides a circuit verification method. The method uses the acquired state verification file of the termination circuit module in the circuit under test as the file representing the ideal state of the termination circuit module, and the acquired simulation output file of the termination circuit module in the circuit under test as the file representing the actual state of the termination circuit module. Furthermore, it uses an acquired mapping file to map the signals to be checked in the state verification file and the simulation output file. Based on the state verification file, simulation output file, and mapping file, the actual operating state of the termination circuit module is automatically verified, avoiding the need for observation and analysis by test personnel, thereby improving the efficiency of the simulation verification of the termination circuit module.

[0085] This disclosure provides a circuit verification method in exemplary embodiments, which can be applied to circuit verification equipment (also known as a circuit verification platform). Figure 1 As shown, Figure 1 A flowchart illustrating a verification method for a circuit provided according to an exemplary embodiment of the present disclosure is shown:

[0086] S100. Obtain the status verification file of the termination circuit module in the circuit under test; the status verification file includes the standard output data of the signal to be checked of the termination circuit module.

[0087] S200. Obtain the simulation output file of the termination circuit module in the circuit under test; the simulation output file includes the actual output waveform of the signal to be checked in the termination circuit module.

[0088] S300. Obtain the mapping file of the termination circuit module in the circuit under test; the mapping file includes the mapping relationship between the status verification file and the signal to be checked in the simulation output file.

[0089] S400. Based on the mapping file, compare the status verification file and the simulation output file to check the status of the signal to be checked in the termination circuit module.

[0090] In this embodiment, a state verification file for the termination circuit module in the circuit under test is obtained. Since the state verification file includes standard output data of the signal to be checked from the termination circuit module, it can serve as a file for determining the ideal state of the termination circuit module. A simulation output file for the termination circuit module in the circuit under test is also obtained. Since the simulation output file includes the actual output waveform of the signal to be checked from the termination circuit module, it can serve as a file for determining the actual state of the termination circuit module. Because there are differences between the signal to be checked in the state verification file and the simulation output file, a mapping file for the termination circuit module in the circuit under test is obtained to ensure that the signal to be checked corresponds in both files. By comparing the state verification file and the simulation output file based on the mapping file, the state of the signal to be checked from the termination circuit module can be checked, automatically verifying the state of the termination circuit module and improving the efficiency of the termination circuit module simulation verification.

[0091] For example, the circuit under test (DUT) is the circuit containing the Dynamic Random Access Memory (DRAM). Simulation testing is needed to verify the state of the DRAM's internal termination circuit modules. The signals to be checked include control signals from different termination sub-modules within the termination circuit module. The state verification file contains standard output data of the signals to be checked from the termination circuit module and a file representing the ideal state of the termination circuit module. Since the standard output data reflects the ideal state of the termination circuit module, it is used as verification data when verifying the state of the termination circuit module. The simulation output file contains the actual output waveforms of the signals to be checked from the termination circuit module and a file representing the actual state of the termination circuit module. Since the actual output waveforms reflect the actual state of the termination circuit module, they are used as the waveforms to be verified when verifying the state of the termination circuit module. The mapping file contains the mapping relationship between the signals to be checked in the state verification file and the simulation output file. This is used to solve the problem of mismatched signals due to differences in the circuit hierarchy descriptions between the state verification file and the simulation output file, establishing a correspondence between the signals to be checked in the state verification file and the simulation output file, and enabling data comparison based on this correspondence. For example, in the state verification file, the hierarchical relationship of the control signals of the first termination submodule is named H1_B2_C3_IO_DQ_TX_V1 (H1_B2_C3 is the hierarchy, and IO_DQ_TX_V1 is the signal name), while in the simulation output file, the hierarchical relationship is named H1_B1_IO_DQ_TX_V1 (H1_B1 is the hierarchy, and IO_DQ_TX_V1 is the signal name). The mapping file associates the two names of the control signals of the first termination module, allowing the voltage values ​​corresponding to the control signals of the first termination module in the two files to be obtained and compared. The state verification file, simulation output file, and mapping file can be generated in real-time or pre-stored.

[0092] In some exemplary embodiments provided in this disclosure, such as Figure 2 As shown, Figure 2 This is a flowchart of a circuit verification method provided according to an exemplary embodiment of the present disclosure, including:

[0093] S500: Obtain the check execution file of the termination circuit module; the check execution file includes the storage path information of the status verification file, simulation output file and mapping file.

[0094] S510. Based on the storage path information in the execution file, locate the status verification file, simulation output file, and mapping file.

[0095] In this embodiment, an inspection execution file is obtained to determine the storage path information of the state verification file, simulation output file, and mapping file for determining the state of the termination circuit module. The state verification file, simulation output file, and mapping file are located based on the inspection execution file, avoiding incorrect file path lookup that could lead to misdetermination of the termination circuit module's state, thereby improving the reliability of the termination circuit module simulation verification.

[0096] In some exemplary embodiments provided in this disclosure, such as Figure 3 As shown, Figure 3 This is a flowchart of a circuit verification method provided according to an exemplary embodiment of the present disclosure, including:

[0097] S110. Obtain the functional check file of the termination circuit module; the functional check file includes simulation parameters and excitation information corresponding to the target function of the circuit under test.

[0098] S120. Based on the functional check file, perform functional verification on the circuit under test, obtain the standard output data of the signal to be checked, and form the status verification file corresponding to the termination circuit module when the target function is completed.

[0099] In this embodiment, a functional check file for the termination circuit module is acquired to determine the test conditions during the verification process of the circuit under test. These test conditions include simulation parameters, the target function, and the corresponding stimulus information. Based on the functional check file, functional verification of the circuit under test is performed, enabling the acquisition of standard output data for the signals to be checked in the termination circuit module. After acquiring the standard output data, a state verification file corresponding to the termination circuit module when the target function is completed is generated. Since the state verification file is generated through functional verification under simulation parameters and the completion of the target function, it can serve as a standard file under ideal conditions when automatically verifying the state of the termination circuit module, thereby achieving automatic verification of the termination circuit module's state and improving the efficiency of the termination circuit module simulation verification.

[0100] For example, the functional check file is a file that includes test conditions. Test conditions include simulation parameters, target functions, and stimulus information. Simulation parameters include test frequency parameters, test process corner parameters, and test temperature parameters. Since the frequency, process corner, and temperature parameters of the circuit under test (DUT) change under different conditions during actual operation, it is necessary to verify the DUT separately with different test frequency, process corner, and temperature parameters. The target function is used to determine the function that the DUT needs to perform during this verification process. When the DUT performs different target functions, the state of the termination circuit module will switch between read, write, and idle states at different start and end times. Therefore, the verification process shown in this disclosure needs to be implemented separately for each function performed by the DUT. The functional check file can contain one target function or multiple target functions working together. When there are multiple target functions, it is possible to verify whether the state of the termination circuit module is normal at the connection point of each target function. The stimulus information is the information used for simulation input. The corresponding stimulus information is different when the target functions are different.

[0101] For example, when performing functional verification on the circuit under test (DUT), a Verilog verification platform is used to perform functional simulation on the DUT containing the first circuit netlist information, outputting standard output data. The first circuit netlist reflects the circuit hierarchy information of the DUT under functional simulation. Since the standard output data is obtained based on the functional check file for functional verification of the DUT, the state of the terminated circuit modules in the standard output data is not affected by parasitic parameters in the DUT. Because the state verification file is formed based on the standard output data, the state of the terminated circuit modules in the state verification file does not contain interference from parasitic parameters in the DUT; therefore, the state of the terminated circuit modules in Verilog functional verification is ideal. Parasitic parameters can be, for example, parasitic capacitance and resistance in the connecting wires.

[0102] In some exemplary embodiments provided in this disclosure, such as Figure 4 As shown, Figure 4 The example illustrates a flowchart of a method for performing functional verification on the circuit under test based on a functional check file in step S120, acquiring standard output data of the signal under test, and forming a status verification file corresponding to the termination circuit module when the target function is completed. The method includes:

[0103] S121. Based on the functional check file, perform functional verification on the circuit under test and generate the functional verification result file corresponding to the circuit under test when the target function is completed.

[0104] S122. Based on the functional check file, obtain the standard output data of the signal to be checked from the functional result verification file to form the status verification file corresponding to the termination circuit module when the target function is completed.

[0105] In this embodiment, based on the functional check file, the circuit under test is functionally verified, generating a functional verification result file corresponding to the circuit under test when the target function is completed. Since the functional verification result file contains a large number of signals, and only a portion of the signals are to be tested, the functional verification result file needs to be extracted and processed. Based on the functional check file, the functional verification result file is processed to obtain the standard output data of the signals to be checked. The standard output data is used to form a state verification file corresponding to the termination circuit module when the target function is completed. This file serves as the ideal state file when automatically verifying the state of the termination circuit module, thereby achieving automatic verification of the termination circuit module's state and improving the efficiency of the termination circuit module simulation verification.

[0106] For example, when processing the functional verification result file based on the functional check file, the standard output data of the signal to be checked under simulation parameters can be obtained as verification data, so that the state verification file reflects the ideal state of the termination circuit module. Simultaneously, in both the functional verification result file and the state verification file, the state of the signal to be checked is represented by digital state information (e.g., the digital state information of the signal to be checked (i.e., the control signal for terminating the resistor) is 1 when the resistor is connected, and 0 when the resistor is disconnected). In the simulation output file reflecting the actual state of the termination circuit module, the state of the signal to be checked is represented by analog state information (e.g., the voltage of the signal to be checked). Therefore, it is necessary to convert the digital state information of the signal to be checked in the corresponding functional result verification file under simulation parameters into analog state information to form the state verification file of the termination circuit module, thereby realizing the state verification of the termination circuit module. For example, for the termination resistor Rx numbered x in the functional result verification file, the digital state information of the corresponding signal to be checked is 1. Because the actual output waveform in the simulation output file has interference fluctuations, when determining the state of the termination circuit module, it is not possible to rely on whether the voltage values ​​of the signal to be checked in the state verification file and the simulation output file are equal. When digital status information 1 is converted to analog status information, it can be determined that the analog status information is greater than a preset voltage value. When the terminating resistor Rx, numbered x in the termination circuit module description file, is disconnected, the digital status information of the corresponding signal to be checked is 0. When digital status information 0 is converted to analog status information, it can be determined that the analog status information is less than a preset voltage value. The preset voltage value can be a multiple of the voltage at which the signal to be checked is high, such as 0.7 times the high-level voltage, 0.8 times the high-level voltage, 0.9 times the high-level voltage, etc. Alternatively, the analog status information can be determined to be equal to the preset voltage value, with a preset deviation range. For example, if the preset voltage value is 0.9 times the high-level voltage, the preset deviation range is [-0.1, 0.1]V.

[0107] In some exemplary embodiments provided in this disclosure, the functional verification of the circuit under test in step S120 is implemented using a functional verification platform that supports the Verilog language. It is understood that, in addition to Verilog, it can also be implemented using other circuit design languages, such as VHDL.

[0108] In this embodiment, Verilog language is used to perform functional verification of the circuit under test. This can accurately and concisely determine the ideal state of the termination circuit module and promptly detect potential errors during simulation verification, thereby improving the efficiency of the simulation verification of the termination circuit module.

[0109] In some exemplary embodiments provided in this disclosure, the functional check file can be formed by acquiring the specifications, simulation parameters, target functions, and stimulus information of the circuit under test. The functional check file is then formed based on the specifications, simulation parameters, target functions, and stimulus information.

[0110] In this embodiment, by acquiring the specifications, simulation parameters, target functions, and other stimulus information of the circuit under test (TBD), the type of TBD, test conditions, and functions to be verified are determined. Based on the specifications, simulation parameters, and target functions, a functional check document is generated to verify whether the state of the termination circuit module is normal under the test conditions and target functions. This achieves state verification of the termination circuit module, thereby improving the efficiency of the simulation verification of the termination circuit module.

[0111] In some exemplary embodiments provided in this disclosure, such as Figure 5 As shown, Figure 5 This is a flowchart of a circuit verification method provided according to an exemplary embodiment of the present disclosure, including:

[0112] S210. Based on the functional check file, obtain the simulation parameters of the termination circuit module; the simulation parameters include test frequency parameters and test process corner parameters.

[0113] S220. Extract the excitation information of the circuit under test from the functional check file to form a simulation excitation file.

[0114] S230. Based on the simulation parameters and simulation stimulus file, generate the simulation check file for the termination circuit module.

[0115] S240. Based on the simulation check file, perform a simulation of the circuit under test with parasitic parameters loaded, obtain the actual output waveform of the signal under test, and form a simulation output file corresponding to the termination circuit module when the target function is completed.

[0116] In this embodiment, simulation parameters of the termination circuit module are obtained based on the functional check file to determine the test conditions for this simulation verification process. Excitation information of the circuit under test (DUT) is extracted from the functional check file to determine the target function of this simulation and form a simulation stimulus file, which serves as the stimulus for the DUT simulation input. Based on the simulation parameters and the simulation stimulus file, a simulation check file for the termination circuit module is generated, serving as the input for the simulation process under test conditions. Based on the simulation check file, the simulation of the DUT with parasitic parameters is completed, and the actual output waveform of the signal to be checked is obtained. The actual output waveform forms the simulation output file corresponding to the termination circuit module when the target function is completed. This file serves as the actual state file during automatic verification of the termination circuit module's state, thereby achieving automatic verification of the termination circuit module's state and improving the efficiency of the termination circuit module simulation verification.

[0117] For example, the simulation stimulus file is a file containing stimulus information. The simulation check file contains stimulus information corresponding to the test conditions and the target function.

[0118] For example, when performing a simulation of the circuit under test with parasitic parameters, timing simulation (post-simulation) is performed on the second circuit netlist and the parasitic parameters, and the actual output waveform is output. The second circuit netlist is used to reflect the circuit hierarchy information of the circuit under test in the timing simulation.

[0119] In some exemplary embodiments provided in this disclosure, such as Figure 6 As shown, Figure 6 The example illustrates a flowchart of the method in step S240, which involves performing a simulation of the circuit under test with parasitic parameters loaded based on a simulation check file, obtaining the actual output waveform of the signal under test, and forming the simulation output file corresponding to the termination circuit module when the target function is completed. The flowchart includes:

[0120] S241. Based on the simulation check file, perform simulation on the circuit under test with parasitic parameters loaded, and generate the simulation verification result file corresponding to the circuit under test when the target function is completed.

[0121] S242. Based on the simulation check file, obtain the actual output waveform of the signal to be checked from the simulation result verification file, and form the simulation output file corresponding to the termination circuit module when the target function is completed.

[0122] In this embodiment, based on the simulation excitation and simulation parameters in the simulation check file, timing simulation is performed on the circuit under test with parasitic parameters, generating a simulation verification result file for the circuit under test. Since the simulation verification result file contains numerous results and redundant interference, it needs to be processed. Based on the functional check file, the simulation result verification file is processed to obtain the actual output waveform of the signal under test. The actual output waveform forms the simulation output file of the termination circuit module, which serves as the actual state file during automatic verification of the termination circuit module's state, thereby improving the efficiency of the termination circuit module simulation verification.

[0123] In some exemplary embodiments provided in this disclosure, the simulation of the circuit under test with parasitic parameters in step S240 can be implemented using simulation software such as Finesim, Hspice, Hsim, or Spectre. It is understood that, in addition to the aforementioned simulation software, other software capable of simulating circuits can also be used.

[0124] In this embodiment, Finesim, Hspice, Hsim, or Spectre simulation software are used to simulate the circuit under test. The simulation is fast and accurate, thereby improving the efficiency of simulation verification of the termination circuit module.

[0125] In some exemplary embodiments provided in this disclosure, such as Figure 7 As shown, Figure 7 This is a flowchart of a circuit verification method provided according to an exemplary embodiment of the present disclosure, including:

[0126] S311. Determine the circuit hierarchy information of the signals to be checked in the status verification file for the termination circuit modules in the circuit under test.

[0127] S312. Determine the circuit hierarchy information of the signals to be checked in the termination circuit module of the circuit under test in the simulation output file.

[0128] S313. Based on the circuit hierarchy information of the signal to be checked in the status verification file and the circuit hierarchy information in the simulation output file, a mapping file is formed.

[0129] In this embodiment, the circuit hierarchy information of the termination circuit module in the state verification file and the circuit hierarchy information of the termination circuit module in the simulation output file are determined. Based on the circuit hierarchy information in the state verification file and the simulation output file, the differences in the circuit hierarchy information can be identified, forming a mapping file containing the mapping relationships of the signals to be checked. By adjusting the mapping relationships of the signals to be checked based on the mapping file formed from the state verification file and the simulation output file, misdetermination of the termination circuit module's state is avoided, thereby improving the reliability of the termination circuit module simulation verification.

[0130] For example, in addition to forming a mapping file based on the circuit hierarchy information of the signal to be checked in the state verification file and the circuit hierarchy information in the simulation output file, a mapping file can also be formed based on the first circuit netlist and the second circuit netlist.

[0131] In some exemplary embodiments provided in this disclosure, such as Figure 8 As shown, Figure 8 An example flowchart illustrates the method for checking the state of the signal to be checked in the termination circuit module in step S400 by comparing the state verification file and the simulation output file according to the mapping file, including:

[0132] S410. Determine the signal to be checked for the termination circuit module based on the status verification file, and obtain the standard output data of the signal to be checked from the status verification file.

[0133] S420. Based on the mapping relationship between the signal to be checked in the state verification file and the signal to be checked in the mapping file, obtain the actual output data of the signal to be checked from the actual output waveform of the simulation output file.

[0134] S430. Compare the standard output data and actual output data of each signal to be checked to verify the status of the signal to be checked in the termination circuit module.

[0135] In this embodiment, the signal to be checked in the termination circuit module is determined according to the state verification file, thereby obtaining standard output data as verification data. Based on the mapping relationship between the signal to be checked in the state verification file and the signal to be checked in the mapping file, the corresponding signal to be checked in the simulation output file is determined, so that actual output data is obtained from the actual output waveform as verification data. Since the termination circuit module contains multiple termination sub-modules, each corresponding to multiple signals to be checked, the standard output data and actual output data of each signal to be checked need to be compared. By obtaining the standard output data and actual output data and comparing them one by one, the state of the termination circuit module is verified, automatically verifying the state of the termination circuit module to improve the efficiency of the termination circuit module simulation verification.

[0136] It is understandable that, in addition to making the standard output data correspond to the actual output data through the method in step S420, the actual output data can also be obtained from the simulation output file first, and then the standard output data can be obtained from the state verification file according to the mapping relationship between the signal to be checked in the simulation output file and the signal to be checked in the mapping file.

[0137] For example, since the actual output data is obtained from the actual output waveform by performing a simulation on the circuit under test with parasitic parameters loaded based on the functional check file, the actual output data is affected by the parasitic parameters in the circuit under test.

[0138] For example, the standard output data is the data of different termination submodules in the termination circuit module in each state of the state verification file, including the voltage data of each signal under test changing over time. The actual output data is the data of different termination submodules in the termination circuit module in each state of the simulation output file, including the voltage data of each signal under test changing over time. For example, when there are 'a' states of the circuit under test and 'b' signals under test, the standard output data is a × b, and the actual output data is a × b. The target function is the function that the circuit under test needs to perform during the state verification of the termination circuit module. Each state of the termination circuit module is the read, write, and idle state under the target function. For example, under the target function, the states of the termination circuit module are read, write, read, and idle states in sequence. Then, the first state is the read state, the second state is the write state, the third state is the write state, and the fourth state is the idle state.

[0139] In some exemplary embodiments provided in this disclosure, such as Figure 9 As shown, Figure 9 An example flowchart illustrates a method for verifying the state of the signal under test in step S430 by comparing the standard output data and the actual output data of each signal under test with the terminal circuit module, including:

[0140] S431. Based on the functional check document, determine the start and end times of each state in the termination circuit module.

[0141] S432. During the start and end time of each state, determine whether the deviation between the actual output data and the standard output data of each signal to be checked is within the preset range.

[0142] S433. When the deviation between the actual output data of the signal to be checked and the standard output data is within the preset range, the state of the signal to be checked is determined to be normal.

[0143] S434. When the deviation between the actual output data of the signal to be checked and the standard output data is outside the preset range, the state of the signal to be checked is determined to be abnormal.

[0144] In this embodiment, the termination circuit module's state varies at different times during circuit verification. When determining the termination circuit module's state based on standard and actual output data, the start and end times of each state under the target function are first determined according to the functional check file to prevent incorrect state determination due to start and end time errors. Within the start and end time of each state, the standard and actual output data of each signal to be checked are compared to determine the signal's state. Since the actual output waveform in the simulation output file contains interference fluctuations, the determination of the signal's state is not based on whether the standard and actual output data are equal, but rather on whether the deviation between the actual and standard output data is within a preset range. When the deviation between the actual and standard output data is within the preset range, the actual output data meets the ideal state requirement, and the signal's state is determined to be normal. When the deviation between the actual and standard output data is outside the preset range, the actual output data does not meet the ideal state requirement, and the signal's state is determined to be abnormal. By comparing the deviation between the actual output data and the standard output data within a preset range, the misdetermination of the state of the termination circuit module caused by interference in the actual output data is avoided, thereby improving the reliability of simulation verification during the state verification process of the termination circuit module.

[0145] For example, in step S431, determining the start and end times of each state in the termination circuit module according to the functional check file can be predefined in the functional check file.

[0146] For example, step S430, comparing the standard output data and actual output data of each signal to be checked to verify the state of the signal to be checked in the termination circuit module, can be divided into verifying whether the state of the termination circuit module is normal and whether the state of the signal to be checked is normal. Regarding the state of the termination circuit module, if at least one deviation between the actual output data and the standard output data is outside a preset range, the state of the termination circuit module is determined to be abnormal. If all deviations between the actual output data and the standard output data are within the preset range, the state of the termination circuit module is determined to be normal. Regarding the state of the signal to be checked, comparing the actual output data and the standard output data of each signal to be checked within the start and end time of each state under the target function determines whether the state of the signal to be checked is normal. By determining the state of the termination circuit module, it is possible to promptly identify whether the overall state of the termination circuit module meets the requirements, avoiding the need to observe the state of each signal to be checked individually, thereby improving the efficiency of the simulation verification of the termination circuit module. By determining the state of the signal to be checked, it is possible to accurately identify the state of the corresponding start and end time and the corresponding signal to be checked in the termination circuit module, identify problems in the circuit under test, and make targeted adjustments, thereby improving the efficiency of the simulation verification.

[0147] For example, in the standard output data, the voltage of the signal to be checked corresponding to the terminating resistor Rx is 0.9U. In the actual output data, the voltage of the signal to be checked corresponding to the terminating resistor Rx in the first state is Ux1 (Ux-0.9U=0.05V), and the voltage of the signal to be checked corresponding to the terminating resistor Rx in the second state is Ux2 (Ux2-0.9U=-0.8V). Therefore, in the first state, the deviation of Ux1 from 0.9U is within a preset range, and the state of the signal to be checked corresponding to the terminating resistor Rx is determined to be normal. In the second state, the deviation of Ux2 from 0.9U is outside the preset range, and the state of the signal to be checked corresponding to the terminating resistor Rx is determined to be abnormal.

[0148] For example, in step S430, comparing the standard output data and the actual output data of each signal to be checked to verify the state of the signal to be checked in the termination circuit module can also determine whether the actual output data of each signal to be checked is within the range of the standard output data within the start and end time of each state, and determine whether the state of the signal to be checked is normal.

[0149] In some exemplary embodiments provided in this disclosure, the circuit verification method further includes the following steps: determining the state of the termination circuit module based on the state of each signal to be inspected; and generating a state inspection report for the termination circuit module.

[0150] In this embodiment, after determining the state of each signal to be checked, the state of the termination circuit module can be determined, thereby generating a state check report. Since the state check report contains the states of the termination circuit module and the signals to be checked, it is possible to identify abnormal signals in the termination circuit module and their corresponding start and end times based on the state check report, so as to make targeted adjustments to the circuit under test and improve the efficiency of simulation verification.

[0151] For example, the status check report may take the form shown in Table 1.

[0152] Table 1:

[0153] V_IO_DQ_TX_1 F_IO_DQ_TX_V1 >0.9U 0 <![CDATA[t1]]> normal V_IO_DQ_TX_1 F_IO_DQ_TX_V1 <0.9U <![CDATA[t1]]> <![CDATA[t2]]> normal V_IO_DQ_TX_1 F_IO_DQ_TX_V1 <0.9U <![CDATA[t2]]> <![CDATA[t3]]> abnormal V_IO_DQ_TX_2 F_IO_DQ_TX_V2 <0.9U 0 <![CDATA[t1]]> normal …… …… …… …… …… ……

[0154] The first signal is the signal to be checked in the status verification file, and the second signal is the signal to be checked in the actual output waveform.

[0155] In some exemplary embodiments provided in this disclosure, the functional check file includes multiple target functions, and the step of forming a status check report for the termination circuit module includes: forming multiple status check reports corresponding to each target function.

[0156] In this embodiment, when the functional check file includes multiple target functions, during the verification process of the circuit under test, the actual output data and standard output data are compared for each target function. When generating the status check report, multiple status check reports are generated corresponding to each target function, allowing testers to check whether the status of the termination circuit module under each target function is normal. By generating multiple status check reports according to the target functions, multiple target functions can be verified at once, and the status of the termination circuit module with abnormal target functions can be quickly determined, thereby improving the efficiency of simulation verification.

[0157] In some exemplary embodiments provided in this disclosure, the functional check file includes multiple target functions, and the step of forming a status check report for the termination circuit module includes: forming a status check report corresponding to a preset target function.

[0158] In this embodiment, when the functional check file includes multiple target functions, during the verification process of the circuit under test, the actual output data and standard output data are compared for each function. When generating the status check report, a unique status check report corresponding to the preset target function is generated, allowing testers to check whether the status of the termination circuit module under the preset target function is normal. By generating a single status check report based on the preset target function, it is possible to quickly determine whether the status of the termination circuit module under the preset target function is abnormal, thereby improving the efficiency of simulation verification. Furthermore, if it is necessary to check the status of the termination circuit module under other target functions later, only the status of the determined termination circuit module needs to be generated to generate the corresponding status check report, thereby improving the efficiency of simulation verification.

[0159] In some exemplary embodiments provided in this disclosure, the functional check file includes multiple simulation parameters, and the step of forming a status check report for the termination circuit module includes: forming multiple status check reports corresponding to each simulation parameter.

[0160] In this embodiment, when the functional check file includes multiple simulation parameters (such as multiple test frequency parameters, multiple test frequency angle parameters, etc.), during the verification process of the circuit under test, the actual output data and standard output data are compared for each simulation parameter. When generating the status check report, multiple status check reports are generated corresponding to each simulation parameter, allowing testers to check whether the status of the termination circuit module is normal under each simulation parameter. By generating multiple status check reports based on the simulation parameters, multiple simulation parameters can be verified at once, and the status of the termination circuit module with abnormal target function can be quickly determined, thereby improving the efficiency of simulation verification.

[0161] In some exemplary embodiments provided in this disclosure, the filenames of the state verification file, simulation output file, mapping file, and / or state check report contain simulation parameters.

[0162] In this embodiment, testers can determine the simulation parameters during the verification process based on the filenames of the state verification file, simulation output file, mapping file, and / or state check report. Simultaneously, the filenames of the state verification file, simulation output file, mapping file, and / or state check report can also be used subsequently under these simulation parameters, avoiding repeated generation and improving the efficiency of the termination circuit module simulation verification.

[0163] For example, the mapping file is stored in the simulation directory of the simulation software for easy retrieval. The check execution file can be formed based on the preset storage path information of the state verification file, simulation output file, and mapping file. When searching for the state verification file, simulation output file, and mapping file, the location of the state verification file, simulation output file, and mapping file is determined one by one according to the storage path information in the check execution file.

[0164] In some exemplary embodiments provided in this disclosure, such as Figure 10 As shown, the circuit verification method includes:

[0165] S600, Obtain the functional check file of the termination circuit module.

[0166] S610. Based on the functional check file, perform functional verification on the circuit under test, obtain the standard output data of the signal to be checked, and form the status verification file corresponding to the termination circuit module when the target function is completed.

[0167] S620: Based on the functional check file, obtain the simulation parameters of the termination circuit module.

[0168] S630. Extract the excitation information of the circuit under test from the functional check file to form a simulation excitation file.

[0169] S640. Based on the simulation parameters and simulation stimulus file, generate the simulation check file for the termination circuit module.

[0170] S650: Based on the simulation check file, perform simulation of the circuit under test with parasitic parameters loaded, obtain the actual output waveform of the signal under test, and form the simulation output file corresponding to the termination circuit module when the target function is completed.

[0171] S660. Determine the circuit hierarchy information of the circuit under test in the status verification file.

[0172] S670. Determine the circuit hierarchy information of the circuit under test in the simulation output file.

[0173] S680. Based on the circuit hierarchy information in the state verification file and the circuit hierarchy information in the simulation output file, a mapping file is formed.

[0174] S690, Obtain the check execution file for the termination circuit module.

[0175] S700: Based on the storage path information in the execution file, locate the status verification file, simulation output file, and mapping file.

[0176] S710. Based on the mapping file, compare the status verification file and the simulation output file to check the status of the signal to be checked in the termination circuit module.

[0177] S720: Determine the state of the termination circuit module based on the state of each signal to be checked.

[0178] S730, generates a status check report for the termination circuit module.

[0179] In this embodiment, a functional verification file is used to perform functional verification on the circuit under test, obtaining standard output data of the signals to be checked, and forming a state verification file reflecting the ideal state of the termination circuit module. A simulation stimulus file is formed based on the simulation parameters in the functional verification file. The circuit under test is simulated using the simulation verification file formed by the simulation parameters and the simulation stimulus file, resulting in a simulation output file reflecting the actual state of the termination circuit module. A mapping file is formed using the circuit hierarchy information in the state verification file and the simulation output file, making the state verification file and the simulation output file correspond. An execution file is obtained, and the state verification file, simulation output file, and mapping file are located. Based on the mapping file, the state verification file and simulation output file are compared to check the state of the signals to be checked in the termination circuit module. By checking the state of the termination circuit module, a state check report is generated, thereby automatically realizing the state verification of the termination circuit module and improving the efficiency of the termination circuit module simulation verification.

[0180] Figure 11 A block diagram of a circuit verification apparatus is shown according to an exemplary embodiment. Figure 11 As shown, the device includes at least a first acquisition module 301, a second acquisition module 302, a third acquisition template 303, and an inspection module 304.

[0181] The first acquisition module 301 is configured to acquire the status verification file of the termination circuit module in the circuit under test; the status verification file includes the standard output data of the signal to be checked of the termination circuit module.

[0182] The second acquisition module 302 is configured to acquire the simulation output file of the termination circuit module in the circuit under test; the simulation output file includes the actual output waveform of the signal to be checked from the termination circuit module.

[0183] The third acquisition module 303 is configured to acquire the mapping file of the termination circuit module in the circuit under test; the mapping file includes the mapping relationship between the status verification file and the signal to be checked in the simulation output file.

[0184] Inspection module 304 is configured to check the status of the signal to be checked in the termination circuit module by comparing the status verification file and the simulation output file with the mapping file.

[0185] In one exemplary embodiment, a circuit verification apparatus is provided, wherein an inspection module 304 is configured to:

[0186] The signal to be checked in the termination circuit module is determined based on the status verification file, and the standard output data of the signal to be checked in the status verification file is obtained.

[0187] Based on the mapping relationship between the signal to be checked in the state verification file and the signal to be checked in the mapping file, the actual output data of the signal to be checked is obtained from the actual output waveform of the simulation output file.

[0188] By comparing the standard output data and the actual output data of each signal to be checked, the status of the signal to be checked in the termination circuit module is verified.

[0189] In one exemplary embodiment, a circuit verification apparatus is provided, wherein an inspection module 304 is configured to:

[0190] Based on the functional check document, determine the start and end times of each state in the termination circuit module.

[0191] During the start and end time of each state, determine whether the deviation between the actual output data and the standard output data of each signal to be checked is within a preset range.

[0192] When the deviation between the actual output data of the signal to be checked and the standard output data is within a preset range, the state of the signal to be checked is determined to be normal.

[0193] When the deviation between the actual output data of the signal to be checked and the standard output data is outside the preset range, the state of the signal to be checked is determined to be abnormal.

[0194] In one exemplary embodiment, a circuit verification apparatus is provided, the apparatus further comprising:

[0195] The fourth acquisition module is configured to acquire the functional check file of the termination circuit module; the functional check file includes simulation parameters and excitation information corresponding to the target function of the circuit under test.

[0196] The first generation module is configured to perform functional verification on the circuit under test based on the functional check file, obtain the standard output data of the signal to be checked, and form the status verification file corresponding to the termination circuit module when the target function is completed.

[0197] In one exemplary embodiment, a circuit verification apparatus is provided, wherein a first generation module is configured to:

[0198] Based on the functional check file, the circuit under test is functionally verified, and a functional verification result file corresponding to the circuit under test when the target function is completed is generated.

[0199] Based on the functional check file, the standard output data of the signal to be checked is obtained from the functional result verification file to form the status verification file corresponding to the termination circuit module when the target function is completed.

[0200] In one exemplary embodiment, a circuit verification apparatus is provided, the apparatus further comprising:

[0201] The fifth acquisition module is configured to acquire simulation parameters of the termination circuit module based on the functional check file; the simulation parameters include test frequency parameters and test process corner parameters.

[0202] The extraction module is configured to extract the excitation information of the circuit under test from the functional check file to form a simulation excitation file.

[0203] The second generation module is configured to generate a simulation check file for the termination circuit module based on the simulation parameters and simulation stimulus file.

[0204] The third generation module is configured to perform a simulation of the circuit under test with parasitic parameters loaded based on the simulation check file, obtain the actual output waveform of the signal under test, and form the simulation output file corresponding to the termination circuit module when the target function is completed.

[0205] In one exemplary embodiment, a circuit verification apparatus is provided, wherein a third generation module is configured to:

[0206] Based on the simulation check file, the circuit under test with parasitic parameters is simulated, and the simulation verification result file corresponding to the circuit under test when the target function is completed is generated.

[0207] Based on the simulation check file, the actual output waveform of the signal to be checked is obtained from the simulation result verification file, and the simulation output file corresponding to the termination circuit module when the target function is completed is formed.

[0208] In one exemplary embodiment, a circuit verification apparatus is provided, the apparatus further comprising:

[0209] The fourth generation module is configured to determine the state of the termination circuit module based on the state of each signal to be inspected.

[0210] Check the status of the termination circuit module and generate a status check report for the termination circuit module.

[0211] In one exemplary embodiment, a circuit verification apparatus is provided, wherein a fourth generation module is configured to:

[0212] Multiple status check reports are generated for each target function.

[0213] In one exemplary embodiment, a circuit verification apparatus is provided, wherein a fourth generation module is configured to:

[0214] Generate a status check report corresponding to the preset target function.

[0215] In one exemplary embodiment, a circuit verification apparatus is provided, wherein a fourth generation module is configured to:

[0216] Multiple status check reports are generated for each simulation parameter.

[0217] In one exemplary embodiment, a circuit verification apparatus is provided, the apparatus further comprising:

[0218] The sixth acquisition module is configured to acquire the check execution file of the termination circuit module; the check execution file includes the storage path information of the status verification file, simulation output file and mapping file.

[0219] The search module is configured to search for status verification files, simulation output files, and mapping files based on the storage path information in the check executable file.

[0220] Figure 12 This is a block diagram illustrating a circuit verification device, namely a computer device 400, according to an exemplary embodiment. For example, the computer device 400 may be provided as a terminal device. (Refer to...) Figure 12 The computer device 400 includes a processor 401, the number of which can be set to one or more as needed. The computer device 400 also includes a memory 402 for storing instructions executable by the processor 401, such as application programs. The number of memories can be set to one or more as needed. The stored application programs can be one or more. The processor 401 is configured to execute instructions to perform the methods described above.

[0221] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, apparatus (devices), or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. Computer storage media include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data), including but not limited to RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible by a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and can include any information delivery medium.

[0222] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is provided, such as a memory 402 including instructions, which can be executed by a processor 401 of the device 400 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0223] A non-transitory computer-readable storage medium, wherein instructions in the storage medium, when executed by a processor of a circuit verification device, enable the circuit verification device to perform:

[0224] Obtain the status verification file of the termination circuit module in the circuit under test; the status verification file includes the standard output data of the signal to be checked of the termination circuit module.

[0225] Obtain the simulation output file of the termination circuit module in the circuit under test; the simulation output file includes the actual output waveform of the signal to be checked in the termination circuit module.

[0226] Obtain the mapping file of the termination circuit module in the circuit under test; the mapping file includes the mapping relationship between the status verification file and the signal to be checked in the simulation output file.

[0227] Based on the mapping file, compare the status verification file and the simulation output file to check the status of the signal to be checked in the termination circuit module.

[0228] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0229] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0230] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0231] In this disclosure, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase “comprising…” does not exclude the presence of additional identical elements in the article or device that includes said element.

[0232] Although preferred embodiments of the present disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0233] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, the intent of this disclosure also includes these modifications and variations.

Claims

1. A method of verifying a circuit, characterized by, The verification method for the circuit includes: Obtain the status verification file of the termination circuit module in the circuit under test; the status verification file includes the standard output data of the signal to be checked of the termination circuit module; Obtain the simulation output file of the termination circuit module in the circuit under test; the simulation output file includes the actual output waveform of the signal to be checked by the termination circuit module; Obtain the mapping file of the termination circuit module in the circuit under test; the mapping file includes the mapping relationship between the status verification file and the signal to be checked in the simulation output file; Based on the mapping file, compare the state verification file and the simulation output file to check the state of the signal to be checked in the termination circuit module; Before obtaining the status verification file of the termination circuit module in the circuit under test, the circuit verification method further includes: Obtain the functional check file of the termination circuit module; the functional check file includes simulation parameters and excitation information corresponding to the target function of the circuit under test. Based on the functional check file, the circuit under test is functionally verified, the standard output data of the signal under test is obtained, and a status verification file corresponding to the termination circuit module when the target function is completed is formed. The step of checking the state of the signal to be checked in the termination circuit module by comparing the state verification file and the simulation output file according to the mapping file includes: The signal to be checked of the termination circuit module is determined according to the status verification file, and the standard output data of the signal to be checked in the status verification file is obtained. Based on the mapping relationship between the signal to be checked in the state verification file and the signal to be checked in the mapping file, the actual output data of the signal to be checked is obtained from the actual output waveform of the simulation output file. By comparing the standard output data and the actual output data of each of the signals to be checked, the state of the signals to be checked in the termination circuit module is verified. The step of comparing the standard output data and the actual output data of each signal to be checked to verify the state of the signal to be checked in the termination circuit module includes: Based on the aforementioned functional check file, determine the start and end times of each state in the termination circuit module; During the start and end time of each state, determine whether the deviation between the actual output data and the standard output data of each signal to be inspected is within a preset range; When the deviation between the actual output data and the standard output data of the signal to be inspected is within the preset range, the state of the signal to be inspected is determined to be normal. When the deviation between the actual output data and the standard output data of the signal to be inspected is outside the preset range, the state of the signal to be inspected is determined to be abnormal.

2. The method of verifying a circuit according to claim 1, wherein, Before obtaining the status verification file of the termination circuit module in the circuit under test, the circuit verification method further includes: Obtain the check execution file of the termination circuit module; the check execution file includes the storage path information of the status verification file, the simulation output file, and the mapping file; Based on the storage path information in the check execution file, locate the status verification file, the simulation output file, and the mapping file.

3. The circuit verification method according to claim 1, characterized in that, The process of performing functional verification on the circuit under test based on the functional check file, obtaining standard output data of the signal under test, and forming a status verification file corresponding to the termination circuit module when the target function is completed includes: Based on the functional check file, the circuit under test is functionally verified, and a functional verification result file corresponding to the circuit under test when the target function is completed is generated. Based on the functional check file, the standard output data of the signal to be checked is obtained from the functional verification result file to form the status verification file corresponding to the termination circuit module when the target function is completed.

4. The circuit verification method according to claim 1, characterized in that, The functional verification of the circuit under test is performed using a functional verification platform that supports the Verilog language.

5. The circuit verification method according to claim 1, characterized in that, Before obtaining the simulation output file of the termination circuit module in the circuit under test, the verification method of the circuit further includes: Based on the functional check file, the simulation parameters of the termination circuit module are obtained; the simulation parameters include test frequency parameters and test process corner parameters. The excitation information of the circuit under test is extracted from the functional test file to form a simulation excitation file; Based on the simulation parameters and the simulation stimulus file, a simulation check file for the termination circuit module is generated; Based on the simulation check file, the circuit under test with parasitic parameters is simulated to obtain the actual output waveform of the signal under test, and a simulation output file corresponding to the termination circuit module when the target function is completed is formed.

6. The circuit verification method according to claim 5, characterized in that, The process involves performing a simulation on the circuit under test based on the simulation check file, obtaining the actual output waveform of the signal under test, and generating a simulation output file corresponding to the termination circuit module when the target function is completed. This includes: Based on the simulation check file, the circuit under test with parasitic parameters loaded is simulated to generate a simulation verification result file corresponding to the circuit under test when the target function is completed. Based on the simulation check file, the actual output waveform of the signal to be checked is obtained from the simulation verification result file to form the simulation output file corresponding to the termination circuit module when the target function is completed.

7. The circuit verification method according to claim 5, characterized in that, The simulation of the circuit under test with parasitic parameters is performed using Finesim simulation software, Hspice simulation software, Hsim simulation software, or Spectre simulation software.

8. The circuit verification method according to claim 1, characterized in that, After verifying the state of the signal under test of the termination circuit module by comparing the standard output data and the actual output data of each signal under test, the verification method of the circuit further includes: The state of the termination circuit module is determined based on the state of each of the signals to be inspected; A status check report is generated for the termination circuit module.

9. The circuit verification method according to claim 8, characterized in that, The functional check file includes multiple target functions; the status check report for forming the termination circuit module includes: Multiple status check reports are generated for each of the target functions.

10. The circuit verification method according to claim 8, characterized in that, The functional check file includes multiple target functions; the status check report for forming the termination circuit module includes: A status check report corresponding to the preset target function is generated.

11. The circuit verification method according to claim 8, characterized in that, The functional check file includes multiple simulation parameters; the status check report for forming the termination circuit module includes: Multiple status check reports are generated for each of the simulation parameters.

12. The circuit verification method according to claim 8, characterized in that, The simulation parameters are included in the filenames of the state verification file, the simulation output file, the mapping file, and / or the state check report.

13. A circuit verification device, characterized in that, The verification device for the circuit includes: The first acquisition module is configured to acquire a status verification file of the termination circuit module in the circuit under test; the status verification file includes standard output data of the signal to be checked of the termination circuit module; The second acquisition module is configured to acquire the simulation output file of the termination circuit module in the circuit under test; the simulation output file includes the actual output waveform of the signal to be checked by the termination circuit module; The third acquisition module is configured to acquire the mapping file of the termination circuit module in the circuit under test; the mapping file includes the mapping relationship between the status verification file and the signal to be checked in the simulation output file; The inspection module is configured to check the status of the signal to be inspected in the termination circuit module by comparing the status verification file and the simulation output file according to the mapping file. The fourth acquisition module is configured to acquire the functional check file of the termination circuit module; the functional check file includes simulation parameters and excitation information corresponding to the target function of the circuit under test; The first generation module is configured to perform functional verification on the circuit under test based on the functional check file, obtain the standard output data of the signal under test, and form a status verification file corresponding to the termination circuit module when the target function is completed. The inspection module is further configured to: determine the signal to be inspected of the termination circuit module according to the status verification file, and obtain the standard output data of the signal to be inspected in the status verification file; obtain the actual output data of the signal to be inspected from the actual output waveform of the simulation output file according to the mapping relationship between the signal to be inspected in the status verification file and the signal to be inspected in the mapping file; and verify the status of the signal to be inspected of the termination circuit module by comparing the standard output data and the actual output data of each signal to be inspected. According to the functional check document, determine the start and end times of each state in the termination circuit module; within the start and end time of each state, determine whether the deviation between the actual output data and the standard output data of each signal to be checked is within a preset range; when the deviation between the actual output data and the standard output data of the signal to be checked is within the preset range, determine that the state of the signal to be checked is normal; when the deviation between the actual output data and the standard output data of the signal to be checked is outside the preset range, determine that the state of the signal to be checked is abnormal.

14. A circuit verification device, characterized in that, The verification equipment for the circuit includes: processor; Memory used to store processor-executable instructions; The processor is configured to perform a verification method for the circuit as described in any one of claims 1-12.

15. A non-transitory computer-readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the circuit verification device, the circuit verification device is able to perform the circuit verification method as described in any one of claims 1-12.

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