Electronic device

Abstract

An electronic device is provided. The electronic device includes a tunable element, a first power supply circuit, and a second power supply circuit. The first power supply circuit and the second power supply circuit are electrically connected to the tunable element. The first power supply circuit drives the tunable element in a first time period. The second power supply circuit drives the tunable element in a second time period.

Description

Technical Field

[0001] This disclosure relates to an electronic device, and more particularly to an electronic device having adjustable elements. Background Technology

[0002] Generally, electronic devices drive electronic components via a driving element. The driving element provides driving power to the electronic components (e.g., pixel circuits or adjustable elements). However, over prolonged operation, the driving element degrades. The operational stability of the electronic components decreases due to the abnormal driving power provided by the degraded driving element. Therefore, reducing the likelihood of driving element degradation to improve the operational stability of electronic components is a key research focus for those skilled in the art. Summary of the Invention

[0003] This disclosure provides an electronic device that can improve the stability of electronic components during long-term operation.

[0004] The disclosed electronic device includes an adjustable element, a first power supply circuit, and a second power supply circuit. The first and second power supply circuits are electrically connected to the adjustable element. The first power supply circuit drives the adjustable element during a first time period. The second power supply circuit drives the adjustable element during a second time period.

[0005] Based on the above, the first and second power supply circuits drive the adjustable components in a time-sharing manner. The first and second power supply circuits can alternately rest. In this way, the possibility of degradation of the first and second power supply circuits can be reduced during long-term operation, thereby improving the stability of the electronic device during operation.

[0006] To make the above-mentioned features and advantages disclosed herein more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the electronic device shown according to the first embodiment of this disclosure;

[0008] Figure 2 This is a schematic diagram of an electronic device according to the second embodiment of this disclosure;

[0009] Figure 3 It is a circuit diagram of the electronic device shown in the second embodiment of this disclosure;

[0010] Figure 4 It is a timing diagram based on the second embodiment of this disclosure;

[0011] Figure 5 This is a schematic diagram of an electronic device according to the third embodiment of this disclosure;

[0012] Figure 6 It is a circuit diagram of an electronic device shown in the third embodiment of this disclosure;

[0013] Figure 7 It is based on Figure 6 The timing diagram shown is shown below;

[0014] Figure 8 This is a layout diagram of the substrate of an electronic device according to an embodiment of the present disclosure.

[0015] Explanation of reference numerals in the attached figures

[0016] 100, 200, 300: Electronic devices

[0017] 110_1, 210_1, 310_1: First power supply circuit

[0018] 110_2, 210_2, 310_2: Second power supply circuit

[0019] 110_n, 210_n, 310_n: The nth power supply circuit

[0020] 120, 220, 330: Selection circuit

[0021] 210_3: Third power supply circuit

[0022] 211_1~211_n, 320: Compensation circuits

[0023] 211_2~212_n: Source follower circuit

[0024] 80: Substrate

[0025] 800S: Side

[0026] 80A: Active Zone

[0027] 80B: Surrounding Area

[0028] Cst: Storage capacitor

[0029] DL: Data cable

[0030] EE: Adjustable element

[0031] GS: Control terminal of the scanning transistor

[0032] ID1: First drive current

[0033] ID2: Second drive current

[0034] IDn: nth driving current

[0035] N1: Node

[0036] ND1: First node

[0037] ND2: Second Node

[0038] ND3: Third Node

[0039] NDn: the nth node

[0040] PB: Bias Period

[0041] PR: Reset Cycle

[0042] PS: Scan cycle

[0043] SB: Bias signal

[0044] SC: Drive current

[0045] SS: Selection Signal

[0046] SR: Reset signal

[0047] t: time

[0048] t1~t7: Time points

[0049] T1-1~T1-n, TD: Power supply transistors

[0050] T2-1~T2-n: Compensation transistors

[0051] TB: Bias Transistor

[0052] TC: Compensation Transistor

[0053] TD: Driving transistor

[0054] TR: Reset transistor

[0055] TS: Scanning Transistor

[0056] TT1~TTn: Time period

[0057] V: Voltage

[0058] Vdata: Data voltage

[0059] Vd: The voltage at the first terminal of the driving transistor

[0060] VDD: High reference voltage

[0061] Vg: Voltage located at the control terminal of the driving transistor

[0062] VG1~VGn: Control signals

[0063] Vs: Voltage located at the second terminal of the driving transistor

[0064] VSS: Low reference voltage

[0065] Vth: Critical Voltage Detailed Implementation

[0066] This disclosure can be understood by referring to the following detailed description, taken in conjunction with the accompanying drawings. It should be noted that, for purposes of clarity and ease of understanding, the various drawings of this disclosure show a portion of an electronic device, and some elements in the various drawings may not be drawn to scale. Furthermore, the number and dimensions of each device shown in the drawings are illustrative only and are not intended to limit the scope of this disclosure.

[0067] Certain terms are used throughout the description and the following claims to refer to specific elements. As those skilled in the art will understand, electronic device manufacturers may use different names to refer to elements. This document is not intended to distinguish elements that differ in name but not in function. In the following description and in the claims, the terms “comprising,” “including,” and “having” are used in an open-ended manner and should therefore be interpreted as meaning “including but not limited to…”. Thus, when the terms “comprising,” “including,” and / or “having” are used in the description of this disclosure, it indicates the presence, but is not limited to, of a corresponding feature, area, step, operation, and / or element, but is not limited to the presence of one or more corresponding features, areas, steps, operations, and / or elements.

[0068] It should be understood that when a component is referred to as "coupled to," "connected to," or "conducted to" another component, the component can be directly connected to the other component and an electrical connection can be directly established, or there may be intermediate components between these components for relaying the electrical connection (indirect electrical connection). In contrast, when a component is referred to as "directly coupled to," "directly connected to," or "directly connected to" another component, there are no intermediate components.

[0069] Although terms such as first, second, third, etc., may be used to describe different constituent elements, such constituent elements are not limited by these terms. The terms are used only to distinguish a constituent element in the specification from other constituent elements. The claims may not use the same terms, but may use terms such as first, second, third, etc., relative to the required order of the elements. Therefore, in the following description, a first constituent element may be a second constituent element in a claim.

[0070] The electronic devices disclosed herein may include, but are not limited to, display devices, antenna devices, sensing devices, light-emitting devices, touch displays, curved displays, or free-shape displays. Electronic devices may include bendable or flexible electronic devices. Electronic devices may include, for example, liquid crystal, light-emitting diodes (LEDs), quantum dot (QD) displays, fluorescent displays, phosphorescent displays, other suitable display media, or combinations of the above materials, but are not limited thereto. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), miniLEDs, microLEDs, or quantum dot LEDs (including QLEDs, QDLEDs), or other suitable materials, or combinations thereof, but are not limited thereto. Display devices may include, for example, video wall displays, but are not limited thereto. Antenna devices may be, for example, liquid crystal antennas or varactor antennas, but are not limited thereto. Antenna devices may include, for example, antenna splicing devices, but are not limited thereto. It should be noted that the electronic device can be any of the aforementioned arrangements and combinations, but is not limited thereto. Furthermore, the electronic device can be rectangular, circular, polygonal, have curved edges, or other suitable shapes. The electronic device may have peripheral systems such as drive systems, control systems, and light source systems to support display devices, antenna devices, or splicing devices, but this disclosure is not limited thereto. Sensing devices may include cameras, infrared sensors, or fingerprint sensors, etc., and this disclosure is not limited thereto. In some embodiments, the sensing device may also include a flash, an infrared (IR) light source, other sensors, electronic components, or combinations thereof, but is not limited thereto.

[0071] In this disclosure, embodiments use the term "pixel" or "pixel unit" as a unit for describing a specific area containing at least one functional circuit for at least one specific function. The area of ​​a "pixel" depends on the unit used to provide the specific function; adjacent pixels may share the same portion or wires, but may also include their own specific portion therein. For example, adjacent pixels may share the same scan line or the same data line, but a pixel may also have its own transistor or capacitor.

[0072] It should be noted that the technical features in the different embodiments described below may be replaced, rearranged or combined with each other to form another embodiment without departing from the spirit of this disclosure.

[0073] Please refer to Figure 1 , Figure 1 This is a schematic diagram of an electronic device according to a first embodiment of the present disclosure. In this embodiment, the electronic device 100 includes a tunable element EE and a first power supply circuit 110_1 to an nth power supply circuit 110_n. The first power supply circuit 110_1 is electrically connected to the tunable element EE. The first power supply circuit 110_1 can drive the tunable element EE in a first time period. A second power supply circuit 110_2 is electrically connected to the tunable element EE. The second power supply circuit 110_2 can drive the tunable element EE in a second time period. Similarly, it can be deduced that the power supply circuit 110_n can drive the tunable element EE in the nth time period. That is, the first power supply circuit 110_1 to the nth power supply circuit 110_n drive the tunable element EE in a time-division multiplexing manner at different time periods. According to some embodiments, the power supply circuit may be a drive circuit.

[0074] According to some embodiments, the first power supply circuit 110_1 to the nth power supply circuit 110_n drive the adjustable element in a time-division multiplexing manner. The first power supply circuit 110_1 to the nth power supply circuit 110_n can alternately rest. In this way, the possibility of degradation of the first power supply circuit 110_1 to the nth power supply circuit 110_n under long-term operation can be reduced, thereby improving the stability of the first power supply circuit 110_1 to the nth power supply circuit 110_n and the adjustable element EE during long-term operation.

[0075] The number of power supply circuits disclosed herein may be multiple and is not limited to this embodiment.

[0076] In this embodiment, the first power supply circuit 110_1 to the nth power supply circuit 110_n each receive the same high reference voltage VDD. According to some embodiments, the first time period and the second time period do not overlap. According to some embodiments, the first time period to the nth time period do not overlap with each other.

[0077] In this embodiment, the electronic device 100 is, for example, suitable for the field of wireless transmission. For instance, the electronic device 100 is suitable for an antenna device. The adjustable component EE can be a communication element, such as a varactor or a radio frequency radiation element. According to some embodiments, specific parameters (e.g., physical parameters) of the adjustable component can be adjusted according to the applied signal. Specific parameters may include, for example, capacitance, inductance, resistance, dielectric constant, or combinations thereof.

[0078] According to some embodiments, such as Figure 8As shown, the electronic device 100 may include a substrate 80, which includes an active region 80A and a peripheral region 80B. The peripheral region 80B is adjacent to the active region 80A. For example, the active region 80A may be located at the center of the substrate 80, and the peripheral region 80B may be located at the edge of the substrate 80 (this disclosure is not limited thereto). More specifically, the peripheral region 80B may be closer to the side edge 800S of the substrate 80 than the active region 80A. The active region 80A may be a region for emitting and receiving electromagnetic waves. According to some embodiments, an adjustable element EE may be disposed on the substrate 80 and within the active region 80A. For example, as Figure 8 As shown, multiple adjustable elements EE can be disposed within the active region 80A of the substrate 80. According to some embodiments, the first power supply circuit 110_1 to the nth power supply circuit 110_n can be disposed within the active region 80A. According to other embodiments, the first power supply circuit 110_1 to the nth power supply circuit 110_n can be disposed within the peripheral region 80B. According to some embodiments, the substrate 80 can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be glass, and the flexible substrate can be plastic or polymer; however, this disclosure is not limited thereto.

[0079] Furthermore, in this embodiment, such as Figure 1 As shown, the electronic device 100 also includes a selection circuit 120 and a storage capacitor Cst. The selection circuit 120 is electrically connected to the data line DL. The selection circuit 120 receives a data voltage Vdata from the data line DL and provides the data voltage Vdata to the first power supply circuit 110_1 to the nth power supply circuit 110_n. The storage capacitor Cst is coupled between the selection circuit 120 and the low reference voltage VSS. The capacitor Cst is used to maintain the voltage value of the data voltage Vdata.

[0080] Taking this embodiment as an example, the data voltage Vdata can be used to change the electronic characteristics of the adjustable element EE. Furthermore, the data voltage Vdata can be used to compensate for the operation of the first power supply circuit 110_1 to the nth power supply circuit 110_n.

[0081] Please refer to Figure 2 , Figure 2 This is a schematic diagram of an electronic device according to a second embodiment of the present disclosure. In this embodiment, the electronic device 200 includes an adjustable element EE, a first power supply circuit 210_1 to an nth power supply circuit 210_n, a selection circuit 220, and a storage capacitor Cst. The first power supply circuit 210_1 to the nth power supply circuit 210_n drive the adjustable element EE in a time-division multiplexing manner at different time periods.

[0082] The first power supply circuit 210_1 includes a compensation circuit 211_1. The second power supply circuit 210_2 includes a compensation circuit 211_2. Similarly, the nth power supply circuit 210_n includes a compensation circuit 211_n. In this embodiment, the compensation circuits 211_1 to 211_n can respectively use the data voltage Vdata to compensate the corresponding power supply circuit. For example, the first compensation circuit 211_1 can use the data voltage Vdata to compensate the first power supply circuit 210_1.

[0083] The first power supply circuit 210_1 also includes a source follower circuit 212_1. The compensation circuit 211_1 can use the data voltage Vdata to compensate for the source follower circuit 212_1. For example, the source follower circuit 212_1 uses a high reference voltage VDD to provide drive power (e.g., drive current or drive voltage) to drive the adjustable element EE. However, due to differences in the manufacturing process or operating environment conditions (e.g., temperature, humidity) of the adjustable element EE, leakage current may occur during operation. The leakage current of the adjustable element EE will affect the drive power provided by the source follower circuit 212_1. Therefore, the compensation circuit 211_1 can use the data voltage Vdata to compensate for the drive power (e.g., drive current or drive voltage) provided by the source follower circuit 212_1.

[0084] Similarly, the second power supply circuit 210_2 also includes a source follower circuit 212_2. The compensation circuit 211_2 can use the data voltage Vdata to compensate for the source follower circuit 212_2. The power supply circuit 210_n also includes a source follower circuit 212_n. The compensation circuit 211_n can use the data voltage Vdata to compensate for the source follower circuit 212_n.

[0085] like Figure 2As shown, in this embodiment, the selection circuit 220 may be electrically connected to at least one, part, or all of the power supply circuits 210_1 to 210_n. For example, the selection circuit 220 is electrically connected to the compensation circuits 211_1 to 211_n. The selection circuit 220 provides a data voltage Vdata based on the voltage value of the selection signal SS and provides the data voltage Vdata to the compensation circuits 211_1 to 211_n. The selection circuit 220 may include a scan transistor TS. A first terminal of the scan transistor TS is electrically connected to the data line DL to receive the data voltage Vdata. A second terminal of the scan transistor TS is electrically connected to the compensation circuits 211_1 to 211_n. The control terminal GS of the scan transistor TS receives the selection signal SS. The scan transistor TS is turned off based on a low voltage value of the selection signal SS. Therefore, the scan transistor TS stops transmitting the data voltage Vdata. The scan transistor TS is turned on based on a high voltage value of the selection signal SS. Therefore, the scan transistor TS can transmit the data voltage Vdata located on the data line DL to the compensation circuits 211_1 to 211_n. According to some embodiments, the selection circuit 220 may be disposed in the active region 80A of the substrate 80, and the first power supply circuit 110_1 to the nth power supply circuit 110_n may be disposed in the active region 80A.

[0086] like Figure 2 As shown, according to some embodiments, the selection circuit 220 can be configured to provide a data voltage Vdata based on the voltage value of the selection signal SS, and provide the data voltage Vdata to the first power supply circuit and the second power supply circuit. Specifically, the selection signal SS can be received during the on-time of the selection circuit 220; this on-time can be referred to as the scan time. The same scan time can be divided into multiple time periods, for example, a first time period, a second time period… an nth time period. That is, for example, the scan time can include a first time period and a second time period. The first time period and the second time period may not overlap. According to some embodiments, the first time period to the nth time period may not overlap with each other.

[0087] In this embodiment, the scanning transistor TS can be implemented using an N-type transistor. The scanning transistor TS is, for example, an N-type thin-film transistor or an NMOS transistor. In other embodiments, the scanning transistor TS can be implemented using a P-type transistor. In these embodiments, the scanning transistor TS is turned off based on the high or low voltage value of the selection signal SS and turned on based on the low voltage value of the selection signal SS. In this specification, for simplicity, an N-type transistor is used as an example, but the invention is not limited thereto. A P-type transistor can also be used, which will not be elaborated further here.

[0088] To further explain, please refer to the following: Figure 3 as well as Figure 4 , Figure 3The circuit diagram is based on the electronic device shown in the second embodiment of this disclosure. Figure 4 This is a timing diagram based on the second embodiment of the present disclosure. In this embodiment, control signals VG1 to VGn may have positive pulses in different time periods TT1 to TTn. For example, the scanning transistor TS is turned on according to the high voltage value of the selection signal SS. Control signal VG1 has a positive pulse in time period TT1. Control signal VG2 has a positive pulse in time period TT2. Control signal VG3 has a positive pulse in time period TT3. Similarly, control signal VGn has a positive pulse in time period TTn. The aforementioned time periods TT1 to TTn may be adjacent to each other and do not overlap. Therefore, based on control signals VG1 to VGn, source follower circuits 212_1 to 212_n sequentially provide approximately the same driving power in different time periods TT1 to TTn. In this embodiment, source follower circuit 212_1 is electrically connected to the first node ND1. In other words, source follower circuit 212_1 is electrically connected to the adjustable element EE through the first node ND1. The source follower circuit 212_1 includes a control terminal. The voltage at the first node ND1 is supplied to the adjustable element EE, following the voltage at the control terminal of the source follower circuit 212_1. The source follower circuit 212_1 is implemented by a power supply transistor T1-1. The first terminal of the power supply transistor T1-1 receives a high reference voltage VDD. The second terminal of the power supply transistor T1-1 is electrically connected to the first node ND1. The control terminal of the power supply transistor T1-1 receives a control signal VG1. The power supply transistor T1-1 can be implemented by an N-type transistor. The power supply transistor T1-1 is, for example, an N-type thin-film transistor or an NMOS transistor. Therefore, the voltage at the first node ND1 can follow the voltage value of the control signal VG1. In other embodiments, the power supply transistor T1-1 can use a P-type transistor, which will not be described further here. According to some embodiments, time periods TT1 and TT2 can partially overlap, that is, the pulses of the control signal VG1 and the control signal VG2 can partially overlap.

[0089] like Figure 3 As shown, the compensation circuit 211_1 includes a compensation transistor T2-1. The first terminal and control terminal of the compensation transistor T2-1 are electrically connected to the second terminal of the scanning transistor TS. The second terminal of the compensation transistor T2-1 is electrically connected to the first node ND1. The compensation transistor T2-1 is electrically connected between the second terminal of the scanning transistor TS and the first node ND1 in a diode-connected manner. The first terminal of the scanning transistor TS is electrically connected to the data line DL to receive the data voltage Vdata.

[0090] For example, the adjustable element EE may experience leakage current during operation. The voltage at the first node ND1 may be lower than the design voltage. Once the voltage at the first node ND1 drops, the voltage difference between the first and second terminals of the power supply transistor T1-1 increases, thereby increasing the voltage stress on the power supply transistor T1-1. In this embodiment, the compensation circuit 211_1 uses the data voltage Vdata to compensate for the voltage at the first node ND1 during the first time period, thereby bringing the voltage at the first node ND1 back to the design voltage. The voltage difference between the first and second terminals of the power supply transistor T1-1 does not increase. Therefore, the voltage stress on the power supply transistor T1-1 does not increase.

[0091] In this embodiment, the source follower circuit 212_2 in the second power supply circuit 210_2 is electrically connected to the adjustable element EE through the second node ND2. The source follower circuit 212_2 includes a control terminal. The voltage at the second node ND2 is supplied to the adjustable element EE following the voltage at the control terminal of the source follower circuit 212_2. The source follower circuit 212_2 is implemented by a power supply transistor T1-2. The first terminal of the power supply transistor T1-2 receives a high reference voltage VDD. The second terminal of the power supply transistor T1-2 is electrically connected to the second node ND2. The control terminal of the power supply transistor T1-2 receives a control signal VG2. The power supply transistor T1-2 can be implemented by an N-type transistor. The power supply transistor T1-2 is, for example, an N-type thin-film transistor or an NMOS transistor. Therefore, the voltage at the second node ND2 follows the voltage value of the control signal VG2.

[0092] The compensation circuit 211_2 includes a compensation transistor T2-2. The first terminal and control terminal of the compensation transistor T2-2 are electrically connected to the second terminal of the scanning transistor TS. The second terminal of the compensation transistor T2-2 is electrically connected to the second node ND2. In this embodiment, the compensation circuit 211_2 uses the data voltage Vdata during the second time period to compensate for the voltage value at the second node ND2, thereby ensuring that the voltage value at the second node ND2 reaches the design voltage value. Therefore, the voltage stress on the power supply transistor T1-2 does not increase.

[0093] In this embodiment, the source follower circuit 212_n in the nth power supply circuit 210_n is electrically connected to the adjustable element EE through the nth node NDn. The source follower circuit 212_n includes a control terminal. The voltage at the nth node NDn is supplied to the adjustable element EE following the voltage at the control terminal of the source follower circuit 212_n. The source follower circuit 212_n is implemented by a power supply transistor T1-n. The first terminal of the power supply transistor T1-n receives a high reference voltage VDD. The second terminal of the power supply transistor T1-n is electrically connected to the nth node NDn. The control terminal of the power supply transistor T1-n receives a control signal VGn. The power supply transistor T1-n can be implemented by an N-type transistor. The power supply transistor T1-n is, for example, an N-type thin-film transistor or an NMOS transistor. Therefore, the voltage at the nth node NDn follows the voltage value of the control signal VGn.

[0094] The compensation circuit 211_n includes a compensation transistor T2-n. The first terminal and control terminal of the compensation transistor T2-n are electrically connected to the second terminal of the scan transistor TS. The second terminal of the compensation transistor T2-n is electrically connected to the nth node NDn. In this embodiment, the compensation circuit 211_n uses the data voltage Vdata during the nth time period to compensate for the voltage value at the nth node NDn, thereby ensuring that the voltage value at the nth node NDn reaches the design voltage value. Therefore, the voltage stress on the power supply transistor T1-n does not increase.

[0095] Please refer to Figure 5 , Figure 5 This is a schematic diagram of an electronic device according to a third embodiment of the present disclosure. In this embodiment, the electronic device 300 includes an adjustable element EE, power supply circuits 310_1 to 310_n, a compensation circuit 320, and a selection circuit 330. The compensation circuit 320 is electrically connected between the first power supply circuit 310_1 and the adjustable element EE. The first power supply circuit 310_1 can provide a first drive current ID1 in a first time period. The second power supply circuit 310_2 can provide a second drive current ID2 in a second time period. The nth power supply circuit 310_n can provide an nth drive current IDn in the nth time period. The first drive current ID1 to the nth drive current IDn can be provided to the adjustable element EE in a time-division multiplexing manner.

[0096] In this embodiment, the compensation circuit 320 is electrically connected to the first power supply circuit 310_1 to the nth power supply circuit 310_n, the selection circuit 330, and the adjustable element EE. At different time periods, one of the first drive currents ID1 to the nth drive current IDn can flow through the adjustable element EE via the compensation circuit 320. Therefore, the compensation circuit 320 can receive one of the first drive currents ID1 to the nth drive current IDn at different time periods. In this embodiment, during a first time period, the compensation circuit 320 receives the first drive current ID1 and compensates for the first drive current ID1 flowing through the adjustable element EE. During a second time period, the compensation circuit 320 receives the second drive current ID2 and compensates for the second drive current ID2 flowing through the adjustable element EE, and so on.

[0097] In this embodiment, the selection circuit 330 is electrically connected to the data line DL. The selection circuit 330 receives the data voltage Vdata from the data line DL. The compensation circuit 320 compensates for the first drive current ID1 to the nth drive current IDn based on the data voltage Vdata. This ensures that the current values ​​of the compensated first drive current ID1 to the nth drive current IDn are approximately the same as the drive current of the adjustable element EE when no leakage current occurs. According to some embodiments, the selection circuit 330 and the compensation circuit 320 may be disposed in the active region 80A of the substrate 80, and the first power supply circuit 110_1 to the nth power supply circuit 110_n may be disposed in the peripheral region 80B.

[0098] Please refer to Figure 6 , Figure 6This is a circuit diagram of an electronic device according to a third embodiment of the present disclosure. In this embodiment, a first power supply circuit 310_1 includes a power supply transistor T1-1, and a second power supply circuit 310_2 includes a power supply transistor T1-2. The first power supply circuit 310_1 is electrically connected to a compensation circuit 320 and configured to provide a first drive current ID1 in a first time period. The second power supply circuit 310_2 is electrically connected to the compensation circuit 320 and configured to provide a second drive current ID2 in a second time period. A first terminal of the power supply transistor T1-1 receives a high reference voltage VDD. A second terminal of the power supply transistor T1-1 is electrically connected to the compensation circuit 320. A control terminal of the power supply transistor T1-1 receives a control signal VG1. The power supply transistor T1-1 can provide the first drive current ID1 according to the control signal VG1 in the first time period. The second power supply circuit 310_2 includes a power supply transistor T1-2. A first terminal of the power supply transistor T1-2 receives a high reference voltage VDD. A second terminal of the power supply transistor T1-2 is electrically connected to the compensation circuit 320. The control terminal of power supply transistor T1-2 receives control signal VG2. Power supply transistor T1-2 can provide a second drive current ID2 according to control signal VG2 in the second time period. Similarly, the nth power supply circuit 310_n includes power supply transistor T1-2. The first terminal of power supply transistor T1-2 receives a high reference voltage VDD. The second terminal of power supply transistor T1-n is electrically connected to compensation circuit 320. The control terminal of power supply transistor T1-n receives control signal VGn. Power supply transistor T1-n can provide an nth drive current IDn according to control signal VGn in the nth time period.

[0099] Selection circuit 330 includes a scan transistor TS. The first terminal of the scan transistor TS is electrically connected to the data line DL to receive the data voltage Vdata. The second terminal of the scan transistor TS is electrically connected to the compensation circuit 320. The control terminal of the scan transistor TS receives the selection signal SS.

[0100] According to some embodiments, such as Figure 6As shown, the compensation circuit 320 may include a bias transistor TB, a compensation transistor TC, a drive transistor TD, a reset transistor TR, and a storage capacitor Cst. The first terminal of the bias transistor TB is electrically connected to the first power supply circuit 310_1 to the nth power supply circuit 310_n. The second terminal of the bias transistor TB is electrically connected to the first terminal of the drive transistor TD. The control terminal of the bias transistor TB receives a bias signal SB. The second terminal of the drive transistor TD is electrically connected to the selection circuit 330 and the adjustable element EE through node N1. The first terminal of the compensation transistor TC is electrically connected to the second terminal of the bias transistor TB. The second terminal of the compensation transistor TC is electrically connected to the control terminal of the drive transistor TD. The control terminal of the compensation transistor TC receives a selection signal SS. The storage capacitor Cst is electrically connected to the first terminal of the bias transistor TB and the control terminal of the drive transistor TD. The first terminal of the reset transistor TR is electrically connected to the first terminal of the bias transistor TB. The second terminal of the reset transistor TR is electrically connected to the control terminal of the drive transistor TD. The control terminal of the reset transistor TR receives a reset signal SR.

[0101] In this embodiment, the bias transistor TB, compensation transistor TC, drive transistor TD, and reset transistor TR can each be implemented using N-type transistors. The power supply transistors T1-n are, for example, N-type thin-film transistors or NMOS transistors.

[0102] Please also refer to Figure 6 as well as Figure 7 , Figure 7 It is based on Figure 6 The timing diagram shown is for this embodiment, where the power supply transistors T1-1 to T1-n are in time-division multiplexing mode. The voltage Vd at the first terminal of the driving transistor TD is at a reference high voltage VDD during the previous bias cycle PB before time point t1. During the reset cycle PR from time point t2 to time point t3, the reset transistor TR is turned on by a high-voltage reset signal SR. The bias signal SB and the selection signal SS have low voltage levels. Therefore, the bias transistor TB, the scan transistor TS, and the compensation transistor TC are turned off. The control terminal of the driving transistor TD can receive the reference high voltage VDD. Furthermore, the voltage Vd at the first terminal of the driving transistor TD can be maintained in the operating state. During the reset cycle PR from time point t2 to time point t3, the voltage Vg at the control terminal of the driving transistor TD and the voltage Vd at the first terminal of the driving transistor TD are approximately equal to the reference high voltage VDD.

[0103] During the scan cycle PS from time point t4 to time point t5, the bias transistor TB is turned off by a bias signal SB with a low voltage level. The scan transistor TS and the compensation transistor TC are turned on by a selection signal SS with a high voltage level, causing the drive transistor TD to operate in a diode-connected manner. Furthermore, the data line DL can supply the data voltage Vdata to the control terminal of the drive transistor TD through the scan transistor TS, the drive transistor TD, and the compensation transistor TC. Therefore, the voltage Vg at the control terminal of the drive transistor TD can be the voltage Vdata + |Vth|, where Vth is the threshold voltage of the drive transistor TD. The voltage Vd at the first terminal of the drive transistor TD is also the voltage Vdata + |Vth|. Furthermore, the voltage Vs at the second terminal of the drive transistor TD is the data voltage Vdata.

[0104] During the bias period PB from time t6 to time t7, the bias transistor TB is turned on by a bias signal SB with a high voltage level. The scan transistor TS and the compensation transistor TC are turned off by a selection signal SS with a low voltage level. Since the bias transistor TB is turned on, the voltage Vd at the first terminal of the drive transistor TD is the high reference voltage VDD. The voltage Vg at the control terminal of the drive transistor TD is maintained at Vdata+|Vth|. The voltage Vs at the second terminal of the drive transistor TD can be the data voltage Vdata. Simultaneously, the adjustable element EE operates, and the second terminal of the drive transistor TD provides the received drive current to the adjustable element EE according to the operating voltage VDD.

[0105] When leakage current occurs in the adjustable element EE, the voltage at node N1 may drop. The voltage Vs at the second terminal of the driving transistor TD may also drop. According to some embodiments, since the voltage Vg at the control terminal of the driving transistor TD can be the voltage of Vdata + |Vth|, and the voltage Vs at the second terminal of the driving transistor TD is the data voltage Vdata, the driving transistor TD can provide a fixed drive current SC (i.e., one of the compensated first drive currents ID1 to the nth drive current IDn) to the adjustable element EE based on the fixed voltage difference between the control terminal and the second terminal of the driving transistor TD. Furthermore, the voltage Vs at the second terminal of the driving transistor TD can compensate for the voltage drop caused by the leakage current of the adjustable element EE.

[0106] In summary, the electronic device disclosed herein includes a first power supply circuit and a second power supply circuit, electrically connected to an adjustable element. The first power supply circuit can drive the adjustable element for a first time period, and the second power supply circuit can drive the same adjustable element for a second time period. Thus, the first and second power supply circuits drive the adjustable element in a time-division multiplexing manner. The first and second power supply circuits can alternately rest. This reduces the likelihood of degradation of the first and second power supply circuits during prolonged operation, thereby improving the stability of the electronic component during operation. According to some embodiments, the electronic device disclosed herein can also compensate for leakage current of the adjustable element.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions disclosed herein, and are not intended to limit them. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments disclosed herein.

Claims

1. An electronic device, characterized in that, The electronic device includes: An adjustable element, wherein the adjustable element is a variable capacitor or a radio frequency radiating element; A first power supply circuit is electrically connected to the adjustable element; A second power supply circuit is electrically connected to the adjustable element, wherein the first power supply circuit drives the adjustable element in a first time period, and the second power supply circuit drives the adjustable element in a second time period. Data cable; and The selection circuit receives data voltage from the data line and provides the data voltage to the first power supply circuit and the second power supply circuit. The selection circuit is activated during the scanning time, which includes the first time period and the second time period. The first power supply circuit includes: A compensation circuit uses the data voltage to compensate the first power supply circuit; and The source follower circuit, wherein the compensation circuit uses the data voltage to compensate the source follower circuit. The compensation circuit includes a first terminal, a second terminal, and a control terminal. The first terminal and the control terminal of the compensation circuit are electrically connected to the selection circuit, and the second terminal of the compensation circuit is electrically connected to the first node. The source follower circuit includes a first terminal, a second terminal, and a control terminal. The first terminal of the source follower circuit receives a high reference voltage. The second terminal of the source follower circuit is electrically connected to the first node. The control terminal of the source follower circuit receives a control signal. The first node is electrically connected to the adjustable element.

2. The electronic device according to claim 1, characterized in that, The electronic device includes a substrate, the substrate including an active region and a peripheral region, the peripheral region being adjacent to the active region, wherein the first power supply circuit and the second power supply circuit are disposed within the active region.

3. The electronic device according to claim 1, characterized in that, The first time period and the second time period do not overlap.

4. The electronic device according to claim 1, characterized in that, During the first time period, the voltage of the first node is supplied to the adjustable element following the voltage at the control terminal of the source follower circuit.

5. The electronic device according to claim 4, characterized in that, The second power supply circuit includes another compensation circuit and another source follower circuit. The other compensation circuit includes a first terminal, a second terminal, and a control terminal. The first terminal and the control terminal of the other compensation circuit are electrically connected to the selection circuit. The second terminal of the other compensation circuit is electrically connected to a second node. The other source follower circuit includes a first terminal, a second terminal, and a control terminal. The first terminal of the other source follower circuit receives a high reference voltage. The second terminal of the other source follower circuit is electrically connected to the second node. The control terminal of the other source follower circuit receives another control signal. The second node is electrically connected to the adjustable element. During the second time period, the voltage of the second node is supplied to the adjustable element following the voltage of the control terminal of the other source follower circuit.

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