Three-dimensional nor memory array with very fine pitch: devices and methods

Abstract

A method of easily fabricating high aspect ratio three-dimensional memory structures for memory cells having feature sizes of 20 nm or less or having a large number of memory layers. The invention also provides improved isolation between adjacent memory cells along the same or opposite sides of an active strip. Improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip and by staggering memory cells on the opposite side of the active strip.

Description

[0001] This application is a divisional application of patent application No. 201880090142.8, with an international filing date of December 21, 2018, filed by Risen Energy Co., Ltd., entitled "Three-dimensional NOR memory array with very fine pitch: apparatus and method". Technical Field

[0002] This invention relates to a non-volatile NOR type memory string. In particular, this invention relates to an architecture for a three-dimensional memory array that allows the formation of minimum or sub-minimum pitch vertical conductors without requiring etching involving high aspect ratios. Background Technology

[0003] In high-density three-dimensional memory structures (such as those described in non-provisional or provisional applications), it is desirable to make memory cells as small as possible—thus increasing memory cell density—while maintaining high manufacturing yield. As the size of each memory cell shrinks, the aspect ratio of the feature (e.g., the depth of a trench divided by the gap size of its horizontal etching) increases. In the example of trenches, with the total thickness of the etched layers remaining constant, the trench aspect ratio increases as the feature size decreases. An alternative to increasing memory cell density is to provide more layers of memory cells in the vertical direction. This alternative necessarily increases the trench aspect ratio without changing the etching process. At the current level of technology, when the trench aspect ratio exceeds approximately 50, trench etching becomes unreliably difficult or excessively expensive. Summary of the Invention

[0004] This invention provides a method for manufacturing a memory structure having a small feature size (e.g., 20 nm or less, in the present art), or having eight or more layers of memory cells in the memory structure. The invention also provides improved isolation between adjacent memory cells on the same or opposite sides of an active stripe in the memory structure. Improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells on the same side of the active stripe and by interleaving the memory cells on opposite sides of the active stripe. (In this detailed specification, the term "active stripe" refers to a portion of the channel region and common source and drain regions of a horizontal, elongated memory structure forming a string of memory cells.)

[0005] According to another embodiment of the invention, improved isolation between adjacent memory cells on the same and opposite sides of the local word lines is stacked in a vertical NOR string memory structure having horizontal local word lines. Improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells on the same side of the local word lines and by interleaving the memory cells on opposite sides of the local word lines.

[0006] The invention will be better understood upon consideration of the following detailed description in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 The illustration shows the initial steps of forming the global interconnect conductors 10 of a three-dimensional NOR-type memory array 50 (not shown) after the supporting circuitry of the memory array (e.g., sense amplifiers, address decoders, input and output circuitry) has been formed on a semiconductor substrate 5 (not explicitly shown) according to an embodiment of the present invention.

[0008] Figure 2 The illustration shows an active stack formed in an intermediate step of manufacturing a three-dimensional NOR memory array 50; the active stack 100 consists of eight active stripes, including active strip 255, which is enlarged on the left for better clarity.

[0009] Figure 3 An embodiment of the present invention is shown in the charge trapping material 240 and P + Semiconductor layer 250 has been deposited and processed. Figure 2 The memory structure 50.

[0010] Figure 4 This shows the use of charge trapping materials 240 and P. + The semiconductor layer 250 is patterned and etched to form the first set of memory cells in the three-dimensional NOR memory array 50. Figure 3 The memory structure 50, P + Semiconductor layer 250 provides the first set of vertical local word line conductors 275.

[0011] Figure 5 This illustrates a conformal deposition of a second charge trapping layer 270 onto a substrate according to an embodiment of the invention. Figure 4 On the sidewalls of the trench 295 between adjacent local word lines 275 of the memory structure 50, a second layer P of the second set of local word line conductors 280 is then deposited to form the second layer. + After semiconductor materials Figure 4 The memory structure 50.

[0012] Figure 6 This illustration shows a second set of global word lines (labeled global word line 290) and corresponding vias (e.g., via 300) formed above a memory structure according to an embodiment of the present invention to connect to the local word line 280. Figure 5 The memory structure 50.

[0013] Figure 7A and Figure 7BA memory structure 50 according to a second embodiment of the present invention is shown, wherein a first set of local word lines and a second set of local word lines are formed successively, and the two sets of word lines are substantially the same in material and dimension.

[0014] To facilitate cross-referencing between figures, the same elements are assigned the same reference numerals. Detailed Implementation

[0015] This invention improves memory cell density and their manufacturing processes in memory structures (e.g., three-dimensional NOR-type memory arrays), as described in the non-provisional and provisional applications incorporated herein by reference. This invention improves, for example, the three-dimensional NOR-type memory array and its manufacturing process described in non-provisional application III with reference to the accompanying drawings.

[0016] Figure 1 The illustration shows the initial steps of forming a three-dimensional NOR-type memory array 50 after the supporting circuitry of the memory array (e.g., sense amplifiers, address decoders, input and output circuitry) has been formed in a semiconductor substrate 5 (not explicitly shown) according to an embodiment of the invention. Figure 1 As shown, an interlayer dielectric (ILD) layer 25 is formed on a semiconductor substrate 5. A set of conductors (e.g., conductors 10) electrically isolated from each other are then formed on the ILD layer 25. Since conductors 10 are intended to connect local word lines of memory cells in the forming three-dimensional NOR-type memory array 50, conductors 10 are referred to herein as “global word lines” 10. (Of course, where appropriate, conductors 10 may also generally serve as interconnect conductors of the memory structure 50 in addition to providing connections to local word lines of memory cells). Each global word line 10 is connected to appropriate circuitry in the semiconductor substrate 5 via a via or buried contact, such that appropriate voltages for memory cell operation (e.g., programming, erasing, programming suppression, reading) can be supplied from the circuitry in the semiconductor substrate 5. Global word lines 10 can be fabricated using any suitable technique, for example, using conductive materials (such as one or more layers of metal (e.g., Ti / TiN / W) or P). + Polycrystalline silicon can be processed using a reduction metallurgical process or a damascene metallurgical process.

[0017] Next, a next ILD layer 233 (not shown) is formed to cover the global word line 10. Then, vias 20 are formed, for example, in a conventional manner (e.g., by etching and conductor deposition in ILD layer 233). Vias 20 are provided to connect local word lines in the forming 3-D NOR memory array 50 to the global word line 10. Vias 20 may be made of the same conductive material as the global word line 10 (i.e., one or more layers of metal (e.g., Ti / TiN / W) or P). +Polycrystalline silicon is formed. Any excess conductive material can be removed from the top surface of ILD layer 233 by any suitable method (e.g., CMP), leaving only conductive material in the etched vias.

[0018] Figure 2 This illustrates an intermediate step in forming a 3-D NOR memory array 50 after several active stacks (e.g., active stack 100) have already been formed. This is achieved by etching deep trenches 235 into the continuously deposited... Figure 1 An active stack is formed in layers of semiconductor and insulating material above the ILD layer 233, using a fabrication process discussed in Non-Provisional Application I in conjunction with its accompanying drawings and description. Figure 2 In the image, the active stack is shown by a representative active stack 100, with a representative active strip 255 in the active stack 100 enlarged on the left for better clarity.

[0019] like Figure 2 As shown, the active stripe 255 contains N + Semiconductor layers 130 and 140 (e.g., silicon or polysilicon) are provided adjacent to metal layers 110 and 120, respectively, and the metal layers 110 and 120 are configured to reduce N. + Resistors in semiconductor layers 130 and 140. Dielectric overlay layers 150, 160, 170, and 180 are provided to electrically insulate metal layers 110 and 120, thereby preventing any accidental short circuits. + Semiconductor layers 130 and 140, together with their corresponding metal layers 110 and 120, form a common source and common drain layer in the string of forming memory cells along the active strip 255. In N + Channel semiconductor layers 190 and 200 are formed between semiconductor layers 130 and 140 on opposite sides of the active strip 255. In this embodiment, the channel semiconductor layers 190 and 200 are formed by filling the cavity obtained by partially removing the sacrificial layer (“SAC1”). In fact, the remaining SAC1 layer... Figure 2 The diagram shows SAC1 layer 210, located between channel semiconductor layers 190 and 200. (In an alternative embodiment, SAC1 layer 210 may subsequently be completely removed, resulting in an air or vacuum void in the space now shown by SAC1 layer 210; alternatively, channel layers 190 and 200 may be allowed to merge together to fill the space previously occupied by the SAC1 layer.)

[0020] Adjacent active strips in the active stack 100 are insulated from each other by a dielectric layer, such as Figure 2The middle is represented by a dielectric layer 220. Furthermore, a hard mask layer 230 is provided before etching the trenches 235 between the active stacks. The hard mask layer 230 stabilizes the subsequent active stacks formed by etching. Using such a hard mask layer 230 and also incorporating the use of struts... Figure 2 (Not shown in the image) to stabilize the high aspect ratio structure is disclosed in non-provisional application III. In this example, each active strip can have a width of 15 nm to 50 nm (along a third direction, such as...). Figure 2 As shown in the diagram, each hard mask 230 can support the formation of eight or more active stripes stacked vertically in each active stack. As disclosed in non-provisional application V, NOR memory arrays can be constructed as “segmented stacks” (i.e., stacks of eight active stripes formed at a time). Using a segmented stack approach, the manufacturing process steps can be repeated many times to form memory arrays with 16, 24, 32, 48, 64… active stripes.

[0021] In one embodiment, N + Semiconductor layers 130 and 140, metal layers 110 and 120, channel semiconductor layers 190 and 200, and dielectric layer 220 can each be approximately 180 nm thick, allowing the eight active stripes in the active stack 100, together with the 50-nm hard mask layer 230, to reach a total height of 1490 nm or higher. In the case of a 45 nm wide local word line 275 and a 45 nm gap or trench between adjacent local word lines, the aspect ratio of the etched trench is 33:1. If the active stack 100 has 12 active stripes, the trench aspect ratio reaches 49:1.

[0022] Subsequently, a charge trapping layer 240 is conformally provided over the sidewalls and bottom of each trench between adjacent active stacks (see, for example...). Figure 3 (as shown in the illustration), which can be a three-layer structure of SiO2-SiN-SiO2 (i.e., oxide-nitride-oxide or "ONO" layer). The charge trapping function of the ONO layer is known to those skilled in the art.

[0023] The charge trapping layer 240 can be composed of, for example, SiO2 (or a dielectric interlayer with a bandgap design) less than 3 nm to 6 nm, 6 nm of SiN, and 6 nm of SiO2 (or a dielectric film with a high dielectric constant, such as an Al2O3 film). After depositing the charge trapping layer 240, a 3-nm thick protective polysilicon layer can also be conformally deposited. A portion of the charge trapping layer 240 and the protective polysilicon layer at the bottom of each trench can then be removed to expose the via 20, thereby allowing subsequent connections between the global word line 10 and the local word lines to be formed next. Although the aspect ratio of this etching is greater than 100, only approximately 20 nm thick layers of the charge trapping layer 240 and the protective polysilicon layer 250 at the bottom of each trench are removed. After this etching, P is deposited. + A semiconductor layer 250 (e.g., silicon or polysilicon) is used to fill the remaining exposed trench 235. Figure 3 An embodiment of the present invention is shown in the charge trapping material 240 and P + Semiconductor layer 250 has been deposited and processed. Figure 2 The memory structure is 50. P + The semiconductor layer 250 can be replaced by a metal conductor (e.g., titanium nitride, titanium, tantalum nitride, tantalum, tungsten nitride, tungsten, or another refractive metal having a suitable work function relative to SiO2).

[0024] The ONO three-layer structure (shown as an example) Figure 4 The charge trapping layer 240, composed of tunneling oxide 242, storage nitride 244, and blocking oxide 246, can be approximately 15 nm thick (measured along a third direction). The charge trapping layer 240 and P... + Semiconductor layer 250 is then patterned and etched (including removing any residual ONO layers in the space not protected by local word lines 275) to form the first set of memory cells in a three-dimensional NOR-type memory array. After etching, P... + Semiconductor layer 275 provides the first set of vertical local word lines, such as Figure 4 As shown. The resulting separation between adjacent local word lines 275 of the first group ( Figure 4 The central indicator (vertical shaft 295) allows for a second set of vertical local word lines 280 and their associated charge trapping layers 270. Figure 5 ) is formed therein. In the current example, the width of each shaft (along the second direction) can be approximately 75 nm (i.e., the 45-nm width of the local word line plus the 15 nm thickness of the ONO three-layer 270 on each side of the local word line 280). The aspect ratio of the etched 75 nm wide trench is approximately 1490 / 75 = 20:1, which is different from the previous one. Figure 4 and Figure 5The 33:1 ratio is significantly looser than in the case of the structure. However, the local word line pitch (i.e., line width plus line-to-line spacing) shrinks from the standard pitch of (45+45) = 90 nm to (45+45+(2*l5)) / 2 = 60 nm, which is one-third the reduction of the standard pitch. Although the local word line 275 along the opposite side of each active stack body is in Figure 4 and Figure 5 The diagram shows alignment in the horizontal direction transverse to the length of the active stripe (i.e., along the third direction), but they can also be provided in an interleaved manner, as taught in non-temporary application IV. In an interleaved configuration, adjacent memory cells on opposite sides of the active stripe are positioned more separately to reduce parasitic programming interference.

[0025] After etching vertical shafts 295 between adjacent local word lines in the first set of local word lines, charge trapping material (e.g., Figure 5 A charge-trapping layer 270, which may be an ONO three-layer layer (including layers labeled 272, 274, and 276), is a second deposition conformally deposited onto the sidewall of each of the shafts 295 adjacent to each of the first set of local letter lines 275. After the formation of the charge-trapping layer 270, P is deposited. + The second layer of semiconductor material is used to form the second set of local word lines (labeled as...). Figure 5 (Local word line 280 in the memory). A portion of the charge trapping layer 270 and the local word line 280 are then removed from the top of the memory structure, thus completing the second set of memory cells. The resulting structure is... Figure 5 The magnified area A1 shows the word lines alternating from the first group (i.e., word line 275) and the second group (i.e., word line 280), each separated from the thickness of the ONO charge trapping layer 270.

[0026] Deposit the second P before forming the local letter line 280. + Prior to the semiconductor layer, the portion of the charge trapping layer 270 at the bottom of the trench can be removed by anisotropic etching to expose the via 20 beneath the memory structure, thereby connecting the word line 280 to the global word line 10 (see [link]). Figure 1 Global word lines 10). However, as discussed below, if the second set of global word lines (e.g., Figure 6 A global word line 290 is provided above the memory structure, and the portion of the charge trapping layer 270 at the bottom of the trench does not need to be removed. Higher-density memory structures can be achieved by providing global word lines on top of and below the memory structure 50. Figure 6As shown, the global word line 290 from the top can contact the local word line on one side of the active strip using vias 300, while the global word line below the memory structure 50 can contact the local word line on the opposite side of the active strip using vias 20. Alternatively, both the first group (i.e., local word line 275) and the second group (i.e., local word line 280) can be contacted from the top (i.e., conductor 290) by the global word lines, or both can be contacted from the bottom (i.e., conductor 10) through appropriately etched vias. Of course, where appropriate, in addition to providing a connection to the local word line 280, the global word line 290 can also generally serve as an interconnect conductor for the memory structure 50.

[0027] Depositing charge trapping layers 240 and 270 in two successive depositions has important positive effects. The first and second sets of charge trapping layers are separate ONO three-layer structures. Figure 5 The discontinuity between the three ONO layers (i.e., layers 242, 244, and 246) associated with the first set of local word lines and the three ONO layers (i.e., layers 272, 274, and 276) associated with the second set of local word lines is shown. This discontinuity provides a strong dielectric barrier film (such as that provided by the blocking oxide layer 272), thereby substantially eliminating lateral conduction of trapped charge between undesirable adjacent memory cells (i.e., trapped charge between the silicon nitride layer 244 associated with the first set of local word lines and the silicon nitride layer 274 associated with the second set of local word lines).

[0028] Although charge trapping layers 240 and 270 are typically deposited to replicate their electrical properties as closely as possible, in some embodiments of the invention, charge trapping layers 240 and 270 may be deposited with completely different electrical properties. For example, charge trapping layer 240 may be optimized for maximum long-term data retention, while charge trapping layer 270 may be optimized separately to provide faster programming / erasing / read operations. In this arrangement, the memory cells associated with charge trapping layer 270 may be used as cache memories with higher write / erasing cycle endurance characteristics (at the expense of shorter data retention times). In some embodiments of the invention, the first and second groups of memory cells do not need to each comprise half of the total number of memory cells in the memory structure.

[0029] Figure 7A and Figure 7B The figure illustrates a second embodiment of the invention. In this second embodiment, it is not the local word lines 275 and the charge trapping layer 240 associated with them (see, for example...). Figure 4 Instead, local word lines 280 and their associated charge trapping layers 270 are used, such that the first and second sets of local word lines have substantially the same structure, such as the structure of the second set of local word lines described above.

[0030] According to this second embodiment, after forming the active stack (e.g., active stack 100), as Figure 2 As shown, trenches 235 are filled by depositing a sacrificial material (e.g., a fast-etching dielectric material, such as porous SiO2). This sacrificial material is then patterned and partially etched to form islands 400 of the sacrificial material, such as... Figure 7A (As indicated by reference numeral 400 in the accompanying illustration). Each island and its adjacent islands are separated from each other by shafts (in... Figure 7A The islands 400 are shown as being filled with a charge trapping layer 270 and local word lines 280, as discussed below. Each of the islands 400 has a predetermined length along the second direction, substantially the same as the separation between adjacent islands in each of the trenches 235. This separation is sufficient to accommodate the width of the local word line (e.g., Figure 5 The width of one of the local word lines 280) plus a charge trapping layer (e.g., Figure 5 The charge trapping layer (270) is twice the thickness of the charge trapping layer to accommodate the charge trapping layers on both sides of the local word line along the second direction.

[0031] Next, a charge-trapping layer is conformally deposited on the sidewalls and bottom of the shafts formed during the formation of island 400, leaving voids within each shaft that can then be filled with a conductive material. This can be substantially made of... Figure 5 The charge trapping layer 270 is provided by the same material as the charge trapping layer (e.g., an oxide-nitride-oxide trilayer having separate composition layers 272, 274, and 276). For simplicity of reference, this charge trapping layer is... Figure 7A The middle part is also marked as 270. Similarly, the conductive material filling the voids in each shaft can be formed by... Figure 5 The same conductive material is provided for the local word lines 280. Again, for simplicity of reference, this conductive material forms a set of conductive pillars around which each free charge trapping layer 270 is surrounded; the conductive pillars are also referred to as local word lines 280. The conductive material may be selected from the group consisting of: titanium, titanium nitride, tantalum nitride, tantalum, tungsten nitride, tungsten, cobalt, heavily doped P + or N + Polycrystalline silicon, or another refractive metal. The conductive material is then removed from the top surface of the active stack by CMP or controlled etching.

[0032] Figure 7AThe conductive pillars 280 and the charge-trapping layer 270 surrounding them are then masked to protect them from the subsequent etching step, which removes the islands 400, thereby creating a second set of shafts. (The conductive pillars 280 and the charge-trapping layer 270 surrounding them are referred to below as the "first set of local word lines" and the "first charge-trapping layer," respectively). The second charge-trapping layer is then conformally deposited over the sidewalls and bottom of each of the second set of shafts, leaving a central void that is filled with pillars of conductive material, thereby forming the second set of local word lines and the second charge-trapping layer, respectively. (The second set of local word lines and the second charge-trapping layer surrounding them may be provided with the same material as the first set of local word lines and the first charge-trapping layer, respectively). The substantially identical word lines are interleaved between the local word lines from the first set and the local word lines from the second set, such as... Figure 7B As shown. Connect the first and second groups of local word lines to global word line 10 (i.e., a group of global word lines below the memory structure; see example). Figure 1 ) and global word lines 290 (i.e., a set of global word lines above the memory structure; see, for example) Figure 6 The remaining process steps follow the corresponding steps of the first embodiment described above.

[0033] First embodiment ( Figure 5 ) and the second embodiment ( Figure 7B The first embodiment has the same, but more advantageous, etching aspect ratio as the prior art. Both embodiments have advantageous physical separation between adjacent local word lines. Although these per-cell area metrics of both embodiments are smaller than those of the prior art, the per-cell area metric of the second embodiment is greater than that of the first embodiment because the separation between adjacent local word lines in the second embodiment includes two back-to-back charge trapping layers (e.g., 2 x 15 nm in one example), while the corresponding separation in the first embodiment includes only a single such charge trapping layer (i.e., 15 nm in the same example). However, the second embodiment has some compensating advantages relative to the first embodiment. First, the adjacent local word lines and their associated charge trapping layers in the second embodiment are substantially identical in construction, so the physical properties of adjacent local word lines can be better traced to each other. Second, the first embodiment requires etching the conductive material 275 all the way down the depth of its trench, which can be challenging when the conductive material 275 contains a refractive metal. The first embodiment also requires etching net charge trapping layers 242, 244, and 246 along the sidewalls of the trench in the area where the conductive material 275 has been removed. In the second embodiment, the first and second groups of word lines are not required to undergo these etching steps because, in the second embodiment, the width of the pillars in each group of word lines is predetermined by the length of the island and the thickness of the charge trapping layer.

[0034] Although the two-step local word line formation of this invention requires more process steps compared to the processes discussed in the non-provisional and provisional applications, this invention provides a smaller silicon area memory array that, from a cost perspective, not only compensates for the additional required process steps.

[0035] This invention allows for the formation of multilayer active stacks, a few micrometers high, requiring low-resistivity conductors to connect global word lines at the top of the memory cells and the logic circuitry in the substrate beneath the active stack. Because the first or second set of local word lines of this invention travels in a vertical direction perpendicular to the flat surface of the substrate, these local word lines can be adapted to more generally serve as high interconnects between one or more conductive layers traveling above the active stack and one or more conductive layers traveling between the bottom of the active stack and the substrate.

[0036] High interconnects can be formed within the memory array, in a dummy active stack, or in a high insulating layer (e.g., Figure 7A In the trenches between the active stripes within the sacrificial dielectric material 400, a high insulating layer is formed adjacent to the active stack and given substantially the same height as the active stack. The dummy active stack itself does not have an electrical function, but only acts as an insulating dielectric to support the high interconnects, and is patterned as a matrix of closely spaced rows and columns of via openings (i.e., deep holes etched through to the bottom of the dummy active stack). In a second embodiment, the via openings can be etched, for example, simultaneously with the etching of the second set of trenches, so that a first charge trapping layer (e.g., an ONO triple layer) can be conformally deposited as a wall insulator on the sidewalls of the via openings. The first charge trapping layer deposited at the bottom of the via, together with the underlying insulating dielectric layer, can be masked and removed by anisotropic etching to expose any desired contact vias below for subsequent electrical connections.

[0037] The vias can then be filled with a conductive material (e.g., titanium, titanium nitride, tantalum nitride, tantalum, tungsten nitride, tungsten, cobalt, or another metallic conductor, such as a refractive metal or silicide). Excess conductive material on the top surface of the active stack can be removed by CMP or by controlled etching (when a damascus-like process is used to isolate individual conductors). An isolation dielectric layer is then deposited on the top surface, and vias through this isolation dielectric layer can be patterned and etched to expose the conductive material in the filled vias below where a top-to-bottom conductor path is required.

[0038] As a further improvement, the charge-trapping layer surrounding each high interconnect can be used to mechanically support and protect the conductive material of the high interconnect, allowing the sacrificial dielectric material between the interconnects to be removed to create an air gap isolation, thereby significantly reducing parasitic capacitive coupling between adjacent high interconnects. When an etchant with different etching selectivity between the sacrificial dielectric material and the charge-trapping layer is available, it is possible to remove the sacrificial dielectric material without etching the charge-trapping layer. For example, when the sacrificial dielectric material is porous silicon oxide and the charge-trapping layer contains silicon nitride, HF can be a suitable chemical etchant because it removes the sacrificial oxide, leaving substantially intact silicon nitride. In this way, even when the high interconnects are tilted toward adjacent high interconnects, the high interconnects are electrically insulated from each other by the respective charge-trapping layers they act as coverings.

[0039] Providing contiguous groups of side-by-side local word lines (and thus, contiguous groups of thin-film storage transistors) can also be applied to three-dimensional vertical thin-film transistor memory strings, as discussed with respect to non-provisional application II. For example, the figures of non-provisional application II each disclose a vertical NOR string of thin-film storage transistors (e.g., having N as a common local bit line). + The vertical NOR string of polysilicon 654, the P-polysilicon layer 656 serving as the left and right common channel, and the N-type ... + (Polycrystalline silicon 655). Such vertical NOR strings can be formed in a sequential operation according to the invention. First, each staggered row of the vertical NOR string can be formed in a first set of trenches (e.g., the trench between adjacent word lines 623p-R and 623p-L). Then, other alternating rows of the vertical NOR string are formed in the gaps between the rows already formed in the vertical NOR string. The charge trapping layers associated with the first and second sets of vertical NOR strings do not need to be the same. In this way, different sets of vertical NOR strings can have completely different storage characteristics.

[0040] The above detailed description is provided to illustrate specific embodiments of the invention and is not intended to be limiting. Various changes and modifications are possible within the scope of this invention. The invention is set forth in the appended claims.

Claims

1. A NOR memory string associated with a first conductor and a second conductor, comprising a first storage transistor and a second storage transistor sharing a common drain region and a common source region, the first conductor serving as the gate electrode of the first storage transistor, and the second conductor serving as the gate electrode of the second storage transistor, each storage transistor having a channel region and a data storage layer provided between its gate electrode and its channel region, wherein any of the following conditions apply: (i) The data storage layer of the first storage transistor surrounds its gate electrode and the data storage layer of the second storage transistor does not surround its gate electrode, or (ii) The data storage layer of the first storage transistor surrounds its gate electrode and the data storage layer of the second storage transistor does not surround its gate electrode, and the first conductor and the second conductor have different compositions, or (iii) The data storage layer of the first storage transistor surrounds its gate electrode and the data storage layer of the second storage transistor does not surround its gate electrode, and the data storage layers of the first storage transistor and the second storage transistor have different compositions, or (iv) The first conductor and the second conductor have different compositions, and the data storage layer of the first storage transistor and the data storage layer of the second storage transistor have different compositions, and the data storage layer of the first storage transistor surrounds its gate electrode while the data storage layer of the second storage transistor does not surround its gate electrode.

2. The NOR memory string of claim 1, wherein the second conductor is adjacent to a portion of the data storage layer of the first storage transistor.

3. The NOR memory string of claim 1, wherein the first conductor comprises the group consisting of: titanium, titanium nitride, tantalum nitride, tantalum, tungsten nitride, tungsten, cobalt, heavily doped p-type materials. + Polycrystalline silicon, heavily doped n + Polycrystalline silicon, and silicides.

4. The NOR memory string as claimed in claim 1, wherein the data storage layer of the first storage transistor comprises an oxide-nitride-oxide three-layer structure.

5. The NOR memory string of claim 1, wherein the NOR memory string is formed of a material layer of an active strip, wherein the first storage transistor and the second storage transistor are provided on opposite sides of the active strip.

6. The NOR memory string of claim 1, wherein the NOR memory string is one of a plurality of NOR memory strings formed in a 3D semiconductor structure, wherein the semiconductor structure further includes first and second global interconnect conductors in an insulating layer above the NOR memory string, wherein the first conductor and the second conductor are electrically connected to the first and second global interconnect conductors, respectively.

7. The NOR memory string of claim 1, wherein the NOR memory string is one of a plurality of NOR memory strings formed in a 3D semiconductor structure, wherein the semiconductor structure further includes a first global interconnect conductor and a second global interconnect conductor, the first global interconnect conductor being formed in a first insulating layer above the NOR memory string, and the second global interconnect conductor being formed between the NOR memory string and a flat surface of the semiconductor substrate, wherein the first conductor is electrically connected to the first global interconnect conductor and the second conductor is electrically connected to the second global interconnect conductor.

8. The NOR memory string of claim 7, wherein the semiconductor structure further comprises a third global interconnect conductor formed between a flat surface of the NOR memory string and the semiconductor substrate, and wherein the third global interconnect conductor is electrically connected to the first conductor.

9. The NOR memory string of claim 7, wherein the semiconductor substrate includes circuitry for supporting memory operation, and wherein the second global interconnect conductor is electrically connected to the circuitry.

10. The NOR memory string of claim 1, wherein the first conductor and the second conductor are electrically isolated from each other through the data storage layer of the first storage transistor.

11. A process for forming a memory structure, comprising: First and second multilayer semiconductor structures are formed above a flat surface of a semiconductor substrate, the first and second multilayer semiconductor structures being separated from each other by trenches having a depth in a first direction substantially perpendicular to the flat surface and a predetermined width in a second direction substantially parallel to the flat surface. A first set of conductors extending along the first direction is formed in the trench, each conductor comprising a first conductive material and each conductor being isolated from each adjacent multilayer semiconductor structure by a first data storage material, wherein the conductors in each trench are separated from each other by a predetermined distance; as well as A second set of conductors is formed extending along the first direction, each conductor in the second set of conductors being provided between two adjacent conductors of the first set of conductors, each conductor in the second set of conductors comprising a second conductive material and each conductor in the second set of conductors being isolated from its adjacent multilayer semiconductor structure by a second data storage material; Each of the first group of conductors or the second group of conductors, and a portion of the first data storage material or the second data storage material between the conductor and one of the multilayer semiconductor structures, forms a gate electrode and a storage layer for a thin-film storage transistor; and In this multilayer semiconductor structure, for a plurality of storage transistors within one of the multilayer semiconductor structures, the multilayer semiconductor structure provides a common source region and a common drain region; and The plurality of storage transistors includes a first storage transistor and a second storage transistor sharing the common drain region and the common source region, wherein a conductor in the first set of conductors serves as the gate electrode of the first storage transistor, and a conductor in the second set of conductors serves as the gate electrode of the second storage transistor; and The data storage layer of the second storage transistor surrounds its gate electrode, while the data storage layer of the first storage transistor does not surround its gate electrode.

12. The process of claim 11, wherein forming the first set of conductors comprises: A layer of the first data storage material is conformally formed on the sidewall of the trench, leaving a space in the trench surrounded by the layer of the data storage material; The space is filled with a first conductive material; The first conductive material in the space is patterned and etched to form the first set of conductors, such that adjacent conductors in the first set of conductors are separated along the second direction by the predetermined distance.

13. The process of claim 12, wherein forming the second set of conductors comprises: Remove the layer of the first data storage material within the predetermined distance that separates each adjacent pair of the first group of conductors; A layer of the second data storage material is conformally formed on the exposed sidewalls of the first group of conductors, leaving a space between adjacent conductors in the first group of conductors surrounded by the layer of the second data storage material; as well as The space surrounded by the layer of the second data storage material is filled with the second conductive material to form the second set of conductors.

14. The process of claim 11, wherein at least one of the first and second conductive materials is selected from titanium, titanium nitride, tantalum nitride, tantalum, tungsten nitride, tungsten, cobalt, and heavily doped p-type materials. + Polycrystalline silicon, heavily doped n + Polycrystalline silicon, and silicides.

15. The process of claim 11, wherein at least one of the first and second data storage layers comprises an oxide-nitride-oxide three-layer structure.

16. The process of claim 11, wherein the conductors formed along lines in a third direction on opposite sides of each multilayer semiconductor structure belong to different conductors in the first group of conductors and the second group of conductors.

17. The process of claim 11, further comprising a first system for forming a global interconnect conductor in an insulating layer between the memory structure and the flat surface of the semiconductor substrate, and wherein the process further comprises removing a portion of the insulating layer and removing the first data storage layer, or the second data storage layer, or both adjacent to the insulating layer, to expose a corresponding portion of the global interconnect conductor to allow connection to a first set of conductors, a second set of conductors, or both.

18. The process of claim 17, further comprising forming a second system of global interconnect conductors over the memory structure, such that the connection allows the first system of the global interconnect conductors to be electrically interconnected to the second system of the global interconnect conductors.

19. The process of claim 11, wherein each of the first set of conductors has a first predetermined width along the second direction, each of the second set of conductors has a second predetermined width along the second direction, and the second data storage layer has a third predetermined width along the second direction, wherein the first predetermined width is less than twice the third predetermined width plus the second predetermined width.

20. The process of claim 11, wherein each conductor in the first group of conductors is electrically insulated from at least one conductor in the second group of conductors by a second data storage layer.

21. The process of claim 11, further comprising providing a hard mask material over the multilayer semiconductor structure for protection during any etching steps performed during the formation of the first set of conductors or the formation of the second set of conductors.

22. A memory structure, comprising: First and second multilayer semiconductor structures located above a flat surface of a semiconductor substrate are separated from each other by trenches having a depth in a first direction substantially perpendicular to the flat surface and a predetermined width in a second direction substantially parallel to the flat surface. A first set of conductors in the trench extending along the first direction, each conductor comprising a first conductive material and each conductor being isolated from each adjacent multilayer semiconductor structure by a first data storage material, wherein the conductors in each trench are separated from each other by a predetermined distance; as well as A second set of conductors extending along the first direction, each conductor in the second set of conductors being provided between two adjacent conductors in the first set of conductors, each conductor in the second set of conductors comprising a second conductive material and each conductor in the second set of conductors being isolated from its adjacent multilayer semiconductor structure by a second data storage material; Each of the first group of conductors or the second group of conductors, and a portion of the first data storage material or the second data storage material between the conductor and one of the multilayer semiconductor structures, forms a gate electrode and a storage layer for a thin-film storage transistor; and Among them, for a plurality of storage transistors in one of the multilayer semiconductor structures, the multilayer semiconductor structure provides a common source region and a common drain region; and The plurality of storage transistors include a first storage transistor and a second storage transistor that share the common drain region and the common source region, wherein each conductor in the first set of conductors serves as the gate electrode of the first storage transistor, and each conductor in the second set of conductors serves as the gate electrode of the second storage transistor.

23. The memory structure of claim 22, wherein each conductor in the first group of conductors is adjacent to a portion of the layer of the second data storage material, the portion being adjacent to a conductor in the second group of conductors.

24. The memory structure of claim 23, wherein the conductors in the second set of conductors are surrounded by a layer of the second data storage material.

25. The memory structure of claim 23, wherein each of the first set of conductors comprises a conductor surrounded by a layer of the first data storage material.

26. The memory structure of claim 25, wherein each of the second set of conductors comprises a conductor surrounded by a layer of the second data storage material.

27. The memory structure of claim 22, wherein at least one of the first and second conductive materials is selected from titanium, titanium nitride, tantalum nitride, tantalum, tungsten nitride, tungsten, cobalt, and heavily doped p-type materials. + Polycrystalline silicon, heavily doped n + Polycrystalline silicon, and silicides.

28. The memory structure of claim 22, wherein at least one of the first and second data storage layers comprises an oxide-nitride-oxide three-layer structure.

29. The memory structure of claim 22, wherein the conductors formed along lines on opposite sides of each active stack belong to different conductors in the first group of conductors and the second group of conductors, the lines extending in a third direction.

30. The memory structure of claim 22, further comprising a first system of global interconnect conductors in an insulating layer between the memory structure and a flat surface of the semiconductor substrate, wherein a portion of the insulating layer is removed and a first data storage layer, or a second data storage layer, or both, is removed adjacent to the insulating layer to expose corresponding portions of the global interconnect conductors to allow connection to the first set of conductors, the second set of conductors, or both.

31. The memory structure of claim 30, further comprising a second system of global interconnect conductors above the memory structure, such that the connection allows the first system of the global interconnect conductors to be electrically interconnected to the second system of the global interconnect conductors.

32. The memory structure of claim 22, wherein each conductor in the first group of conductors is electrically insulated from at least one conductor in the second group of conductors by a second data storage layer.

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