用于具有部分漏极侧选择栅极的存储器设备的经改善的编程技术
By electrically floating the unselected portion of the SGD transistors in the NAND memory device and utilizing the capacitive coupling effect to reduce the voltage difference, the interference effect of adjacent SGDs caused by shallow etched feature cutting is solved, improving device performance and reliability and saving resources.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SANDISK TECH
- Filing Date
- 2022-05-25
- Publication Date
- 2026-07-17
AI Technical Summary
In NAND memory devices, when shallow etched features cut through memory holes, the exposure of some drain-side gate select (SGD) transistors causes adjacent SGDs to be unintentionally turned on, resulting in current leakage and damage to programming sensing operations. Existing technologies have difficulty effectively solving the adjacent SGD interference (NSI) problem.
By implementing electrical floating in the unselected portion of the SGD transistors and utilizing the capacitive coupling effect to reduce the voltage difference between adjacent transistors or memory cells, the use of negative voltage pumps/sources is avoided, thus preventing the NSI effect.
It effectively prevents the selected SGD from being accidentally turned on, reduces current leakage, improves the performance and reliability of memory devices, and saves resource usage.
Smart Images
Figure CN115910164B_ABST