Memory device and method of operating the same

Abstract

The present disclosure relates to memory devices and methods of operating the same. A memory device includes a memory block including memory cells to which a program voltage is applied through a word line. The memory device also includes a peripheral circuit configured to perform, for each of a plurality of program levels, a verify operation that compares a threshold voltage of the memory cells to a verify voltage. The memory device further includes a control logic circuit configured to control the peripheral circuit to apply a plurality of blind voltages related to a target level among the plurality of program levels to the word line, and to determine, using a number of fail bits for each of the plurality of blind voltages, a start time point of a verify operation corresponding to a next program level of the target level.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0106153, filed on August 11, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to electronic devices, and more specifically, to memory devices and methods of operating such memory devices. Background Technology

[0004] A storage device is a device that stores data under the control of a host device, such as a computer or smartphone. A storage device can include a memory device for storing data and a memory controller for controlling the memory device. Memory devices can be classified as volatile memory devices or non-volatile memory devices.

[0005] Volatile memory devices are devices that store data only while power is supplied and lose the stored data when power is cut off. Volatile memory devices can include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0006] Non-volatile memory devices are devices that do not lose data even when power is cut off. Non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, etc. Summary of the Invention

[0007] According to one embodiment of this disclosure, a memory device may include a memory block comprising memory cells to which a programming voltage is applied via word lines. The memory device may also include peripheral circuitry configured to perform a verification operation for each of a plurality of programming levels, comparing a threshold voltage of a memory cell with a verification voltage. The memory device may further include control logic configured to control the peripheral circuitry to apply a plurality of blind voltages associated with a target level among the plurality of programming levels to the word lines, and to determine the start time of the verification operation corresponding to the next programming level of the target level using the number of failure bits for each of the plurality of blind voltages.

[0008] According to one embodiment of this disclosure, a memory device may include a memory block comprising memory cells to which a programming voltage is applied via word lines. The memory device may also include peripheral circuitry configured to perform a verification operation for each of a plurality of programming levels, comparing a threshold voltage of a memory cell with a verification voltage. The memory device may further include control logic configured to control the peripheral circuitry to apply a plurality of blind voltages associated with a first level of the plurality of programming levels to the word lines in voltage magnitude order, and to determine the start time of a verification operation corresponding to a second level, which is the next programming level after the first level, using the number of failure bits for each of the plurality of blind voltages.

[0009] According to one embodiment of this disclosure, a method of operating a memory device may include: applying a programming voltage to a memory cell via a word line, and performing a verification operation for each of a plurality of programming levels, comparing a threshold voltage of the memory cell with a verification voltage. Performing the verification operation may include: applying a plurality of blind voltages associated with a target level among the plurality of programming levels to the word line, and using the number of failure bits for each of the plurality of blind voltages to determine a start time point for the verification operation corresponding to the next programming level of the target level.

[0010] According to one embodiment of this disclosure, a method of operating a memory device may include: applying a programming voltage to a memory cell via a word line, and performing a verification operation for each of a plurality of programming levels, comparing a threshold voltage of the memory cell with a verification voltage. Performing the verification operation may include: applying a plurality of blind voltages associated with a first level of the plurality of programming levels to the word line in voltage magnitude order, and determining a start time point for a verification operation corresponding to a second level, which is the next programming level after the first level, using the number of failure bits for each of the plurality of blind voltages. Attached Figure Description

[0011] Figure 1 This is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0012] Figure 2 It is a diagram. Figure 1 A diagram of a memory device.

[0013] Figure 3 It is a diagram. Figure 2 A diagram showing the configuration of any memory block within the memory blocks.

[0014] Figure 4It is a diagram illustrating the multiple programming cycles included in the programming operation, as well as the programming voltage application operation and verification operation included in each programming cycle.

[0015] Figure 5A and Figure 5B This is a diagram illustrating the threshold voltage distribution of a single-stage unit.

[0016] Figure 6A and Figure 6B This is a diagram illustrating the threshold voltage distribution of a multi-level unit.

[0017] Figure 7A and Figure 7B This is a diagram illustrating the threshold voltage distribution of the three-level unit.

[0018] Figure 8A and Figure 8B This is a diagram illustrating the threshold voltage distribution of a four-level unit.

[0019] Figure 9 This is a diagram illustrating the start and end times of a verification operation in multiple programming loops according to an embodiment of the present disclosure.

[0020] Figure 10 This is a block diagram illustrating a method for performing a verification operation according to an embodiment of the present disclosure.

[0021] Figure 11 This is a diagram illustrating a method for determining a target voltage from a plurality of blind voltages according to an embodiment of the present disclosure.

[0022] Figure 12 This is a flowchart illustrating a method for performing a verification operation according to an embodiment of the present disclosure.

[0023] Figure 13 This is a flowchart illustrating a method for performing a verification operation according to another embodiment of the present disclosure.

[0024] Figure 14 This is a diagram illustrating a data processing system including a solid-state drive according to an embodiment of the present disclosure.

[0025] Figure 15 It is a diagram. Figure 14 A diagram showing the configuration of the controller.

[0026] Figure 16 This is a diagram illustrating a data processing system including a data storage device according to an embodiment of the present disclosure.

[0027] Figure 17 This is a diagram illustrating a data processing system including a data storage device according to an embodiment of the present disclosure.

[0028] Figure 18This is a diagram illustrating a network system including a data storage device according to an embodiment of the present disclosure. Detailed Implementation

[0029] The specific structural or functional descriptions of the presented embodiments are disclosed in accordance with the concepts of this disclosure. However, these embodiments are not exhaustive and should not be construed as limiting this specification or application. Additional embodiments are possible in accordance with the teachings of this disclosure as set forth in the appended claims.

[0030] Figure 1 This is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0031] refer to Figure 1 The memory system 50 may include a memory device 100 and a memory controller 200, the memory controller 200 controlling the operation of the memory device. The memory system 50 may be a device that stores data under the control of a host 300, such as a cellular phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0032] Depending on the host interface that determines the communication method with host 300, memory system 50 can be manufactured as one of various types of memory systems. For example, memory system 50 can be configured as any type of storage device, such as SSDs, multimedia cards in the form of MMC, eMMC, RS-MMC, and micro MMC, secure digital cards in the form of SD, mini SD, and micro SD, universal serial bus (USB) storage devices, universal flash storage (UFS) devices, PCMCIA card type storage devices, peripheral component interconnect (PCI) card type storage devices, PCI Express (PCI-E) card type storage devices, compact flash (CF) cards, smart media cards, and memory sticks.

[0033] The memory system 50 can be manufactured in any of the various types of packages. For example, the memory system 50 can be manufactured in any of the various types of packages, such as POP, SIP, SOC, MCP, COB, WFP, and WSP.

[0034] The memory device 100 can store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) comprising a plurality of memory cells for storing data.

[0035] Each memory cell in the memory unit can be configured as: a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a three-level cell (TLC) that stores three data bits, or a four-level cell (QLC) that can store four data bits.

[0036] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In one embodiment, a page may be a unit for storing data in or retrieving data stored in memory device 100. A memory block may be a unit for erasing data.

[0037] In one embodiment, the memory device 100 may use Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Torque Random Access Memory (STT-RAM), etc. For ease of description in this specification, it is assumed that the memory device 100 uses NAND flash memory.

[0038] Memory device 100 can be configured to receive a command CMD and an address ADDR from memory controller 200, and access a region in the memory cell array selected by the address ADDR. Memory device 100 can perform the operation indicated by the command CMD on the region selected by the address ADDR. For example, memory device 100 can perform a programming operation, a read operation, or an erase operation. During a programming operation, memory device 100 can store data in the region selected by the address ADDR. During a read operation, memory device 100 can read data from the region selected by the address ADDR. During an erase operation, memory device 100 can erase data stored in the region selected by the address ADDR.

[0039] Memory device 100 may include multiple planes. A plane can be a unit capable of performing operations independently. For example, memory device 100 may include two, four, or eight planes. Multiple planes can independently and simultaneously perform each of the programming, reading, and erasing operations.

[0040] In one embodiment, the memory device 100 may perform a background media scan (BGMS) operation. The BGMS operation can be performed during idle time when no commands are being received from the memory controller 200. Furthermore, the BGMS operation can be performed to prevent read failures in advance, i.e., to apply Uncorrectable Error Correction Codes (UECC) to the read data during a read operation.

[0041] For example, memory device 100 can scan (read) data stored in memory cells during idle time. Based on the scan results, memory device 100 can select pages for which read operations are likely to fail and perform a refresh operation. In this case, memory device 100 can scan the data sequentially according to memory block numbers or according to random access memory block numbers.

[0042] During BGMS, memory device 100 can detect pages potentially having UECC by scanning the data stored in the pages. Memory device 100 can prevent UECC in advance by programming the data of the detected pages into another memory block. Memory device 100 can improve data reliability by detecting pages that may potentially have UECC due to read disturbances and holding.

[0043] The memory controller 200 can control the overall operation of the memory system 50.

[0044] When power is applied to the memory system 50, the memory controller 200 can execute firmware (FW). When the memory device 100 is a flash memory device, the firmware (FW) may include a host interface layer (HIL) that controls communication with the host 300, and the memory controller 200 may include a flash translation layer (FTL) that controls communication between the host 300 and the memory device 100, and a flash interface layer (FIL) that controls communication with the memory device 100.

[0045] The memory controller 200 can receive write data and logical block addresses (LBAs) from the host 300, and can translate the LBAs into physical block addresses (PBAs). The PBAs indicate the addresses of memory cells included in the memory device 100 where data is to be stored. In this specification, LBA and "logic address" or "logical address" may be used interchangeably. In this specification, PBA and "physical address" may be used interchangeably.

[0046] The memory controller 200 can control the memory device 100 to perform programming operations, read operations, erase operations, etc., according to the request of the host 300. During programming operations, the memory controller 200 can provide programming commands, PBA, and data to the memory device 100. During read operations, the memory controller 200 can provide read commands and PBA to the memory device 100. During erase operations, the memory controller 200 can provide erase commands and PBA to the memory device 100.

[0047] In one embodiment, the memory controller 200 can independently generate commands, addresses, and data regardless of requests from the host 300, and transmit these commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100 for performing read and programming operations in conjunction with wear leveling, read recycling, garbage collection, etc.

[0048] In one embodiment, the memory controller 200 may control at least two memory devices 100. In this case, the memory controller 200 may control the memory devices 100 according to an interleaving method to improve operational performance. The interleaving method may be a method of controlling the operation of at least two memory devices 100 to overlap with each other. Alternatively, the interleaving method may be a method in which at least two memory devices 100 operate in parallel.

[0049] A buffer memory (not shown) may temporarily store data provided from the host 300, i.e., data to be stored in the memory device 100, or the buffer memory may temporarily store data read from the memory device 100. In one embodiment, the buffer memory (not shown) may be volatile memory. For example, the buffer memory (not shown) may be dynamic random access memory (DRAM) or static random access memory (SRAM).

[0050] The host 300 can communicate with the memory system 50 using at least one of a variety of communication methods, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCIe, Non-Volatile Memory Faster (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Away DIMM (LRDIMM).

[0051] Figure 2It is a diagram. Figure 1 A diagram of a memory device.

[0052] refer to Figure 2 The memory device 100 may include a memory cell array 110, an address decoder 120, a read and write circuit 130, a control logic circuit 140, a voltage generator 150, and a current sensing circuit 160. The address decoder 120, the read and write circuit 130, the voltage generator 150, and the current sensing circuit 160 may be collectively referred to as the peripheral circuit controlled by the control logic circuit 140.

[0053] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz can be connected to the address decoder 120 via word lines WL. The multiple memory blocks BLK1 to BLKz can be connected to read and write circuitry 130 via bit lines BL1 to BLm. Each memory block among the multiple memory blocks BLK1 to BLKz may include multiple memory cells. In one embodiment, the multiple memory cells are non-volatile memory cells and can be configured using non-volatile memory cells with a vertical channel structure. The memory cell array 110 may be configured as a memory cell array with a two-dimensional structure. According to one embodiment, the memory cell array 110 may be configured as a memory cell array with a three-dimensional structure. Furthermore, each memory cell among the multiple memory cells included in the memory cell array may store at least one bit of data. In one embodiment, each memory cell among the multiple memory cells included in the memory cell array 110 may be an SLC storing one bit of data. In another embodiment, each memory cell among the multiple memory cells included in the memory cell array 110 may be an MLC storing two bits of data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a TLC storing three bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a QLC storing four bits of data. According to one embodiment, the memory cell array 110 may include a plurality of memory cells each storing five or more bits of data.

[0054] Address decoder 120 can be connected to memory cell array 110 via word line WL. Address decoder 120 can be configured to operate in response to control of control logic circuitry 140. Address decoder 120 can receive addresses via input / output buffers (not shown) inside memory device 100.

[0055] Address decoder 120 can be configured to decode block addresses among received addresses. Address decoder 120 can select at least one memory block based on the decoded block address. Furthermore, during the read voltage application operation, address decoder 120 can apply the read voltage Vread generated in voltage generator 150 to the selected word line of the selected memory block, and apply voltage Vpass to the remaining unselected word lines. Additionally, during the program verification operation, address decoder 120 can apply the verification voltage generated in voltage generator 150 to the selected word line of the selected memory block, and apply voltage Vpass to the remaining unselected word lines.

[0056] Address decoder 120 can be configured to decode the column address of a received address. Address decoder 120 can transmit the decoded column address to read and write circuitry 130.

[0057] Read and programming operations on memory device 100 can be performed on a page-by-page basis. The address received at the time of a read or programming operation request may include a block address, a row address, and a column address. Address decoder 120 can select a memory block and a word line based on the block address and row address. The column address can be decoded by address decoder 120 and provided to read and write circuitry 130. In this specification, a memory cell connected to a word line may be referred to as a "physical page".

[0058] The read and write circuit 130 may include multiple page buffers PB1 to PBm. The read and write circuit 130 can operate as a "read circuit" during read operations of the memory cell array 110 and as a "write circuit" during write operations of the memory cell array 110. The multiple page buffers PB1 to PBm can be connected to the memory cell array 110 via bit lines BL1 to BLm. During read and program verification operations, in order to sense the threshold voltage of the memory cell, while continuously supplying sensing current to the bit lines connected to the memory cell, the multiple page buffers PB1 to PBm can sense changes in the amount of current flowing according to the programming state of the corresponding memory cell via sensing nodes, and latch the sensed changes as sensed data. The read and write circuit 130 can operate in response to a page buffer control signal output from the control logic circuit 140. In this specification, the write operation of the write circuit can be used in the same sense as the programming operation of the selected memory cell.

[0059] During a read operation, the read and write circuitry 130 can sense data in the memory cell, temporarily store the read data, and output the data to an input / output buffer (not shown) of the memory device 100. In one embodiment, in addition to a page buffer (or page register), the read and write circuitry 130 may also include column select circuitry, etc. According to one embodiment of this disclosure, the read and write circuitry 130 may be a page buffer.

[0060] Control logic circuitry 140 can be connected to address decoder 120, read and write circuitry 130, voltage generator 150, and current sensing circuitry 160. Control logic circuitry 140 can receive commands CMD and control signals CTRL via input / output buffers (not shown) of memory device 100. Control logic circuitry 140 can be configured to control the overall operation of memory device 100 in response to control signal CTRL. Furthermore, control logic circuitry 140 outputs control signals for adjusting the precharge potential levels of sensing nodes in multiple page buffers PB1 to PBm. Control logic circuitry 140 can control read and write circuitry 130 to perform read operations on memory cell array 110.

[0061] Simultaneously, in response to a pass signal PASS or a failure signal FAIL received from the current sensing circuit 160, the control logic circuit 140 can determine whether the verification operation for a specific target programming state has passed or failed.

[0062] In response to a control signal output from control logic circuit 140, voltage generator 150 generates a read voltage Vread and a pass voltage Vpass during a read operation. To generate multiple voltages with various voltage levels, voltage generator 150 may include multiple pump capacitors that receive an internal power supply voltage. In response to control by control logic circuit 140, voltage generator 150 can generate multiple voltages by selectively activating these multiple pump capacitors.

[0063] During the verification operation, the current sensing circuit 160 can generate a reference current and a reference voltage in response to the enable bit VRY_BTI<#> received from the control logic circuit 140. The generated reference voltage can be compared with a sensed voltage VPB received from the page buffers PB1 to PBm included in the read and write circuit 130, or the generated reference current can be compared with a sensed current received from the page buffers PB1 to PBm included in the read and write circuit 130, and a PASS or FAIL signal can be output.

[0064] The address decoder 120, read and write circuitry 130, voltage generator 150, and current sensing circuitry 160 can be used as "peripheral circuitry" to perform read, write, and erase operations on the memory cell array 110. The peripheral circuitry can perform read, write, and erase operations on the memory cell array 110 based on the control of the control logic circuitry 140.

[0065] Figure 3 It is a diagram. Figure 2 A diagram showing the configuration of any memory block within the memory blocks.

[0066] In this example, memory block BLKz represents Figure 2 Any one of the memory blocks BLK1 to BLKz.

[0067] refer to Figure 3 Multiple word lines arranged in parallel to each other can be connected between a first select line and a second select line. Here, the first select line can be a source select line (SSL), and the second select line can be a drain select line (DSL). More specifically, the memory block BLKz can include multiple strings (ST) connected between bit lines BL1 to BLm and the source line SL. Bit lines BL1 to BLm can be connected to strings ST individually, and the source line SL can be connected together to strings ST. Since strings ST can be configured identically to each other, as an example, the string connected to the first bit line BL1 will be specifically described.

[0068] A string may include, in series between the source line SL and the first bit line BL1, a source select transistor SST, multiple memory cells MC1 to MC16, and a drain select transistor DST. A string may include at least one or more of the source select transistor SST and the drain select transistor DST, and may include more than Figure 3 The sixteen memory cells shown are MC1 to MC16, and more memory cells.

[0069] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST can be connected to the source select line SSL, the gates of the drain select transistor DST can be connected to the drain select line DSL, and the gates of memory cells MC1 to MC16 can be connected to multiple word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different strings ST can be referred to as a page PG. Therefore, a memory block BLKz can include a number of page PGs equal to the number of word lines WL1 to WL16.

[0070] A memory cell can store one bit of data. This is often referred to as SLC. In this case, a physical page (PG) can store one logical page (LPG) of data. A logical page (LPG) of data can include the same number of data bits as the cells included in a physical page (PG).

[0071] A memory cell can store two or more bits of data. In this case, a physical page (PG) can store two or more logical pages (LPG) of data.

[0072] Figure 4 It is a diagram illustrating the multiple programming cycles included in the programming operation, as well as the programming voltage application operation and verification operation included in each programming cycle.

[0073] refer to Figure 4 Programming operations can include multiple programming loops. For example... Figure 4 As shown, this can be achieved by executing the first programming loop 1. st The PGM Loop is used to begin programming operations. Even after the first programming loop (1) has been executed... st If the PGM Loop also fails to complete the programming operation on the selected memory cell, the second programming loop 2 can be executed. nd PGM Loop. Even if the second programming loop 2 is executed. nd If the PGM Loop also fails to complete the programming operation on the selected memory cell, the third programming loop can be executed. rd PGM Loop. In this way, the programming loop can be repeatedly executed until the programming operation is completed.

[0074] At the same time, if the programming operation is not completed even if the programming loop is repeated up to the predetermined maximum number of programming loops, it can be determined that the programming operation has failed.

[0075] Figure 5A and Figure 5B This is a graph illustrating the threshold voltage distribution of an SLC.

[0076] refer to Figure 5A and Figure 5B The horizontal axis indicates the threshold voltage of the memory cell, and the vertical axis indicates the number of memory cells.

[0077] Memory devices can be programmed in units of word lines. Multiple memory cells connected to a word line can be configured into a physical page. A physical page can be the unit of programming or reading operations.

[0078] Memory devices can be programmed to store data in memory cells on selected word lines connected among multiple word lines.

[0079] Before performing programming operations, such as Figure 5A As shown, the selected memory cell, which is a memory cell connected to the selected word line, can have a threshold voltage distribution corresponding to the erase state E.

[0080] When a memory cell stores data corresponding to a bit, the memory cell can be programmed to have a threshold voltage corresponding to either the erase state E or the first programming state P1.

[0081] The erase state E can correspond to data '1', and the first programming state P1 can correspond to data '0'. However, the data corresponding to the first programming state P1 is an example, and the erase state E can correspond to data '0', while the first programming state P1 can correspond to data '1'.

[0082] like Figure 5B As shown, when the programming operation has ended, the selected memory cell can have a threshold voltage corresponding to either the erase state E or the first programming state P1. The memory device can read the data stored in the selected memory cell by performing a read operation using a first read voltage R1 between the erase state E and the first programming state P1.

[0083] Figure 6A and Figure 6B This is a graph illustrating the threshold voltage distribution of an MLC.

[0084] refer to Figure 6A and Figure 6B The horizontal axis indicates the threshold voltage of the memory cell, and the vertical axis indicates the number of memory cells.

[0085] Before performing programming operations, such as Figure 6A As shown, the selected memory cell, which is a memory cell connected to the selected word line, can have a threshold voltage distribution corresponding to the erase state E.

[0086] When a memory cell stores data corresponding to two bits, the memory cell can be programmed to have a threshold voltage corresponding to any one of the erase state E, the first programming state P1, the second programming state P2, and the third programming state P3.

[0087] The erase state E can correspond to the data '11', the first programming state P1 can correspond to the data '10', the second programming state P2 can correspond to the data '00', and the third programming state P3 can correspond to the data '01'. However, the data corresponding to each programming state is an example and can be modified in various ways.

[0088] like Figure 6B As shown, when the programming operation has ended, the selected memory cell can have a threshold voltage corresponding to any one of the erase state E, the first programming state P1, the second programming state P2, and the third programming state P3. The memory device can read the data stored in the selected memory cell by performing a read operation using the first read voltage R1 to the third read voltage R3.

[0089] The first read voltage R1 can be the read voltage that distinguishes between the erase state E and the first programming state P1, the second read voltage R2 can be the read voltage that distinguishes between the first programming state P1 and the second programming state P2, and the third read voltage R3 can be the read voltage that distinguishes between the second programming state P2 and the third programming state P3.

[0090] Figure 7A and Figure 7B This is a graph illustrating the threshold voltage distribution of a TLC.

[0091] refer to Figure 7A and Figure 7B The horizontal axis indicates the threshold voltage of the memory cell, and the vertical axis indicates the number of memory cells.

[0092] Before performing programming operations, such as Figure 7A As shown, the selected memory cell, which is a memory cell connected to the selected word line, can have a threshold voltage distribution corresponding to the erase state E.

[0093] When a memory cell stores three bits of data, the memory cell can be programmed to have a threshold voltage corresponding to any one of the following states: erase state E, first programming state P1, second programming state P2, third programming state P3, fourth programming state P4, fifth programming state P5, sixth programming state P6, and seventh programming state P7.

[0094] The erase state E corresponds to the data '111', the first programming state P1 corresponds to the data '110', the second programming state P2 corresponds to the data '101', the third programming state P3 corresponds to the data '100', the fourth programming state P4 corresponds to the data '011', the fifth programming state P5 corresponds to the data '010', the sixth programming state P6 corresponds to the data '001', and the seventh programming state P7 corresponds to the data '000'. However, the data corresponding to each programming state is an example and can be modified in various ways.

[0095] like Figure 7BAs shown, when the programming operation has ended, the selected memory cell may have a threshold voltage corresponding to any one of the following states: erase state E, first programming state P1, second programming state P2, third programming state P3, fourth programming state P4, fifth programming state P5, sixth programming state P6, and seventh programming state P7. The memory device can read the data stored in the selected memory cell by performing a read operation using the first read voltage R1 to the seventh read voltage R7.

[0096] The first read voltage R1 can be the read voltage that distinguishes between the erase state E and the first programming state P1; the second read voltage R2 can be the read voltage that distinguishes between the first programming state P1 and the second programming state P2; the third read voltage R3 can be the read voltage that distinguishes between the second programming state P2 and the third programming state P3; the fourth read voltage R4 can be the read voltage that distinguishes between the third programming state P3 and the fourth programming state P4; the fifth read voltage R5 can be the read voltage that distinguishes between the fourth programming state P4 and the fifth programming state P5; the sixth read voltage R6 can be the read voltage that distinguishes between the fifth programming state P5 and the sixth programming state P6; and the seventh read voltage R7 can be the read voltage that distinguishes between the sixth programming state P6 and the seventh programming state P7.

[0097] Figure 8A and Figure 8B This is a graph illustrating the threshold voltage distribution of a QLC.

[0098] refer to Figure 8A and Figure 8B The horizontal axis indicates the threshold voltage of the memory cell, and the vertical axis indicates the number of memory cells.

[0099] Before performing programming operations, such as Figure 8A As shown, the selected memory cell, which is a memory cell connected to the selected word line, can have a threshold voltage distribution corresponding to the erase state E.

[0100] When a memory cell stores data corresponding to four bits, the memory cell can be programmed to have a threshold voltage corresponding to any one of the erase state E and the first programming state P1 to the fifteenth programming state P15.

[0101] The erase state E corresponds to the data '1111', the first programming state P1 corresponds to the data '1110', the second programming state P2 corresponds to the data '1101', the third programming state P3 corresponds to the data '1100', the fourth programming state P4 corresponds to the data '1011', the fifth programming state P5 corresponds to the data '1010', the sixth programming state P6 corresponds to the data '1001', and the seventh programming state P7 corresponds to the data '1000'. Furthermore, the eighth programming state P8 can correspond to the data '0111', the ninth programming state P9 can correspond to the data '0110', the tenth programming state P10 can correspond to the data '0101', the eleventh programming state P11 can correspond to the data '0100', the twelfth programming state P12 can correspond to the data '0011', the thirteenth programming state P13 can correspond to the data '0010', the fourteenth programming state P14 can correspond to the data '0001', and the fifteenth programming state P15 can correspond to the data '0000'. However, the data corresponding to each programming state is an example and can be modified in various ways.

[0102] like Figure 8B As shown, when the programming operation has ended, the selected memory cell can have a threshold voltage corresponding to any one of the erase state E and the first programming states P1 to the fifteenth programming states P15. The memory device can read the data stored in the selected memory cell by performing a read operation using the first read voltage R1 to the fifteenth read voltage R15.

[0103] The first read voltage R1 can be used to distinguish between the erase state E and the first programming state P1; the second read voltage R2 can be used to distinguish between the first programming state P1 and the second programming state P2; the third read voltage R3 can be used to distinguish between the second programming state P2 and the third programming state P3; the fourth read voltage R4 can be used to distinguish between the third programming state P3 and the fourth programming state P4; the fifth read voltage R5 can be used to distinguish between the fourth programming state P4 and the fifth programming state P5; the sixth read voltage R6 can be used to distinguish between the fifth programming state P5 and the sixth programming state P6; the seventh read voltage R7 can be used to distinguish between the sixth programming state P6 and the seventh programming state P7; and the eighth read voltage R8 can be used to distinguish between the seventh programming state P7 and the eighth programming state P8. The ninth read voltage R9 can be used to distinguish between the eighth programming state P8 and the ninth programming state P9; the tenth read voltage R10 can be used to distinguish between the ninth programming state P9 and the tenth programming state P10; the eleventh read voltage R11 can be used to distinguish between the tenth programming state P10 and the eleventh programming state P11; the twelfth read voltage R12 can be used to distinguish between the eleventh programming state P11 and the twelfth programming state P12; the thirteenth read voltage R13 can be used to distinguish between the twelfth programming state P12 and the thirteenth programming state P13; the fourteenth read voltage R14 can be used to distinguish between the thirteenth programming state P13 and the fourteenth programming state P14; and the fifteenth read voltage R15 can be used to distinguish between the fourteenth programming state P14 and the fifteenth programming state P15.

[0104] Figure 9 This is a diagram illustrating the start and end times of a verification operation in multiple programming loops according to an embodiment of the present disclosure.

[0105] exist Figure 9 In this context, it is assumed that each of the multiple memory cells is an MLC, TLC, or QLC. (Reference) Figure 9 The diagram illustrates multiple programming cycles. Each programming cycle may include a programming voltage application operation and a verification operation. After the programming voltage is applied, the verification operation can be performed on multiple programming levels. Figure 9 In the diagram, the horizontal axis indicates time, and the vertical axis indicates the voltage amplitude.

[0106] According to one embodiment of this disclosure, programming time can be reduced by performing verification operations on specific programming levels instead of all programming levels. The programming level for which verification operations are performed can be determined based on the number of failure bits for the voltage applied to the word line.

[0107] exist Figure 9 In the first programming cycle PL1, after applying the first programming voltage Vp1, a first verification voltage V1 can be applied to verify the programming level of multiple memory cells. The first verification voltage V1 can be a voltage applied to the word line to verify the first programming level.

[0108] When executing the (N-2)th programming cycle PL(N-2), the (N-2)th programming voltage Vp(N-2) can be applied. Within the (N-2)th programming cycle PL(N-2), a first verification voltage V1 and a second verification voltage V2 can be applied sequentially. The second verification voltage V2 can be a voltage applied to a word line to verify a second programming level. The (N-2)th programming cycle PL(N-2) to which the second verification voltage V2 is applied can be the start point of the verification operation corresponding to the second verification voltage V2. The second verification voltage V2 is applied for the first time in the (N-2)th programming cycle PL(N-2).

[0109] In one embodiment of this disclosure, a first verification voltage V1 may be applied up to the (N-1)th programming loop PL(N-1). The (N-1)th programming loop PL(N-1) to which the first verification voltage V1 is finally applied may be the end point of the verification operation corresponding to the first verification voltage V1. In the Nth programming loop PLN, only the verification operation for the second verification voltage V2 may be performed.

[0110] In one embodiment of this disclosure, the start time of the verification operation corresponding to the second programming level can be determined as the (N-2)th programming cycle PL(N-2) by means of the verification operation performed in the first programming cycle PL1. The end time of the verification operation corresponding to the first programming level can be determined as the (N-1)th programming cycle PL(N-1) by means of the verification operation performed in the first programming cycle PL1.

[0111] Similarly, the start and end times of the verification operation corresponding to each of the multiple programming levels can be determined.

[0112] Figure 10 This is a block diagram illustrating a method for performing a verification operation according to an embodiment of the present disclosure.

[0113] refer to Figure 10 The control logic circuit 140 can control the address decoder 120, the read and write circuit 130, the voltage generator 150, and the current sensing circuit 160.

[0114] According to one embodiment of this disclosure, control logic circuitry 140 can transmit control signals to read and write circuitry 130 and current sensing circuitry 160. Memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to read and write circuitry 130 via bit lines BLs. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells.

[0115] Address decoder 120 can be connected to memory cell array 110 via word lines WLs. Address decoder 120 can apply voltage generated by voltage generator 150 to selected memory cells via word lines.

[0116] The read and write circuitry 130 includes multiple page buffers PB1 to PBm. These page buffers PB1 to PBm are connected to the memory cell array 110 via bit lines BL1 to BLm. The page buffers PB1 to PBm transmit sensed data to the current sensing circuitry 160, which obtains the sensed data by sensing changes in the amount of current flowing according to the programming state of the corresponding memory cell.

[0117] Voltage generator 150 can generate various voltages via control logic circuit 140. Voltage generator 150 can generate programmable verification voltages, programmable read voltages, and programmable dual verification voltages. The generated voltages can be applied to selected memory cells via word lines.

[0118] The current sensing circuit 160 can receive sensing data from the read and write circuit 130 and perform current sensing operations. The current sensing operation can be an operation to determine whether a memory cell has been programmed to a target state, and can include individual current sensing operations and overall current sensing operations.

[0119] The current sensing circuit 160 can generate a reference current and a reference voltage in response to a preset enable bit, and can generate a verification current and a verification voltage based on the sensed data. The current sensing circuit 160 can compare the reference voltage and the verification voltage with each other and transmit a signal or a failure signal to the control logic circuit 140.

[0120] In one embodiment of this disclosure, the current sensing circuit 160 can count the number of failure bits by comparing a verification voltage applied to a word line with a threshold voltage of a memory cell. The current sensing circuit 160 can transmit information about the counted number of failure bits to the control logic circuit 140.

[0121] In another embodiment of this disclosure, the control logic circuit 140 may include a failure bit counter. The failure bit counter can count the number of failure bits by comparing a verification voltage applied to a word line with a threshold voltage of a memory cell based on a signal received from the current sensing circuit 160.

[0122] Control logic circuitry 140 can control address decoder 120, read and write circuitry 130, voltage generator 150, and current sensing circuitry 160 to perform a verification operation comparing a threshold voltage of a memory cell with a verification voltage for each of a plurality of programming levels. Control logic circuitry 140 can also control address decoder 120 and voltage generator 150 to apply a plurality of blind voltages associated with or related to a target level among the plurality of programming levels to the word lines. Control logic circuitry 140 can use the number of failure bits for each of the plurality of blind voltages to determine the start time of the verification operation corresponding to the next programming level of the target level.

[0123] The multiple blind voltages generated by voltage generator 150 may include a target level verification voltage, a target level read voltage, a target level next programming level double verification voltage, or a target level next programming level verification voltage.

[0124] The control logic circuit 140 may include a reference value manager 141, a verification manager 143, and a storage device 145.

[0125] The reference value manager 141 can control the address decoder 120 and the voltage generator 150 to apply two or more blind voltages from a plurality of blind voltages to the word line. The reference value manager 141 can determine a reference value for the number of failure bits. In one embodiment of this disclosure, the reference value manager 141 can determine the reference value based on the number of failure bits stored in a lookup table according to pre-programmed pulses.

[0126] Verification manager 143 can determine a target voltage among a plurality of blind voltages that has the number of failure bits closest to a reference value. Verification manager 143 can determine the start time of the verification operation corresponding to the next programming level of the target level based on the number of failure bits for the target voltage. In one embodiment of this disclosure, verification manager 143 can determine the end time of the verification operation corresponding to the target level based on the number of failure bits for the target voltage.

[0127] Storage device 145 can store information about the number of failure bits, reference value, or target voltage for each of a plurality of blind voltages.

[0128] In another embodiment of this disclosure, control logic circuitry 140 may control address decoder 120 and voltage generator 150 to apply a plurality of blind voltages associated with a first level among a plurality of programming levels to word lines in order of voltage magnitude. In one embodiment, the voltage magnitude order is an increasing order of voltage magnitude. Control logic circuitry 140 may use the number of failure bits for each of the plurality of blind voltages to determine the start time of a verification operation corresponding to a second level, which is the next programming level after the first level.

[0129] The multiple blind voltages generated by voltage generator 150 may include a first-level verification voltage, a first-level read voltage, a second-level dual verification voltage, or a second-level verification voltage.

[0130] The reference value manager 141 can control the address decoder 120 and the voltage generator 150 to apply multiple blind voltages associated with a first level in sequence according to voltage amplitude until a target voltage with a number of failure bits greater than or equal to a reference value is applied to the word line. The reference value manager 141 can determine the start time of the verification operation corresponding to the second level based on the number of failure bits for the target voltage. The reference value manager 141 can also determine the end time of the verification operation corresponding to the first level based on the number of failure bits for the target voltage.

[0131] Figure 11 This is a diagram illustrating a method for determining a target voltage from a plurality of blind voltages according to an embodiment of the present disclosure.

[0132] refer to Figure 11 The threshold voltage distribution of a memory cell can be increased by applying a programming voltage to the word line. After applying the programming voltage, multiple blind voltages can be applied. Figure 11 The vertical axis can indicate the number of memory cells, and the horizontal axis can indicate the threshold voltage of the memory cells.

[0133] exist Figure 11 In this context, it can be assumed that the first programming cycle is being executed. When a programming voltage is applied to the word line of a memory cell in erase state E, the threshold voltage distribution of the memory cell can be changed to P. After the programming voltage is applied, the control logic circuit 140 can perform a verification operation.

[0134] In one embodiment of this disclosure, control logic circuitry 140 may control an address decoder and a voltage generator to apply a plurality of blind voltages associated with a first authentication level to word lines. The plurality of blind voltages applied to memory cells via word lines may include a first authentication voltage corresponding to the first authentication level, a first read voltage, a second authentication voltage corresponding to a second authentication level, and a second double authentication voltage.

[0135] In one embodiment of this disclosure, control logic circuitry 140 may obtain information about the number of failure bits for each of a plurality of blind voltages. Control logic circuitry 140 may determine the start time of the verification operation corresponding to the second verification level based on the number of failure bits.

[0136] During the verification operation, control logic circuit 140 may count a first number of failure bits in response to a first verification voltage applied to the word line. During the verification operation, control logic circuit 140 may count a second number of failure bits in response to a first read voltage applied to the word line. During the verification operation, control logic circuit 140 may count a third number of failure bits in response to a second double verification voltage applied to the word line. During the verification operation, control logic circuit 140 may count a fourth number of failure bits in response to a second verification voltage applied to the word line.

[0137] For example, the threshold voltage distribution of a memory cell can be altered to P due to the programming voltage applied to the word line of the memory cell in an erase state E. The reference value manager 141 can determine a reference value for determining a target voltage from a plurality of blind voltages. In one embodiment of this disclosure, the reference value manager 141 can determine the reference value based on the number of failure bits stored in a lookup table according to a pre-programmed pulse.

[0138] The control logic circuit 140 can compare the reference value with each of the first number, the second number, the third number, and the fourth number of failure bits. Figure 11 In this process, the threshold voltage of the memory cell can be increased above the first verification voltage due to the first programming voltage, and therefore the first number of failure bits can be 0. The verification manager 143 can determine a target voltage among a plurality of blind voltages that has the number of failure bits closest to the reference value.

[0139] exist Figure 11 In this process, the blind voltage closest to the reference value is the first read voltage. According to one embodiment of this disclosure, the first read voltage can be determined as the target voltage. The verification manager 143 can determine the start time of the verification operation corresponding to the second verification level based on a second number of failure bits counted in response to the first read voltage. The verification manager 143 can determine the end time of the verification operation corresponding to the first verification level based on the second number of failure bits.

[0140] The number of failure bits corresponding to the target voltage can indicate the programming speed of the memory cell. For example, as the programming speed of the memory cell increases, the number of failure bits corresponding to the target voltage can decrease. Conversely, as the programming speed of the memory cell decreases, the number of failure bits corresponding to the target voltage can increase. The verification manager 143 can adjust the start time of the verification operation corresponding to the next programming level of the target level based on the number of failure bits.

[0141] In another embodiment of this disclosure, control logic circuitry 140 may control address decoder 120 and voltage generator 150 to apply a plurality of blind voltages associated with a first verification level to word lines in voltage magnitude order. Reference value manager 141 may determine a reference value for determining a target voltage from the plurality of blind voltages. During verification operation, verification manager 143 may compare the number of failure bits for the voltage applied to the word lines with the reference value. Verification manager 143 may determine a target voltage having a number of failure bits greater than or equal to the reference value. Verification manager 143 may determine the start time of verification operation corresponding to a second verification level based on the number of failure bits for the target voltage.

[0142] According to another embodiment of this disclosure, in Figure 11 In this process, the verification manager 143 can determine the target voltage as the second double verification voltage. The second double verification voltage can be a blind voltage with a number of failure bits greater than the reference value.

[0143] Figure 12 This is a flowchart illustrating a method for performing a verification operation according to an embodiment of the present disclosure.

[0144] refer to Figure 12 During the verification operation, control logic circuit 140 can count the number of failure bits for multiple blind voltages applied to the word lines to determine the target voltage. Based on the number of failure bits for the target voltage, control logic circuit 140 can determine the start time of the verification operation corresponding to the next programming level of the target level.

[0145] In step S1210, control logic circuitry 140 can control peripheral circuitry to apply multiple blind voltages associated with a target level among multiple programming levels to the word line. Reference value manager 141 can control the address decoder and voltage generator to apply two or more blind voltages from the multiple blind voltages to the word line.

[0146] In step S1220, the reference value manager 141 may determine a reference value for the number of failure bits. In one embodiment of this disclosure, the reference value manager 141 may determine the reference value based on the number of failure bits stored in a lookup table according to a pre-programmed pulse.

[0147] In step S1230, the verification manager 143 can determine a target voltage from a plurality of blind voltages. In one embodiment of this disclosure, the verification manager 143 can determine a target voltage from the plurality of blind voltages that has the number of failure bits closest to a reference value.

[0148] In step S1240, the verification manager 143 may determine the start time of the verification operation corresponding to the next programming level of the target level. In one embodiment of this disclosure, the verification manager 143 may determine the start time of the verification operation corresponding to the next programming level of the target level based on the number of failure bits for the target voltage.

[0149] In step S1250, the verification manager 143 may determine the end time of the verification operation corresponding to the target level. In one embodiment of this disclosure, the verification manager 143 may determine the end time of the verification operation corresponding to the target level based on the number of failure bits for the target voltage.

[0150] Figure 13 This is a flowchart illustrating a method for performing a verification operation according to another embodiment of the present disclosure.

[0151] refer to Figure 13 During the verification operation, control logic 140 can compare the number of failure bits for multiple blind voltages applied to the word line in voltage magnitude order with a reference value. When a target voltage with a number of failure bits greater than or equal to the reference value is detected, control logic 140 may not apply voltage to the word line. Control logic 140 can determine the start time of the verification operation corresponding to the next programming level of the target level based on the number of failure bits for the target voltage.

[0152] In step S1310, the control logic circuit 140 can control the peripheral circuitry to apply a plurality of blind voltages associated with a first level to the word lines in order of voltage magnitude. The control logic circuit 140 can control the address decoder and the voltage generator to apply a plurality of blind voltages associated with a first level among a plurality of programming levels to the word lines in order of voltage magnitude. The plurality of blind voltages generated by the voltage generator may include a verification voltage for the first level, a read voltage for the first level, a double verification voltage for the second level, or a verification voltage for the second level.

[0153] In step S1320, the reference value manager 141 may determine a reference value for the number of failure bits. In one embodiment of this disclosure, the reference value manager 141 may determine the reference value based on the number of failure bits stored in a lookup table according to preprogrammed pulses.

[0154] In step S1330, the verification manager 143 can determine a target voltage from a plurality of blind voltages. In one embodiment of this disclosure, the reference value manager 141 can control the address decoder and voltage generator to apply a plurality of blind voltages associated with a first level in order of voltage magnitude until a target voltage having a number of failure bits greater than or equal to a reference value is applied to the word line. The reference value manager 141 can refuse to apply blind voltages to the word line in response to the determination of the target voltage.

[0155] In step S1340, the verification manager 143 may determine the start time of the verification operation corresponding to the second level. In one embodiment of this disclosure, the reference value manager 141 may determine the start time of the verification operation corresponding to the second level based on the number of failure bits for the target voltage.

[0156] In step S1350, the verification manager 143 may determine the end time of the verification operation corresponding to the first level. In one embodiment of this disclosure, the reference value manager 141 may determine the end time of the verification operation corresponding to the first level based on the number of failure bits for the target voltage.

[0157] Figure 14 This is a diagram illustrating a data processing system including a solid-state drive (SSD) according to an embodiment of the present disclosure. Reference Figure 14 The data processing system 2000 may include a host device 2100 and an SSD 2200.

[0158] The SSD 2200 may include a controller 2210, a buffer memory device 2220, non-volatile memory 2231 to 223n, a power supply 2240, a signal connector 2250, and a power connector 2260.

[0159] The controller 2210 can control the overall operation of the SSD 2200.

[0160] Buffer memory device 2220 can temporarily store data to be stored in non-volatile memories 2231 to 223n. Furthermore, buffer memory device 2220 can temporarily store data read from non-volatile memories 2231 to 223n. Data temporarily stored in buffer memory device 2220 can be transferred to host device 2100 or non-volatile memories 2231 to 223n under the control of controller 2210.

[0161] Non-volatile memories 2231 to 223n can be used as storage media for the SSD 2200. Each of the non-volatile memories 2231 to 223n can be connected to the controller 2210 through multiple channels CH1 to CHn. One or more non-volatile memories can be connected to a single channel. Non-volatile memories connected to a single channel can be connected to the same signal bus and data bus.

[0162] Power supply 2240 can provide power PWR input via power connector 2260 to SSD 2200. Power supply 2240 may include auxiliary power supply 2241. Auxiliary power supply 2241 can supply power to allow SSD 2200 to shut down normally in the event of a sudden power failure. Auxiliary power supply 2241 may include a large-capacity capacitor capable of being charged by power PWR.

[0163] The controller 2210 can exchange signals SGL with the host device 2100 via signal connector 2250. Here, the signal SGL may include commands, addresses, data, etc. Depending on the interface method between the host device 2100 and the SSD 2200, the signal connector 2250 can be configured as various types of connectors.

[0164] Figure 15 It is a diagram. Figure 14 A diagram showing the controller configuration. (See reference) Figure 15 The controller 2210 may include a host interface unit 2211, a control unit 2212, a random access memory 2213, an error correction code (ECC) unit 2214, and a memory interface unit 2215.

[0165] The host interface unit 2211 can interface the host device 2100 and the SSD 2200 according to the protocol of the host device 2100. For example, the host interface unit 2211 can communicate with the host device 2100 via any of the following protocols: Secure Digital, Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), PCMCIA, Parallel Advanced Technology Attachment (PATA), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI-E, and Universal Flash Storage (UFS). Furthermore, the host interface unit 2211 can perform disk emulation, which allows the host device 2100 to recognize the SSD 2200 as a general-purpose data storage device, such as a hard disk drive (HDD).

[0166] Control unit 2212 can analyze and process the signal SGL input from host device 2100. Control unit 2212 can control the operation of internal function blocks according to the firmware or software used to drive SSD 2200. Random access memory 2213 can be used as operating memory for driving such firmware or software.

[0167] ECC unit 2214 can generate parity data for the data to be transferred to non-volatile memories 2231 to 223n. The generated parity data, along with the data, can be stored in the non-volatile memories 2231 to 223n. ECC unit 2214 can detect errors in the data read from the non-volatile memories 2231 to 223n based on the parity data. When the detected error is within the correction range, ECC unit 2214 can correct the detected error.

[0168] The memory interface unit 2215, under the control of the control unit 2212, can provide control signals such as commands and addresses to the non-volatile memories 2231 to 223n. Furthermore, the memory interface unit 2215, under the control of the control unit 2212, can exchange data with the non-volatile memories 2231 to 223n. For example, the memory interface unit 2215 can provide data stored in the buffer memory device 2220 to the non-volatile memories 2231 to 223n, or provide data read from the non-volatile memories 2231 to 223n to the buffer memory device 2220.

[0169] Figure 16 This is a diagram illustrating a data processing system including a data storage device according to an embodiment of the present disclosure. Reference Figure 16 The data processing system 3000 may include a host device 3100 and a data storage device 3200.

[0170] The host device 3100 can be configured as a board, such as a printed circuit board. Although not shown, the host device 3100 may include internal function blocks for performing the functions of the host device.

[0171] The host device 3100 may include connection terminals 3110 such as sockets, slots, or connectors. The data storage device 3200 may be mounted on the connection terminals 3110.

[0172] The data storage device 3200 can be configured as a board, such as a printed circuit board. The data storage device 3200 can be referred to as a memory module or memory card. The data storage device 3200 may include a controller 3210, a buffer memory device 3220, non-volatile memory 3231 to 3232, a power management integrated circuit (PMIC) 3240, and a connection terminal 3250.

[0173] Controller 3210 can control the overall operation of data storage device 3200. Controller 3210 can interact with... Figure 14 The controller 2210 shown is configured exactly the same.

[0174] The buffer memory device 3220 can temporarily store data to be stored in the non-volatile memories 3231 to 3232. Furthermore, the buffer memory device 3220 can temporarily store data read from the non-volatile memories 3231 to 3232. The data temporarily stored in the buffer memory device 3220 can be transferred to the host device 3100 or the non-volatile memories 3231 to 3232 under the control of the controller 3210.

[0175] Non-volatile memories 3231 to 3232 can be used as storage media for data storage device 3200.

[0176] The PMIC 3240 can supply power input through the connection terminal 3250 to the data storage device 3200. The PMIC 3240 can manage the power of the data storage device 3200 according to the control of the controller 3210.

[0177] Connection terminal 3250 can be connected to connection terminal 3110 of the host device. Through connection terminal 3250, power and signals, such as commands, addresses, and data, can be transmitted between the host device 3100 and the data storage device 3200. Depending on the interface method between the host device 3100 and the data storage device 3200, connection terminal 3250 can be configured in various ways. Connection terminal 3250 can be located on either side of the data storage device 3200.

[0178] Figure 17 This is a diagram illustrating a data processing system including a data storage device according to an embodiment of the present disclosure. Reference Figure 17 The data processing system 4000 may include a host device 4100 and a data storage device 4200.

[0179] The host device 4100 may be configured as a board, such as a printed circuit board. Although not shown, the host device 4100 may include internal function blocks for performing the functions of the host device.

[0180] Data storage device 4200 can be configured for surface mount packaging. Data storage device 4200 can be mounted on host device 4100 using solder balls 4250. Data storage device 4200 may include controller 4210, buffer memory device 4220, and non-volatile memory 4230.

[0181] Controller 4210 can control the overall operation of data storage device 4200. Controller 4210 can interact with... Figure 14 The controller 2210 shown is configured exactly the same.

[0182] The buffer memory device 4220 can temporarily store data to be stored in the non-volatile memory 4230. Furthermore, the buffer memory device 4220 can temporarily store data read from the non-volatile memory 4230. Data temporarily stored in the buffer memory device 4220 can be transferred to the host device 4100 or the non-volatile memory 4230 under the control of the controller 4210.

[0183] The non-volatile memory 4230 can be used as the storage medium of the data storage device 4200.

[0184] Figure 18 This is a diagram illustrating a network system including a data storage device according to an embodiment of the present disclosure. Reference Figure 18 The network system 5000 may include a server system 5300 and multiple client systems 5410 to 5430 connected via the network 5500.

[0185] Server system 5300 can serve data in response to requests from multiple client systems 5410 to 5430. For example, server system 5300 can store data provided from multiple client systems 5410 to 5430. As another example, server system 5300 can provide data to multiple client systems 5410 to 5430.

[0186] Server system 5300 may include host device 5100 and data storage device 5200. Data storage device 5200 may include... Figure 1 Memory device 100 Figure 14 SSD2200, Figure 16 Data storage device 3200, and Figure 17 4200 data storage devices.

[0187] Because this disclosure can be implemented in other specific forms without altering its technical spirit or essential features, those skilled in the art to which this disclosure pertains should understand that the embodiments described above are illustrative and not limited in any way. The scope of this disclosure is indicated by the claims described later rather than in detail, and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of this disclosure.

Claims

1. A memory device, comprising: A memory block comprising memory cells to which a programming voltage is applied via word lines; Peripheral circuitry is configured to perform a verification operation for each of a plurality of programming levels, comparing a threshold voltage of the memory cell with a verification voltage. as well as Control logic circuitry is configured to control the peripheral circuitry to apply a plurality of blind voltages associated with a target level among the plurality of programming levels to the word lines, and to determine the start time of a verification operation corresponding to the next programming level of the target level using the number of failure bits for each of the plurality of blind voltages. The plurality of blind voltages include the verification voltage of the target level, the read voltage of the target level, the double verification voltage of the next programming level of the target level, or the verification voltage of the next programming level of the target level.

2. The memory device of claim 1, wherein the control logic circuitry includes a reference value manager capable of applying at least two of the plurality of blind voltages to the word line and determining a reference value for the number of failure bits.

3. The memory device of claim 2, wherein the reference value manager is capable of determining the reference value based on the number of failure bits stored in a lookup table according to a preprogrammed pulse.

4. The memory device of claim 2, wherein the control logic circuitry includes a verification manager capable of determining a target voltage having the number of failure bits closest to the reference value among the plurality of blind voltages.

5. The memory device of claim 4, wherein the verification manager is capable of determining the start time of the verification operation corresponding to the next programming level of the target level based on the number of failure bits for the target voltage.

6. The memory device of claim 4, wherein the verification manager is capable of determining the end time of a verification operation corresponding to the target level based on the number of failure bits for the target voltage.

7. The memory device of claim 4, wherein the control logic circuitry includes a storage device configured to store information about at least one of the following: the number of failure bits for each of the plurality of blind voltages, the reference value, and the target voltage.

8. A memory device, comprising: A memory block comprising memory cells to which a programming voltage is applied via word lines; Peripheral circuitry is configured to perform a verification operation for each of a plurality of programming levels, comparing a threshold voltage of the memory cell with a verification voltage. as well as Control logic circuitry is configured to control the peripheral circuitry to apply a plurality of blind voltages associated with a first level of the plurality of programming levels in order of voltage magnitude to the word lines, and to determine the start time of a verification operation corresponding to a second level, which is the next programming level after the first level, using the number of failure bits for each of the plurality of blind voltages. The plurality of blind voltages include the first level of verification voltage, the first level of read voltage, the second level of dual verification voltage, or the second level of verification voltage.

9. The memory device of claim 8, wherein the control logic circuitry includes a reference value manager capable of applying a reference value for the number of failure bits based on the number of failure bits stored in a lookup table according to a preprogrammed pulse.

10. The memory device of claim 9, wherein the control logic circuitry includes a verification manager capable of applying the plurality of blind voltages associated with the first level in the order of the voltage magnitudes until a target voltage having a number of failure bits greater than or equal to the reference value is applied to the word line, and the verification manager being capable of determining the start time of the verification operation corresponding to the second level based on the number of failure bits for the target voltage.

11. The memory device of claim 10, wherein the verification manager is capable of determining the end time of the verification operation corresponding to the first level based on the number of failure bits for the target voltage.

12. The memory device of claim 10, wherein the control logic circuitry includes a storage device configured to store information about at least one of the following: the number of failure bits for each of the plurality of blind voltages, the reference value, and the target voltage.

13. A method of operating a memory device, the method comprising: The programming voltage is applied to the memory cell through the word line; as well as For each of a plurality of programming levels, a verification operation is performed that compares a threshold voltage of the memory cell with a verification voltage, wherein performing the verification operation includes: Multiple blind voltages associated with a target level among the multiple programming levels are applied to the word line; as well as The start time of the verification operation corresponding to the next programming level of the target level is determined by using the number of failure bits for each of the plurality of blind voltages. The plurality of blind voltages include the verification voltage of the target level, the read voltage of the target level, the double verification voltage of the next programming level of the target level, or the verification voltage of the next programming level of the target level.

14. The method of claim 13, wherein applying the plurality of blind voltages to the word lines comprises: At least two of the following are applied to the word line: the verification voltage of the target level, the read voltage of the target level, the double verification voltage of the next programming level of the target level, and the verification voltage of the next programming level of the target level; as well as Determine a baseline value for the number of failure bits.

15. The method of claim 14, wherein determining the start time point of the verification operation corresponding to the next programming level of the target level comprises: Determine the target voltage among the plurality of blind voltages that has the number of failure bits closest to the reference value; as well as The start time of the verification operation corresponding to the next programming level of the target level is determined based on the number of failure bits for the target voltage.

16. The method of claim 15, further comprising: The end time of the verification operation corresponding to the target level is determined based on the number of failure bits for the target voltage.

17. A method of operating a memory device, the method comprising: The programming voltage is applied to the memory cell through the word line; as well as For each of a plurality of programming levels, a verification operation is performed that compares a threshold voltage of the memory cell with a verification voltage, wherein performing the verification operation includes: Multiple blind voltages associated with the first of the multiple programming levels are applied to the word line in order of voltage magnitude. as well as The start time of the verification operation corresponding to the second level is determined using the number of failure bits for each of the plurality of blind voltages, which is the next programming level after the first level. The plurality of blind voltages include the first level of verification voltage, the first level of read voltage, the second level of dual verification voltage, or the second level of verification voltage.

18. The method of claim 17, wherein performing the verification operation comprises: The reference value is determined based on the number of failure bits stored in the lookup table according to the pre-programmed pulse; The plurality of blind voltages associated with the first level are applied sequentially according to the voltage amplitude until a target voltage having a number of failure bits greater than or equal to the reference value is applied to the word line; as well as The start time of the verification operation corresponding to the second level is determined based on the number of failure bits for the target voltage.

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