System and method for generating test multi-core ssd firmware based on pre-processing conditions

Abstract

Embodiments of the present disclosure provide a system for testing multi-core firmware (FW) in a memory system and a method thereof. A testing system includes a testing device; and a storage device including a plurality of flash translation layer (FTL) cores each associated with a plurality of memory blocks. The testing device generates a plurality of test pre-condition for the plurality of FTL cores and provides the plurality of test pre-condition to the plurality of FTL cores, the plurality of test pre-condition being different from each other. Each of the plurality of FTL cores performs one or more test operations based on a respective test pre-condition of the plurality of test pre-condition.

Claims

1. A testing system, comprising: The storage device includes multiple flash translation layer cores, i.e., multiple FTL cores, each FTL core being associated with multiple storage blocks; as well as The testing apparatus controls the multiple FTL kernels to execute one or more test operations based on test preprocessing conditions generated for and provided to the multiple FTL kernels. These test preprocessing conditions include various conditions. Each of the plurality of FTL kernels performs one or more test operations based on a corresponding test preprocessing condition in the test preprocessing conditions. The test preprocessing conditions include erase and read operation parameter values ​​for each of the plurality of storage blocks, and Each FTL kernel selectively performs one or more test operations on the plurality of storage blocks based on the erase and read operation parameter values.

2. The test system according to claim 1, wherein each of the test preprocessing conditions indicates the state of the plurality of storage blocks.

3. The testing system according to claim 2, wherein the test preprocessing conditions are test preprocessing conditions of the same type but with different parameter values.

4. The test system according to claim 2, wherein the test preprocessing conditions are of different types.

5. The testing system according to claim 1, wherein the testing device is included in a real or virtual host device, the real or virtual host device being connected to or included in the storage device.

6. A testing system, comprising: The storage device includes multiple flash translation layer cores, i.e., multiple FTL cores, each FTL core being associated with multiple storage blocks; as well as The testing device generates test preprocessing conditions for the multiple FTL kernels and provides these test preprocessing conditions to the multiple FTL kernels. The test preprocessing conditions include different conditions. Each of the plurality of FTL kernels performs one or more test operations based on a corresponding test preprocessing condition in the test preprocessing conditions. Each of the test preprocessing conditions indicates the state of the plurality of storage blocks, and The test preprocessing conditions include the erase counter value and read counter value for each of the plurality of storage blocks.

7. The test system of claim 6, wherein each FTL core selectively performs one or more test operations, including at least one of wear leveling operation and read interference operation, on the plurality of memory blocks based on read counter values ​​and erase counter values.

8. The test system according to claim 7, wherein when the erase counter value is greater than the erase threshold, each FTL core performs the wear leveling operation on the plurality of storage blocks.

9. The test system according to claim 7, wherein when the read counter value is greater than the read threshold, each FTL core performs a read refresh operation on the plurality of storage blocks.

10. A method for testing a storage device, the storage device comprising a plurality of flash translation layer cores, i.e., a plurality of FTL cores, each FTL core associated with a plurality of storage blocks, the method comprising: The test preprocessing conditions for the multiple FTL kernels are generated by the test device; The test preprocessing conditions are provided to the plurality of FTL cores by the test device, and the test preprocessing conditions are different from each other; and Based on the test preprocessing conditions, the multiple FTL kernels are controlled to execute one or more test operations. The test preprocessing conditions mentioned above include different conditions. Each of the plurality of FTL kernels performs one or more test operations based on a corresponding test preprocessing condition in the test preprocessing conditions. The test preprocessing conditions include erase and read operation parameter values ​​for each of the plurality of storage blocks, and Each FTL kernel selectively performs one or more test operations on the plurality of storage blocks based on the erase and read operation parameter values.

11. The method of claim 10, wherein each of the test preprocessing conditions indicates the state of the plurality of storage blocks.

12. The method of claim 11, wherein the test preprocessing conditions are test preprocessing conditions of the same type but with different parameter values.

13. The method of claim 11, wherein the test preprocessing conditions are of different types.

14. The method of claim 10, wherein the testing apparatus is included in a real or virtual host device, the real or virtual host device being connected to or included in the storage device.

15. A method for testing a storage device, the storage device comprising a plurality of flash translation layer cores, i.e., a plurality of FTL cores, each FTL core associated with a plurality of storage blocks, the method comprising: The test preprocessing conditions for the multiple FTL kernels are generated by the test device; The test preprocessing conditions are provided to the plurality of FTL cores by the test device, and the test preprocessing conditions include different conditions; as well as Each of the plurality of FTL kernels performs one or more test operations based on a corresponding test preprocessing condition in the test preprocessing conditions, wherein the test preprocessing conditions include the erase counter value and read counter value of each of the plurality of memory blocks.

16. The method of claim 15, wherein each FTL core selectively performs one or more test operations, including at least one of a wear leveling operation and a read interference operation, on the plurality of memory blocks based on a read counter value and an erase counter value.

17. The method of claim 16, wherein when the erase counter value is greater than the erase threshold, each FTL core performs the wear leveling operation on the plurality of memory blocks.

18. The method of claim 16, wherein when the read counter value is greater than the read threshold, each FTL core performs a read refresh operation on the plurality of memory blocks.

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