Techniques for storing sub-alignment data when aligning accelerated smith-waterman sequences

Abstract

This disclosure relates to techniques for storing sub-alignment data when accelerating Smith-Waterman sequence alignment. Various techniques are provided for accelerating Smith-Waterman sequence alignment. For example, threads in a group of threads are used to store relevant data in registers using an interleaved cell layout while computing sub-alignment data for one or more local alignment problems. In another example, specialized instructions are used that reduce the number of cycles needed to compute each sub-alignment score. In another example, threads are used to compute sub-alignment data for a subset of columns of one or more local alignment problems, while other threads start computing sub-alignment data based on partial result data received from previous threads. Upon computing a maximum sub-alignment score, the threads store the maximum sub-alignment score and the corresponding position in a global memory.

Description

Technical Field

[0001] Various embodiments generally relate to parallel processing systems, and more specifically, to techniques for storing sub-alignment data when accelerating Smith-Waterman sequence alignment. Background Art

[0002] The Smith-Waterman algorithm is used in various applications, such as scientific, engineering and data applications, to quantify how well the subsequences of two sequences align, and to determine the optimized subsequence alignment or "local alignment" of these sequences. For example, the Smith-Waterman algorithm is a building block of many genomics algorithms, such as algorithms for determining the DNA sequence of an organism and comparing DNA or protein sequences with genomic databases.

[0003] To solve the local alignment problem of the target sequence "T" and the query sequence "Q" using the Smith-Waterman algorithm, a software application implements a matrix filling phase and a backtracking phase or a reverse matrix filling phase. In the matrix filling phase, the software application implements dynamic programming techniques to decompose the calculation of the optimized local alignment into the calculation of interdependent sub-alignment scores included in a two-dimensional (2D) scoring matrix "H". The scoring matrix includes, but is not limited to, a topmost row and a leftmost column of initial values, a distinct row for each symbol of the target sequence, and a distinct column for each symbol of the query sequence. For a target sequence of length M and a query sequence Q of length N, the scoring matrix is thus a (M+1)x(N+1) matrix. Due to the offset introduced by the row and column of initial values, for 0<j<=M and 0<k<=N, the sub-alignment score denoted as H(j,k) quantifies the maximum similarity between any subsequence of T ending at symbol T(j-1) and any subsequence of Q ending at symbol Q(k-1). As part of the matrix filling phase, the software application determines the maximum sub-alignment score and the position of the maximum sub-alignment score within the scoring matrix. In the backtracking phase or the reverse matrix filling phase, the software application determines the starting position within the scoring matrix that corresponds to the maximum sub-alignment score. The starting position and the position of the maximum sub-alignment score define the target subsequence and the query subsequence corresponding to the optimized local alignment of the target sequence and the query sequence.

[0004] Since performing the matrix filling phase for T of length M and Q of length N requires (MxN) time or "quadratic time", and performing the backtracking phase requires (M+N) or "linear time", the matrix filling phase may be a performance bottleneck when solving many local alignment problems. In this regard, for 0<j<=M and 0<k<=N, H(j,k) can be calculated by the following equations (1a)–(1c):

[0005]

[0006]

[0007]

[0008] In equations (1a)-(1c), E and F are matrices that store intermediate results for reuse when calculating the correlation sub-alignment scores. GapDeleteExtend, GapDeleteExtend, GapInsertOpen, and GapInsertExtend are "gap" constants; Substitution(T(j-1), Q(k-1)) is the substitution value included in the substitution matrix for symbols T(j-1) and Q(k-1) corresponding to symbol matching values ​​(e.g., 4) or symbol mismatch values ​​(e.g., -1).

[0009] Because a large amount of computation must be performed in the matrix-filling stage of DNA and protein sequences of typical sizes, some software applications use instruction sets or “programs” executed on parallel processors to accelerate the matrix-filling stage. These types of processors can achieve very high computational throughput by executing a large number of threads in parallel across many different processing cores. A traditional approach to performing the Smith-Waterman matrix-filling stage on a parallel processor involves distributing the computation of position-associated sub-alignment scores across groups of threads, which can be computed independently of each other. Returning to equations (1a)-(1c), H(j,k) depends on H(j-1,k-1) corresponding to the adjacent top-left diagonal position, E(j-1,k) and H(j-1,k) corresponding to the adjacent top position, and F(j,k-1) and H(j,k-1) corresponding to the adjacent left-side position. Therefore, the sub-alignment scores along each anti-diagonal of the scoring matrix can be computed independently of each other. In the “anti-diagonal” implementation, the anti-diagonals of the scoring matrix are processed one at a time, starting from the top-left corner of the scoring matrix. To process each anti-diagonal line, each position along the anti-diagonal line is assigned to a different thread, which calculates the E, F, H, and replacement values ​​corresponding to the assigned position in parallel. Then, the threads write the E, F, and H values ​​to the corresponding positions in the E matrix, F matrix, and scoring matrix stored in shared memory, respectively.

[0010] One drawback of the above method is that the computational inefficiency associated with each sub-alignment score limits the performance improvements attributable to parallelizing the entire matrix filling stage. Computing each sub-alignment score involves sequentially executing ten instructions, including at least five addition / subtraction instructions and five binary operand maximization instructions. Retrieving the F-value, E-value, sub-alignment score, and replacement values ​​for the instruction calls used to compute each sub-alignment score typically involves executing additional data movement instructions that reduce computational throughput. Furthermore, determining and storing the maximum sub-alignment score and its associated location requires executing several instructions for each sub-alignment score. Due to the inefficiency caused by these additional instructions, the time required to execute the matrix filling stage can be very long. For example, using the above method, performing the matrix filling stage on the 47-megabase-pair (Mbp) long human chromosome 21 and the 33-megabase-pair (Mbp) long chimpanzee chromosome 22 could take nearly a day.

[0011] As mentioned above, there is a need in the art for more efficient techniques for the matrix filling stage of executing the Smith-Waterman algorithm on parallel processors. Summary of the Invention

[0012] One embodiment of the present invention provides a computer-implemented method for storing sub-alignment data during the matrix filling phase of the Smith-Waterman algorithm. The method includes determining a top E-value and a top sub-alignment score based on the top cell of the top position in a scoring matrix, wherein the scoring matrix is ​​associated with at least a first target sequence and at least a first query sequence; calculating a current E-value associated with the current position in the scoring matrix based on the top E-value and the top sub-alignment score; storing the current E-value in the current cell of the current position in the scoring matrix; calculating a current sub-alignment score associated with the current position in the scoring matrix based on the current E-value, a diagonal sub-alignment score stored in a diagonal cell of the diagonal position in the scoring matrix, and a current replacement value associated with the first target sequence, the first query sequence, and the current position in the scoring matrix; and storing the current sub-alignment score in the current cell.

[0013] At least one technical advantage of the disclosed technique over the prior art is that, using the disclosed technique, when executing the matrix filling stage of the Smith-Waterman algorithm using a parallel processor, the number of instructions executed to compute each sub-alignment score can be reduced. In this regard, using the disclosed technique, a single Smith-Waterman instruction or a six-instruction Smith-Waterman sequence can be used to concurrently compute one, two, or four sub-alignment score alignment problems associated with one, two, or four different localities, respectively. Because the disclosed technique allows the sub-alignment scores and intermediate results associated with each position in the scoring matrix to be stored in an interleaved manner within a single cell, the inefficiencies associated with data movement can be reduced compared to conventional techniques for retrieving the same data from separate matrices. Furthermore, using the disclosed technique, instructions instructing the selected operands when determining the minimum or maximum value of two operands can be used to reduce the number of instructions executed when determining and storing the maximum sub-alignment score and associated positions. These technical advantages provide one or more technical improvements over prior art methods. Attached Figure Description

[0014] To gain a more detailed understanding of the above-described features of the various embodiments, a more specific description of the inventive concept briefly outlined above can be obtained by referring to the various embodiments (some of which are shown in the accompanying drawings). However, it should be noted that the drawings illustrate only typical embodiments of the inventive concept and should not be construed as limiting the scope in any way, and that other equally effective embodiments exist.

[0015] Figure 1 This is a block diagram illustrating a system configured to implement one or more aspects of various embodiments;

[0016] Figure 2 Included according to various embodiments Figure 1 A block diagram of the parallel processing unit in the parallel processing subsystem;

[0017] Figure 3A Included according to various embodiments Figure 2 A block diagram of a general-purpose processing cluster in a parallel processing unit;

[0018] Figure 3B According to various embodiments Figure 3A A block diagram of a streaming multiprocessor;

[0019] Figure 4 Based on various embodiments and Figure 1 Example illustration of Smith-Waterman data associated with a Smith-Waterman kernel;

[0020] Figure 5 It is based on various other embodiments and Figure 1 Example illustration of Smith-Waterman data associated with a Smith-Waterman kernel;

[0021] Figure 6 The diagram illustrates various embodiments of the invention. Figure 1 The Smith-Waterman kernel executes Smith-Waterman instructions;

[0022] Figure 7 The following are illustrations based on various other embodiments. Figure 1 The Smith-Waterman kernel executes Smith-Waterman sequences;

[0023] Figure 8 The diagram illustrates various embodiments of the invention. Figure 1 The minimum / maximum values ​​executed by the Smith-Waterman kernel and their corresponding source pointer instructions;

[0024] Figure 9 According to various embodiments, Figure 1 An example illustration of pseudocode for the Smith-Waterman two-problem executed by the Smith-Waterman kernel;

[0025] Figure 10 According to various other embodiments Figure 1 An example illustration of Smith-Waterman single-problem pseudocode executed by the Smith-Waterman kernel;

[0026] Figure 11 Various embodiments are shown. Figure 6 and Figure 9 How are the instructions implemented in the execution unit?

[0027] Figure 12A According to various embodiments, Figure 3A An exemplary illustration of the dual-path single instruction multiple data (SIMD) matrix filling stage executed by a cooperative thread array (CTA);

[0028] Figure 12B According to various other embodiments Figure 3A Example illustration of the dual-channel SIMD matrix filling phase of CTA execution;

[0029] Figure 13 This is a flowchart of method steps for storing sub-aligned data during the matrix filling phase of performing the Smith-Waterman algorithm, according to various embodiments;

[0030] Figure 14 This is a flowchart of method steps for performing sub-alignment calculations by a single instruction during the matrix filling phase of the Smith-Waterman algorithm, according to various embodiments;

[0031] Figure 15 This is a flowchart of method steps for performing sub-alignment calculations via a sequence of instructions during the matrix filling phase of the Smith-Waterman algorithm, according to various embodiments; and

[0032] Figure 16 This is a flowchart of method steps for performing the matrix filling phase of the Smith-Waterman algorithm via a thread group, according to various embodiments. Detailed Implementation

[0033] In the following description, numerous specific details are set forth to provide a more thorough understanding of the various embodiments. However, it will be apparent to those skilled in the art that the concepts of the invention can be practiced without one or more of these specific details. For purposes of explanation only, this document uses reference numerals to identify objects and bracketed alphanumeric characters to identify instances as needed to denote multiple instances of similar objects.

[0034] As described earlier in this paper, in a typical approach to executing the matrix filling phase of the Smith-Waterman algorithm on a parallel processor, a thread group processes one anti-diagonal line of the scoring matrix at a time, starting from the top left corner. To process each anti-diagonal line, the thread group concurrently computes sub-alignment data (e.g., E-value, F-value, replacement value, and sub-alignment score) for each position of the anti-diagonal line. The thread group stores the E-value, F-value, and sub-alignment score in the E matrix, F matrix, and scoring matrix, respectively, in shared memory.

[0035] One drawback of the above method is that the computational inefficiency associated with each sub-alignment score limits the performance improvement attributable to parallelizing the entire matrix filling stage. Computing the sub-alignment score involves executing data move instructions to retrieve the necessary F-values, E-values, sub-alignment scores, and replacement values ​​from shared memory, followed by a sequence of ten instructions. Furthermore, determining and storing the maximum sub-alignment score and its associated position as the output of the matrix filling stage requires executing several instructions for each sub-alignment score. Due to the inefficiency caused by these additional instructions, the time required to execute the matrix filling stage can be very long.

[0036] To address the aforementioned issues, in some embodiments, the software application 190 executing on the main processor configures a thread group to concurrently execute the Smith-Waterman (SW) kernel 192 on a parallel processor to perform the matrix filling phase of one or more local alignment problems. The following is in conjunction with... Figure 1 A more detailed description of the software application 190.

[0037] The SW core 192 is an instruction set (e.g., programs, functions, etc.) that can be executed on parallel processors. As combined below... Figure 4 , 5 As described in detail on 13, in some embodiments, the SW core 192 implements one or more data interleaving techniques to reduce the movement of sub-aligned data. In the same or other embodiments, the parallel processor implements one or more instructions specifically designed to improve computational efficiency during the matrix filling phase, and the SW core 192 uses any number of dedicated instructions. In some embodiments, the SW core 192 uses a single dedicated SW instruction or a sequence of six dedicated instructions to compute the sub-alignment score. In the same or other embodiments, the SW core 192 uses the VIMNMX instruction, which instructs the selected operand when choosing the minimum or maximum value of two operands, to reduce the number of instructions required to determine and store the maximum sub-alignment score and its associated location. The following is in conjunction with... Figure 6 , Figure 9 , Figure 14 A detailed explanation of the SW command. The following text combines... Figure 7 , Figure 10 , Figure 11 , Figure 15 This section provides a detailed introduction to the six-instruction sequence and related instructions. The following text combines... Figure 8 and Figure 11 Describe the VIMNMX instruction in detail.

[0038] In some embodiments, to increase throughput, the thread group executing the SW kernel 192 concurrently performs matrix filling stages for multiple alignment problems using SIMD interleaved threading. In SIMD interleaved threading, each thread in a warp performs row-by-row sub-alignment calculations for a different subset of columns, and each thread except thread 0 performs the calculation one row after the thread immediately following it in terms of sub-alignment. For example, in some embodiments, during the initial iteration, thread 0 performs sub-alignment calculations corresponding to H(1,1)–H(1,C) for P local alignment problems, where C and P can be any positive integers. In the next iteration, thread 0 performs sub-alignment calculations corresponding to H(2,1)–H(2,C) for P local alignment problems, and thread 1 performs sub-alignment calculations corresponding to H(1,C+1)–H(1,2C) for P local alignment problems.

[0039] For illustrative purposes only, the functionality of software application 190 and SW kernel 192 is combined as follows Figure 1-16 This is described in the context of determining, but not limited to, the maximum sub-alignment score and the maximum sub-alignment position in the scoring matrix for each problem in any number of local sequence alignment problems. In some embodiments, the SW kernel 192 does not retain the scoring matrix. For example, in some embodiments, at most two rows of the scoring matrix are stored in memory at any given time.

[0040] In some embodiments, for each maximum sub-alignment score exceeding a matching threshold, software application 190 causes SW kernel 192 to generate a backtracking matrix while re-executing the matrix filling phase for the corresponding local alignment problem. The backtracking matrix specifies the derivation position of each sub-alignment score and can therefore be used to determine the optimized local alignment.

[0041] In some other embodiments, for each maximum sub-alignment score exceeding a matching threshold, software application 190 inverts the corresponding target sequence and the corresponding query sequence. The software application then causes SW kernel 192 to re-execute the matrix filling phase based on the reversed sequence. The position of the maximum sub-alignment score corresponds to a starting position within the scoring matrix, which can be used to determine the optimized local alignment.

[0042] Note that the techniques described herein are illustrative rather than limiting, and modifications can be made without departing from the broader spirit and scope of the invention. Many modifications and variations to the functionality provided by the software application 190, SW kernel 192, warp, parallel processing subsystem 112, PPU, SM, and CPU will be readily apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

[0043] Exemplary System Overview

[0044] For illustrative purposes only, the functions of software application 190 and SW kernel 192 are combined below. Figure 1-16 This is described in the context of some embodiments implemented within system 100. As will be described in more detail below, in... Figure 1-16 In the embodiment depicted, software application 190 executes on CPU 102 and causes thread groups to execute SW kernel 192 concurrently on one or more streaming multiprocessors (SMs).

[0045] Figure 1This is a block diagram illustrating a system 100 configured to implement one or more aspects of various embodiments. As shown, system 100 includes, but is not limited to, a CPU 102 and system memory 104 coupled to a parallel processing subsystem 112 via a memory bridge 105 and a communication path 113. In some embodiments, at least a portion of the system memory 104 is host memory associated with the CPU 102. The memory bridge 105 is also coupled to an input / output (I / O) bridge 107 via a communication path 106, and the I / O bridge 107 is in turn coupled to a switch 116.

[0046] In operation, I / O bridge 107 is configured to receive user input information from input device 108, such as a keyboard or mouse, and forward the input information to CPU 102 for processing via communication path 106 and memory bridge 105. Switch 116 is configured to provide connectivity between I / O bridge 107 and other components of system 100, such as network adapter 118 and add-on cards 120 and 121.

[0047] As also shown in the figure, I / O bridge 107 is coupled to system disk 114, which can be configured to store content, applications, and data for use by CPU 102 and parallel processing subsystem 112. Generally, system disk 114 provides non-volatile storage for applications and data and may include fixed or removable hard disk drives, flash memory devices, optical disc read-only memory, digital versatile optical disc read-only memory, Blu-ray, high-definition digital versatile optical discs, or other magnetic, optical, or solid-state storage devices. Finally, although not explicitly shown, other components, such as universal serial bus or other port connections, optical disc drives, digital versatile optical disc drives, movie recording devices, etc., may also be connected to I / O bridge 107.

[0048] In various embodiments, memory bridge 105 may be a northbridge chip, while I / O bridge 107 may be a southbridge chip. Furthermore, communication paths 106 and 113, as well as other communication paths within system 100, may be implemented using any technically suitable protocol, including but not limited to Peripheral Component Interconnect Express, Accelerated Graphics Port, HyperTransport, or any other bus or point-to-point communication protocol known in the art.

[0049] In some embodiments, the parallel processing subsystem 112 includes, but is not limited to, one or more parallel processors. In some embodiments, each parallel processor is a PPU that includes, but is not limited to, one or more SMs. Each SM includes, but is not limited to, multiple execution units also referred to herein as “processor cores.” In some embodiments, the PPUs may be the same or different, and each PPU may be associated with a dedicated parallel processing (PP) memory or not. In some embodiments, the PP memory associated with a given PPU is also referred to as “device memory” associated with the PPU. In the same or other embodiments, each core launched on a given PPU resides in the device memory of the PPU.

[0050] In some embodiments, the parallel processing subsystem 112 includes circuitry optimized for general-purpose processing. As combined below... Figure 2 In more detail, such circuitry can be incorporated across one or more PPUs, which can be configured to perform general-purpose processing operations. In the same or other embodiments, the parallel processing subsystem 112 also includes circuitry optimized for graphics processing. Such circuitry can be incorporated across one or more PPUs, which can be configured to perform graphics processing operations. In the same or other embodiments, any number of PPUs can output data to any number of display devices 110. In some embodiments, zero or more PPUs can be configured to perform general-purpose processing operations instead of graphics processing operations, zero or more PPUs can be configured to perform graphics processing operations instead of general-purpose processing operations, and zero or more PPUs can be configured to perform both general-purpose processing operations and / or graphics processing operations. In some embodiments, a software application executing under the control of the CPU 102 can launch a kernel on one or more PPUs.

[0051] In some embodiments, the parallel processing subsystem 112 can be connected with Figure 1 One or more other components are integrated to form a single system. For example, the parallel processing subsystem 112 may be integrated with the CPU 102 and other interconnecting circuitry on a single chip to form a system-on-a-chip. In the same or other embodiments, any number of CPUs 102 and any number of parallel processing subsystems 112 may be distributed across any number of shared geographic locations and / or any number of different geographic locations and / or implemented in any combination within one or more cloud computing environments (i.e., encapsulated shared resources, software, data, etc.).

[0052] System memory 104 may include, but is not limited to, any number and / or type of system software (e.g., operating systems, device drivers, libraries, utilities, etc.), any number and / or type of software applications, or any combination thereof. The system software and software applications included in system memory 104 may be organized in any technically feasible manner.

[0053] As shown in the figure, in some embodiments, system memory 104 includes, but is not limited to, a programming platform software stack 160 and software applications 190. The programming platform software stack 160 is associated with a programming platform for accelerating computational tasks by utilizing the hardware in the parallel processing subsystem 112. In some embodiments, software developers can access the programming platform through, but not limited to, libraries, compiler instructions, and / or extensions to programming languages. In the same or other embodiments, the programming platform may be, but is not limited to, Computing Unified Device Architecture (CUDA). Developed by NVIDIA in Santa Clara, California), Radeon Open Computing Platform (ROCm), OpenCL (OpenCL... TM Developed by the Khronos Group), SYCL, or Intel OneAPI.

[0054] In some embodiments, the programming platform software stack 160 provides an execution environment for software application 190 and zero or more other software applications (not shown). In some embodiments, software application 190 may be any type of software application (e.g., a genomics application) residing in any amount and / or type of memory and executing any number and / or type of instructions on CPU 102 and / or any number and / or type of instructions on parallel processing subsystem 112. In some embodiments, software application 190 executes any number and / or type of instructions associated with any number of local sequence alignments. In the same or other embodiments, software application 190 may execute any number and / or type of instructions on parallel processing subsystem 112 in any technically feasible manner. For example, in some embodiments, software application 190 may include, but is not limited to, any computer software capable of being launched on programming platform software stack 160.

[0055] In some embodiments, the software application 190 and the programming platform software stack 160 execute under the control of the CPU 102. In the same or other embodiments, the software application 190 may access one or more PPUs included in the parallel processing subsystem 112 via the programming platform software stack 160. In some embodiments, the programming platform software stack 160 includes, but is not limited to, any number and / or types of libraries (not shown), any number and / or types of runtimes (not shown), any number and / or types of drivers (not shown), or any combination thereof.

[0056] In some embodiments, each library may include, but is not limited to, data and programming code that can be used by computer programs (e.g., software application 190, SW kernel 192, etc.) and utilized during software development. In the same or other embodiments, each library may include, but is not limited to, pre-written code, kernels, subroutines, functions, macros, any number and / or types of other instruction sets, or any combination thereof, optimized for use in one or more SMs of the parallel processing subsystem 112. In the same or other embodiments, libraries included in the programming platform software stack 160 may include, but are not limited to, classes, values, type specifications, configuration data, documentation, or any combination thereof. In some embodiments, a library is associated with one or more application programming interfaces (APIs) that expose at least a portion of the content implemented in the library.

[0057] Although not shown, in some embodiments, one or more software libraries may include, but are not limited to, pre-written code, kernels (including SW kernel 192), subroutines, functions, macros, any number and / or types of other instruction sets, classes, values, type specifications, configuration data, documents, or any combination thereof, which are optimized to execute on one or more SMs within the parallel processing subsystem 112.

[0058] In some embodiments, at least one device driver is configured to manage the processing operations of one or more PPUs within the parallel processing subsystem 112. In the same or other embodiments, any number of device drivers implement instructions that enable a software application to execute specified API functions via API calls on one or more PPUs. In some embodiments, any number of device drivers provide compilation capabilities for generating machine code specifically optimized for the parallel processing subsystem 112.

[0059] In the same or other embodiments, at least one runtime includes, but is not limited to, any technically feasible runtime system capable of supporting the execution of software application 190 and zero or more other software applications. In some embodiments, the runtime is implemented as one or more libraries associated with one or more runtime APIs. In the same or other embodiments, one or more drivers are implemented as libraries associated with driver APIs.

[0060] In some embodiments, one or more runtime APIs and / or one or more driver APIs scan and expose, but are not limited to, any number of functions for each of memory management, execution control, device management, error handling, and synchronization. Memory management functions may include, but are not limited to, functions for allocating, dealing with, and copying device memory, as well as functions for transferring data between host memory and device memory. Execution control functions may include, but are not limited to, the function for booting the kernel on the PPU included in the parallel processing subsystem 112. In some embodiments, the driver APIs are lower-level APIs that provide more fine-grained control over the PPU, relative to the runtime APIs.

[0061] In the same or other embodiments, parallel runtime enables software applications to dispatch thread groups across one or more SMs. Each software application can reside in any amount of memory and execute on any number of processors in any combination. Some examples of processors include, but are not limited to, CPU 102, parallel processing subsystem 112, and PPU. In some embodiments, a software application executing under the control of CPU 102 can launch kernels on one or more PPUs.

[0062] Software application 190 can call any number and / or type of functions to configure thread groups to concurrently execute the matrix filling phase of the SW algorithm for one or more local alignment problems. In some embodiments, each local alignment problem is associated with a target sequence, a query sequence, a set of constants, and a replacement matrix. In some embodiments, each of the target sequence, query sequence, length of the target sequence, length of the query sequence, set of constants, and replacement matrix associated with a local sequence alignment problem may be the same as or different from each of the target sequence, query sequence, length of the target sequence, length of the query sequence, set of constants, and replacement matrix associated with other local sequence alignment problems, respectively. For illustrative purposes only, the target sequence, query sequence, set of constants, and replacement matrix are also referred to herein as “SW input data”.

[0063] In some embodiments, for each local alignment problem, the matrix filling phase of the SW algorithm results in the maximum sub-alignment score and the maximum score position (e.g., row and column indices) within the associated score matrix. In the same or other embodiments, only a portion of the score matrix is ​​stored in memory at any given time. For example, in some embodiments, only two rows of the score matrix are stored in memory at any given time. In some embodiments, one, two, or four local alignment problems share each score matrix.

[0064] In some embodiments, to configure the thread group to concurrently execute the matrix filling phase, software application 190 selects SW kernel 192 from one or more SW kernels, each SW kernel based on any number and / or type of criteria associated with different characteristics. For example, in some embodiments, some SW kernels use a single SW instruction to compute the sub-aligned data, while some other SW kernels use a sequence of six instructions to compute the sub-aligned data. In some embodiments, some SW kernels implement SIMD interleaved threading technology to divide each local alignment problem among multiple threads. In the same or other embodiments, some SW kernels assign each local alignment problem to a single thread. In some embodiments, the type of input data (e.g., unsigned 32-bit integer, signed 32-bit integer, etc.) varies in the SW kernels.

[0065] In some embodiments, software application 190 allocates device memory for storing the target sequence, query sequence, constant set, substitution matrix, and results. Software application 190 then copies the target sequence, query sequence, constant set, and substitution matrix from host memory to device memory. Software application 190 can organize the target sequence, query sequence, constant set, substitution matrix, and results in any technically feasible manner to optimize memory access for SW kernel 192.

[0066] In the same or other embodiments, software application 190 invokes or "starts" SW kernel 192 via a kernel call (not shown). The kernel call includes, but is not limited to, the name of SW kernel 192, execution configuration (not shown), and the argument values ​​(not shown) of the arguments of SW kernel 192. In some embodiments, the execution configuration specifies, but does not limit, the configuration of the thread group (e.g., size, dimensions, etc.). The thread group can be organized in any technically feasible manner, and the configuration of the thread group can be specified in any technically feasible manner.

[0067] For example, in some embodiments, thread groups are organized as a grid of Cooperative Thread Arrays (CTAs), and the execution configuration specifies, but is not limited to, a one-dimensional or multi-dimensional grid size and a one-dimensional or multi-dimensional CTA size. Each thread in the CTA grid is configured to execute SW kernel 192 on different input data. More specifically, in some embodiments, each PPU is configured to concurrently process one or more CTA grids, and each CTA in the grid concurrently executes the same program on different input data. In the same or other embodiments, each SM is configured to concurrently process one or more CTAs. Each CTA is also referred to as a “thread block.” In some embodiments, each SM divides each CTA into one or more groups of parallel threads, called “thread bundles,” which the SM creates, manages, schedules, and executes in a Single Instruction Multithreaded (SIMT) manner. In some embodiments, each thread bundle includes, but is not limited to, a fixed number of threads (e.g., 32). Each thread bundle in the CTA concurrently executes the same program on different input data, and each thread in the thread bundle concurrently executes the same program on different input data. In some embodiments, threads in a thread bundle may diverge and reconverge during execution.

[0068] The mesh size and CTA size can be determined in any technically feasible manner based on any number and / or type of criteria. In some embodiments, software application 190 determines the mesh size and CTA size based on the dimensions of the SW input data and the amount of hardware resources (such as memory or registers) available for the mesh and CTA. In the same or other embodiments, software application 190, SW kernel 192, or both determine any number and / or type of problem configuration data associated with SW kernel 192 based on the mesh size, CTA size, dimensions of the SW input data, or any combination thereof. For example, when SW kernel 192 implements SIMD interleaved thread matrix filling technology, the number of columns allocated to each thread can be determined based on register pressure. For example, to avoid register overflow, the number of columns allocated to each thread can be reduced.

[0069] Note that the techniques described herein are illustrative rather than restrictive, and modifications can be made without departing from the broader spirit and scope of the invention. Numerous modifications and variations to the functionality provided by system 100, CPU 102, parallel processing subsystem 112, software application 190, SW kernel 192, programming platform software stack 160, zero or more libraries, zero or more drivers, and zero or more runtime will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

[0070] It should be understood that the system illustrated herein is illustrative and variations and modifications are possible. The connection topology can be modified as needed, including the number and arrangement of bridges, the number of CPUs 102, and the number of parallel processing subsystems 112. For example, in some embodiments, system memory 104 may be directly connected to CPU 102 instead of via memory bridge 105, and other devices may communicate with system memory 104 via memory bridge 105 and CPU 102. In other alternative topologies, parallel processing subsystems 112 may be connected to I / O bridge 107 or directly to CPU 102 instead of via memory bridge 105. In other embodiments, I / O bridge 107 and memory bridge 105 may be integrated into a single chip rather than existing as one or more discrete devices. Finally, in some embodiments, Figure 1 One or more of the components shown may be absent. For example, switch 116 may be removed, and network adapter 118 and add-on cards 120, 121 will be directly connected to I / O bridge 107.

[0071] As described earlier herein, in some embodiments, any software application executing on any main processor can configure a thread group to concurrently execute SW kernel 192 on a parallel processor to perform a matrix filling stage for one or more local alignment problems. As referred to herein, a “processor” can be any instruction execution system, apparatus, or device capable of executing instructions. For purposes of explanation, the terms “function” and “program” are used herein to refer to any set of one or more instructions that can be executed by any number and / or type of processors. Furthermore, the term “kernel” is used to refer to a set of instructions (e.g., a program, function, etc.) that can be executed on one or more parallel processors.

[0072] As mentioned herein, a "parallel processor" can be any computing system including, but not limited to, multiple parallel processing elements that can be configured to perform any number and / or type of computations. Furthermore, a "parallel processing element" of a computing system is a physical unit that executes concurrently within the computing system. In some embodiments, a parallel processor can be a parallel processing unit (PPU), a graphics processing unit (GPU), a tensor processing unit, a multi-core central processing unit (CPU), an intelligent processing unit, a neural processing unit, a neural network processor, a data processing unit, a vision processing unit, or any other type of processor or accelerator that now or in the future can support multi-threaded parallel execution.

[0073] As mentioned herein, the “main processor” can be any type of parallel processor or any other type of processor capable of booting a kernel on a parallel processor. In some embodiments, the main processor is a latency-optimized general-purpose processor, such as a CPU. In some embodiments, the software application 190 executes on the parallel processor and the thread group executing on the parallel processor can be configured to implement any number of techniques described herein with respect to SW kernel 192 in any technically feasible manner.

[0074] Figure 2 Included according to various embodiments Figure 1 A block diagram of PPU202 in the parallel processing subsystem 112. Although Figure 2 A PPU 202 is depicted, but as described above, the parallel processing subsystem 112 may include zero or more other PPUs identical to PPU 202 and zero or more other PPUs different from PPU 202. As shown, PPU 202 is coupled to local parallel processing (PP) memory 204. PPU 202 and PP memory 204 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits, or memory devices, or in any other technically feasible manner.

[0075] As shown in the figure, PPU 202 includes circuitry optimized for general-purpose processing, and PPU 202 can be configured to perform general-purpose processing operations. Although in Figure 2 Not shown, but in some embodiments, PPU 202 also includes circuitry optimized for graphics processing, including, for example, video output circuitry. In such embodiments, PPU 202 can be configured to perform general processing operations and / or graphics processing operations.

[0076] Refer again Figure 1 and Figure 2 In some embodiments, CPU 102 is the main processor of system 100, controlling and coordinating the operations of other system components. Specifically, CPU 102 issues commands to control the operations of PPU 202. In some embodiments, CPU 102 writes the command stream for PPU 202 into a data structure that can be located in system memory 104, PPU memory 204, or another storage location accessible to both CPU 102 and PPU 202. Figure 1 or Figure 2(Not explicitly shown in the text). A pointer to a data structure is written to a push buffer to initiate processing of the command stream in the data structure. PPU 202 reads the command stream from the push buffer and then executes the commands asynchronously relative to the operation of CPU 102. In embodiments that generate multiple push buffers, the scheduling of different push buffers can be controlled by the application (specifying the execution priority for each push buffer via a device driver (not shown)).

[0077] Now return to the reference Figure 2 and Figure 1 In some embodiments, PPU 202 includes I / O unit 205 that communicates with the rest of system 100 via communication path 113 connected to memory bridge 105. In some embodiments, I / O unit 205 communicates with the rest of system 100 via communication path 113 directly connected to CPU 102. In the same or other embodiments, the connection of PPU 202 to the rest of system 100 may vary. In some embodiments, parallel processing subsystem 112 including at least one PPU 202 is implemented as an add-in card that can be inserted into an expansion slot of system 100. In some other embodiments, PPU 202 may be integrated into a single chip with a bus bridge, such as memory bridge 105 or I / O bridge 107. In some other embodiments, some or all of the components of PPU 202 may be included together with CPU 102 in a single integrated circuit or system-on-a-chip.

[0078] I / O unit 205 generates packets (or other signals) for transmission on communication path 113 and also receives all incoming packets (or other signals) from communication path 113, directing the incoming packets to the appropriate components of PPU 202. For example, commands associated with processing tasks may be directed to host interface 206, while commands associated with memory operations (e.g., reading from or writing to PPU memory 204) may be directed to crossbar switch unit 210. Host interface 206 reads each push buffer and transmits the command stream stored in the push buffer to front end 212.

[0079] In operation, front-end 212 sends processing tasks received from host interface 206 to a work allocation unit (not shown) within task / work unit 207. The work allocation unit receives a pointer to a processing task encoded as Task Metadata (TMD) and stores it in memory. The pointer to the TMD is included in a command stream, which is stored as a push buffer and received by front-end 212 from host interface 206. A processing task that can be encoded as a TMD includes an index associated with the data to be processed, as well as state parameters and commands defining how the data should be processed. For example, the state parameters and commands can define a program to be executed on the data.

[0080] The PPU 202 advantageously implements a highly parallel processing architecture based on a processing cluster array 230 comprising a set of C GPCs 208, where C ≥ 1. Each GPC 208 is capable of concurrently executing a large number (e.g., hundreds or thousands) of threads, where each thread is an instance of a program (e.g., a kernel). In various applications, different GPCs 208 can be assigned to handle different types of programs or to perform different types of computations. The allocation of GPCs 208 can vary depending on the workload generated by each type of program or computation. GPCs 208 receive processing tasks to be executed from work allocation units within task / work units 207.

[0081] Task / work unit 207 receives processing tasks from front-end 212 and ensures that the General Processing Cluster (GPC) 208 is configured to an active state before each processing task specified by a TMD is started. A priority can be assigned to each TMD used to schedule the execution of processing tasks. Processing tasks can also be received from processing cluster array 230. Optionally, a TMD may include parameters that control whether the TMD is added to the head or tail of the processing task list (or to a list of pointers to processing tasks), thus providing another level of control over execution priority.

[0082] The memory interface 214 includes a set of D partition units 215, where D ≥ 1. Each partition unit 215 is coupled to one or more dynamic random access memories (DRAMs) 220 residing within the PP memory 204. In some embodiments, the number of partition units 215 is equal to the number of DRAMs 220, and each partition unit 215 is coupled to a different DRAM 220. In some other embodiments, the number of partition units 215 may differ from the number of DRAMs 220. Those skilled in the art will understand that the DRAMs 220 can be replaced by any other technically suitable storage device. In operation, various targets can be stored across the DRAMs 220, allowing the partition units 215 to write portions of each target in parallel to efficiently utilize the available bandwidth of the PP memory 204.

[0083] A given GPC 208 can process data to be written to any DRAM 220 within the PP memory 204. A crossbar switch unit 210 is configured to route the output of each GPC 208 to the input of any partition unit 215 or any other GPC 208 for further processing. GPCs 208 communicate with the memory interface 214 via the crossbar switch unit 210 to read from or write to any number of DRAMs 220. In some embodiments, the crossbar switch unit 210 has a connection to I / O unit 205 in addition to the connection to the PP memory 204 via the memory interface 214, thereby enabling SMs within different GPCs 208 to communicate with system memory 104 or other memories not local to the PPU 202. Figure 2 In some embodiments, the crossbar switch unit 210 is directly connected to the I / O unit 205. In various embodiments, the crossbar switch unit 210 may use a virtual channel to separate the traffic flow between the GPC 208 and the partition unit 215.

[0084] Similarly, GPC 208 can be programmed to perform processing tasks associated with various applications and / or algorithms. In some embodiments, PPU 202 is configured to transfer data from system memory 104 and / or PP memory 204 to one or more on-chip memory cells, process the data, and write the resulting data back to system memory 104 and / or PP memory 204. The resulting data can then be accessed by other system components, including CPU 102, another PPU 202 within parallel processing subsystem 112, or another parallel processing subsystem 112 within system 100.

[0085] As described above, the parallel processing subsystem 112 may include any number of PPUs 202. For example, multiple PPUs 202 may be provided on a single add-in card, or multiple add-in cards may be connected to the communication path 113, or one or more PPUs 202 may be integrated into a bridge chip. The PPUs 202 in a multi-PPU system may be the same or different from each other. For example, different PPUs 202 may have different numbers of processor cores and / or different numbers of PP memories 204. In an implementation with multiple PPUs 202, these PPUs 202 can be computed in parallel to process data at a higher throughput than a single PPU 202 might be. Systems combining one or more PPUs 202 can be implemented in various configurations and form factors, including but not limited to desktops, laptops, handheld personal computers or other handheld devices, servers, workstations, game consoles, embedded systems, etc.

[0086] Figure 3A Included according to various embodiments Figure 2A block diagram of GPC 208 in PPU 202. In operation, GPC 208 can be configured to execute a large number of threads in parallel. In some embodiments, each thread executing on GPC 208 is an instance of a specific program executed on a specific input dataset. In some embodiments, Single Instruction Multiple Data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In some other embodiments, SIMT technology is used to support the parallel execution of a large number of typically synchronous threads using a common instruction unit configured to issue instructions to a set of processing engines within GPC 208. Unlike SIMD execution mechanisms where all processing engines typically execute the same instructions, SIMT execution allows different threads to more easily follow different execution paths through a given program. Those skilled in the art will understand that SIMD processing mechanisms represent a subset of the functionality of SIMT processing mechanisms.

[0087] The operations of GPC 208 are controlled by pipeline manager 305, which distributes processing tasks received from the work assignment unit (not shown) within task / work unit 207 to one or more SMs 310. Pipeline manager 305 can also be configured to control work assignment crossbar switch 316 by specifying the destination of the processed data output by SM 310.

[0088] In some embodiments, GPC 208 includes, but is not limited to, M SM 310s, where M ≥ 1. In the same or other embodiments, each of the SM 310 includes, but is not limited to, a group of execution units (not in...). Figure 3A (As shown in the diagram). Processing operations specific to any execution unit can be piped, allowing new instructions to be issued for execution before the previous instruction has finished executing. Any combination of execution units within a given SM310 can be provided. In various embodiments, execution units can be configured to support a wide variety of operations, including integer and floating-point arithmetic (e.g., addition and multiplication), comparison operations, Boolean operations (e.g., AND, OR, XOR), shifting, and computation of various algebraic functions (e.g., plane interpolation and trigonometric functions, exponential and logarithmic functions, etc.). Advantageously, the same execution unit can be configured to perform different operations.

[0089] As previously described herein, in some embodiments, each SM 310 is configured to handle one or more thread bundles. In some embodiments, the SM 310 may issue and execute thread bundle-level instructions. In particular, in some embodiments, the SM 310 may issue and execute thread bundle warp shuffle instructions (e.g., SHFL_SYNC), which enable direct register-to-register data exchange between threads within a thread bundle.

[0090] In some embodiments, multiple associated thread bundles included in CTA 312 may be active simultaneously within SM 310 (at different execution phases). In the same or other embodiments, the size of CTA 312 is equal to m*k, where k is the number of threads executing concurrently in the thread bundle, which is typically an integer multiple of the number of execution units within SM 310, and m is the number of thread bundles active simultaneously within SM 310. In some embodiments, each CTA 312 may be a single thread, a one-dimensional array of threads, or a multi-dimensional block of threads configured to execute the same procedure concurrently on different input data. In the same or other embodiments, each SM 310 may concurrently process a maximum number of CTA 312s (e.g., one, two, etc.) depending on the size of CTA 312.

[0091] In some embodiments, each thread in each CTA 312 is assigned a unique thread identifier (ID), which the thread can access during execution. The thread ID, which can be defined as a one-dimensional or multi-dimensional numerical value, controls various aspects of the thread's processing behavior. For example, the thread ID can be used to determine which part of the input dataset the thread will process and / or which part of the output dataset the thread will produce or write. In some embodiments, each thread in CTA 312 can access a portion of shared memory allocated to CTA 312. In the same or other embodiments, threads in each CTA 312 can synchronize together, cooperate, communicate, or any combination thereof in any technically feasible manner (e.g., via shared memory).

[0092] As mentioned earlier in this article Figure 1 In some embodiments, CTAs 312 configured to execute the same kernel are organized into a one-dimensional or multi-dimensional grid. In the same or other embodiments, each CTA 312 is assigned a unique CTA ID, which is accessible to each thread within the CTA 312 during thread execution.

[0093] Return to reference Figure 2 as well as Figure 3A In some embodiments, each CTA 312 in a given grid is scheduled to one of the SMs 310 included in the PPU 202. Subsequently, threads in each CTA 312 concurrently execute the same program on different input data, wherein each thread in the CTA 312 executes on a different execution unit within the SM 310 to which the CTA 312 is scheduled.

[0094] In some embodiments, each SM 310 includes a Level 1 (L1) cache. Figure 3A(Not shown in the diagram) or use space in the corresponding L1 cache outside the SM310 to support load and store operations, etc. Each SM 310 can also access a secondary (L2) cache (not shown) shared among all GPCs 208 in the PPU 202. In some embodiments, the L2 cache can be used to transfer data between threads. Finally, the SM 310 can also access off-chip “global” memory, which may include PP memory 204 and / or system memory 104. It should be understood that any memory outside the PPU 202 can be used as global memory. Additionally, as Figure 3A As shown, a Level 1.5 (L1.5) cache 314 may be included within the GPC 208 and configured to receive and store data requested from memory by the SM 310 via the memory interface 214, and to provide the data requested by the SM 310. Such data may include, but is not limited to, instructions, uniform data, and constant data. In embodiments where the GPC 208 has multiple SMs 310, the SMs 310 may advantageously share common instructions and data cached in the L1.5 cache 314.

[0095] Each GPC 208 may have an associated memory management unit (MMU) 318 configured to map virtual addresses to physical addresses. In various embodiments, the MMU 318 may reside within the GPC 208 or within the memory interface 214. The MMU 318 includes a set of page table entries for mapping virtual addresses to physical addresses of blocks or memory pages, and optionally caches line indexes. The MMU 318 may include an address translation back buffer or cache, which may reside within the SM 310, one or more L1 caches, or within the GPC 208.

[0096] In some embodiments, each SM 310 transfers the processed task to the job allocation crossbar switch 316 so that the processed task can be provided to another GPC 208 for further processing or stored in an L2 cache (not shown), a PP memory 204, or a system memory 104 via the crossbar switch unit 210.

[0097] It should be understood that the core architecture described herein is illustrative and variations and modifications are possible. Any number and / or type of processing units, such as the SM 310, can be included within the GPC 208. Furthermore, as combined with the above... Figure 2As described, the PPU 202 may include any number of GPCs 208 configured to be functionally similar to each other, such that their performance is independent of which of the GPCs 208 receives a particular processing task. Furthermore, in some embodiments, each GPC 208 operates independently of the other GPCs 208 in the PPU 202 to execute tasks for one or more applications. In view of the foregoing, those skilled in the art will understand... Figure 1 The architecture described in -3 does not limit the scope of this disclosure.

[0098] As italicized in CTA 312, in some embodiments, each thread in one or more CTA 312 executes SW kernel 192 concurrently. CTA 312 can be configured to execute SW kernel 192 in any technically feasible manner. Furthermore, CTA 312 can be scheduled onto SM 310 in any technically feasible manner.

[0099] Figure 3B According to various embodiments Figure 3A A block diagram of SM 310 is shown. As illustrated, in some embodiments, SM 310 includes, but is not limited to, sub-partitioning units 320(1)-320(4), a memory input / output (MIO) control unit 370, an MIO unit 380, an L1 cache 390, and a convergence barrier unit (CBU) 360. In some other embodiments, SM 310 may include any number of sub-partitioning units 320.

[0100] In some embodiments, the thread bundles allocated to SM 310 are distributed among sub-partition units 320. Any number of thread bundles can be allocated to each sub-partition unit 320; however, a given thread bundle is allocated to only one sub-partition unit 320. As shown, each sub-partition unit 320 includes, but is not limited to, an instruction cache 342, a micro-scheduler dispatch unit 340, a core data path unit 350, and a unified register file 332. The bracketed number “x” in each unified register file 332(x), instruction cache 342(x), micro-scheduler dispatch unit 340(x), and core data path unit 350(x) indicates the associated sub-partition unit 320(x).

[0101] Such as combination Figure 3AThe SM 310 receives processing tasks from the pipeline manager 305. For each thread bundle, the allocated sub-partition unit 320(x) receives the allocated processing task and stores the associated instructions in the instruction cache 342(x). The micro-scheduler dispatch unit 340(x) reads instructions from the instruction cache 342(x). In some embodiments, the micro-scheduler dispatch unit 340(x) includes, but is not limited to, one or more instruction decoders (not shown). In the same or other embodiments, each instruction decoder is coupled to any number of execution units. After the instruction decoders included in the micro-scheduler dispatch unit 340(x) decode a given instruction, the micro-scheduler dispatch unit 340(x) issues the instruction to one of the execution units. If the instruction is targeted to one of any number of execution units 354(x) included in the core data path unit 350(x), the micro-scheduler dispatch unit 340(x) issues the instruction to the execution unit. Otherwise, the micro-scheduler dispatch unit 340(x) forwards the instruction to the MIO control unit 370. In some embodiments, the micro-scheduler scheduling unit 340(x) includes, but is not limited to, two scheduling units (not shown) capable of enabling the issuance of two different instructions from the same thread bundle in each clock cycle. In some other embodiments, each micro-scheduler scheduling unit 340(x) may include a single scheduling unit or additional scheduling units.

[0102] The core data path unit 350(x) includes, but is not limited to, execution unit 354(x) and register file 352(x). Each execution unit 354(x) included in the core data path unit 350(x) can perform any number and type of operations to execute thread bundles allocated to sub-partition units 320(x). Each execution unit 354(x) included in the core data path unit 350(x) has a fixed latency, such as an arithmetic logic unit (ALU). Each execution unit 354(x) included in the core data path unit 350(x) is connected to register file 352(x) and unified register file 332(x) via any number of buses.

[0103] Register file 352(x) is a cache memory, including but not limited to any number of registers and any number of read and / or write ports. In some embodiments, each register in register file 352(x) is assigned to one of the threads in one thread bundle, and one of the threads in one thread bundle is assigned to sub-partition unit 320(x) and cannot be directly accessed by any other thread. In this way, each thread in each thread bundle assigned to sub-partition unit 320(x) exclusively uses a set of registers in register file 352(x). In some embodiments, any number of registers can be organized as a vector register storing N M-bit values. For example, in some embodiments, the vector register can store different 32-bit values ​​for each thread in a 32-thread thread bundle. Register file 352(x) can be implemented in any technically feasible manner. In some other embodiments, registers included in register file 352(x) can be arranged and assigned to threads and / or thread bundles in any technically feasible manner.

[0104] The unified register file 332(x) is a cache memory, including but not limited to any number of unified registers and any number of read and / or write ports. The unified register file 332(x) can be implemented in any technically feasible manner. In some embodiments, each unified register in the unified register file 332(x) can be accessed by all threads included in a thread bundle. In some other embodiments, the unified registers included in the register file 352(x) can be arranged and allocated to threads and / or thread bundles in any technically feasible manner.

[0105] In some embodiments, the CBU 360 manages diverging threads, performs synchronization operations, and ensures the forward progress of all non-exiting threads included in the thread bundle. Threads in the thread bundle are referred to here as "diverging" during instruction execution when only a subset of threads in the thread bundle participate in the instructions. The CBU 360 can be configured to perform any number and type of synchronization operations based on any number and type of synchronization instructions.

[0106] In some embodiments, the MIO unit 380 includes, but is not limited to, any number of execution units 354(0). In the same or other embodiments, each execution unit 354(0) included in the MIO unit 380 may perform any number and type of operations to execute threads assigned to the SM 310, regardless of the assigned sub-partition units 320. Each execution unit 354(0) included in the MIO unit 380 is connected to register files 352(1)-452(4) and unified register files 332(1)-332(4) via any number of buses.

[0107] As shown in the figure, in some embodiments, the MIO unit 380 interfaces with register files 352(1)-452(4), unified register files 332(1)-432(4), and L1 cache 390. The L1 cache 390 may include any type and number of on-chip memories arranged in any technically feasible manner. The MIO unit 380 and any number of buses enable each execution unit 354(0)-354(4) included in the SM310 to access memory locations included in the L1 cache 390.

[0108] In some embodiments, each SM 310 implements, but is not limited to, one or more integer pipelines (not shown) and one or more floating-point pipelines (not shown). In the same or other embodiments, each integer pipeline performs 32-bit integer operations through a set of 32-bit integer execution units, and each floating-point pipeline performs 32-bit integer operations through a set of 32-bit floating-point execution units (...). Figure 3A (Not shown in the image) Performs 32-bit floating-point operations. In some embodiments, each SM 310 can issue and execute integer instructions in parallel with floating-point instructions.

[0109] In some embodiments, each SM 310 can issue and execute one or more instructions specifically designed to improve the computational efficiency of the matrix filling stage of the SW algorithm. For example, in some embodiments, each SM 310 can issue and execute SW instructions, VIADD instructions, VIADDMNMX instructions, VIMNMX3 instructions, VIMNMX instructions, or any combination thereof. The following description, in conjunction with... Figure 6 A more detailed description of the SW command is provided below. Figure 7 A more detailed description of the VIADD, VIADDMNMX, and VIMNMX3 instructions is provided below. Figure 7 A more detailed description of the VIMNMX instructions Figure 8 .

[0110] In the same or other embodiments, SW instructions, VIADD instructions, VIADDMNMX instructions, VIMNMX3 instructions, VIMNMX instructions, or any combination thereof, are associated with threaded computation modes (not shown) of no-SIMD, dual-SIMD, and quad-SIMD. As described in more detail below, in the no-SIMD, dual-SIMD, and quad-SIMD threaded computation modes, each thread computes a sub-alignment score for one, two, or four local alignment problems. In the same or other embodiments, one or more SW libraries in the programming platform software stack 160 include, but are not limited to, pre-written code, kernels, subroutines, intrinsics, macros, classes, values, type specifications, etc., which facilitate the use of one or more specialized instructions.

[0111] In some embodiments, the SW instruction computes SW sub-aligned data for a single thread. The SM 310 can implement the SW instruction in any technically feasible manner. In some embodiments, the SW instruction is a native instruction executed directly by the SM 310. In the same or other embodiments, the SW instruction is executed in an integer pipeline. The following is combined with... Figure 5 A more detailed description of the SW command.

[0112] For the purpose of explanation, Figure 4-16 The document describes the SW kernel 192, special instructions, macros, intrinsics, etc., for threaded computation modes (not shown) in SIMD-free, dual-SIMD, and quad-SIMD scenarios. As described in more detail below, in these threaded computation modes, each thread computes a sub-alignment score for one, two, or four local alignment problems in one or more specified columns of a scoring matrix. In some other embodiments, the techniques described herein can be modified to implement the SW kernel, special instructions, macros, intrinsics, etc., which can assign any portion (including all) of any number of local alignment problems to each thread in any technically feasible manner.

[0113] Interleaving sub-aligns data to reduce data movement

[0114] Figure 4 Based on various embodiments and Figure 1 An example illustration of SW data 402(0) associated with SW kernel 192. More specifically, SW data 402(0) illustrates, but is not limited to, data associated with a single thread executing SW kernel 192 and a (M+1)x(N+1) scoring matrix corresponding to the maximum value of M target symbols and N query symbols, where M and N can be any positive integers. In some embodiments, including Figure 4 In the embodiment described, SW data 402(0) is optimized for a scoring matrix traversal pattern, wherein each thread computes sub-aligned data for each column set specified in row j before computed for the sub-aligned data for the column set specified in row j+1, where j is an integer from 1 to M.

[0115] As shown in the figure, in some embodiments, SW data 402(0) includes, but is not limited to, problem configuration data 410, SW input data 430, staggered cell layout 450(0), matrix filling dataset 490(0), and result dataset 492(0). As shown in the dashed box, if the threaded computation mode is dual-path SIMD or quad-path SIMD, then SW data 402(0) also includes, but is not limited to, result dataset 492(1). As depicted by the two dashed boxes, if the threaded computation model is quad-path SIMD, then SW data 402(0) also includes, but is not limited to, result dataset 492(3) and result dataset 492(3).

[0116] Problem configuration data 410 includes, but is not limited to, any number and / or types of data, or any combination thereof, of columns, E-values, H-values, sub-alignment values, and replacement values ​​of the scoring matrix assigned to each thread, which can be used to determine the number of local sequence alignment problems. Each thread can determine problem configuration data 410 in any technically feasible manner. In some embodiments, each thread retrieves and / or derives problem configuration data 410 on demand based on built-in variables or attributes of variables. In the same or other embodiments, each thread stores any portion (including all) of problem configuration data 410 in a register file. As shown, in some embodiments, problem configuration data 410 includes, but is not limited to, problems 412 for each thread and columns 414 for each thread.

[0117] For each thread, problem 412 specifies the number of local alignment problems for which the thread computes at least a portion of the sub-alignment score. As shown in italics, in some embodiments, the problem for each thread 412 is denoted as P and equal to 1, 2, or 4. If the problem for each thread 412 is 1, then each thread computes at least a portion of the alignment score for one local alignment problem. However, if the problem for each thread 412 is 2, then each thread computes at least a portion of the sub-alignment score for two local alignment problems. And if the problem for each thread 412 is 4, then each thread computes at least a portion of the sub-alignment score for four local alignment problems. Thus, problems 1, 2, and 4 for each thread 412 correspond to thread computation modes of no SIMD, two-way SIMD, and four-way SIMD, respectively.

[0118] In some embodiments, each of one or more scoring matrices represents sub-alignment data for a different set of P local alignment problems. If problem 412 for each thread is 1, then each scoring matrix is ​​associated with a single local alignment problem. However, if problem 412 for each thread is 2, then each scoring matrix is ​​associated with two different sets of local alignment problems. And if problem 412 for each thread is 4, then each scoring matrix is ​​associated with a different set of four local alignment problems.

[0119] In some embodiments, for each thread, column 414, denoted herein as C, specifies the number of columns in the corresponding scoring matrix assigned to the thread. For example, in some embodiments, the columns of the scoring matrix are evenly distributed among the 16 threads, with each thread having N / 16 columns for 414, where N is the total number of symbols included in the longest query sequence.

[0120] The SW input data 430 includes, but is not limited to, any number and / or type of data that can be used to compute sub-alignment values. In some embodiments, the SW input data 430 includes, but is not limited to, a target sequence 432(0) denoted as T0, a query sequence 434(0) denoted as Q0, a gap constant 442, and a replacement matrix 444. As depicted by the two dashed boxes, if the thread computation mode is dual-path SIMD or quad-path SIMD, the SW input data 430 also includes, but is not limited to, a target sequence 432(1), denoted as T1, and a query sequence 434(1), denoted as T1 as Q1. As depicted by the two dashed boxes, if the thread computation mode is quad-path SIMD, the SW input data 430 further includes, but is not limited to, a target sequence 432(2), a query sequence 434(2), a target sequence 432(3), and a query sequence 434(3), denoted as T2, Q2, T3, and Q3, respectively.

[0121] In some embodiments, each target sequence in the SW input data 430 includes, but is not limited to, a sequence of M symbols or fewer than M symbols, which is padded with virtual symbols to a length of M. In the same or other embodiments, each query sequence included in the SW input data 430 includes, but is not limited to, a sequence of N symbols or fewer than N symbols padded with virtual symbols to a length of N.

[0122] As shown in the figure, in some embodiments, the gap constant 442 (denoted as "consts") includes, but is not limited to, GapDeleteOpen, GapDeleteExtend, GapInsertOpen, and GapInsertExtend, respectively, denoted as gdo, gde, gio, and gie. In the same or other embodiments, the substitution matrix 444 includes, but is not limited to, substitution values ​​that may be included for each possible combination of symbols in the target sequence and the query sequence. For example, in some embodiments, the target sequence and the query sequence are DNA sequences, where each symbol is one of four types of nucleotides (A, G, C, and T), and the substitution matrix 444 is a 4x4 matrix that assigns one value to matrix elements corresponding to the same symbol and another value to matrix elements corresponding to different symbols.

[0123] In some other embodiments, the target sequence and the query sequence are protein sequences, where each symbol is one of 20 amino acids, and the substitution matrix 444 is a 20x20 matrix that assigns the same value to matrix elements corresponding to the same symbol and different values ​​to the remaining matrix elements. In the same or other embodiments, the SW input data 430 may include, but is not limited to, P different sets of gap constants and / or P different substitution matrices corresponding to P different local alignment problems, and the techniques described herein are modified accordingly.

[0124] In some embodiments, each result dataset (e.g., result dataset 492(0), result dataset 492(1), result dataset 492(2), and result dataset 492(3)) includes, but is not limited to, any number and / or the ability to compute the maximum sub-alignment score for the corresponding local alignment problem. Figure 4 (not shown in the image) and the location of the maximum score ( Figure 4 The variable type (not shown in the diagram). In the same or other embodiments, threads assigned to each local alignment problem collaborate in any technically feasible manner over the resulting dataset to incrementally compute the maximum sub-alignment score and the maximum score position for the local alignment problem.

[0125] For example, in some embodiments, the resulting dataset 492 associated with the highest thread assigned to each local alignment problem includes, but is not limited to, variables (e.g., row and column indices) for the maximum sub-alignment score and the corresponding maximum score position of the local alignment problem. In the same or other embodiments, each of the other resulting datasets 492 includes, but is not limited to, variables for the maximum row sub-alignment score and the corresponding maximum column within the row.

[0126] In some embodiments, the target sequence and query sequence are stored in global memory. In the same or other embodiments, each thread copies at least a portion of each assigned query to an array residing in a register file, and copies a portion (e.g., two symbols) of each assigned target sequence from global memory to a variable or array residing in the register file as needed. In some embodiments, the gap constant 442 is stored in constant memory. In the same or other embodiments, the result dataset 492 is stored in the register file.

[0127] As shown in the figure, in some embodiments, each thread temporarily stores sub-alignment data (e.g., E-values, F-values, replacement values, and sub-alignment values) in a register file based on an interleaved cell layout 450(0). The interleaved cell layout 450(0) enables threads to compute the relevant sub-alignment data without performing arbitrary data shift operations. In some embodiments, instead of storing the E-values, F-values, replacement values, and sub-alignment values ​​for the (C+1) column of the previous row and the (C+1) column of the current row in two arrays of up to SWcell 460 residing in contiguous memory locations in the register file or memory, each thread temporarily stores the E-values, F-values, replacement values, and sub-alignment values ​​in a separate matrix in shared memory. In some embodiments, if the thread computes a SIMD mode that is dual-path SIMD or quad-path SIMD, each thread compresses two or four values ​​into the same number of bits to represent a single value when the thread computes a SIMD mode that is non-path SIMD.

[0128] As shown in the figure, when the thread computes the SIMD mode as SIMD-free, each SWcell 460 is an SWcell32 462. In some embodiments, each SWcell32 462 stores, but is not limited to, four 32-bit values ​​corresponding to a single local alignment problem. In the same or other embodiments, SWcell32 462 stores a 32-bit E value across 32-bit E data, a 32-bit F value across 32-bit F data, a 32-bit replacement value across 32-bit replacement data, and a 32-bit sub-alignment score across 32-bit sub-alignment score data. As described earlier in this document, due to the offset in the scoring matrix introduced by the initial row and initial column, SWcell32 462(j,k) corresponds to a subsequence ending with the symbols T0(j-1) and Q0(k-1).

[0129] In some embodiments, SWcell32 462(j,k) includes, but is not limited to, replacement values ​​for the sub-alignment fractions H(j,k), E(j,k), F(j,k), and the symbol T(j+1), and the symbol Q(k+1) denoted as S(j+1,k+1). In some other embodiments, the order of H(j,k), E(j,k), F(j,k), and S(j+1,k+1) within SWcell32(j,k) can vary. In the same or other embodiments, SWcell32(j,k) may store S(j,k) instead of S(j+1,k+1) or omit S(j+1,k+1).

[0130] As shown in the figure, when the thread computes SIMD in dual-path SIMD mode, each SWcell 460 is an SWcell16 464. In some embodiments, each SWcell16 464 stores, but is not limited to, eight 16-bit values ​​corresponding to two local alignment problems. In the same or other embodiments, SWcell16 464 stores two 16-bit E values ​​across 32-bit E data, two 16-bit F values ​​across 32-bit F data, two 16-bit replacement values ​​across 32-bit replacement data, and two 16-bit sub-alignment scores across 32-bit sub-alignment score data. SWcell16 464(j,k) corresponds to the subsequences ending with the symbols T0(j-1), Q0(k-1), T1(j-1), and Q1(j-1).

[0131] In some embodiments, SWcell16 464(j,k) includes, but is not limited to, H0(j,k), H1(j,k), E0(j,k), E1(j,k), F0(j,k), F1(j,k), S0(j+1,k+1), and S1(j+1,k+1). In the same or other embodiments, H0(j,k) and H1(j,k) are compressed into a single 32-bit value and can be accessed as H(j,k). In some embodiments, E0(j,k) and E1(j,k) are compressed into a single 32-bit value and can be accessed as E(j,k). In some embodiments, F0(j,k) and F1(j,k) are compressed into a single 32-bit value and can be accessed as F(j,k). In some embodiments, S0(j+1,k+1) and S1(j+1,k+1) are compressed into a single 32-bit value and can be accessed as S(j,k). In some other embodiments, the order of the 32-bit values ​​H(j,k), E(j,k), F(j,k), and S(j+1,k+1) in SWcell16 464(j,k) can be varied. In the same or other embodiments, the order of H0(j,k) and H1(j,k) within H(j,k); the order of E0(j,k) and E1(j,k) within E(j,k); the order of F0(j,k) and F1(j,k) within F(j,k); the order of S0(j+1,k+1) and S1(j+1,k+1) within S(j+1,k+1); or any combination thereof can be interchanged.

[0132] As shown in the figure, when the thread computes the SIMD mode in a four-way SIMD configuration, each SWcell 460 is an SWcell8 466. In some embodiments, each SWcell8 466 stores, but is not limited to, sixteen 8-bit values ​​corresponding to four local alignment problems. In the same or other embodiments, SWcell16 464 stores four 8-bit E values ​​across 32-bit E data, four 8-bit F values ​​across 32-bit F data, four 8-bit substitution values ​​across 32-bit substitution data, and four 8-bit sub-alignment scores across 32-bit sub-alignment score data. SWcell8 466 corresponds to a subsequence ending with the symbols T0(j-1), Q0(k-1), T1(j-1), Q1(j-1), T2(j-1), Q2(k-1), T3(j-1), and Q3(j-1).

[0133] In some embodiments, SWcell8 466(j,k) includes, but is not limited to, H0(j,k), H1(j,k), H2(j,k), H3(j,k), E0(j,k), E1(j,k), E2(j,k), E3(j,k), F0(j,k), F1(j,k), F2(j,k), F3(j,k), S0(j+1,k+1), S1(j+1,k+1), S2(j+1,k+1), and S3(j+1,k+1). In the same or other embodiments, H0(j,k), H1(j,k), H2(j,k), and H3(j,k) are compressed into a single 32-bit value, which can be accessed as H(j,k). In some embodiments, E0(j,k), E1(j,k), E(j,k), and E3(j,k) are compressed into a single 32-bit value that can be accessed as E(j,k). In some embodiments, F0(j,k) and F1(j,k) are compressed into a single 32-bit value that can be accessed as F(j,k). In some embodiments, S0(j+1,k+1) and S1(j+1,k+1) are compressed into a single 32-bit value that can be accessed as S(j,k). In some other embodiments, the order of the 32-bit values ​​H(j,k), E(j,k), F(j,k), and S(j+1,k+1) within SWcell8 466(j,k) can be varied. In the same or other embodiments, the order of H0(j,k), H1(j,k), H2(j,k), and H3(j,k) in H(j,k); the order of E0(j,k), E1(j,k), E2(j,k), and E3(j,k) in E(j,k); the order of F0(j,k), F1(j,k), F2(j,k), and F3(j,k) in F(j,k); the order of S0(j+1,k+1), S1(j+1,k+1), S2(j+1,k+1), and S3(j+1,k+1) in S(j+1,k+1); or any combination thereof can be changed.

[0134] In some embodiments, Figure 1 The programming platform software stack 160 includes an SW kernel 192 and / or one or more SW libraries, including but not limited to one or more mappings that facilitate writing data to and reading data from SWcell 460. SWcell32 462, SWcell16 464, and SWcell8 462. For example, in some embodiments, the SW kernel 192 and / or one or more SW libraries include the following type definition (2):

[0135]

[0136]

[0137] In the same or other embodiments, Figure 1 the programming platform software stack 160 including the SW core 192 and / or one or more SW libraries includes, but is not limited to, one or more mappings that facilitate non-SIMD, two-way SIMD and four-way SIMD operations involving the gap constant 442. For example, in some embodiments, the SW core 192 and / or one or more SW libraries include the following type definition (3):

[0138]

[0139]

[0140] In some embodiments, each thread stores the information required to calculate the sub-alignment data corresponding to the assigned columns of the scoring matrix through the matrix filling dataset 490(0), and the thread reuses this dataset for each row 0<=j<M. With reference to equations (1a)-(1c) in conjunction with the arrows superimposed on the matrix filling dataset 490(0), H(j,k) stored in SWcell 460(j,k) depends on H(j-k-1) and S(j,k) stored in SWcell 460(j-1,k-1), E(j-1,k) and H(j-1,k) stored in SWcell 460(j-1,k), and F(j,k-1) and H(j,k-1) stored in SWcell 460(j,k-1).

[0141] For illustrative purposes only, Figure 4The matrix-filled dataset 490(0) depicted corresponds to thread 0, which computes the sub-aligned data of columns 1 to C of the scoring matrix corresponding to the query symbols Q*(0) to Q*(C-1), respectively. For illustrative purposes, for thread-computed SIMD modes without SIMD, dual-path SIMD, and quad-path SIMD, Q* represents Q0, Q0-Q1, and Q0-Q3, respectively, and T* represents T0, T0-T1, and T0-T3, respectively. As shown, in some embodiments, the matrix-filled dataset 490(0) includes, but is not limited to, two arrays of (C+1) SWcells 460 residing in consecutive register locations or consecutive memory locations. One array corresponds to the target symbol T*(j-1) and includes, but is not limited to, SWcell 460(0,0) included in the initial column and SWcells 460(0,1) to 460(0,C) corresponding to the query symbols Q*(0) to Q*(C-1), respectively. Another array corresponds to the target symbol T*(j) and includes, but is not limited to, SWcell 460(1,0) included in the initial column and SWcell460(1,1) to 460(1,C) corresponding to the query symbols Q*(0) to Q*(C-1) respectively.

[0142] Although not shown, in some embodiments, each thread maintains a "current row" register variable pointing to an array of SWcell 460 corresponding to the current row and a "previous row" register variable pointing to an array of SWcell 460 corresponding to the previous row. After calculating the sub-alignment data for the current row, the thread updates the current row register variable and the previous row register variable such that the previous row register variable points to the array of SWcell 460 previously pointed to by the current row register, and the current row register variable points to the array of SWcell 460 previously pointed to by the previous row register. Threads can swap the designations of the current row and the previous row in any technically feasible manner.

[0143] In some embodiments, in order to swap the current row and previous row specifications of rows 1 to M of the scoring matrix corresponding to the target symbols T*(0) to T*(M-1), the SW kernel 192 implements the following pseudocode (4):

[0144]

[0145] Note that for pseudocode (4), each even-numbered row of the rating matrix (including the initialization row) is represented by an array of cells starting from the initial cell represented as cell [0, 0]. In the same or other embodiments, each odd-numbered row of the rating matrix is ​​represented by an array of cells starting from the initial cell represented as cell [1, 0].

[0146] Advantageously, because each thread computes the sub-aligned data of the current row from left to right, the correlation of H(j,k) is automatically satisfied by matrix filling of dataset 490(0) and current row / previous row swapping techniques without the need to execute arbitrary memory move instructions.

[0147] Figure 5 It is based on various other embodiments and Figure 1 An example illustration of SW data 402(1) associated with SW kernel 192. More specifically, SW data 402(1) illustrates, but is not limited to, data associated with a single thread executing SW kernel 192 and with a (M+1)x(N+1) scoring matrix corresponding to the maximum values ​​of M target symbols and N query symbols, where M and N can be any positive integers. In some embodiments, including Figure 5 In the embodiment described, SW data 402(1) is optimized for a scoring matrix traversal pattern, wherein each thread computes sub-aligned data for the allocated column set of row j before computed sub-aligned data for the allocated column set of row j+1, where j is an integer from 1 to M.

[0148] As shown in the figure, in some embodiments, SW data 402(1) includes, but is not limited to, problem configuration data 410, SW input data 430, staggered cell layout 450(1), matrix filling dataset 490(1), and result dataset 492(0). As shown in the dashed box, if the threaded computation mode is dual-path SIMD or quad-path SIMD, then SW data 402(1) also includes, but is not limited to, result dataset 492(1). As depicted by the two dashed boxes, if the threaded computation model is quad-path SIMD, then SW data 402(1) also includes, but is not limited to, result dataset 492(3) and result dataset 492(3).

[0149] In some embodiments, the problem configuration data 410, SW input data 430, and result datasets 492(0)-492(3) included in SW data 402(1) are the same as the problem configuration data 410, SW input data 430, and result datasets 492(0)-492(3) included in SW data 402(0) and are combined prior to this document. Figure 4 As described. The amount of memory required to store the staggered cell layout 450(1) and the matrix-filled dataset 490(1) included in SW data 402(1) is reduced compared to the staggered cell layout 450(0) and the matrix-filled dataset 490(0) included in SW data 402(0).

[0150] As shown in the figure, in some embodiments, each thread temporarily stores sub-alignment data (e.g., E-values, F-values, replacement values, and sub-alignment values) based on an interleaved cell layout 450(1). The interleaved cell layout 450(1) enables threads to compute relevant sub-alignment data without performing any data movement operations. In some embodiments, each thread temporarily stores the sub-alignment scores and E-values ​​of the (C+1) column of the previous row and the (C+1) column of the current row in up to two HEcell 560 arrays located in adjacent register or memory locations. Each thread temporarily stores the F-value of the (C+1) column of the current row in an array of F structures 570 residing in contiguous register or memory locations. In the same or other embodiments, for performance reasons, each thread temporarily stores the replacement value of the C column of the current row in an array of S structures 580 residing in contiguous register or memory locations. In some other embodiments, each thread temporarily stores a single replacement value in a single instance of an S structure 580 residing in a register or memory. In some embodiments, if the thread computes the SIMD mode as dual-path SIMD or quad-path SIMD, each thread compresses two or four values ​​into the same number of bits to represent a single value when the thread computes the SIMD mode as non-path SIMD.

[0151] As shown in the figure, when the thread computes the SIMD mode without SIMD, each HEcell 560 is an HEcell32 562, which stores two 32-bit values ​​corresponding to a single local alignment problem. Each F structure 570 is an F32 572, which stores a 32-bit F value corresponding to the same local alignment problem. Each S structure 580 is an S32 582, which stores a 32-bit S value corresponding to the same local alignment problem. In the same or other embodiments, HEcell32 562 stores a 32-bit E value spanning 32 bits of E data and a 32-bit sub-alignment score spanning 32 bits of sub-alignment score data. As described earlier in this document, due to the offset in the scoring matrix introduced by the initial rows and initial columns, HEcell32 562(j,k), F32 572(k), and S32 582(k) correspond to the subsequences ending with the symbols T0(j-1) and Q0(k-1). In some embodiments, HEcell32 562(j,k) includes, but is not limited to, a sub-alignment fraction H(j,k) following E(j,k). In some other embodiments, HEcell32 562(j,k) includes, but is not limited to, a sub-alignment fraction H(j,k) following E(j,k).

[0152] As shown in the figure, when the thread computes SIMD in dual-path SIMD mode, each HEcell 560 is an HEcell16564, storing four 16-bit values ​​corresponding to two local alignment problems; each F structure 570 is an F16x2 574, storing two 16-bit F values ​​corresponding to two local alignment problems; and each S structure 580 is an S16x2 584, storing two 16-bit S values ​​corresponding to two local alignment problems. In the same or other embodiments, HEcell16 564 stores two 16-bit E values ​​across 32-bit E data and two 16-bit sub-alignment scores across 32-bit sub-alignment score data. HEcell16 564(j,k), F16x2 574(k), and S16x2 584(k) correspond to subsequences ending with the symbols T0(j-1), Q0(k-1), T1(j-1), and Q1(k-1).

[0153] In some embodiments, HEcell16 564(j,k) includes, but is not limited to, H0(j,k), H1(j,k), E0(j,k), and E1(j,k). In the same or other embodiments, H0(j,k) and H1(j,k) are compressed into a single 32-bit value that can be accessed as H(j,k). In some embodiments, E0(j,k) and E1(j,k) are compressed into a single 32-bit value that can be accessed as E(j,k). In some other embodiments, the order of the 32-bit values ​​H(j,k) and E(j,k) within HEcell16 564(j,k) can vary. In the same or other embodiments, the order of H0(j,k) and H1(j,k) within H(j,k), the order of E0(j,k) and E1(j,k) within E(j,k), or any combination thereof can be interchanged.

[0154] As shown in the figure, when the thread computes SIMD in four-way SIMD mode, each HEcell 560 is an HEcell8566, storing eight 8-bit values ​​corresponding to four local alignment problems; each F structure 570 is an F8x4 576, storing four 8-bit F values ​​corresponding to four local alignment problems; and each S structure 580 is an S8x4 586, storing four 8-bit S values ​​corresponding to four local alignment problems. In the same or other embodiments, HEcell8 566 stores four 8-bit E values ​​across 32-bit E data and four 8-bit sub-alignment scores across 32-bit sub-alignment score data. HEcell8 566(j,k), F8x4 576(k), and S8x4 586(k) correspond to subsequences ending with the symbols T0(j-1), Q0(k-1), T1(j-1), Q1(k-1), T2(j-1), Q2(k-1), T3(j-1), and Q3(k-1).

[0155] In some embodiments, HEcell8 566(j,k) includes, but is not limited to, H0(j,k), H1(j,k), H2(j,k), H3(j,k), E0(j,k), E1(j,k), E2(j,k), and E3(j,k). In the same or other embodiments, H0(j,k), H1(j,k), H2(j,k), and H3(j,k) are compressed into a single 32-bit value, which can be accessed as H(j,k). In some embodiments, E0(j,k), E1(j,k), E(j,k), and E3(j,k) are compressed into a single 32-bit value, which can be accessed as E(j,k). In some embodiments, F0(j,k) and F1(j,k) are compressed into a single 32-bit value, which can be accessed as F(j,k). In some embodiments, the order of H0(j,k), H1(j,k), H2(j,k) and H3(j,k) in H(j,k); the order of E0(j,k), E1(j,k), E2(j,k) and E3(j,k) in E(j,k); or any combination thereof can be changed.

[0156] In some embodiments, including Figure 1 The programming platform software stack 160 includes, but is not limited to, one or more SW kernels 192 and / or one or more SW libraries, including but not limited to one or more mappings that facilitate writing data to and reading data from HEcell 560, HEcell32 562, HEcell16 564, and HEcell8 566. In the same or other embodiments, including... Figure 1 The SW kernel 192 and / or one or more SW libraries in the programming platform software stack 160 include, but are not limited to, one or more mappings that facilitate SIMD-free, dual-path SIMD, and quad-path SIMD operations involving a gap constant 442. For example, in some embodiments, the SW kernel 192 and / or one or more SW libraries include those previously mentioned herein. Figure 4 The type definition described (3).

[0157] In some embodiments, each thread stores, via the matrix fill data set 490(1), the information required to compute sub-alignment data corresponding to the assigned columns of the scoring matrix, and the thread reuses this data set for each row where 0<=j<M. With reference to equations (1a)-(1c) in conjunction with the arrows overlaid on the matrix fill data set 490(1), H(j,k) stored in HEcell 560(j,k) depends on H(j-1,k-1) stored in HEcell 560(j-1,k-1), E(j-1,k) and H(j-1,k) stored in HEcell 560(j-1,k-1), H(j,k-1) stored in HEcell 560(j-1,k-1), S(j,k) and F(j,k-1).

[0158] For illustrative purposes only, Figure 5 the matrix fill data set 490(1) described in corresponds to thread 0, which computes sub-alignment data for columns 1-C of the scoring matrix respectively corresponding to query symbols Q*(0)-Q*(C-1). As shown in the figure, in some embodiments, the matrix fill data set 490(1) includes, but is not limited to, two arrays of (C+1) HEcells 560 residing in consecutive register locations or consecutive memory locations, F structures 570(0)-570(C) residing in consecutive register locations or consecutive memory locations, and S structures 580(1)-580(C) residing in consecutive register locations or consecutive memory locations. One array of HEcells 560 corresponds to the target symbol T*(j-1), and includes, but is not limited to, HEcell 560(0,0) included in the initial column and HEcells 560(0,1)-560(0,C) respectively corresponding to query symbols Q*(0)-Q*(C-1). The other array of HEcells 560 corresponds to the target symbol T*(j), and includes, but is not limited to, HEcell 560(1,0) included in the initial column and HEcells 560(1,1)-560(1,C) respectively corresponding to query symbols Q*(0)-Q*(C-1). F structure 570(0) corresponds to the initial column, and F structures 570(1)-570(C) respectively correspond to query symbols Q*(0)-Q*(C-1). S structures 580(1)-580(C) respectively correspond to query symbols Q*(0)-Q*(C-1).

[0159] Relative to the earlier part of this document in conjunction with Figure 4The described matrix-filled dataset 490(0) and matrix-filled dataset 490(1) store (2C+3)*32 fewer bits in the register file. For example, if thread 0 is allocated 100 columns and uses matrix-filled dataset 490(1) instead of matrix-filled dataset 490(0) to store sub-aligned data, then thread 0 will store 6496 bits in the register file.

[0160] Although not shown, in some embodiments, each thread maintains a "current row" register variable pointing to the HEcell 560 array corresponding to the current row and a "previous row" register variable pointing to the HEcell 560 array corresponding to the previous row. After calculating the sub-alignment data for the current row, the thread updates the current row register variable and the previous row register variable such that the previous row register variable points to the HEcell 560 array previously pointed to by the current row register, and the current row register variable points to the HEcell 560 array previously pointed to by the previous row register. Threads can swap the designations of the current row and the previous row in any technically feasible manner. Advantageously, because each thread calculates the sub-alignment data for the current row from left to right, the correlation of H(j,k) is automatically satisfied by matrix filling dataset 490(1) and the current row / previous row swapping technique without executing any memory move instructions.

[0161] Specialized instructions for Smith-Waterman calculations

[0162] Figure 6 The diagram illustrates various embodiments of the invention. Figure 1 The SW kernel executes the SW instruction 610. In some embodiments, the SW instruction 610 is a per-thread instruction issued and executed in a SIMT manner. As mentioned earlier in this document... Figures 3A-3B As noted, in some embodiments, each SM 310 may issue and execute SW instructions 610 in any technically feasible manner.

[0163] As depicted in SW instruction description 614, in some embodiments, SW instruction 610 is a per-thread instruction for computing SW sub-alignment data. In the same or other embodiments, SW instruction 610 generates sub-alignment data associated with a single position in a scoring matrix. In some embodiments, SW instruction 610 supports, but is not limited to, multiple SIMD variants, data types / sizes, or any combination thereof.

[0164] In some embodiments, a SIMD-free variant of the SW instruction 610 operates on 32-bit data to generate sub-alignment data associated with a single location for a single local alignment problem. In the same or other embodiments, a dual-SIMD variant of the SW instruction 610 operates on 16-bit data to generate sub-alignment data associated with a single location and two local alignment problems. In some embodiments, a quad-SIMD variant of the SW instruction 610 operates on 8-bit data to generate sub-alignment data associated with a single location and four local alignment problems.

[0165] As shown in the figure, in some embodiments, the SW instruction format 612 is “SW{.variant}result,diag,top,left,consts”. Therefore, each SW instruction 610 includes, but is not limited to, the instruction name “SW”, the optional .variant modifier, the destination address result, and the source addresses diag, top, left, and consts. In some embodiments, the .variant modifier represents a SIMD variant. In the same or other embodiments, allowed values ​​for the .variant modifier include, but are not limited to, 1, 2, and 4, which represent no SIMD, dual-channel SIMD, and quad-channel SIMD, respectively.

[0166] In some embodiments, the SW instruction 610 is designed to operate on operands having an interleaved cell layout 450(0), and the operands result, diag, top, and left specify the location of SWcell 460 residing in a register. In some embodiments, the operand consts is the address of a set of constants, including but not limited to GapDeleteOpen, GapDeleteExtend, GapInsertOpen, and GapInsertExtend. In the same or more embodiments, the operand consts specifies the location of gap constant 442 residing in a unified register, constant memory, or register.

[0167] In some embodiments, the SW instruction 610 computes data for the SWcell 460 specified by the operand result based on per-thread input from the SWcell 460 specified by the diag, top, and left operands, and a constant input consistent across all threads and specified by the operand consts. In some embodiments, the per-thread correlation 602 graphically depicts the per-thread input data read by the SW instruction 610 from the SWcell 460 corresponding to the diag, top, and left operands, and the output data computed and written by the SW instruction 610 to the SWcell 460 corresponding to the result operand. As shown, the result, diag, top, and left operands correspond to SWcell 460(j, k), 460(j-1, k-1), 460(j-1, k), and 460(j, k-1), respectively. In some embodiments, based on H(j-1,k-1) and S(j,k) in SWcell 460(j-1,k-1), H(j-1,k) and E(j-1,k) in SWcell 460(j-1,k), and G(j,k-1) and F(j,k-1) in SWcell 460(j,k-1), the SW instruction 610 calculates E(j,k), F(j,k), and H(j,k) in SWcell 460(j,k-1). The SW instruction 610 can cause the SM 310 to calculate E(j,k), F(j,k), and H(j,k) in any technically feasible manner.

[0168] The pseudocode 630 of the SW instruction illustrates an exemplary operation that, in some embodiments, can be performed by the SM 310 when the SW instruction 610 is executed. In some embodiments, if the .variant modifier is 1, the thread executing on the SM 310 performs the following calculations (5a)-(5c):

[0169] result.E=max(top.E–consts.gde,top.H–consts.gdo); (5a)

[0170] result.F=max(left.F–consts.gie,left.H–consts.gio); (5b)

[0171] result.H=max(result.E,result.F,diag.H+diag.S,0); (5c)

[0172] In some embodiments, if the .variant modifier is 2, then SM 310 performs the following calculations (6a)-(6f):

[0173] result.E0=max(top.c16.E0–consts.gde,top.c16.H0–consts.gdo); (6a)

[0174] result.F0=max(left.c16.F0–consts.gie,left.c16.H0–consts.gio); (6b)

[0175]

[0176] result.E1=max(top.c16.E1–consts.gde,top.c16.H1–consts.gdo); (6d)

[0177] result.F1=max(left.c16.F1–consts.gie,left.c16.H1–consts.gio); (6e)

[0178]

[0179] Although not shown, in some embodiments, if the .variant modifier is 4, then SM 310 performs the following calculations (7a)-(7l):

[0180] result.E0=max(top.c8.E0–consts.gde,top.c8.H0–consts.gdo); (7a)

[0181] result.F0=max(left.c8.F0–consts.gie,left.c8.H0–consts.gio); (7b)

[0182]

[0183] result.E1=max(top.c8.E1–consts.gde,top.c8.H1–consts.gdo); (7d)

[0184] result.F1=max(left.c8.F1–consts.gie,left.c8.H1–consts.gio); (7e)

[0185]

[0186] result.E2=max(top.c8.E2–consts.gde,top.c8.H2–consts.gdo); (7g)

[0187] result.F2=max(left.c8.F2–consts.gie,left.c8.H2–consts.gio); (7h)

[0188]

[0189] result.E3=max(top.c8.E3–consts.gde,top.c8.H3–consts.gdo); (7j)

[0190] result.F3=max(left.c8.F3–consts.gie,left.c8.H3–consts.gi (7k)

[0191]

[0192] Advantageously, and as depicted in SW instruction improvement table 690, SW instruction 610 requires fewer instructions and fewer cycles than the conventional 10 instruction sequence to compute sub-alignment data associated with a single position in the scoring matrix. For illustrative purposes, in Figure 6 In the context of this document, the required number of cycles is based on an embodiment of the four-cycle throughput of the SW instruction 610. In other embodiments, the cycle throughput of the SW instruction 610 and therefore the required number of cycles may differ.

[0193] As shown in the figure, in some embodiments, to compute sub-alignment data associated with a single position in the scoring matrix for a single local alignment problem (corresponding to the SIMD-free variant), a conventional 10-instruction sequence requires 10 instructions and 10 cycles, while the SW instruction 610 requires 1 instruction and 4 cycles. Compared to the conventional 10-instruction sequence, the SIMD-free variant of the SW instruction 610 can thus reduce instructions by 90% and cycles by 60%.

[0194] In some embodiments, to compute the sub-alignment data associated with a single position in the scoring matrix of two local alignment problems (corresponding to the dual-path SIMD variant), a conventional 10-instruction sequence requires 20 instructions and 20 cycles, while the SW instruction 610 requires one instruction and four cycles. The dual-path SIMD variant of the SW instruction 610 thus reduces instructions by 95% and cycles by 80% compared to the conventional 10-instruction sequence.

[0195] In some embodiments, to compute sub-alignment data associated with a single position in the scoring matrix for four local alignment problems (corresponding to the four-way SIMD variant), a conventional 10-instruction sequence requires 30 instructions and 30 cycles, while the SW instruction 610 requires one instruction and four cycles. The four-way SIMD variant of the SW instruction 610 thus reduces instructions by 96% and cycles by 86% compared to the conventional 10-instruction sequence.

[0196] Note that the techniques described herein are illustrative and not restrictive, and modifications can be made without departing from the broader spirit and scope of the invention. Many modifications and variations to the functionality provided by SM 310, SW instruction 610, and SW kernel 192 will be readily apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. For example, in some other embodiments, variants of SW instruction 610 can operate on operands having a layout different from the staggered cell layout 450(0), different SIMD variants with different data types / formats, E values, F values, substitution values, and sub-alignment fractions.

[0197] Figure 7 The following are illustrations based on various other embodiments. Figure 1 The SW kernel 192 executes the SW sequence 740. In some embodiments, the SW sequence 740 is a per-thread sequence of six instructions for computing SW sub-alignment data. In the same or other embodiments, the SW sequence 740 generates sub-alignment data associated with a single position in the scoring matrix. In some embodiments, the SW sequence 740 supports, but is not limited to, multiple SIMD variants, data types / sizes, or any combination thereof.

[0198] In some embodiments, a SIMD-free variant of the SW sequence 740 operates on 32-bit data to generate sub-alignment data associated with a single location for a single local alignment problem. In the same or other embodiments, a dual-SIMD variant of the SW sequence 740 operates on 16-bit data to generate sub-alignment data associated with a single location and two local alignment problems. In some embodiments, a quad-SIMD variant of the SW sequence 740 operates on 8-bit data to generate sub-alignment data associated with a single location and four local alignment problems.

[0199] As shown in the figure, in some embodiments, the SW sequence 740 includes three VIADD instructions, two VIADDMNMX instructions, and one VIAMNMX3 instruction. In some embodiments, each VIADD instruction, VIADDMNMX instruction, and VIAMNMX3 instruction is a per-thread instruction issued and executed in a SIMT manner. In some embodiments, each SM 310 may issue and execute each VIADD instruction, VIADDMNMX instruction, and VIAMNMX3 instruction in any technically feasible manner.

[0200] In some embodiments, each VIADD instruction, VIADDMNMX instruction, and VIMNMX3 instruction supports, but is not limited to, multiple SIMD variants, data types / sizes, or any combination thereof. In some embodiments, each SIMD-free variant of the VIADD instruction, VIADDMNMX instruction, and VIMNMX3 instruction operates on a 32-bit integer to produce a single 32-bit result. In the same or other embodiments, each dual-path SIMD variant of the VIADD instruction, VIADDMNMX instruction, and VIMNMX3 instruction operates on a 16-bit integer to produce two 16-bit integers compressed into a 32-bit result. In some embodiments, a quad-path SIMD variant of the SW instruction 610 operates on an 8-bit integer to produce four 8-bit integers compressed into a 32-bit result.

[0201] In some embodiments, VIADD is an integer addition instruction executed in the floating-point (FP) pipeline of the SM 310. Advantageously, in some embodiments, the SM 310 can issue and execute integer instructions in parallel with floating-point instructions. Therefore, executing the VIADD instruction in the FP pipeline can increase the overlap / pipelining of multiple instructions, thereby increasing the overall computational throughput.

[0202] As shown in the figure, in some embodiments, the VIADD instruction format 710 is "VIADD{.fmt}result,source_a,{-}source_b". Therefore, each VIADD instruction includes, but is not limited to, the instruction name "SW", the optional .fmt modifier, result, source_a, and the optional negated source_b. result is the target operand and the instruction result. source_a and source_b are the source operands. In some embodiments, the allowed values ​​for the .fmt modifier include, but are not limited to, .32, .16x2, and .8x4, corresponding to a 32-bit integer (no SIMD), compressed data including two 16-bit integers (dual-channel SIMD), and four 8-bit integers (quad-channel SIMD), respectively. The VIADD instruction allows the SM 310 to implement result = source_a + {-}source_b in any technically feasible manner.

[0203] In some embodiments, the VIADD instruction causes SM 310 to set each element in the result to the sum of the corresponding element in source_a and the corresponding element in source_b (which can be selected as the inverse). If the .fmt modifier is .32, then result, source_a, and source_b each include a 32-bit integer element. If the .fmt modifier is .16, then result, source_a, and source_b each include two elements, each of which is a 16-bit integer. If the .fmt modifier is .8, then result, source_a, and source_b each include four elements, each of which is an 8-bit integer.

[0204] In the same or other embodiments, the operation that can be performed by SM 310 to execute the VIADD instruction is illustrated by the following exemplary pseudocode (8):

[0205]

[0206]

[0207] In some embodiments, the VIADDMNMX instruction is an integer addition, minimum / maximum value comparison, and optionally executes against zero instructions executed in the integer pipeline of the SM310. It is noteworthy that the VIADDMNMX instruction combines multiple regular instructions into a single instruction. As shown in the figure, in some embodiments, the VIADDMNMX instruction format 720 is “VIADDMNMX{.fmt}{.relu}result,source_a,{-}source_b,source_c,min_or_max”. Therefore, each VIADDMNMX instruction includes, but is not limited to, the instruction name “VIADDMNMX”, the optional .fmt modifier, the optional .relu modifier, result, source_a, the optional inverse source_b, source_c, and the optional min_or_max specifier. result is the target operand and the instruction result. source_a, source_b, and source_c are the source operands. The min_or_max specifier specifies whether the VIADDMNMX instruction performs a minimum or maximum comparison. In some embodiments, the allowed value modifiers for .fmt include, but are not limited to, “.U32”, “.S32”, “.U16x2”, “.S16x2”, “.U16x2”, “.U8x4”, and “.S8x4”, respectively, corresponding to a 32-bit unsigned integer, a 32-bit signed integer, compressed data including two 16-bit unsigned integers, compressed data including four 8-bit unsigned integers, and compressed data including four 8-bit signed integers. In the same or other embodiments, if the optional .relu modifier is present, the VIADDMNMX instruction performs a max / min operation against 0.

[0208] In some embodiments, the VIADDMNMX instruction causes SM 310 to set each element in the result to equal to the minimum or maximum value of the corresponding element in source_c, the sum of the corresponding element in source_a and the optionally inverse corresponding element in source_b, and optionally zero. If the .fmt modifier is .32, then result, source_a, source_b, and source_c each include a 32-bit integer element. If the .fmt modifier is .16, then result, source_a, source_b, and source_c each include two elements, each of which is a 16-bit integer. If the .fmt modifier is .8, then result, source_a, source_b, and source_c each include four elements, each of which is an 8-bit integer.

[0209] In the same or other embodiments, the operation that can be performed by SM 310 executes the VIADDMNMX instruction, which is illustrated by the following exemplary pseudocode (8):

[0210]

[0211]

[0212]

[0213] In some embodiments, the VIMNMX3 instruction is optionally an integer three-operand minimum / maximum operation performed against a zero instruction executed in the integer pipeline of the SM 310. It is noteworthy that the VIMNMX3 instruction adds at least a third operand to the regular minimum / maximum operation instruction. As shown, in some embodiments, the VIMNMX3 instruction format 730 is “VIMNMX3{.fmt}{.relu}result,source_a,source_b,source_c,min_or_max”. Therefore, each VIMNMX3 instruction includes, but is not limited to, the instruction name “VIMNMX3”, the optional .fmt modifier, the optional .relu modifier, result, source_a, source_b, source_c, and the optional min_or_max specifier. result is the target operand and the instruction result. source_a, source_b, and source_c are the source operands. The min_or_max specifier specifies whether the VIMNMX3 instruction calculates the minimum or maximum value of source_a, source_b, and source_c. In some embodiments, the allowed values ​​for the .fmt modifier include, but are not limited to, ".U32", ".S32", ".U16x2", ".S16x2", ".U16x2", ".S16x2", ".U8x4", and ".S8x4", respectively, corresponding to a 32-bit unsigned integer, a 32-bit signed integer, compressed data including two 16-bit unsigned integers, compressed data including four 8-bit unsigned integers, and compressed data including four 8-bit signed integers. In the same or other embodiments, if the optional .relu modifier is present, the VIMNMX3 instruction performs a max / min operation against 0.

[0214] In some embodiments, the VIMNMX3 instruction causes SM 310 to set each element in the result to the minimum or maximum value of the corresponding element in source_a, the minimum or maximum value of the corresponding element in source_b, the minimum or maximum value of the corresponding element in source_c, and optionally 0. If the .fmt modifier is .32, then result, source_a, source_b, and source_c each include a 32-bit integer element. If the .fmt modifier is .16, then result, source_a, source_b, and source_c each include two elements, each of which is a 16-bit integer. If the .fmt modifier is .8, then result, source_a, source_b, and source_c each include four elements, each of which is an 8-bit integer.

[0215] In some embodiments, operations executable by SM 310 perform VIMNMX3 instructions, which are illustrated by the following exemplary pseudocode (10):

[0216]

[0217]

[0218] In some embodiments, because the SIMD-free, dual-SIMD, and quad-SIMD variants support VIADD, VIADDMNMX, and VIMNMX3 instructions, each of the SIMD-free SW sequence 742, dual-SIMD SW sequence 744, and quad-SIMDSW sequence 746 includes, but is not limited to, six instructions. In some other embodiments, the SW sequence 740 includes, but is not limited to, six instructions for each SIMD variant that supports VIADD, VIADDMNMX, and VIMNMX3 instructions.

[0219] SIMD-free SW sequence 742, dual-SIMD SW sequence 744, and quad-SIMD SW sequence 746 are different variations of SW sequence 740. In some embodiments, regardless of the SIMD variant, SW sequence 740 is a sequence of six instructions. In some embodiments, SW sequence 740 consists of a first VIADD instruction executed in the FP pipeline, a first VIADDMNMX instruction executed in the integer pipeline, a second VIADD instruction executed in the FP pipeline, a second VIADDMNMX instruction executed in the integer pipeline, a third VIADD instruction executed in the FP pipeline, and a VIMNMX3.RELU instruction executed in the integer pipeline. As previously described herein, in some embodiments, executing three VIADD instructions in the FP pipeline and three other instructions in the integer pipeline can increase the overlap / pipelining of multiple instructions and thus increase overall computational throughput.

[0220] Figure 7 The SIMD-free SW sequence 742 depicted is an exemplary instruction sequence that operates on 32-bit data to generate sub-alignment data associated with a single location for a single local alignment problem. As shown, in some embodiments, the first VIADD.32 instruction in the SIMD-free SW sequence 742 executes in the integer pipeline and sets temp1 to equal E_top + gde. The first VIADDMNMX.S32 instruction in the SIMD-free SW sequence 742 executes in the FP pipeline and sets E to the maximum value between (H_top + gde) and temp1. The second VIADD.32 instruction in the SIMD-free SW sequence 742 executes in the integer pipeline and sets temp2 to equal F_left + gie. The second VIADDMNMX.S32 instruction in the SIMD-free SW sequence 742 executes in the integer pipeline and sets F to the maximum value between (H_left + gie) and temp2. ​​The third VIADD.32 instruction in the SIMD-free SW sequence 742 executes in the integer pipeline and sets temp3 to equal H_diag + S. The VIMNMX3.S32.RELU instruction in SIMD SW sequence 742 is executed in the FP pipeline and sets H to the maximum value among temp1, temp2, temp3, and 0.

[0221] Figure 7The dual-channel SIMD SW sequence 744 depicted is an exemplary instruction sequence that operates on 16-bit data to generate sub-alignment data associated with a single location and two local alignment issues. The SIMD-free instruction variants VIADD.32, VIADDMNMX.S32, and VIAMNMX3.S32.RELU are replaced by the dual-channel SIMD instruction variants VIADD.16X2, VIADDMNMX.S16X2, and VIAMNMX3.S16X2.RELU, respectively, in relation to the no-SIMD SW sequence 742.

[0222] Figure 7 The four-way SIMD SW sequence 746 depicted is an exemplary instruction sequence that operates on 8-bit data to generate sub-alignment data associated with a single location and four local alignment problems. The SIMD instruction variants VIADD.32, VIADDMNMX.S32, and VIAMNMX3.S32.RELU are replaced by the four-way SIMD instruction variants VIADD.8X4, VIADDMNMX.8X4, and VIAMNMX3.8X4.RELU, respectively, in relation to the no-SIMD SW sequence 742.

[0223] Advantageously, and as depicted in the SW sequence improvement table 790, the SW sequence 740 requires fewer instructions and fewer cycles than a conventional 10-instruction sequence to compute sub-alignment data associated with a single position in the scoring matrix. For illustrative purposes, in Figure 7 In the context of this document, the required number of cycles described is based on an embodiment with one cycle per instruction throughput. In other embodiments, the instruction cycle throughput and therefore the required number of cycles may vary.

[0224] As shown in the figure, in some embodiments, to compute sub-alignment data associated with a single position in the scoring matrix for a single local alignment problem (corresponding to the SIMD-free variant), a conventional 10-instruction sequence requires 10 instructions and 10 cycles, while the SIMD-free SW sequence 742 requires six instructions and six cycles. Compared to the conventional 10-instruction sequence, the SIMD-free SW sequence 742 can therefore reduce the number of instructions and cycles by 40%.

[0225] In some embodiments, to compute sub-alignment data associated with a single position in the scoring matrix of two local alignment problems (corresponding to a dual-path SIMD variant), a conventional 10-instruction sequence requires 20 instructions and 20 cycles, while the dual-path SIMD SW sequence 744 requires six instructions and six cycles. The dual-path SIMD SW sequence 744 thus reduces instructions and cycles by 70% compared to the conventional 10-instruction sequence.

[0226] In some embodiments, to compute sub-alignment data associated with a single position in the scoring matrix for four local alignment problems (corresponding to a four-way SIMD variant), a conventional 10-instruction sequence requires 30 instructions and 30 cycles, while the four-way SIMD SW sequence 746 requires six instructions and six cycles. The four-way SIMD SW sequence 746 thus reduces instructions and cycles by 80% compared to a conventional 10-instruction sequence.

[0227] In some embodiments, including Figure 7 In the embodiments described, the source operands and destination operands of the VIADD, VIADDMNMX, and VIMNMX3 instructions are compared with... Figure 4 staggered cell layout 450(0) and Figure 5 Both the staggered cell layout 450(1) and the other are compatible. In some embodiments, the SW kernel 192 executes the SW sequence 740, which includes, but is not limited to, VIADD, VIADDMNMX, and VIAMNMX3 instructions specifying one or more operands included in one or more SWcells 460. In embodiments, the SW kernel 192 executes the SW sequence 740, which includes, but is not limited to, VIADD, VIADDMNMX, and VIAMNMX3 instructions specifying one or more operands included in one or more HEcells 560.

[0228] In some embodiments, SW kernel 192, one or more other kernels, one or more SW libraries, or any combination thereof, including but not limited to one or more intrinsic functions, calculate sub-aligned data corresponding to various parts (e.g., individual positions, rows, line segments, wholes) of the scoring matrix of any number of SIMD variants, based on SW instruction 610 and staggered cell layout 450(0), SW sequence 740 and staggered cell layout 450(0), SW sequence 740 and staggered cell layout 450(1), or any combination thereof.

[0229] Note that the techniques described herein are illustrative and not restrictive, and modifications can be made without departing from the broader spirit and scope of the invention. Many modifications and variations provided by SM 310, VIADD instructions, VIADDMNMX instructions, VIMNMX3 instructions, SW sequence 740, SIMD-less SW sequence 742, dual-channel SIMD SW sequence 744, quad-channel SIMD SW sequence 746, and SW kernel 192 will be readily apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. For example, in some other embodiments, variants of SW sequence 740 use conventional addition instructions executed in an integer pipeline instead of VIADD instructions. In the same or other embodiments, SIMD-less SW sequence 742, dual-channel SIMD SW sequence 744, and quad-channel SIMD SW sequence 746 can operate on 32-bit integers, two compressed 16-bit integers, and four compressed 8-bit integers, respectively, which are not associated with either interleaved cell layout 450(0) or interleaved cell layout 450(1).

[0230] Figure 8 The minimum / maximum values ​​and their corresponding values ​​according to various embodiments are shown. Figure 1 The source indicator instruction executed by the SW kernel 192. The minimum / maximum value and the corresponding source indicator instruction are VIMNMX instructions 810. In some embodiments, the SW kernel 192 uses VIMNMX instructions 810 to determine the maximum sub-alignment score and the corresponding maximum score column (in the score matrix) and / or the corresponding maximum score row (in the score matrix) for each of any number of local sequence alignment problems.

[0231] Some conventional methods for determining the maximum sub-alignment score and the maximum score position for a single local sequence alignment problem involve executing a conventional maximum score / column sequence 802 or similar instruction sequence for each sub-alignment score. As shown in the figure, the conventional maximum score / column sequence 802 is a three-instruction sequence. The first instruction is the ISETP.GT instruction, which determines whether the current score (denoted as H) is greater than the maximum score (denoted as maxH) and writes the comparison result (denoted as P0) to the predicate register. The second instruction is the SEL instruction, which overwrites the maximum score with the current score if the predicate indicates that the maximum score has been updated. The third instruction is the SEL instruction, which overwrites the maximum score column (denoted as col) with the current column (denoted as col) if the predicate indicates that the maximum score has been updated.

[0232] As shown in the figure, executing the conventional maximum score / column sequence 802 requires 3 instructions and 6 problem slots in the integer pipeline. Although not shown, determining the maximum sub-aligned score and the corresponding maximum score column for the additional local sequence alignment problem corresponding to dual-path SIMD requires additional instructions and additional problem slots in the integer pipeline, compared to the conventional maximum score / column sequence 802. Furthermore, determining the maximum sub-aligned score and the corresponding maximum score column for the additional local sequence alignment problem corresponding to quad-path SIMD requires even more instructions and more problem slots in the integer pipeline.

[0233] In some embodiments, and as depicted via VIMNMX instruction description 814, VIMNMX instruction 810 is a per-thread minimum / maximum instruction that indicates which operands are the source of the minimum / maximum value. In the same or other embodiments, VIMNMX instruction 810 provides a predicate to indicate which operands are the source of the minimum / maximum value. Subsequent instructions can use the predicate to select and store multiple values ​​based on the predicate. Advantageously, VIMNMX instruction 810 can be used to optimize many software applications that store multiple values ​​based on conventional comparison instructions. In some embodiments, SW instruction 610 supports, but is not limited to, multiple SIMD variants, data types / sizes, or any combination thereof.

[0234] As shown in the figure, in some embodiments, the VIMNMX instruction format 812 is “VIMNMX{.fmt}result,pu,pv,px,py,source_a,source_b,min_or_max”. Therefore, each VIMNMX instruction 810 includes, but is not limited to, the instruction name “VIMNMX”; an optional .fmt modifier; and specifiers for result, pu, pv, px, py, source_a, source_b, and min_or_max. In some embodiments, result is the target operand, source_a and source_b are the source operands, and the min_or_max specifier specifies whether the VIMNMX instruction calculates the minimum or maximum value of source_a and source_b.

[0235] In some embodiments, pu, pv, px, and py are predicate values ​​for channels 0-3, respectively. In the same or other embodiments, the allowed values ​​for the .fmt modifier include, but are not limited to, “.U32”, “.S32”, “.U16x2”, “.S16x2”, “.U16x2”, “.S16x2”, “.U8x4”, and “.S8x4”, respectively, corresponding to a 32-bit unsigned integer, a 32-bit signed integer, two compressed 16-bit unsigned integers, two compressed 16-bit signed integers, four compressed 8-bit unsigned integers, and four compressed 8-bit signed integers.

[0236] In some embodiments, the VIMNMX.U32 and VIMNMX.S32 instructions are not SIMD variants of the VIMNMX instruction 810; they set result equal to the minimum / maximum value of source_a and source_b, and indicate whether source_b is the minimum / maximum value via the predicate value pu. In the same or other embodiments, the VIMNMX.U32 and VIMNMX.S32 instructions do not use pv, px, and py. In some embodiments, pv, px, and py can be omitted from the VIMNMX.U32 and VIMNMX.S32 instructions.

[0237] In some embodiments, the VIMNMX.U16x2 and VIMNMX.S16x2 instructions are dual-channel SIMD variants of the VIMNMX instruction 810 that set the first 16 bits of the result equal to the minimum / maximum value of the first 16 bits of source_a and source_b; indicate via the predicate pu whether the first 16 bits of source_b are the minimum / maximum value; set the last 16 bits of the result equal to the minimum / maximum value of the last 16 bits of source_a and source_b; and indicate via the predicate pv whether the last 16 bits of source_b are the minimum / maximum value. In the same or other embodiments, the VIMNMX.U16x2 and VIMNMX.S16x2 instructions do not use px and py. In some embodiments, px and py can be omitted from VIMNMX.U16x2 and VIMNMX.S16x2.

[0238] In the same or other embodiments, the VIMNMX.U8x4 and VIMNMX.S8x4 instructions are four-way SIMD variants of the VIMNMX instruction 810, which determine compressed 8-bit integers corresponding to channels 0-3 and predicate values ​​pu, pv, px, py in the result based on the result, wherein the result is based on the compressed 8-bit integers corresponding to channels 0-3 in source_a and the compressed 8-bit integers corresponding to channels 0-3 in source_b.

[0239] Each SM 310 can issue and execute VIMNMX instructions 810 in any technically feasible manner. In some embodiments, the operation that can be performed by the SM 310 to execute VIMNMX instructions 810 is illustrated by the following exemplary pseudocode (11):

[0240]

[0241]

[0242]

[0243]

[0244] In some embodiments, when calculating each sub-alignment score in an arbitrary number of local sequence alignment problems row by row, the SW kernel 192 implements a maximum score / column sequence 830(0) to determine the maximum sub-alignment score and the corresponding maximum score column (in the score matrix).

[0245] As shown in the figure, the maximum score / column sequence 830(0) is a two-instruction sequence. The first instruction is the VIMNMX instruction 810, which overwrites the maximum score (represented as maxH) with the current score (represented as H) and writes the comparison result (represented as P0) to indicate whether the maximum score has been updated to the predicate register. The second instruction is the SEL instruction, which overwrites the maximum score column (represented as maxHcol) with the current column (represented as col) if the predicate indicates that the maximum score has been updated.

[0246] As shown in the figure, executing the maximum score / column sequence 830(0) requires 2 instructions. The maximum score / column sequence 830(0) requires fewer instructions than the conventional maximum score / column sequence 802. Although not shown, the dual-channel SIMD variant using the VIMNMX instruction 810 requires 3 fewer instructions than two conventional maximum score / column sequences. Furthermore, the quad-channel SIMD variant using the VIMNMX instruction 810 reduces the number of instructions by 5 compared to four conventional maximum score / column sequences.

[0247] In some other embodiments, when calculating each sub-alignment score in an arbitrary number of local sequence alignment problems row by row, the SW kernel 192 implements a maximum score / column sequence 830(1) to determine the maximum sub-alignment score and the corresponding maximum score column (in the score matrix).

[0248] As shown in the figure, the maximum score / column sequence 830(1) is a two-instruction sequence. The first instruction is the VIMNMX instruction 810, which overwrites the maximum score (represented as maxH) with the current score (represented as H) and writes the comparison result (represented as P0) to indicate whether the maximum score has been updated to the predicate register. The second instruction is the predicate BRA instruction, which branches to the code (represented as updateMaxHcol) to update the maximum score column (represented as maxHcol) with the current column (represented as col) if the predicate indicates that the maximum score has been updated.

[0249] As shown in the figure, executing the maximum score / column sequence 830(1) requires two problem slots in the integer pipeline and one problem slot in the branch pipeline. Compared to the conventional maximum score / column sequence 802, the maximum score / column sequence 830(1) requires two fewer problem slots in the integer pipeline, thus increasing the overall computational throughput. Although not shown, the dual-way SIMD variant using the VIMNMX instruction 810 can further increase the overall computation compared to two conventional maximum score / column sequences. And compared to four conventional maximum score / column sequences, the quad-way SIMD variant using the VIMNMX instruction 810 can further increase the overall computation.

[0250] Generally, the VIMNMX instruction 810 performs minimum / maximum operations on 1-4 maximum "base" values ​​and provides 1-4 predicates indicating the comparison results. As shown in the maximum score / column sequence 830(0) and 830(1), using predicates to save other values ​​based on the comparison results can increase computational throughput when saving multiple values ​​based on various types of conventional comparison instructions.

[0251] Figure 9 According to various embodiments, by Figure 1 The example of pseudocode 910 for the two-problem SW execution by the SW kernel 192 is illustrated below. For illustrative purposes, pseudocode 910 for the two-problem SW illustrates the matrix filling phase, where each thread in CTA 312 computes the sub-alignment score, maximum sub-alignment score, maximum score column, and maximum score row for each position in the corresponding scoring matrix. Because each thread computes the sub-alignment score for the two local alignment problems, the thread computed SIMD mode is dual-path SIMD. It is worth noting that pseudocode 1010 for the single-problem SW uses an interleaved cell layout 450(0), SW instruction 610, and VIMNMX instruction 810.

[0252] According to initialization pseudocode 920, SW kernel 192 initializes the result set residing in the register file and two arrays of (N+1) SWcell16 464 residing in the register file. The result set includes, but is not limited to, six 16-bit integers, which correspond to the maximum sub-alignment score, the maximum score column, and the maximum score row for each of the two local alignment problems.

[0253] The SW kernel 192 iterates through the scoring matrix row by row, starting from the row after the initialization row. (As mentioned earlier in this article...) Figure 4 As described, the SW kernel 192 implements a current row / previous row swapping technique to reuse two arrays of SWcell16s 464. Row identifier swapping pseudocode 930 identifies the corresponding part of the two issues in SW pseudocode 910.

[0254] Based on the substitution value assignment pseudocode 940, for all columns in the current row except the initialization column, SW kernel 192 copies the two substitution values ​​from substitution matrix 444 to the appropriate SWcell 16 464. Advantageously, implementing the substitution value loop independently of the sub-alignment loop allows one thread bundle to execute the substitution value loop using a set of instructions (e.g., load, etc.), while another thread bundle executes the main loop using a different set of instructions (e.g., SW.16 instructions, etc.).

[0255] According to the main loop of pseudocode 910 for the two problems in SW, for all columns in the current row except the initialization column, SW kernel 192 executes sub-alignment calculation pseudocode 950 and result calculation pseudocode 960. Sub-alignment calculation pseudocode 950 is a call to the intrinsic function __SW_16, which is a wrapper for the dual-path SIMD variant (SW.2) of SW instruction 610. Execution of the SW.2 instruction causes SM310 to calculate the current sub-aligned data row and the current column for two specified local alignment problems. Therefore, SW kernel 192 executes a single instruction to calculate and store (in one of SWcell16 464 residing in the register file) two E values, two F values, and two sub-alignment scores.

[0256] As shown in the figure, the result calculation pseudocode 960 includes, but is not limited to, calls to the intrinsic function __vimnmx_16, which acts as a wrapper for a dual-path SIMD variant (VIMNMX.S16X2) of the VIMNMX instruction 810, followed by two sets of predicate condition update pseudocodes. Therefore, the SW kernel 192 executes a single instruction to compute and store the two maximum sub-alignment scores and two predicate values ​​pu and pv so far. The SW kernel 192 then conditionally updates the maximum score column and maximum score row based on pu and pv for unassigned local alignment problems, and for one or two assigned local alignment problems.

[0257] Figure 10 According to various other embodiments Figure 1 This example illustrates pseudocode 1010 for a single problem in the SW kernel 192. For illustrative purposes, pseudocode 1010 describes the matrix filling phase, where each thread in CTA 312 computes the sub-alignment score, maximum sub-alignment score, maximum score column, and maximum score row for each position in the corresponding scoring matrix. Because each thread computes the sub-alignment score for a single local alignment problem, the thread-computed SIMD mode is SIMD-free.

[0258] The SW single-problem pseudocode 1010 uses an interleaved cell layout 450(1), SW sequence pseudocode 1002, and VIMNMX instruction 810. As shown, SW sequence pseudocode 1002 is the intrinsic function __sw6_1, which is a per-thread six-instruction sequence for the threaded computation mode without SIMD, matrix-filled dataset 490(1), and SW score computation for 32-bit signed integers. The per-thread six-instruction sequence is a specific variant of SW sequence 740 corresponding to the threaded computation mode without SIMD, matrix-filled dataset 490(1), and 32-bit signed integers. As shown, SW sequence pseudocode 1002 uses the intrinsic functions __viadd, __viaddmnmx, and __vimnmx3, which are wrappers for the VIADD.32 instruction, VIADDMNMX.S32 instruction, and VIMNMX3.S32 instruction, respectively, to implement the SIMD-free SW sequence 742, which is combined with the previous text. Figure 5 The SIMD-free SW sequence 742 has been described to use 32-bit signed integer operands included in the matrix filling dataset 490(1).

[0259] Referring now to the SW single-problem pseudocode 1010, and based on the initialization pseudocode 1020, the SW kernel 192 initializes the result set residing in the register file. This includes two arrays of (N+1) HEcell32 562 values, an array of F(N+1) 32-bit integers, and an S array consisting of N 32-bit integers. The result set includes, but is not limited to, three 32-bit integers corresponding to the maximum sub-aligned score, the maximum score column, and the maximum score row.

[0260] The SW kernel 192 iterates through the scoring matrix row by row, starting from the row after the initialization row. (As mentioned earlier in this article...) Figure 5 As described, the SW kernel 192 implements a current row / previous row swapping technique to reuse two arrays of HEcell32 562. Row identifier swapping pseudocode 1030 identifies the corresponding part of SW single-issue pseudocode 1010.

[0261] Based on the substitution value assignment pseudocode 1040, for all columns in the current row except the initialization column, SW kernel 192 copies the substitution value from substitution matrix 444 to array S. Advantageously, implementing the substitution value loop independently of the sub-alignment loop allows one thread bundle to execute the substitution value loop using an instruction set (e.g., load, etc.), while another thread bundle is executing the main loop using a different instruction set (e.g., VIADD.32 instructions, etc.).

[0262] Based on the main loop of SW single-problem pseudocode 1010, for all columns in the current row except the initialization column, SW kernel 192 executes sub-alignment calculation pseudocode 1050 and result calculation pseudocode 1060. Sub-alignment calculation pseudocode 1050 is a call to the intrinsic function __sw6_1 described above in conjunction with SW single-problem pseudocode 1010. Execution of intrinsic function __sw6_1 causes SM 310 to execute a six-instruction sequence to calculate and store the local alignment problem assigned to the current row and current column, the E value and sub-alignment score in one of HEcell32562, and the F value in the F array.

[0263] As shown in the figure, the result calculation pseudocode 1060 includes, but is not limited to, calls to the intrinsic function __vimnmx_32, which acts as a wrapper for a SIMD-free variant (VIMNMX.U32) of the VIMNMX instruction 810 followed by predicate conditional update pseudocode. Therefore, the SW kernel 192 executes a single instruction to compute and store the maximum sub-alignment score and predicate value pu so far. The SW kernel 192 then conditionally updates the maximum score column and maximum score row of the assigned local alignment problem based on pu.

[0264] Figure 11 Various embodiments are shown. Figure 6 and 9 How are the instructions implemented in the execution unit? As shown in the figure, instruction implementation 1180 includes, but is not limited to, VIADD implementation 1182, VIADDMNMX implementation 1184, VIMNMX3 implementation 1186, and VIMNMX implementation 1188. For illustrative purposes only, the following aspects are discussed... Figure 11 Optional negation and the .relu modifier are ignored.

[0265] Return to reference Figure 3B In some embodiments, a floating-point execution unit 1110 and an integer execution unit 1130 are included in each core data path unit 350. In the same or other embodiments, the floating-point execution unit 1110 and the integer execution unit 1130 are execution units. In some embodiments, instructions are decoded by an instruction decoder included in a work assignment crossbar switch 316 and issued to the execution units by a micro-schedule scheduling unit 340 and / or an MIO control unit 370.

[0266] In some embodiments, VIADD implementation 1182 describes the combination of the preceding text. Figure 11The description pertains to the implementation of the VIADD instruction in adder 1120, which is included in an example of floating-point execution unit 1110, an example of which is implemented in the FP pipeline of SM 310 in some embodiments. As shown, the signals corresponding to the source operands source_a and source_b of the VIADD instruction are denoted as "A" and "B" and are input into adder 1120. In response, adder 1120 calculates and outputs a signal representing (A+B) corresponding to the result of the VIADD instruction.

[0267] In some embodiments, VIADDMNMX implementation 1184, VIMNMX3 implementation 1186, and VIMNMX implementation 1188 describe implementations of corresponding instructions for exemplary portions of an integer execution unit 1130 implemented in the integer pipeline of SM 310 in some embodiments. In some embodiments, the integer execution unit 1130 includes, but is not limited to, adder 1140, multiplexer 1150, adder 1160, and multiplexer 1170. Instruction control 1132 is routed to and controls the operation of each of adder 1140, multiplexer 1150, adder 1160, and multiplexer 1170.

[0268] The signals corresponding to the source operands source_a and source_b of each of the VIADDMNMX, VIMNMX3, and VIMNMX instructions 810 are represented as "A" and "B" and are input to adder 1140. The signal corresponding to the source operand source_c of each of the VIADDMNMX and VIMNMX3 instructions is represented as "C" and is input to adder 1160 and multiplexer 1170.

[0269] In some embodiments, according to VIADDMNMX implementation 1184, adder 1140 calculates (A+B). Multiplexer 1150 selects (A+B). Adder 1160 calculates (A+B+C) and control signal 1134(1). Based on control signal 1134(1), multiplexer 1170 outputs the maximum or minimum value of (A+B) and signal C.

[0270] In some embodiments, according to the VIMNMX3 implementation 1186, adder 1140 calculates (A+B) and control signal 1134(0). Based on control signal 1134(0), multiplexer 1150 selects the minimum or maximum value of A and B. Adder 1160 calculates C+(the minimum or maximum value of A and B) and control signal 1134(1). Based on control signal 1134(1), multiplexer 1170 outputs the maximum or minimum value of A, B, and C.

[0271] In some embodiments, according to VIMNMX implementation 1188, adder 1140 outputs (A+B) and predicate values ​​pu, pv, px and py.

[0272] Figure 12A According to various embodiments, Figure 3A An example illustration of the dual-path SIMD matrix filling stage 1210(0) performed by the CTA 312. More specifically, Figure 12A This example illustrates how CTA 312 applies the "multiple questions per thread" technique to perform a dual-path SIMD matrix filling phase. In the multiple questions per thread technique, each thread in CTA 312 is assigned two distinct local alignment questions. For each local alignment question, the assigned thread computes, row-by-row, the sub-alignment score for each position in the relevant scoring matrix, the maximum sub-alignment score, and the maximum score position in the row and column of the specified maximum sub-alignment score in the scoring matrix.

[0273] In the computation, a given thread initializes the values ​​of E0, E1, H0, and H1 in each initial cell of initial row 0 and the values ​​of F0, F1, H0, and H1 in each initial cell of initial column 0, where E0, F0, and H0 correspond to one specified local alignment problem, and E1, F1, and H1 correspond to another specified local alignment problem. The thread then sequentially calculates the values ​​of E0, E1, H0, and H1 corresponding to positions (1, 1)–(1, N+1) in row 1 from left to right, updating one or two maximum sub-alignment scores and maximum score positions in each row (as appropriate). After traversing row 1, the thread sequentially calculates the values ​​of E0, E1, H0, and H1 corresponding to positions (2, 1)–(2, N+1) in row 2 from left to right. The thread continues processing positions in the scoring matrix in this manner until it has finished processing positions (M, N) in the scoring matrix. The thread then stores the maximum sub-alignment score and maximum score position for each assigned local alignment problem in global memory.

[0274] For illustrative purposes, the incremental processes of threads 1220(0) and 1220(1) are depicted using two snapshots corresponding to the earlier time 1202 and the later time 1230. As shown, thread 1220(0) handles local alignment problems 1212(0) and 1212(1). As shown, thread 1220(1) handles local alignment problems 1212(2) and 1212(3).

[0275] At an earlier time 1202, thread 1220(0) had processed one-third of the rows in the scoring matrix (not shown) associated with thread 1220(0) and local alignment problems 1212(0) and 1212(1). The processed rows correspond to one-third of the target symbols associated with local alignment problem 1212(0) and one-third of the target symbols associated with local alignment problem 1212(1). At an earlier time 1202, thread 1220(1) had processed one-third of the rows in the scoring matrix (not shown) associated with thread 1220(1) and local alignment problems 1212(2) and 1212(3). The processed rows correspond to one-third of the target symbols associated with local alignment problem 1212(2) and one-third of the target symbols associated with local alignment problem 1212(3).

[0276] At a later time 1230, thread 1220(0) has processed half a row in the scoring matrix associated with thread 1220(0) and local alignment problems 1212(0) and 1212(1). The processed row corresponds to half of the target symbols associated with local alignment problem 1212(0) and half of the target symbols associated with local alignment problem 1212(1). At a later time 1230, thread 1220(1) has processed half a row in the scoring matrix associated with thread 1220(1) and local alignment problems 1212(2) and 1212(3). The processed row corresponds to half of the target symbols associated with local alignment problem 1212(2) and half of the target symbols associated with local alignment problem 1212(3).

[0277] Note that the techniques described herein are illustrative rather than limiting, and modifications can be made without departing from the broader spirit and scope of the invention. Many modifications and variations to the functionality provided by the software application 190, SW kernel 192, CTA 312, parallel processing subsystem 112, PPU, SM, and CPU will be readily apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. Furthermore, numerous techniques can be used to traverse the scoring matrix, and any number of these techniques can be used in combination with any number of the techniques described above.

[0278] Figure 12B According to various other embodiments Figure 3A An example illustration of the dual-path SIMD matrix filling stage 1210(1) performed by the CTA 312. More specifically, Figure 12AAn example is shown of how thread bundles in CTA 312 apply the “interleaved threading” technique to perform a dual-path SIMD matrix filling phase. In some embodiments, in the interleaved threading technique, each thread bundle in CTA 312 is assigned two distinct local alignment problems. Each thread is assigned a set of columns based on the thread ID in the thread bundle. Thread 1220(0) is assigned column 1–N / T, where T is the total number of threads in the thread bundle (e.g., 32), thread 1220(1) is assigned column (N / T+1)–(2*N / T), and so on.

[0279] For the purpose of explanation, assigned to Figure 12B The local alignment problems of the thread bundles described herein are referred to as "Problem A" and "Problem B". In some embodiments, the thread bundles perform matrix filling phases for Problems A and B on a total of (M+T-1) iterations 1280. Each thread participates in M ​​iterations. For each thread, the initial iteration is equal to the thread ID, the final iteration is equal to (thread ID+M-1), and the thread processes the columns assigned in the first row during the initial iteration, the columns assigned in the second row in the next iteration, and so on. In some embodiments, the SW kernel can implement the thread interleaving described herein through the following pseudocode (12):

[0280]

[0281] In some embodiments, each thread initializes a different matrix-filled dataset residing in the associated register file. Thread 1220(0) also initializes the initial H and initial F associated with the initial column to zero. After processing each row, each of threads 1220(0)-1220(T-2) provides the overflow dataset 1290 to the thread with the next thread ID. Threads may provide the overflow dataset 1290 in any technically feasible manner. In some embodiments, threads perform register-to-register data swaps to exchange the overflow dataset 1290 via a warp shuffle instruction (e.g., SHFL_SYNC). In some embodiments, each warp shuffle instruction causes each thread in a subset of threads participating in the warp shuffle to transfer data from a register associated with the thread to another register associated with another thread.

[0282] As shown in the figure, in some embodiments, each overflow dataset 1290 includes, but is not limited to, rightmostH, rightmostF, maxH, and maxHCol. For the thread providing the overflow dataset 1290, rightmostH includes the H value corresponding to the last assigned column of the row and the assigned local alignment problem, rightmostF includes the F value corresponding to the last assigned column of the row and the assigned local alignment problem, maxH specifies the maximum sub-alignment score in the row corresponding to the assigned local alignment problem so far, and maxHcol specifies the column corresponding to the maximum sub-alignment score in that row so far.

[0283] In some embodiments, before processing each row, each of threads 1220(1)-1220(T-1) performs an initialization operation based on the overflow dataset 1290 received by thread 1220 for that row. In the same or other embodiments, thread 1220(T-1) appropriately initializes and updates the maximum sub-alignment score and maximum score position of the assigned local alignment problem based on the overflow dataset 1290 received from thread 1220(T-2). After processing the last row, thread 1220(T-1) stores the maximum sub-alignment score and maximum score position of each assigned local alignment problem in global memory.

[0284] For the purpose of explanation, Figure 12B The progress of threads 1220(0)-1220(4) after the fifth iteration is shown. It is noteworthy that threads 1220(5)-1220(T-1) have not yet processed any rows. As shown, thread 1220(0) is assigned problem A part 1252(0) corresponding to column 1-(N / T) of the local alignment problem A, and problem B part 1254(0) corresponding to column 1-(N / T) of the local alignment problem B. Thread 1220(1) is assigned problem A part 1252(1) and problem B part 1254(1), and so on.

[0285] exist Figure 12BAt the points in time shown, thread 1220(0) has processed lines 1-5 of part A, 1252(0), and lines 1-5 of part B, 1254(0), and has exchanged overflow dataset 1290 with thread 1220(1) via a thread bundle shuffle operation. Thread 1220(1) has processed lines 1-4 of part A, 1252(1), and lines 1-4 of part B, 1254(1), and has exchanged overflow dataset 1290 with thread 1220(2) via a thread bundle shuffle operation. Although not shown, thread 1220(2) has processed lines 1-3 of part A, 1252(2), and lines 1-3 of part B, 1254(2), and has exchanged overflow dataset 1290 with thread 1220(3) via a thread bundle shuffle operation. Thread 1220(3) has processed lines 1-2 of part A (1252(3)) and lines 1-2 of part B (1254(3), and has swapped the overflow dataset 1290 with thread 1220(4) through a thread bundle shuffle operation. As shown in the figure, thread 1220(4) has processed line 1 of part A (1252(4)) and line 1 of part B (1254(4), and has swapped one of the overflow datasets 1290 with thread 1220(5) through a thread bundle shuffle operation.

[0286] Note that the techniques described herein are illustrative rather than limiting, and modifications can be made without departing from the broader spirit and scope of the invention. Many modifications and variations to the functionality provided by the software application 190, SW kernel 192, CTA 312, parallel processing subsystem 112, PPU, SM, and CPU will be readily apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. In one example, the interleaved threading technique for dual-path SIMD described herein can be modified and applied to both a four-path SIMD matrix filling stage and a no-SIMD matrix filling stage. In another example, in some embodiments, the interleaved threading technique can be applied to half-thread bundles instead of thread bundles, wherein each half-thread bundle is assigned a different set of 1, 2, or 4 local alignment problems.

[0287] Figure 13 This is a flowchart of method steps for storing sub-alignment data during the matrix filling phase of performing the Smith-Waterman algorithm, according to various embodiments. Although references... Figure 1-1 The system described in section 2 outlines the method steps, but those skilled in the art will understand that any system configured to implement the method steps in any order falls within the scope of this invention.

[0288] As shown in the figure, method 1300 begins at step 1302, where a program (e.g., software application 190 or SW kernel 192) determines that the problem 412 for each thread is represented as P, the column 414 for each thread is represented as C, and whether the staggered cell layout will be compatible with SW instruction 610. If, at step 1304, the program determines that the staggered cell layout will be compatible with SW instruction 610, then method 1300 proceeds to step 1306.

[0289] In step 1306, if the program determines that there are four problems for each thread 412, then method 1300 proceeds to step 1308. In step 1308, the program determines that each cell layout is an interleaving of four consecutive 8-bit H values, four consecutive 8-bit E values, four consecutive 8-bit F values, and four consecutive 8-bit S values, so each SWcell 460 is SWcell8 486. Method 1300 then proceeds directly to step 1316. In step 1316, the program causes each thread in one or more CTA 312 to store sub-aligned data across two arrays of (C+1) SWcell 460 when executing SW instruction 610 or SW sequence 740 for each combination of C query symbols and M target symbols. Then method 1300 terminates.

[0290] However, if in step 1306, the program determines that each thread's problem 412 is not four, then method 1300 proceeds directly to step 1310. In step 1310, if the program determines that each thread's problem 412 is two, then method 1300 proceeds to step 1312. In step 1312, the program determines that each cell layout consists of two consecutive 16-bit H values, two consecutive 16-bit E values, two consecutive 16-bit F values, and two consecutive 16-bit S values, therefore each SWcell 460 is SWcell16 484. Method 1300 then proceeds directly to step 1316. In step 1316, when SW instruction 610 or SW sequence 740 is executed for each combination of C query symbols and M target symbols, the program causes each thread in one or more CTA 312 to store sub-aligned data across two arrays of (C+1) SWcells 460. Then method 1300 terminates.

[0291] However, if in step 1310 the program determines that each thread 412 has more than two problems, then method 1300 proceeds directly to step 1314. In step 1314, the program determines that each cell layout is a 32-bit interleaved H value, a 32-bit E value, a 32-bit F value, and a 32-bit S value, therefore each SWcell460SWcell132 482. Then method 1300 proceeds directly to step 1316. In step 1316, the program causes each thread in one or more CTA 312 to store sub-aligned data across two arrays spanning (C+1) SWcell 460 when SW instruction 610 or SW sequence 740 is executed for each combination of C query symbols and M target symbols. Then method 1300 terminates.

[0292] Returning to step 1304, if in step 1304 the program determines that the interleaved cell layout is incompatible with SW instruction 610, then method 1300 proceeds directly to step 1318. In step 1318, if the program determines that the problem for each thread 412 is four, then method 1300 proceeds to step 1320. In step 1320, the program determines that each F structure 570 will include four 8-bit F values ​​and each S structure 580 will include four 8-bit S values. In step 1322, the program determines that each cell layout is an interleaving of four consecutive 8-bit H values ​​and four consecutive 8-bit E values, therefore each HEcell 560 is SWcell8 566. Method 1300 then proceeds directly to step 1334. In step 1334, when SW sequence 740 is executed for each combination of C query symbols and M target symbols, the program causes each thread in one or more CTA 312 to store sub-aligned data across two arrays 560 of (C+1) HEcells. Then method 1300 terminates.

[0293] However, if in step 1318, the program determines that there are not four problems 412 for each thread, then method 1300 proceeds directly to step 1324. In step 1324, if the program determines that there are two problems 412 for each thread, then method 1300 proceeds to step 1326. In step 1326, the program determines that each F structure 570 will include two 16-bit F values ​​and each S structure 580 will include two 16-bit S values. In step 1328, the program determines that each cell layout is an interleaving of two consecutive 16-bit H values ​​and two consecutive 16-bit E values, therefore each HEcell 560 is SWcell16564. Then method 1300 proceeds directly to step 1334. In step 1334, when SW sequence 740 is executed for each combination of C query symbols and M target symbols, the program causes each thread in one or more CTAs 312 to store sub-aligned data across two arrays 560 of (C+1) HEcells. Then method 1300 terminates.

[0294] However, if in step 1324, the program determines that each thread 412 has more than two problems, then method 1300 proceeds directly to step 1330. In step 1330, the program determines that each F structure 570 will include a 32-bit F value and each S structure 580 will include a 32-bit S value. In step 1332, the program determines that each cell layout is an interleaving of 32-bit H values ​​and 32-bit E values, therefore each HEcell 560 is SWcell32 562. Then method 1300 proceeds directly to step 1334. In step 1334, when SW sequence 740 is executed for each combination of C query symbols and M target symbols, the program causes each thread in one or more CTA 312 to store sub-aligned data across two arrays of (C+1) HEcells 560. Then method 1300 terminates.

[0295] Figure 14 This is a flowchart of method steps for performing sub-alignment calculations by a single instruction during the matrix filling phase of the Smith-Waterman algorithm, according to various embodiments. Although references... Figure 1-4 The systems described in 6, 8-9, and 11-12 are method steps, but those skilled in the art will understand that any system configured to implement the method steps in any order is within the scope of this invention.

[0296] As shown in the figure, method 1400 begins at step 1402, where the thread executing SW kernel 192 initializes two arrays of (N+1) SWcell 460s residing in the register file, designating one array as the previous row and the other as the current row. In step 1404, for each local alignment problem, the thread initializes the maximum sub-alignment score and maximum score position residing in the register file and selects an initial target symbol. In step 1406, for each selected target symbol, the thread generates N replacement values, including those from the leftmost N SWcell 460s in the previous row. In step 1408, the thread selects the second column from the leftmost position.

[0297] In step 1410, the thread executes the SW instruction to generate H, E, and F values ​​included in the SWcell 460 of the current row and the selected column, based on the two SWcell 460s in the column to the left of the selected column and the SWcell 460s in the previous row and the selected column. In step 1412, the thread executes the VIMNMX instruction to update the maximum sub-alignment score and set the corresponding predicate. In step 1414, the thread updates the maximum score position corresponding to each non-zero predicate.

[0298] In step 1416, the thread determines whether the selected column is the last column. If in step 1416 the thread determines that the selected column is not the last column, method 1400 proceeds to step 1418. In step 1418, the thread selects the next column. Method 1400 then returns to step 1410, where the thread executes the SW instruction to generate the H, E, and F values ​​included in SWcell 460 in the current row and the selected column.

[0299] However, if in step 1416 the thread determines that the selected column is the last column, then method 1400 proceeds directly to step 1420. In step 1420, the thread determines whether all selected target symbols are the last target symbols in the corresponding target sequence. If in step 1420, SW kernel 192 determines that at least one selected target symbol is not the last target symbol, then method 1400 proceeds to step 1422. In step 1422, SW kernel 192 swaps the rows to specify and selects the next target symbol. Method 1400 then returns to step 1406, where for each selected target symbol, the thread generates the corresponding N replacement values ​​included in the leftmost N SWcells 460 of the previous row.

[0300] However, if in step 1420, the SW kernel 192 determines that all selected target symbols are the last target symbols of the corresponding target sequence, then method 1400 terminates.

[0301] Figure 15This is a flowchart of method steps for performing sub-alignment calculations via a sequence of instructions during the matrix filling phase of the Smith-Waterman algorithm, according to various embodiments. Although references... Figure 1-5 The systems described in 7-8 and 10-12 describe the method steps, but those skilled in the art will understand that any system configured to implement the method steps in any order is within the scope of this invention.

[0302] As shown in the figure, method 1500 begins at step 1502, where the thread executing SW kernel 192 initializes the matrix padding dataset (e.g., matrix padding dataset 490(0) or matrix padding dataset 490(1)) residing in the register file, designating one cell array as the previous row and another cell array as the current row. In step 1504, for each local alignment problem, the thread initializes the maximum sub-alignment score and maximum score position residing in the register file and selects an initial target symbol.

[0303] In step 1506, each selected target symbol generates N corresponding replacement values ​​included in the matrix filling dataset. In step 1508, the thread selects an initial query symbol for each local sub-alignment problem. In step 1510, the thread executes the VIADD, VIADDMNMX, VIADD, VIADDMNMX, VIADD, and VIMNMX3 instruction sequence to generate the E-value, F-value, and sub-alignment score included in the matrix filling dataset corresponding to the selected target symbol and the selected query symbol.

[0304] In step 1512, the thread executes the VIMNMX instruction to update the maximum sub-alignment score and set the corresponding predicate. In step 1514, the thread updates the maximum score position corresponding to each non-zero predicate.

[0305] In step 1516, the thread determines whether the selected query symbol is a query symbol. If, in step 1516, the thread determines that the selected query symbol is not the last query symbol, then method 1500 proceeds to step 1518. In step 1518, the thread selects the next query symbol. Method 1500 then returns to step 1510, where the thread executes the VIADD, VIADDMNMX, VIADD, VIADDMNMX, VIADD, and VIMNMX3 instruction sequence to generate a dataset including E-values, F-values, and sub-alignment scores in matrix filling corresponding to the selected target symbol and the selected query symbol.

[0306] However, if in step 1516 the thread determines that the selected column is the last column, then method 1500 proceeds directly to step 1520. In step 1520, the thread determines whether all selected target symbols are the last target symbols in the corresponding target sequence. If in step 1520 the thread determines that at least one selected target symbol is not the last target symbol, then method 1500 proceeds to step 1522. In step 1522, the thread swaps the specified rows and selects the next target symbol. Method 1500 then returns to step 1506, where for each selected target symbol, the thread generates N corresponding replacement values ​​included in the leftmost N SWcell 460s or HEcell 560s of the previous row.

[0307] However, if in step 1520 the thread determines that all selected target symbols are the last target symbols of the corresponding target sequence, then method 1500 terminates.

[0308] Figure 16 This is a flowchart of method steps for performing the matrix filling phase of the Smith-Waterman algorithm via a thread group, according to various embodiments. Although references... Figure 1-1 The system described in section 2 outlines the method steps, but those skilled in the art will understand that any system configured to implement the method steps in any order falls within the scope of this invention.

[0309] As shown in the figure, method 1600 begins at step 1602, where each thread in the thread bundle of the execution SW kernel 192 initializes a different matrix padding dataset (e.g., matrix padding dataset 490(0) or matrix padding dataset 490(1)) residing in the associated register file. At step 1604, each thread sets the iteration to 0. At step 1606, each thread sets the row to be equal to the iteration minus thread ID + 1. At step 1608, the thread with rows greater than 0 and less than or equal to M is selected.

[0310] In step 1610, each selected thread with a thread ID greater than 0 sets the leftmost sub-alignment score, leftmost F-value, maximum row sub-alignment score, and maximum score column based on the associated overflow dataset. In step 1612, each selected thread computes the sub-alignment data for the assignment column of that row and updates the maximum row sub-alignment score and maximum score column for each local alignment problem to reflect the newly computed sub-alignment score. In step 1614, each selected thread with a thread ID less than (T-1) passes the overflow dataset to its neighboring thread with a higher thread ID.

[0311] In step 1616, if the highest thread is selected, it updates the maximum sub-alignment score and maximum score position for each local alignment problem. In step 1618, the thread determines whether the current iteration is the last iteration. If, in step 1618, the thread determines that the current iteration is not the last iteration, the thread proceeds to step 1620. In step 1620, the thread increments the iteration. Then method 1600 returns to step 1606, where each thread sets a row equal to the iteration minus the thread ID + 1.

[0312] However, if in step 1618 the thread determines that the current iteration is the last iteration, the thread proceeds directly to step 1622. In step 1622, the thread with the highest thread ID stores the maximum sub-alignment score and the maximum score position for each local alignment problem in global memory. Then method 1600 terminates.

[0313] In some embodiments, one or more SW libraries and / or one or more SW kernels in the programming platform software stack 160 include, but are not limited to, pre-written code, kernels, subroutines, intrinsic functions, macros, classes, values, type specifications, etc., which facilitate the use of one or more of the following: staggered cell layout 450(0), staggered cell layout 450(1), SW instruction 610, SW sequence 740, staggered cell layout 450(1), VIADD instruction, VIADDMNMX instruction, VIMNMX3 instruction, VIMNMX instruction 810, SIMD per-threaded multiple-problem technique, SIMD staggered thread technique, or any combination thereof. In particular, one or more SW libraries may include, but are not limited to, intrinsic functions for computing sub-aligned data based on SW instruction 610 and staggered cell layout 450(0), SW sequence 740 and staggered cell layout 450(0), SW sequence 740 and staggered cell layout 450(1), or any combination thereof.

[0314] In summary, the disclosed techniques can be used to efficiently accelerate the matrix filling stage of the SW algorithm using parallel processors. In some embodiments, a software application configures a thread bundle to execute the SW kernel on a parallel processor to concurrently perform the matrix filling stage for one to four local sequence alignment problems. In some embodiments, the SW kernel implements one or more data interleaving techniques, using a single SW instruction or a sequence of SW instructions to compute sub-alignment scores, using minimum / maximum instructions indicating selected operands to determine the maximum sub-alignment score and associated position, or any combination thereof. In the same or other embodiments, each thread in the thread bundle is responsible for the matrix filling stage of one, two, or four different alignment problems or a subset of columns for one, two, or four shared alignment problems.

[0315] In some embodiments, each thread in a thread bundle stores sub-aligned data of the previous and current rows in an interleaved manner using two cell arrays residing in a register file. More specifically, if the current row is j, the k-th cell in the cell array corresponding to the current row stores 32-bit data represented as H(j,k), 32-bit data represented as E(j,k), 32-bit data represented as F(j,k), and 32-bit data represented as S(j+1,k+1). The k-th cell in the other cell array stores 32-bit data represented as H(j-1,k), 32-bit data represented as E(j-1,k), 32-bit data represented as F(j–1,k), and 32-bit data represented as S(j,k+1). Each of H(j,k), E(j,k), F(j,k), S(j+1,k+1), H(j-1,k), E(j-1,k), F(j–1,k), and S(j,k+1) can include a single 32-bit value corresponding to a single alignment problem, two compressed 16-bit values ​​corresponding to two alignment problems, or four compressed 8-bit values ​​corresponding to four alignment problems. SW instructions and SW instruction sequences can be used in conjunction with SWcell.

[0316] In some other embodiments, to reduce the amount of register memory required to store sub-aligned data, each thread stores the relevant H and E values ​​of the previous and current rows in two HE cell arrays residing in the register file, along with the relevant F value of the current row in a 32-bit value array residing in the register file, and the relevant S value of the current row in a 32-bit value array residing in the register file. A sequence of SW instructions, rather than a single SW instruction, can be used in conjunction with HE cells.

[0317] The SW instruction is a per-thread instruction that performs SW sub-alignment calculations for a single location. In some embodiments, the SW instruction format is SW{.variant}result, diag, top, left, consts. The .variant modifier is 1 (no SIMD), 2 (two-way SIMD), or 4 (four-way SIMD); result, diag, top, and left are instances of SWcell; the constants are GapDeleteExtend, GapInsertExtend, GapDeleteExtend, and GapInsertOpen.

[0318] The SW instruction sequence is a six-instruction sequence per thread, performing SW sub-alignment calculations on a single location, and supports SIMD-free, dual-path SIMD, and quad-path SIMD. The instruction sequence includes, but is not limited to, the first VIADD instruction, the first VIADDMNMX instruction, the second VIADD instruction, the second VIADDMNMX instruction, the third VIADD instruction, and the VIMNMX3 instruction. The VIADD, VIADDMNMX, and VIMNMX3 instruction formats all support SIMD-free, dual-path SIMD, and quad-path SIMD variants.

[0319] In some embodiments, each thread in a thread bundle is responsible for one, two, or four different local alignment problems. Each thread in the thread bundle does not sequentially perform SIMD-free, single-path SIMD, or four-path SIMD SW sub-alignment calculations for positions corresponding to a set of columns and the next row before performing a score calculation for the position corresponding to that set of columns and the next row. In some other embodiments, one, two, or four alignment problems are distributed among the threads in the thread bundle. For positions corresponding to a different set of columns, each thread performs a SIMD-free, single-path SIMD, or four-path SIMD SW sub-alignment calculation, and except for thread 0, each thread performs the sub-alignment calculation on the row immediately following the lower-level thread.

[0320] At least one technical advantage of the disclosed technique over the prior art is that, using the disclosed technique, when executing the matrix filling stage of the SW algorithm using a parallel processor, the number of instructions executed to compute each sub-alignment score can be reduced. In this regard, using the disclosed technique, a single SW instruction or a six-instruction SW sequence can be used to concurrently compute one, two, or four sub-alignment scores associated with one, two, or four different local alignment problems, respectively. Because the sub-alignment scores associated with each position in the scoring matrix can be stored in an interleaved manner within a single cell using the disclosed technique, the inefficiencies associated with data movement can be reduced compared to conventional techniques for retrieving the same data from separate matrices. Furthermore, using the disclosed technique, instructions instructing the selected operands when determining the minimum or maximum value of two operands can be used to reduce the number of instructions executed when determining and storing the maximum sub-alignment score and associated position. These technical advantages provide one or more technical improvements over prior art methods.

[0321] Any and all combinations of any claim elements recited in any claim and / or any elements described in this application fall within the intended scope of the embodiments and protection in any manner.

[0322] The various embodiments described are for illustrative purposes only and are not intended to be exhaustive or limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

[0323] Aspects of this embodiment may be embodied as a system, method, or computer program product. Therefore, aspects of this disclosure may take the form of a completely hardware embodiment, a completely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, all of which can be collectively referred to herein as a “module,” “system,” or “computer.” Furthermore, any hardware and / or software technology, process, function, component, engine, module, or system described in this disclosure may be implemented as a circuit or a set of circuits. Additionally, aspects of this disclosure may take the form of a computer program product embodied in one or more computer-readable media having a computer-readable program codec embodied thereon.

[0324] Any combination of one or more computer-readable media may be used. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example, but not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any suitable combination thereof. More specific examples (not an exhaustive list) of computer-readable storage media will include: an electrical connection having one or more wires, a portable computer floppy disk, a hard disk, random access memory, read-only memory, erasable programmable read-only memory, flash memory, optical fiber, portable optical disc read-only memory, optical storage device, magnetic storage device, or any suitable combination thereof. In the context of this document, a computer-readable storage medium may be any tangible medium that may include or store programs for use by or in connection with an instruction execution system, apparatus, or device.

[0325] Flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure describe aspects of this disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine. When executed by a processor of a computer or other programmable data processing apparatus, the instructions are capable of implementing the functions / actions specified in the flowchart and / or block diagram blocks or more blocks. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a dedicated processor, or a field-programmable gate array (FPGA).

[0326] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, comprising one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may not appear in the order indicated in the figures. For example, two blocks shown consecutively may actually execute substantially concurrently, or these blocks may sometimes execute in reverse order, depending on the functions involved. It should also be noted that each block shown in the block diagrams and / or flowcharts, and combinations of blocks shown in the block diagrams and / or flowcharts, may be implemented by a hardware-based dedicated system performing the specified function or action, or a combination of dedicated hardware and computer instructions.

[0327] Although the foregoing description is directed to embodiments of this disclosure, other and further embodiments of this disclosure may be designed without departing from its basic scope, which is defined by the appended claims.

Claims

1. A computer-implemented method for storing sub-alignment data during the matrix filling phase of executing the Smith-Waltman algorithm, the method comprising: Based on the top cell at the top position in the scoring matrix, determine the top E value and the top sub-alignment score, wherein the scoring matrix is ​​associated with at least a first target sequence and at least a first query sequence; Based on the top E value and the top sub-alignment score, calculate the current E value associated with the current position in the scoring matrix; Store the current E value in the current cell of the current position in the scoring matrix; The current F value associated with the current position in the rating matrix is ​​calculated based on the left F value and the left child alignment score, wherein the left F value and the left child alignment score are stored in the left cell of the left position of the rating matrix; Store the current F value in the current cell; The current sub-alignment score associated with the current position in the scoring matrix is ​​calculated based on the current E value, the current F value, the diagonal sub-alignment score stored in the diagonal cell at the diagonal position in the scoring matrix, and the current replacement value associated with the first target sequence, the first query sequence, and the current position in the scoring matrix. as well as Store the current sub-alignment score in the current cell.

2. The computer-implemented method according to claim 1, wherein calculating the current sub-alignment score comprises: Set the current sub-alignment score to the maximum of the current F value, the current E value, the sum of the diagonal sub-alignment score and the current replacement value, and zero.

3. The computer-implemented method according to claim 1, wherein calculating the current sub-alignment score comprises: The current F-value associated with the current position in the rating matrix is ​​calculated based on the left F-value stored in the F-value array and the left sub-alignment score stored in the left cell at the left position of the rating matrix. Store the current F value in the F value array; as well as Set the current sub-alignment score to the maximum of the current F value, the current E value, the sum of the diagonal sub-alignment score and the current replacement value, and zero.

4. The computer-implemented method of claim 1, further comprising, before determining the top E value and the top sub-alignment score: Calculate multiple replacement values ​​including the current replacement value; and The multiple replacement values ​​are stored in an integer array.

5. The computer-implemented method of claim 1, further comprising, before determining the top E value and the top sub-alignment score: Calculate multiple replacement values ​​including the current replacement value; and Store the current replacement value in the diagonal cell.

6. The computer-implemented method of claim 1, wherein determining the top E value and the top sub-alignment score comprises: Decompress multiple E values, including the top E value, from the first compressed data stored in the top cell, wherein the multiple E values ​​are associated with multiple local alignment issues; as well as Decompress multiple sub-alignment fractions, including the top sub-alignment fraction, from the second compressed data stored in the top cell, including each of the multiple sub-alignment fractions associated with the multiple local alignment issues.

7. The computer-implemented method of claim 1, further comprising, before determining the top E value and the top sub-alignment score, having a first thread allocate and initialize a matrix filling dataset, the matrix filling dataset comprising: A first array of cells associated with a first plurality of consecutive register locations and even rows in the scoring matrix, and a second array of cells associated with a second plurality of consecutive register locations and odd rows in the scoring matrix, wherein the top cell is included in the first array of cells and the current cell is included in the second array of cells.

8. The computer-implemented method of claim 7, wherein the first cell array comprises an initial cell and different cells for each symbol in the first query sequence.

9. The computer-implemented method of claim 7, comprising storing in a first cell of the first cell array one, two, or four sub-aligned fractional data storage across 32 bits, one, two, or four E values ​​of data storage across 32 bits, one, two, or four F values ​​of data storage across 32 bits, and one, two, or four replacement values ​​of data storage across 32 bits.

10. The computer-implemented method of claim 1, wherein storing the top E value and the top sub-alignment score in the top cell comprises: The top E value and at least one other top E value are compressed into the first compressed data included in the top cell, and the top sub-alignment score and at least one other top sub-alignment score are compressed into the second compressed data included in the top cell.

11. One or more non-transitory computer-readable media comprising instructions that, when executed by one or more processors, cause the one or more processors to store sub-alignment data during the matrix filling phase of the Smith-Waltman algorithm by performing the following steps: Based on the top cell at the top position in the scoring matrix, determine the top E value and the top sub-alignment score, wherein the scoring matrix is ​​associated with at least a first target sequence and at least a first query sequence; Based on the top E value and the top sub-alignment score, calculate the current E value associated with the current position in the scoring matrix; Store the current E value in the current cell of the current position in the scoring matrix; The current F value associated with the current position in the rating matrix is ​​calculated based on the left F value and the left child alignment score, wherein the left F value and the left child alignment score are stored in the left cell of the left position of the rating matrix; Store the current F value in the current cell; The current sub-alignment score associated with the current position in the scoring matrix is ​​calculated based on the current E value, the current F value, the diagonal sub-alignment score stored in the diagonal cell at the diagonal position in the scoring matrix, and the current replacement value associated with the first target sequence, the first query sequence, and the current position in the scoring matrix. as well as Store the current sub-alignment score in the current cell.

12. One or more non-transitory computer-readable media according to claim 11, wherein calculating the current sub-alignment score comprises: Set the current sub-alignment score to the maximum of the current F value, the current E value, the sum of the diagonal sub-alignment score and the current replacement value, and zero.

13. One or more non-transitory computer-readable media according to claim 11, wherein calculating the current sub-alignment score comprises: The current F-value associated with the current position in the rating matrix is ​​calculated based on the left F-value stored in the F-value array and the left sub-alignment score stored in the left cell at the left position of the rating matrix. Store the current F value in the F value array; as well as Set the current sub-alignment score to the maximum of the current F value, the current E value, the sum of the diagonal sub-alignment score and the current replacement value, and zero.

14. The non-transitory computer-readable medium of claim 11, further comprising, before determining the top E value and the top sub-alignment score: Calculate multiple replacement values ​​including the current replacement value; and The multiple replacement values ​​are stored in an integer array.

15. The non-transitory computer-readable medium of claim 11, further comprising, before determining the top E value and the top sub-alignment score: Calculate multiple replacement values ​​including the current replacement value; and Store the current replacement value in the diagonal cell.

16. One or more non-transitory computer-readable media according to claim 11, wherein the top cell stores 32-bit sub-alignment fraction data including the top sub-alignment fraction, stores a sequence of two 16-bit sub-alignment fractions including the top sub-alignment fraction, or stores a sequence of four 8-bit sub-alignment fractions including the top sub-alignment fraction.

17. The non-transitory computer-readable medium of claim 11, further comprising, before determining the top E value and the top sub-alignment score, having a first thread allocate and initialize a matrix filling dataset, the matrix filling dataset comprising: A first array of cells associated with a first plurality of consecutive register locations and even rows in the scoring matrix, and a second array of cells associated with a second plurality of consecutive register locations and odd rows in the scoring matrix, wherein the top cell is included in the first array of cells and the current cell is included in the second array of cells.

18. One or more non-transitory computer-readable media according to claim 17, wherein the first cell array comprises an initial cell and distinct cells for each symbol in a first subset of the first query sequence assigned to the first thread.

19. One or more non-transitory computer-readable media of claim 17, comprising storing one, two or four sub-aligned fractions across 32-bit sub-aligned fractional data and one, two or four E values ​​across 32-bit E data in a first cell of the first cell array, and wherein the matrix-filled dataset further comprises at least the current replacement value and a third array of F values ​​associated with a third plurality of consecutive register locations.

20. A system comprising: One or more memories that store instructions; as well as One or more processors, coupled to the one or more memories, perform the following steps when the instructions are executed: Based on the top cell at the top position in the scoring matrix, determine the top E value and the top sub-alignment score, wherein the scoring matrix is ​​associated with at least a first target sequence and at least a first query sequence; Based on the top E value and the top sub-alignment score, calculate the current E value associated with the current position in the scoring matrix; Store the current E value in the current cell of the current position in the scoring matrix; The current F value associated with the current position in the rating matrix is ​​calculated based on the left F value and the left child alignment score, wherein the left F value and the left child alignment score are stored in the left cell of the left position of the rating matrix; Store the current F value in the current cell; The current sub-alignment score associated with the current position in the scoring matrix is ​​calculated based on the current E value, the current F value, the diagonal sub-alignment score stored in the diagonal cell at the diagonal position in the scoring matrix, and the current replacement value associated with the first target sequence, the first query sequence, and the current position in the scoring matrix. as well as Store the current sub-alignment score in the current cell.

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