Semiconductor structure and method of forming the same

Abstract

A method for forming a semiconductor structure includes forming a semiconductor layer on an insulating layer; forming a dielectric layer on the semiconductor layer; forming an adhesion layer on the dielectric layer; forming an anti-reflective layer on the adhesion layer; forming a patterned photoresist on the anti-reflective layer; etching the anti-reflective layer to have a first opening; etching the adhesion layer in the first opening to have a second opening; removing the patterned photoresist; and etching the anti-reflective layer and the dielectric layer synchronously to have no anti-reflective layer on a top surface of the adhesion layer and to form a third opening in the dielectric layer, wherein the second opening is substantially aligned with the third opening and a top surface of the semiconductor layer is exposed from the second opening and the third opening. There is no residual anti-reflective layer on the top surface of the adhesion layer of the semiconductor structure, and etching can be stopped on the top surface of the semiconductor layer of the semiconductor structure, which can improve a product yield of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure and a method for forming a semiconductor structure. Background Technology

[0002] Generally, anti-reflective layers serve as masking layers to block light and can be coated onto the substrate. During photolithography, the anti-reflective layer prevents light from entering the semiconductor structure, thus avoiding damage. However, during the etching process, the anti-reflective layer may remain on the substrate, and the etching process may etch into the semiconductor layer of the semiconductor structure, causing damage and reducing the product yield. Summary of the Invention

[0003] The technical state disclosed herein is a semiconductor structure.

[0004] According to one embodiment of this disclosure, a semiconductor structure includes an insulating layer, a semiconductor layer, a dielectric layer, an adhesion layer, and a metal contact. The semiconductor layer is located on the insulating layer. The dielectric layer is located on the semiconductor layer. The adhesion layer is located on the dielectric layer, and the top surface of the adhesion layer has no anti-reflective layer. The metal contact is located in the dielectric layer and on the top surface of the semiconductor layer.

[0005] In one embodiment of this disclosure, the aforementioned adhesion layer has an inner sidewall, and the inner sidewall of the adhesion layer is substantially aligned with the inner sidewall of the dielectric layer in the vertical direction.

[0006] In one embodiment of this disclosure, the semiconductor structure further includes an isolation layer. The isolation layer is located on the bottom surface of the insulating layer.

[0007] In one embodiment of this disclosure, the semiconductor structure further includes a gate. The gate is located on the bottom surface of the isolation layer.

[0008] The present invention discloses a method for forming a semiconductor structure.

[0009] According to one embodiment of this disclosure, a method for forming a semiconductor structure includes: forming a semiconductor layer on an insulating layer; forming a dielectric layer on the semiconductor layer; forming an adhesion layer on the dielectric layer; forming an anti-reflective layer on the adhesion layer; forming a patterned photoresist on the anti-reflective layer; etching the anti-reflective layer to give the anti-reflective layer a first opening; etching the adhesion layer in the first opening to give the adhesion layer a second opening; removing the patterned photoresist; and simultaneously etching the anti-reflective layer and the dielectric layer to remove the anti-reflective layer from the top surface of the adhesion layer and form a third opening in the dielectric layer, wherein the second opening and the third opening are substantially aligned, and the top surface of the semiconductor layer is exposed from the second opening and the third opening.

[0010] In one embodiment of this disclosure, the aforementioned simultaneous etching of the anti-reflective layer and dielectric layer uses hydrogen bromide and carbon tetrafluoride.

[0011] In one embodiment of this disclosure, during the simultaneous etching of the antireflective layer and the dielectric layer, the etching rate of the antireflective layer and the dielectric layer is higher than the etching rate of the adhesion layer.

[0012] In one embodiment of this disclosure, during the simultaneous etching of the antireflective layer and the dielectric layer, the etching rate of the antireflective layer and the dielectric layer is higher than the etching rate of the semiconductor layer.

[0013] In one embodiment of this disclosure, the method further includes forming a metal contact on the top surface of the semiconductor layer in the third opening.

[0014] In one embodiment of this disclosure, the method further includes: forming an isolation layer on the gate; and forming an insulating layer on the isolation layer.

[0015] In the above-described embodiments disclosed herein, during the etching process, since the anti-reflective layer and dielectric layer of the semiconductor structure are etched simultaneously, the condition on the top surface of the attachment layer of the semiconductor structure can be improved. That is, there is no residual anti-reflective layer on the top surface of the attachment layer of the semiconductor structure, and the etching can stop on the top surface of the semiconductor layer of the semiconductor structure without etching into the semiconductor layer of the semiconductor structure, so as to avoid damaging the semiconductor layer of the semiconductor structure, thereby improving the product yield of the semiconductor structure. Attached Figure Description

[0016] One embodiment of this disclosure is best understood when read in conjunction with the accompanying figures, from which the following detailed description is obtained. It should be emphasized that, according to standard industry practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0017] Figure 1 A cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure is shown.

[0018] Figure 2 A flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the present disclosure is shown.

[0019] Figures 3 to 7 Cross-sectional views of different stages of semiconductor structure formation are shown. Detailed Implementation

[0020] The following description of embodiments provides many different implementations, or examples, of various features for achieving the provided objectives. Specific examples of elements and arrangements are described below to simplify the subject matter. Of course, these examples are merely illustrative and are not intended to be limiting. Furthermore, element symbols and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not, in itself, specify the relationship between the various embodiments and / or configurations discussed.

[0021] Spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for descriptive purposes to describe the relationship between one element or feature and another, as shown in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the apparatus in use or operation other than those shown in the accompanying drawings. The apparatus may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0022] Figure 1 A cross-sectional view of a semiconductor structure 100 according to an embodiment of this disclosure is shown. Please refer to... Figure 1 The semiconductor structure 100 includes an insulating layer 130, a semiconductor layer 140, a dielectric layer 150, an adhesion layer 160, and a metal contact 180. The semiconductor layer 140 of the semiconductor structure 100 is located on the insulating layer 130, and the semiconductor layer 140 may include amorphous silicon, but this is not intended to limit the scope of this disclosure. Furthermore, the insulating layer 130 of the semiconductor structure 100 may include an insulating material, for example, a nitride, a low-k dielectric material, or a combination of the above materials. The dielectric layer 150 of the semiconductor structure 100 is located on the top surface 142 of the semiconductor layer 140, and the dielectric layer 150 of the semiconductor structure 100 may include a dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, or a combination of the above materials. The adhesion layer 160 of the semiconductor structure 100 is located on the dielectric layer 150, and there is no anti-reflective layer on the top surface 162 of the adhesion layer 160 (at...). Figure 3 (Detailed description). Furthermore, the attachment layer 160 of the semiconductor structure 100 may include carbides, but this is not intended to limit the scope of this disclosure. The metal contact 180 of the semiconductor structure 100 is located in the dielectric layer 150 of the semiconductor structure 100 and on the top surface 142 of the semiconductor layer 140. The metal contact 180 of the semiconductor structure 100 may include a conductive material, for example, polysilicon, metal, conductive metal, or a combination of the above materials.

[0023] In this embodiment, the attachment layer 160 of the semiconductor structure 100 has an inner sidewall 164, and the inner sidewall 164 of the attachment layer 160 of the semiconductor structure 100 is substantially aligned with the inner sidewall 154 of the dielectric layer 150 of the semiconductor structure 100 in the vertical direction D1. Furthermore, the semiconductor structure 100 also includes an isolation layer 120. The isolation layer 120 of the semiconductor structure 100 is located on the bottom surface 132 of the insulating layer 130. The isolation layer 120 of the semiconductor structure 100 may include carbides, but is not intended to limit this disclosure. Additionally, the semiconductor structure 100 also includes a gate 110. The gate 110 of the semiconductor structure 100 is located on the bottom surface 122 of the isolation layer 120 of the semiconductor structure 100. The gate 110 of the semiconductor structure 100 may include a conductive material, for example, polysilicon, tungsten, a conductive metal, or a combination of the above materials.

[0024] The following description will explain the method for forming the semiconductor structure 100. The component connections and materials already described will not be repeated, but will be stated in the preceding text.

[0025] Figure 2 A flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the present disclosure is shown. The method for forming the semiconductor structure includes the following steps: First, in step S1, a semiconductor layer is formed on an insulating layer. Next, in step S2, a dielectric layer is formed on the semiconductor layer. Then, in step S3, an adhesion layer is formed on the dielectric layer. Subsequently, in step S4, an anti-reflective layer is formed on the adhesion layer. Next, in step S5, a patterned photoresist is formed on the anti-reflective layer. Next, in step S6, the anti-reflective layer is etched to give the anti-reflective layer a first opening. Then, in step S7, the adhesion layer in the first opening is etched to give the adhesion layer a second opening. Subsequently, in step S8, the patterned photoresist is removed. Next, in step S9, the anti-reflective layer and the dielectric layer are simultaneously etched to remove the anti-reflective layer from the top surface of the adhesion layer and to form a third opening in the dielectric layer, wherein the second opening and the third opening are substantially aligned, and the top surface of the semiconductor layer is exposed from the second opening and the third opening. The above steps will be described in detail in the following description.

[0026] Figures 3 to 7 Illustration of semiconductor structure 100 (see) Figure 1 Cross-sectional views of the formation process at different stages. Please refer to... Figure 3 An isolation layer 120 is formed on the gate 110, and an insulating layer 130 is formed on the isolation layer 120. Next, a semiconductor layer 140 is formed on the insulating layer 130, and a dielectric layer 150 is formed on the top surface 142 of the semiconductor layer 140. Next, an adhesion layer 160 is formed on the dielectric layer 150, and an anti-reflective layer 170 is formed on the adhesion layer 160. Next, a patterned photoresist 200 is formed on the anti-reflective layer 170.

[0027] In this embodiment, the adhesion layer 160 provides an adhesion effect, allowing the anti-reflective layer 170 to be uniformly formed on the adhesion layer 160, thus ensuring that the anti-reflective layer 170 has a consistent thickness. During photolithography, the anti-reflective layer 170 provides sufficient blocking effect to prevent unwanted light from entering. Figure 3 Damage may occur to the structure. In this embodiment, the anti-reflective layer 170 may include a silicon carbide compound, but this is not intended to limit the scope of this disclosure.

[0028] Please see Figure 4 After forming a patterned photoresist 200 on the anti-reflective layer 170, the anti-reflective layer 170 is then etched to give it a first opening O1. (See also...) Figure 5 After the anti-reflective layer 170 has a first opening O1, the adhesion layer 160 in the first opening O1 is then etched to give the adhesion layer 160 a second opening O2. In this embodiment, the width of the second opening O2 is smaller than the width of the first opening O1.

[0029] See also Figure 5 and Figure 6 After the adhesion layer 160 has the second opening O2, the patterned photoresist 200 is then removed to expose the antireflective layer 170. See also... Figure 6 and Figure 7 After removing the patterned photoresist 200 to expose the anti-reflective layer 170, the anti-reflective layer 170 and the dielectric layer 150 are simultaneously etched so that there is no residual anti-reflective layer 170 on the top surface 162 of the adhesion layer 160, and a third opening O3 is formed in the dielectric layer 150, wherein the second opening O2 and the third opening O3 are substantially aligned, and the top surface 142 of the semiconductor layer 140 is exposed from the second opening O2 and the third opening O3.

[0030] In this embodiment, hydrogen bromide and carbon tetrafluoride are used for the simultaneous etching of the antireflective layer 170 and the dielectric layer 150. Using hydrogen bromide and carbon tetrafluoride as etching gases, the etching rate of the antireflective layer 170 (e.g., silicon carbide compound) and the dielectric layer 150 (e.g., oxide) is higher than the etching rate of the adhesion layer 160 (e.g., carbide) during the simultaneous etching of the antireflective layer 170 and the dielectric layer 150. Therefore, after the simultaneous etching of the antireflective layer 170 and the dielectric layer 150 is completed, no residual antireflective layer 170 remains on the top surface 162 of the adhesion layer 160.

[0031] Furthermore, by using hydrogen bromide and carbon tetrafluoride as etching gases, the etching rate of the antireflective layer 170 (e.g., silicon carbide compound) and the dielectric layer 150 (e.g., oxide) is higher than that of the semiconductor layer 140 (e.g., amorphous silicon) during the simultaneous etching of the antireflective layer 170 and the dielectric layer 150. Therefore, after performing the simultaneous etching of the antireflective layer 170 and the dielectric layer 150, the etching can stop on the top surface 142 of the semiconductor layer 140 without etching into the semiconductor layer 140, thereby avoiding damage to the semiconductor layer 140 and thus improving product yield.

[0032] See also Figure 1 and Figure 7 After simultaneously etching the anti-reflective layer 170 and the dielectric layer 150, so that the top surface 162 of the adhesion layer 160 is free of the anti-reflective layer 170, and after forming a third opening O3 in the dielectric layer 150, the formation method further includes forming a metal contact 180 on the top surface 142 of the semiconductor layer 140 in the third opening O3. In this way, a result can be obtained as follows... Figure 1 The semiconductor structure 100 shown.

[0033] Specifically, during the etching process, since the anti-reflective layer 170 and dielectric layer 150 of the semiconductor structure 100 are etched simultaneously, the condition on the top surface 162 of the adhesion layer 160 of the semiconductor structure 100 can be improved. That is, there is no residual anti-reflective layer 170 on the top surface 162 of the adhesion layer 160 of the semiconductor structure 100, and the etching can stop on the top surface 142 of the semiconductor layer 140 of the semiconductor structure 100 without etching into the semiconductor layer 140 of the semiconductor structure 100, so as to avoid damaging the semiconductor layer 140 of the semiconductor structure 100, thereby improving the product yield of the semiconductor structure 100.

[0034] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them without departing from the spirit and scope of this disclosure.

[0035] [Symbol Explanation]

[0036] 100: Semiconductor Structure

[0037] 110: Gate

[0038] 120: Isolation layer

[0039] 122: Bottom surface

[0040] 130: Insulation layer

[0041] 132: Bottom surface

[0042] 140: Semiconductor layer

[0043] 142: Top surface

[0044] 150: Dielectric layer

[0045] 154: Sidewall

[0046] 160: Adhesion layer

[0047] 162: Top surface

[0048] 164: Sidewall

[0049] 170: Anti-reflective layer

[0050] 180: Metal contact

[0051] 200: Optical Resist

[0052] D1: Vertical direction

[0053] S1: Steps

[0054] S2: Steps

[0055] S3: Steps

[0056] S4: Steps

[0057] S5: Steps

[0058] S6: Steps

[0059] S7: Steps

[0060] S8: Steps

[0061] S9: Steps.

Claims

1. A semiconductor structure, characterized in that, Include: Insulating layer; The semiconductor layer is located on the insulating layer; The dielectric layer is located on the semiconductor layer; An adhesion layer is located on the dielectric layer, and the top surface of the adhesion layer has no anti-reflective layer; as well as A metal contact is located on the top surface of the dielectric layer and the semiconductor layer, wherein the metal contact extends to the top surface of the attachment layer, and the top and bottom surfaces of the attachment layer directly contact the metal contact and the dielectric layer, respectively. The semiconductor layer is defined as an etch stop layer, such that the first contact surface between the metal contact and the semiconductor layer is coplanar with the second contact surface between the semiconductor layer and the dielectric layer.

2. The semiconductor structure of claim 1, wherein the attachment layer has an inner sidewall, and the inner sidewall of the attachment layer is substantially aligned with the inner sidewall of the dielectric layer in the vertical direction.

3. The semiconductor structure according to claim 1, further comprising: An isolation layer is located on the bottom surface of the insulation layer.

4. The semiconductor structure according to claim 3, further comprising: The gate is located on the bottom surface of the isolation layer.

5. A method for forming a semiconductor structure, characterized in that, Include: A semiconductor layer is formed on the insulating layer; A dielectric layer is formed on the semiconductor layer; An adhesion layer is formed on the dielectric layer; An anti-reflective layer is formed on this adhesion layer; Patterned photoresist is formed on this anti-reflective layer; The anti-reflective layer is etched to create a first opening in the anti-reflective layer; The adhesion layer in the first opening is etched to give the adhesion layer a second opening; Remove the patterned photoresist; The anti-reflective layer and the dielectric layer are etched simultaneously, so that the top surface of the attachment layer is free of the anti-reflective layer and a third opening is formed in the dielectric layer, wherein the second opening and the third opening are approximately aligned, wherein the semiconductor layer is defined as an etch stop layer, and the top surface of the semiconductor layer is exposed from the second opening and the third opening; as well as A metal contact is formed on the top surface of the semiconductor layer in the third opening, wherein the metal contact extends to the top surface of the attachment layer, and the top and bottom surfaces of the attachment layer directly contact the metal contact and the dielectric layer, respectively. The first contact surface between the metal contact and the semiconductor layer is coplanar with the second contact surface between the semiconductor layer and the dielectric layer.

6. The method of claim 5, wherein the simultaneous etching of the antireflective layer and the dielectric layer is performed using hydrogen bromide and carbon tetrafluoride.

7. The method of claim 5, wherein during the simultaneous etching of the antireflective layer and the dielectric layer, the etching rate of the antireflective layer and the dielectric layer is higher than the etching rate of the attached layer.

8. The method of claim 5, wherein during the simultaneous etching of the antireflective layer and the dielectric layer, the etching rate of the antireflective layer and the dielectric layer is higher than the etching rate of the semiconductor layer.

9. The method of claim 5, further comprising: An isolation layer is formed on the gate; and The insulating layer is formed on the isolation layer.

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