Wafer processing chamber and system
By using a combination of gate valves, isolation valves, and flow controllers in the wafer processing system, precise control of the purging gas was achieved, solving the problem of moisture accumulation, improving the uniformity and throughput of wafer processing, and reducing operating costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ASM IP HLDG BV
- Filing Date
- 2019-05-29
- Publication Date
- 2026-06-19
AI Technical Summary
In the prior art, the existing flow control technology for handling nitrogen and argon cannot effectively reduce the accumulation of moisture on the wafer surface, leading to oxidation and changes in resistivity, which increases operating costs and reduces throughput.
By employing a combination design of multiple gate valves, isolation valves, flow limiters, and flow controllers, the purge gas flow path and flow rate are precisely controlled to achieve uniform distribution and localized enhanced purging, thereby reducing moisture accumulation.
It effectively reduces moisture buildup on the wafer surface, lowers the risk of oxidation, improves the uniformity and throughput of wafer processing, and reduces operating costs.
Smart Images
Figure CN115910870B_ABST
Abstract
Description
[0001] This application is a divisional application of the invention patent application filed on May 29, 2019, with application number 201910461004.2 and entitled "Wafer Processing Chamber with Reduced Moisture". Technical Field
[0002] This disclosure generally relates to semiconductor processing tools. More specifically, this disclosure relates to a wafer processing mechanism having a purging function for reducing moisture around the wafer. Background Technology
[0003] The wafer can travel through several different chambers during processing. For example, the wafer may move from a wafer storage container into a wafer processing chamber. The wafer may then move from the wafer processing chamber into a reaction chamber. During this process, moisture may accumulate on the wafer, causing oxidation. Oxidation is undesirable, forming unwanted products on the wafer. Additionally, oxidation may increase resistivity, alter the work function, and change the nucleation process for subsequent depositions.
[0004] Previous methods involved purging nitrogen as the wafer traveled through different chambers and regulating the chamber pressure. Regulating chamber pressure might require altering environmental conditions, which could lead to a delay in the next wafer returning to equilibrium. Furthermore, the ability to reduce chamber pressure is limited by pumping capacity. Additionally, increasing the flow rate of purging nitrogen is also limited by pumping capacity. Oxidation can increase the non-uniformity of the wafer's tuning voltage.
[0005] Other problems with previous methods include increased operating costs due to reduced moisture penetration. Additionally, reducing ingress moisture adhering to the wafer requires a degassing step, increasing costs and reducing throughput. Furthermore, moisture can enter the chambers via load locks, potentially leading to oxidation on the wafer. Therefore, reducing moisture in various chambers is desirable, aiming to reduce the amount of oxidation occurring on the wafer. Summary of the Invention
[0006] For the purpose of summarizing aspects of the invention and the advantages achieved over related technologies, certain objectives and advantages of the invention are described in this disclosure. It should be understood, of course, that not all such objectives or advantages can be achieved according to any particular embodiment of the invention. Therefore, by way of example, those skilled in the art will recognize that the invention may be practiced or carried out in a manner that achieves or optimizes one or more advantages as taught herein, without necessarily achieving other objectives or advantages as may be taught or stated herein.
[0007] In various embodiments, a wafer processing chamber configured to process a semiconductor substrate may include a housing; a first gate valve disposed on the housing, wherein the first gate valve may be configured to allow the semiconductor substrate to pass through and enter the housing; a first injector port disposed near the first gate valve; a first isolation valve disposed outside the housing; a first flow limiter coupled to the first isolation valve, wherein the first isolation valve and the first flow limiter regulate the amount of purge gas flowing to the first injector port; a load-locked injector port disposed within the housing; a load-locked isolation valve disposed outside the housing; a load-locked flow limiter coupled to the load-locked isolation valve, wherein the load-locked isolation valve and the load-locked flow limiter regulate the amount of purge gas flowing to the load-locked injector port; and / or a flow controller configured to regulate the amount of purge gas flowing to the housing. In various embodiments, closing the first isolation valve may result in a reduced amount of purge gas flowing to the first injector port; and / or closing the load-locked isolation valve may result in a reduced amount of purge gas flowing to the load-locked injector port. In various embodiments, the purge gas may include at least one of the following: nitrogen (N2); argon (Ar); hydrogen (H2); and krypton (Kr).
[0008] In various embodiments, the chamber may further include a second gate valve disposed on the housing, wherein the second gate valve may be configured to allow a semiconductor substrate to pass through and enter the housing; a second injector port disposed near the second gate valve; a second isolation valve disposed outside the housing; and / or a second flow limiter coupled to the second isolation valve, wherein the second isolation valve and the second flow limiter may regulate the amount of purge gas flowing to the second injector port. In various embodiments, the chamber may further include a third gate valve disposed on the housing, wherein the third gate valve may be configured to allow a semiconductor substrate to pass through and enter the housing; a third injector port disposed near the third gate valve; a third isolation valve disposed outside the housing; and / or a third flow limiter coupled to the third isolation valve, wherein the third isolation valve and the third flow limiter may regulate the amount of purge gas flowing to the third injector port. In various embodiments, the chamber may further include a fourth gate valve disposed on the housing, wherein the fourth gate valve may be configured to allow the semiconductor substrate to pass through and enter the housing; a fourth injector port disposed near the fourth gate valve; a fourth isolation valve disposed outside the housing; and / or a fourth flow restrictor coupled to the fourth isolation valve, wherein the fourth isolation valve and the fourth flow restrictor regulate the amount of purge gas flowing to the fourth injector port.
[0009] In various embodiments, closing each of the first isolation valve and the first gate valve, the second isolation valve and the second gate valve, the third isolation valve and the third gate valve, the fourth isolation valve and the fourth gate valve, and the load-locked isolation valve can result in a uniform distribution of gas to the first injector port, the second injector port, the third injector port, the fourth injector port, and the load-locked injector port. In various embodiments, opening only the first isolation valve and the first gate valve can result in an increased localized purging at the first injector port.
[0010] In various embodiments, the chamber may further include a ring for an injector port disposed within the housing. In various embodiments, the ring for the injector port may be selectively actuated to allow purging at a particular injector port to be switched on and off. In various embodiments, the flow controller may include at least one of a mass flow controller or a pressure flow controller.
[0011] In various embodiments, a reaction system configured to deposit a film on a semiconductor substrate may include a first reaction chamber configured to allow at least one gas to flow onto the semiconductor substrate to form a film on the semiconductor substrate; and a wafer processing chamber coupled to the first reaction chamber. In various embodiments, the wafer processing chamber may include a housing; a first gate valve disposed on the housing, wherein the first gate valve may be configured to allow the semiconductor substrate to travel between the first reaction chamber and the wafer processing chamber; a first injector port disposed near the first gate valve; a first isolation valve disposed outside the housing; a first flow limiter coupled to the first isolation valve, wherein the first isolation valve and the first flow limiter regulate the amount of purge gas flowing to the first injector port; a load-locked injector port disposed within the housing; a load-locked isolation valve disposed outside the housing; a load-locked flow limiter coupled to the load-locked isolation valve, wherein the load-locked isolation valve and the load-locked flow limiter may regulate the amount of purge gas flowing to the load-locked injector port; and / or a flow controller configured to regulate the amount of purge gas flowing to the housing. In various embodiments, closing the first isolation valve can result in a reduced amount of purge gas flowing to the first injector port; and / or closing the load-lock isolation valve can result in a reduced amount of purge gas flowing to the load-lock injector port. In various embodiments, the purge gas flow can occur at the first injector port when the first gate valve is open and the semiconductor substrate can travel between the first reaction chamber and the wafer processing chamber.
[0012] In various embodiments, the reaction system may further include a second reaction chamber configured to flow at least one gas onto the semiconductor substrate to etch a film onto the semiconductor substrate. In various embodiments, the purge gas may include at least one of the following: nitrogen (N2); argon (Ar); hydrogen (H2); and krypton (Kr). In various embodiments, flowing the purge gas through the first injector orifice may result in a lower oxygen content in the film on the semiconductor substrate. In various embodiments, the flow controller may include at least one of the following: a mass flow controller or a pressure flow controller.
[0013] All these embodiments are intended to be within the scope of the invention disclosed herein. These and other embodiments will become apparent to those skilled in the art from the following detailed description of certain embodiments with reference to the accompanying drawings, and the invention is not limited to any particular embodiment disclosed. Attached Figure Description
[0014] Although this specification concludes with claims that specifically point out and expressly claim protection to the contents regarded as embodiments of the invention, the advantages of embodiments of the present disclosure can be more readily determined from the description of certain examples of embodiments of the present disclosure when read in conjunction with the accompanying drawings, in which:
[0015] Figure 1 This is a schematic layout of a semiconductor processing machine according to at least one embodiment of the present invention.
[0016] Figure 2 This is an illustration of a wafer processing chamber according to at least one embodiment of the present invention.
[0017] It should be understood that the components in the figures are for simplicity and clarity only and are not necessarily drawn to scale. For example, the dimensions of some components in the figures may be enlarged relative to other components to improve the understanding of the embodiments illustrated in this disclosure. Detailed Implementation
[0018] Although certain embodiments and examples are disclosed below, those skilled in the art will understand that the invention extends beyond the specific embodiments and / or uses disclosed herein, as well as obvious modifications and equivalents thereof. Therefore, it is intended that the scope of the invention be limited to the specific disclosed embodiments described below.
[0019] A semiconductor wafer processing system may include multiple different chambers. Figure 1A representative semiconductor wafer processing system is described. The system may include a wafer processing chamber 10, multiple reaction chambers 20A-20D, and a load-locking chamber 30. Semiconductor wafers may first enter the system from a wafer cassette into the load-locking chamber 30. A gate valve located between the load-locking chamber 30 and the wafer processing chamber 10 may be lowered to allow the semiconductor wafer to enter the wafer processing chamber 10. Other gate valves may be located between the wafer processing chamber 10 and the reaction chambers 20A-20D.
[0020] Reaction chambers 20A-20D can be assigned to perform different deposition steps. For example, reaction chamber 20A can be used for film deposition steps on a semiconductor wafer. The semiconductor wafer can then proceed to reaction chamber 20B (via wafer processing chamber 10), where the semiconductor wafer can undergo film etching steps or other steps.
[0021] As the semiconductor wafer travels between the wafer processing chamber 10 and the various reaction chambers 20A-20D and the load-locking chamber 30, it can be purged with, for example, nitrogen. Other gases that can be used include, for example, argon or krypton. This purging effect can result in a lower oxygen content in the deposited film on the semiconductor wafer.
[0022] Figure 2 A wafer processing chamber 100 according to at least one embodiment of the present invention is described. The wafer processing chamber 100 may include a flow controller 110, a plurality of isolation valves 120A-120E, a plurality of flow limiters 130A-130E, a plurality of injector ports 140A-140D and a load-locking injector port 150.
[0023] Flow controller 110 is connected via flow lines to a plurality of isolation valves 120A-120E and a plurality of flow restrictors 130A-130E and controls the amount of gas flowing to the plurality of isolation valves and the plurality of flow restrictors. Flow controller 110 may include a digital mass flow controller or a pressure flow controller manufactured by Horiba. The plurality of isolation valves 120A-120E may include DP series valves manufactured by Swagelock. The plurality of flow restrictors 130A-130E may be restrictors manufactured by Lenox. The plurality of isolation valves 120A-120E and the plurality of flow restrictors 130A-130E are all connected via flow lines to corresponding injector ports 140A-140D and load-locked injector ports 150. The plurality of injector ports 140A-140D and load-locked injector ports 150 may be positioned close to gate valves disposed between the wafer processing chamber and different chambers.
[0024] The operation of multiple isolation valves 120A-120E and multiple flow limiters 130A-130E can affect the flow of purge gas into the wafer processing chamber 100. For example, if isolation valve 120A is closed, the purge gas will only travel through flow limiter 130A, resulting in a lower purge gas flow rate compared to when isolation valve 120A is fully open.
[0025] If every gate valve is closed and each of the multiple isolation valves 120A-120E is closed, then a uniform distribution of purge gas can be achieved. In this case, all purge gas will flow through the multiple flow restrictors 130A-130E. A low uniform purge gas flow will be evenly distributed among the multiple flow restrictors 130A-130E.
[0026] In the case of a semiconductor wafer being transferred from the reactor chamber to the wafer processing chamber 100, a higher purge gas flow may be required. If the semiconductor wafer is being passed through a gate valve associated with injector port 140A, it may be advantageous to pass a higher purge gas flow through injector port 140A. This can be achieved by opening isolation valve 120A and keeping other isolation valves 120B-120E closed.
[0027] Another way to operate the isolation valves 120A-120E and the flow restrictors 130A-130E according to at least one embodiment is to achieve a reversal of the flow behavior. If all isolation valves 120A-120E are open and all gate valves are closed, this will result in a low flow rate, leading to a uniform flow distribution. If the isolation valve associated with the injector orifice is open and the other isolation valves are closed, then a high flow rate can be achieved only in one injector orifice.
[0028] It is possible for multiple flow restrictors to be replaced by other isolation valves. Additionally, depending on the required purge gas flow rate, multiple valves parallel to each injector orifice may be desirable. Other possibilities include using independent mass flow controllers or pressure flow controllers to vary the flow rate at each location. The flow rate at a specific location can be increased by replacing gate valve actuation with specific robotic motion. Ultimately, multiple flow locations can open synchronously with each other. This can occur when isolation valves on the left and right sides of the wafer can open simultaneously or alternately to allow increased purge flow at the wafer.
[0029] Although the figure only shows five ejector ports, other arrangements of additional ejector ports are possible. For example, a ring of ejector ports can be installed to cover the entire path the semiconductor substrate travels. Patterns of ejector ports within an operating wafer processing chamber can be utilized, where certain purging sections can be switched on and off.
[0030] The specific embodiments shown and described are illustrative of this disclosure and its best mode, and are not intended to limit the scope of the aspects and embodiments in any other way. In fact, for the sake of brevity, conventional manufacturing, connection, preparation, and other functional aspects of the system may not be described in detail. Furthermore, the connecting lines shown in the figures are intended to represent exemplary functional relationships and / or physical couplings between various components. Many alternative or additional functional relationships or physical connections may exist in the actual system, and / or may not exist in some embodiments.
[0031] The subject matter of this disclosure includes all novel and non-obvious combinations and sub-combinations of the various processes, systems and configurations disclosed herein, as well as other features, functions, actions and / or characteristics, and any and all equivalents thereof.
Claims
1. A wafer processing chamber configured for processing a semiconductor substrate, the wafer processing chamber comprising: case; A first gate valve disposed on the housing, wherein the first gate valve is configured to allow the semiconductor substrate to pass through and enter the housing; Positioned close to the first injector port of the first gate valve; A first isolation valve is located outside the housing; A first flow limiter is coupled in parallel to the first isolation valve, wherein the first isolation valve and the first flow limiter regulate the amount of purge gas flowing to the first injector port; A load-locking injector port is installed within the housing; A load-locking isolation valve is installed outside the housing; A load-locking flow limiter is coupled in parallel to the load-locking isolation valve, wherein the load-locking isolation valve and the load-locking flow limiter regulate the amount of purge gas flowing to the load-locking injector orifice; and A flow controller configured to regulate the amount of purge gas flowing into the housing; Closing the first isolation valve results in a reduced amount of purge gas flowing to the first injector port; Closing the load-lock isolation valve results in a reduced amount of purge gas flowing to the load-lock injector port; The flow of the purge gas through the first injector orifice results in a low oxygen content in the film on the semiconductor substrate.
2. The wafer processing chamber of claim 1, wherein opening only the first isolation valve and the first gate valve results in an increase in localized purging at the first ejector port.
3. A wafer processing chamber configured for processing a semiconductor substrate, the wafer processing chamber comprising: case; A first gate valve disposed on the housing, wherein the first gate valve is configured to allow the semiconductor substrate to pass through and enter the housing; Positioned close to the first injector port of the first gate valve; A first isolation valve is disposed outside the housing and is connected to the first injector port via a first flow line. The first isolation valve is configured to regulate the amount of purge gas flowing to the first injector port via the first flow line. A first flow limiter is coupled in parallel to the first isolation valve, wherein the first isolation valve and the first flow limiter are configured to regulate the amount of purge gas flowing through the first flow line to the first injector port; as well as A flow controller connected to the first isolation valve, the flow controller being configured to regulate the amount of purge gas flowing from the first injector orifice into the housing; The first injector port, the first isolation valve, and the flow controller are configured to work together to reduce the oxygen content of the semiconductor substrate based on the amount of purge gas flowing into the housing. In response to closing the first isolation valve, the purge gas continues to flow through the first injector port, reducing the amount of purge gas flowing from the first injector port to the housing.
4. The wafer processing chamber of claim 3, wherein closing the first isolation valve causes a reduced amount of the purge gas to flow to the first injector port.
5. The wafer processing chamber according to claim 3, further comprising: A second gate valve disposed on the housing, wherein the second gate valve is configured to allow the semiconductor substrate to pass through and enter the housing; The second injector port is positioned close to the second gate valve; A second isolation valve is disposed outside the housing and connected to the second injector port via a second flow line. The second isolation valve is configured to regulate a second amount of purge gas flowing to the second injector port via the second flow line. The flow controller is connected to the second isolation valve; A third gate valve disposed on the housing, wherein the third gate valve is configured to allow the semiconductor substrate to pass through and enter the housing; The third injector port is positioned close to the third gate valve; A third isolation valve is disposed outside the housing, the third isolation valve is connected to the third injector port via a third flow line, and the third isolation valve is configured to regulate a third amount of purge gas flowing to the third injector port through the third flow line; The flow controller is connected to the third isolation valve; A fourth gate valve disposed on the housing, wherein the fourth gate valve is configured to allow the semiconductor substrate to pass through and enter the housing; The fourth injector port is positioned close to the fourth gate valve; A fourth isolation valve is disposed outside the housing, the fourth isolation valve is connected to the fourth injector port via a fourth flow line, and the fourth isolation valve is configured to regulate a fourth amount of purge gas flowing to the fourth injector port through the fourth flow line; The flow controller is connected to the fourth isolation valve.
6. The wafer processing chamber of claim 5, wherein opening or closing each of the first isolation valve and the first gate valve, the second isolation valve and the second gate valve, the third isolation valve and the third gate valve, the fourth isolation valve and the fourth gate valve results in a substantially uniform distribution of gas to the first injector port, the second injector port, the third injector port, and the fourth injector port.
7. The wafer processing chamber of claim 5, wherein the first ejector port, the second ejector port, the third ejector port, and the fourth ejector port are configured to be selectively operated by the flow controller to allow purging at a particular ejector port to be turned on and off.
8. A system suitable for processing a substrate, the system comprising: Chip processing room; Reaction chamber; A gate valve disposed between the wafer processing chamber and the reaction chamber, wherein the gate valve is configured to allow a substrate to enter the wafer processing chamber from the reaction chamber; The injector port is positioned close to the gate valve; An isolation valve is connected to the injector port via a flow line, and the isolation valve is configured to regulate the amount of purge gas flowing to the injector port via the flow line; A flow controller electrically connected to the isolation valve, the flow controller being configured to regulate the amount of purge gas flowing through the flow line to the injector orifice; A flow limiter is coupled in parallel to the isolation valve, wherein the isolation valve and the flow limiter are configured to regulate the amount of purge gas flowing through the flow line to the injector orifice. The injector orifice is configured to allow purge gas to flow into the wafer processing chamber and to reduce the oxygen content of the substrate based on the amount of purge gas. In response to closing the isolation valve, the purge gas continues to flow through the flow restrictor to the injector port, reducing the amount of purge gas flowing from the injector port.