Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The application provides a semiconductor structure manufacturing method and a semiconductor structure. The method comprises the following steps: providing a first preliminary substrate and a second substrate, wherein the first preliminary substrate comprises a first substrate and a groove in the first substrate; sequentially forming at least a first insulating layer, a trap-rich layer and a second insulating layer on the exposed surface of the groove to obtain a first substrate; and bonding the first substrate and the second substrate with the surface of the first substrate on the two sides of the groove as a bonding interface to obtain a bonded structure. The first insulating layer is used to isolate the trap-rich layer from the first substrate, so that the trap-rich layer does not directly contact the first substrate, which ensures that the trap-rich layer will not be recrystallized at high temperature, thereby ensuring that the stability of the high resistance performance of the device is good. In addition, the existence of the trap-rich layer inhibits the formation of a weak mobile charge accumulation zone between the trap charges in the second insulating layer and the interface shallow layer of the first substrate.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically, to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] In existing technologies, adding a polysilicon trap-rich layer between the oxide layer and silicon in an SOI (Silicon-On-Insulator) wafer can effectively counteract the negative impact of fixed charges in the oxide layer and maintain the high resistivity of the substrate to some extent. However, at high temperatures, the polysilicon in contact with the silicon recrystallizes, reducing the trap-rich layer's ability to capture mobile charges. Furthermore, impurities between the polysilicon and the high-resistivity substrate diffuse into the substrate, both contributing to a decrease in substrate resistance. This decrease in substrate resistance increases RF signal loss, and the weak mobile charges introduce crosstalk between devices.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] The main objective of this application is to provide a method for fabricating a semiconductor structure and the semiconductor structure itself, in order to solve the problems of high radio frequency signal loss and signal crosstalk caused by adding a trap-rich layer between the oxide layer and silicon of an SOI wafer in the prior art.

[0005] To achieve the above objectives, according to one aspect of this application, a method for fabricating a semiconductor structure is provided, comprising: providing a first pre-substrate and a second substrate, the first pre-substrate including a first substrate and a groove located in the first substrate; forming at least a first insulating layer, a trap-rich layer and a second insulating layer sequentially on the exposed surface of the groove to obtain a first substrate; and bonding the first substrate and the second substrate with the plane containing the surfaces of the first substrate on both sides of the groove as a bonding interface to obtain a bonded structure.

[0006] Optionally, at least a first insulating layer, a trap-rich layer, and a second insulating layer are sequentially formed on the exposed surface of the groove to obtain a first substrate, including: at least the first insulating layer, the trap-rich layer, and the second insulating layer are sequentially formed on the exposed surface of the groove to fill the groove and obtain the first substrate.

[0007] Optionally, the second substrate includes a stacked second substrate and a third insulating layer. At least a first insulating layer, a trap-rich layer, and a second insulating layer are sequentially formed on the exposed surface of the groove to obtain the first substrate. This includes: forming at least the first insulating layer and the trap-rich layer sequentially on the exposed surface of the groove; forming the second insulating layer in the remaining groove and on the exposed surface of the first substrate to obtain the first substrate; and bonding the first substrate and the second substrate using the plane containing the surfaces of the first substrate on both sides of the groove as the bonding interface. This includes: bonding the first substrate and the second substrate using the third insulating layer and the second insulating layer as the bonding interface.

[0008] Optionally, forming the second insulating layer in the remaining grooves and on the exposed surface of the first substrate includes: forming a first pre-insulating layer in the remaining grooves and on the exposed surface of the first substrate; performing chemical mechanical polishing on the first pre-insulating layer to remove a portion of the first pre-insulating layer to obtain a second pre-insulating layer; etching the second pre-insulating layer to form a plurality of spaced sub-grooves in the second pre-insulating layer, with the remaining second pre-insulating layer forming the second insulating layer.

[0009] Optionally, forming at least the first insulating layer and the trap-rich layer sequentially on the exposed surface of the groove includes: sequentially forming the first insulating layer, the trap-rich layer, and a protective layer on the exposed surface of the groove; and sequentially forming the first insulating layer, the trap-rich layer, and the protective layer on the exposed surface of the groove includes: sequentially depositing a first insulating material, a trap-rich material, and a protective material on the exposed surface of the first pre-substrate; sequentially removing the protective material and the trap-rich material from the surface of the first substrate, with the remaining protective material forming the protective layer, the remaining trap-rich material forming the trap-rich layer, and the remaining first insulating material forming the first insulating layer.

[0010] Optionally, the material of the protective layer includes silicon nitride.

[0011] Optionally, the materials of the first insulating layer and the second insulating layer respectively include silicon oxide, and the material of the trap-rich layer includes at least one of polycrystalline silicon, SiC and SiGe.

[0012] According to another aspect of this application, a semiconductor structure is also provided, which is fabricated using any of the methods described above.

[0013] According to another aspect of this application, a semiconductor structure is also provided, including a first substrate and a second substrate, wherein the first substrate includes a first substrate, a groove, a first insulating layer, a trap-rich layer, and a second insulating layer, wherein the groove is located in the first substrate, the first insulating layer is located in the groove, and the trap-rich layer is located on the surface of the first insulating layer away from the inner wall of the groove; the second insulating layer is located on the surface of the trap-rich layer away from the first insulating layer; the second substrate is located on the surface of the first substrate, and the second substrate is bonded to the first substrate, the bonding interface being a plane containing the surfaces of the first substrate on both sides of the groove.

[0014] Optionally, the second insulating layer fills the groove.

[0015] Optionally, the second substrate includes a stacked second substrate and a third insulating layer, the second insulating layer filling the groove and located on the surface of the first substrate, the third insulating layer and the second insulating layer forming the bonding interface between the second substrate and the first substrate.

[0016] Optionally, the first substrate further includes a plurality of sub-grooves located in the second insulating layer.

[0017] Optionally, the first substrate further includes a protective layer between the trap-rich layer and the second insulating layer.

[0018] According to the technical solution of this application, the method for fabricating the semiconductor structure first provides a first pre-substrate including a first substrate and a groove, and a second substrate. Then, at least a first insulating layer, a trap-rich layer, and a second insulating layer are sequentially formed on the exposed surface of the groove to obtain the first substrate. Finally, the first substrate and the second substrate are bonded using the plane containing the surfaces of the first substrate on both sides of the groove as the bonding interface. This semiconductor structure fabrication method uses the first insulating layer to isolate the trap-rich layer from the first substrate, ensuring that the trap-rich layer does not directly contact the first substrate. This guarantees that the trap-rich layer will not recrystallize at high temperatures, thus ensuring good stability of the high-resistivity performance of the device. Furthermore, the presence of the trap-rich layer suppresses the formation of a weak mobile charge accumulation region between the trap charge in the second insulating layer and the shallow interface region of the first substrate, effectively suppressing the negative impact of the trap charge in the second insulating layer. This ensures low device loss and low signal crosstalk between devices, solving the problem of high RF signal loss and signal crosstalk caused by adding a trap-rich layer between the oxide layer and silicon of an SOI wafer in the prior art. Attached Figure Description

[0019] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0020] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application is shown;

[0021] Figures 2 to 9 The following are schematic diagrams of the semiconductor structures formed after each process step in the method for fabricating a semiconductor structure according to an embodiment of this application.

[0022] Figure 10 A schematic diagram of the structure of a high-frequency device made from a semiconductor structure according to an embodiment of this application is shown.

[0023] The above figures include the following reference numerals:

[0024] 100, First substrate; 101, Groove; 102, First insulating layer; 103, Trap-rich layer; 104, Second insulating layer; 105, Sub-groove; 106, Protective layer; 200, Second substrate; 201, Third insulating layer; 300, First insulating material; 301, Trap-rich material; 302, Protective material; 400, Back electrode; 401, Source electrode; 402, Gate electrode; 403, Drain electrode; 404, Drift region. Detailed Implementation

[0025] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0026] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0027] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0028] As described in the background section, the main objective of this application is to provide a method for fabricating a semiconductor structure and a semiconductor structure in order to solve the problems of high radio frequency signal loss and signal crosstalk caused by adding a trap-rich layer between the oxide layer and silicon of an SOI wafer in the prior art.

[0029] According to a typical embodiment of this application, a method for fabricating a semiconductor structure is provided. Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application, such as... Figure 1 As shown, the method for fabricating this semiconductor structure includes the following steps:

[0030] Step S101: Provide a first pre-substrate and a second substrate, wherein the first pre-substrate includes a first substrate 100 and a recess 101 located in the first substrate 100, such as... Figure 2 As shown;

[0031] In step S102, at least a first insulating layer 102, a trap-rich layer 103, and a second insulating layer 104 are sequentially formed on the exposed surface of the groove to obtain a first substrate;

[0032] Step S103: Using the plane containing the surfaces of the first substrate on both sides of the groove as the bonding interface, the first substrate and the second substrate are bonded together to obtain the following... Figure 7 ,like Figure 8 Or such as Figure 9 The bonding structure shown.

[0033] In the above-described semiconductor structure fabrication method, a first pre-substrate and a second substrate, including a first substrate and a groove, are first provided. Then, at least a first insulating layer, a trap-rich layer, and a second insulating layer are sequentially formed on the exposed surface of the groove to obtain the first substrate. Finally, the first substrate and the second substrate are bonded together using the plane containing the surfaces of the first substrate on both sides of the groove as the bonding interface. This semiconductor structure fabrication method uses the first insulating layer to isolate the trap-rich layer from the first substrate, preventing direct contact between the trap-rich layer and the first substrate. This ensures that the trap-rich layer does not recrystallize at high temperatures, thus guaranteeing good stability of the device's high-resistivity performance. Furthermore, the presence of the trap-rich layer suppresses the formation of a weak mobile charge accumulation region at the shallow interface between the trap charge in the second insulating layer and the first substrate, effectively suppressing the negative impact of the trap charge in the second insulating layer. This ensures low device loss and low signal crosstalk between devices, solving the problem of high RF signal loss and signal crosstalk caused by adding a trap-rich layer between the oxide layer and silicon of an SOI wafer in the prior art.

[0034] The first insulating layer described in this application can be grown using either dry or wet oxygen. This first insulating layer separates the subsequently grown trap-rich layer from the first substrate, thereby preventing recrystallization of the trap-rich layer at high temperatures. The thermally grown first insulating layer does not need to be too thick, allowing charges that generate power consumption and signal interference to cross over the first insulating layer and be trapped by the trap-rich layer. The trap-rich layer can be a polycrystalline silicon layer. It is obtained by depositing an amorphous silicon material layer on the first insulating layer and then thermally annealing the amorphous silicon material layer. Polycrystalline silicon has a large number of interface states, which act as carrier traps, trapping carriers and preventing them from generating substrate crosstalk. Besides polycrystalline silicon, the trap-rich layer can also be made of materials such as SiC or SiGe.

[0035] In practical applications, the area of ​​the aforementioned groove can be determined according to the needs of the actual device or circuit. Photoresist is deposited and developed in this area, and then etched to form the groove. The etching method can be dry etching, wet etching, or a combination of dry and wet etching. The depth of the groove is determined by the requirements of the device or circuit design, typically ranging from 200 nm to 2 μm. In one specific embodiment, to further reduce parasitic capacitance, the groove can be etched to form a groove with a high aspect ratio. The first insulating layer, the trap-rich layer, and the second insulating layer are then filled into the groove to obtain a cavity structure.

[0036] To further ensure low parasitic power loss and low harmonic disturbance of the aforementioned semiconductor structure in high-frequency applications, in a specific embodiment of this application, the first substrate can be a high-resistivity substrate, and the first substrate is a silicon substrate; the first insulating layer is a silicon oxide layer; the second insulating layer is a silicon oxide layer; the trap-rich layer is a polycrystalline silicon layer; and the second substrate is a second substrate, which can be a high-resistivity substrate, and the second substrate is a silicon substrate. Through silicon-silicon interface bonding, the following is obtained: Figure 9 The bonding structure of the first substrate and the second substrate shown above.

[0037] To ensure a relatively simple process for obtaining the first substrate, according to another specific embodiment of this application, such as... Figure 2 and Figure 9As shown, at least a first insulating layer, a trap-rich layer, and a second insulating layer are sequentially formed on the exposed surface of the aforementioned groove to obtain a first substrate. This includes: at least the first insulating layer 102, the trap-rich layer 103, and the second insulating layer 104 are sequentially formed on the exposed surface of the aforementioned groove 101 to fill the groove 101, thus obtaining the aforementioned first substrate. This further ensures that the trap-rich layer will not recrystallize at high temperatures, thereby further ensuring good stability of the device in high-temperature environments, and further ensuring low device loss and low signal crosstalk between devices.

[0038] According to a specific embodiment of this application, at least the first insulating layer 102, the trap-rich layer 103, and the second insulating layer 104 are sequentially formed on the exposed surface of the groove 101 to fill the groove 101 and obtain the first substrate. The method includes: sequentially depositing a first insulating material, a trap-rich material, a protective material, and a second insulating material on the exposed surface of the first pre-substrate to fill the groove; removing a portion of the second insulating material, the protective material, the trap-rich material, and the first insulating material to expose the surface of the first substrate; the remaining second insulating material forms the second insulating layer; the remaining protective material forms the protective layer; the remaining trap-rich material forms the trap-rich layer; and the remaining first insulating material forms the first insulating layer.

[0039] In practical applications, according to another specific embodiment of this application, such as... Figure 7 As shown, the second substrate includes a stacked second substrate 200 and a third insulating layer 201. At least a first insulating layer, a trap-rich layer, and a second insulating layer are sequentially formed on the exposed surface of the groove to obtain the first substrate, including: at least sequentially forming the first insulating layer 102 and the trap-rich layer 103 on the exposed surface of the groove; and forming the second insulating layer 104 in the remaining grooves and on the exposed surface of the first substrate, to obtain... Figure 6 The first substrate shown above, using the plane containing the surfaces of the first substrate on both sides of the groove as the bonding interface, bonds the first substrate and the second substrate together, including: using the third insulating layer 201 and the second insulating layer 104 as the bonding interface, to bond the first substrate and the second substrate together, resulting in the following: Figure 7 The bonding structure shown.

[0040] In practical applications, the process of forming the second substrate includes: providing a second substrate; forming a third preliminary insulating layer on the exposed surface of the second substrate; planarizing the third preliminary insulating layer using physical or physicochemical methods, such that the remaining thickness of the third preliminary insulating layer is between 1 nanometer and 50 nanometers, thereby obtaining the third insulating layer. The method for forming the third insulating layer can be dry oxygen growth or wet oxygen growth, or other feasible methods in the prior art.

[0041] Specifically, both the third insulating layer and the second insulating layer are silicon dioxide layers, and the above process realizes silicon dioxide-silicon dioxide bonding between the first substrate and the second substrate.

[0042] To further ensure a small parasitic capacitance in the obtained bonding structure, and thus further ensure good device performance, according to another specific embodiment of this application, the second insulating layer is formed in the remaining groove and on the exposed surface of the first substrate, including: forming a first preliminary insulating layer in the remaining groove and on the exposed surface of the first substrate; performing chemical mechanical polishing on the first preliminary insulating layer to remove a portion of the first preliminary insulating layer to obtain a second preliminary insulating layer; and etching the second preliminary insulating layer to form a structure such as... Figure 8 The multiple spaced sub-grooves 105 shown are further reinforced by the remaining second pre-insulating layer forming the second insulating layer 104. The sub-grooves formation process results in multiple cavity structures within the bonded structure after the first and second substrates are bonded. These cavity structures ensure low thermal resistance and low parasitic capacitance of the device. Furthermore, the sub-grooves do not expose the trap-rich layer. This method forms multiple cavity regions without exposing the trap-rich layer, further ensuring low parasitic capacitance. The fourth insulating layer between the cavities forms supporting pillars, further ensuring good stability of the cavity structure.

[0043] It should be noted that the process of obtaining the second preparative insulating layer is not limited to the chemical mechanical polishing described above; physical or combined physical and chemical methods can also be used to grind it smooth.

[0044] According to another specific embodiment of this application, at least the first insulating layer and the trap-rich layer are sequentially formed on the exposed surface of the groove, including: sequentially forming the first insulating layer, the trap-rich layer, and a protective layer on the exposed surface of the groove, including: such as Figures 2 to 5 As shown, a first insulating material 300 (such as...) is sequentially deposited on the exposed surface of the first prepared substrate. Figure 3As shown), rich trap material 301 and protective material 302 are used to obtain the following: Figure 4 The structure shown is obtained by sequentially removing the protective material 302 and the trap-rich material 301 from the surface of the first substrate 100. The remaining protective material 302 forms the protective layer 106, the remaining trap-rich material 301 forms the trap-rich layer 103, and the remaining first insulating material 300 forms the first insulating layer 102, resulting in the structure shown. Figure 5 The structure shown illustrates this. By growing a protective layer on the surface of the trap-rich layer, the trap-rich layer is protected from damage during subsequent processes, thereby further ensuring good device performance. Of course, if there are no subsequent processes that significantly affect the trap-rich layer, the growth of the protective layer can be omitted. It should be noted that the above removal process can also remove part or all of the first insulating material on the surface of the first substrate. Those skilled in the art can flexibly choose whether to retain the first insulating material on the surface of the first substrate based on the actual situation.

[0045] In practical applications, the materials of the aforementioned protective layers can all be feasible materials available in the prior art. In one specific embodiment, the material of the protective layer includes silicon nitride. In a more specific embodiment, the material of the protective layer is silicon nitride. The materials of the aforementioned structural layers can all be feasible materials available in the prior art. According to another specific embodiment of this application, the materials of the first insulating layer and the second insulating layer respectively include silicon oxide, and the material of the trap-rich layer includes at least one of polycrystalline silicon, SiC, and SiGe. According to yet another more specific embodiment of this application, the materials of the first insulating layer and the second insulating layer are both silicon oxide, and the material of the trap-rich layer is at least one of polycrystalline silicon, SiC, and SiGe.

[0046] In another specific embodiment of this application, after bonding the first substrate and the second substrate to obtain a bonded structure, the method further includes thinning the bonded structure.

[0047] It should be noted that all steps in the above method, especially the bonding step, must be carried out in a cleanroom to ensure that bonding does not introduce impurities at the interface.

[0048] These structural layers can be formed by one or more of molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), hydride vapor phase epitaxy (HVPE) and / or other known crystal growth processes.

[0049] According to another typical embodiment of this application, a semiconductor structure is provided, wherein the semiconductor structure is fabricated using any of the above-described semiconductor structure fabrication methods.

[0050] The aforementioned semiconductor structure is fabricated using any of the above semiconductor structure fabrication methods. This method uses the first insulating layer to isolate the rich trap layer from the first substrate, ensuring that the rich trap layer does not directly contact the first substrate. This guarantees that the rich trap layer will not recrystallize at high temperatures, thus ensuring good stability of the high-resistivity performance of the obtained semiconductor structure. Furthermore, the presence of the rich trap layer suppresses the formation of a weak mobile charge accumulation region at the shallow interface between the trap charge in the second insulating layer and the first substrate, effectively suppressing the negative impact of the trap charge in the second insulating layer. This ensures low loss in the semiconductor structure and low signal crosstalk between the semiconductor structures, solving the problem of high RF signal loss and signal crosstalk caused by adding a rich trap layer between the oxide layer and silicon of the SOI wafer in the prior art.

[0051] According to another typical embodiment of this application, a method is provided as follows: Figure 7 ,like Figure 8 And such as Figure 9 The semiconductor structure shown includes a first substrate and a second substrate. The first substrate includes a first substrate, a groove, a first insulating layer, a trap-rich layer, and a second insulating layer. The groove is located in the first substrate, the first insulating layer is located in the groove, and the trap-rich layer is located on the surface of the first insulating layer away from the inner wall of the groove. The second insulating layer is located on the surface of the trap-rich layer away from the first insulating layer. The second substrate is located on the surface of the first substrate and is bonded to the first substrate. The bonding interface is the plane containing the surfaces of the first substrate on both sides of the groove.

[0052] The aforementioned semiconductor structure includes a first substrate and a second substrate. The first substrate includes a first substrate, a trench, a first insulating layer, a trap-rich layer, and a second insulating layer. The second substrate is bonded to the first substrate, and the bonding interface is the plane containing the surfaces of the first substrate on both sides of the trench. This semiconductor structure uses the first insulating layer to isolate the trap-rich layer from the first substrate, preventing direct contact between the trap-rich layer and the first substrate. This ensures that the trap-rich layer does not recrystallize at high temperatures, thus guaranteeing good stability of the device's high-resistivity performance. Furthermore, the presence of the trap-rich layer suppresses the formation of a weak mobile charge accumulation region at the shallow interface between the trap charges in the second insulating layer and the first substrate, effectively suppressing the negative impact of the trap charges in the second insulating layer. This ensures low device loss and minimal signal crosstalk between devices, solving the problem of high RF signal loss and signal crosstalk caused by adding a trap-rich layer between the oxide layer and silicon in an SOI wafer in the prior art.

[0053] To further ensure the good stability of the above semiconductor structure, in a specific embodiment, such as... Figure 7 as well as Figure 9 As shown, the second insulating layer 104 fills the groove.

[0054] According to another specific embodiment of this application, the second substrate includes a stacked second substrate and a third insulating layer. The second insulating layer fills the groove and is located on the surface of the first substrate. The third insulating layer and the second insulating layer constitute the bonding interface between the second substrate and the first substrate.

[0055] To further ensure that the parasitic capacitance of the obtained bonding structure is small, and thus further ensure good device performance, according to another specific embodiment of this application, such as... Figure 8 As shown, the first substrate further includes multiple sub-grooves 105 located within the second insulating layer 104. The semiconductor structure forms multiple cavity regions without exposing the trap-rich layer, further ensuring a small parasitic capacitance of the device. Furthermore, the fourth insulating layer between the cavities forms supporting pillars, further ensuring good stability of the cavity structure.

[0056] To further prevent damage to the trap-rich layer from subsequent processes, in one specific embodiment, the first substrate further includes a protective layer 106, which is located between the trap-rich layer 103 and the second insulating layer 104. By growing a protective layer on the surface of the trap-rich layer, the trap-rich layer is protected from damage in subsequent processes, thereby further ensuring good device performance. Of course, if there are no subsequent processes that significantly affect the trap-rich layer, the growth of the protective layer may be omitted.

[0057] According to another specific embodiment of this application, the first substrate may be a high-resistivity silicon substrate, the first insulating layer is a silicon oxide layer, the second insulating layer is a silicon oxide layer, the third insulating layer is a silicon oxide layer, the trap-rich layer is a polysilicon layer, the second substrate is a high-resistivity silicon substrate, and the protective layer is a silicon nitride layer.

[0058] In one specific embodiment, the above-described semiconductor structure can be applied to the design and manufacture of high-frequency devices, such as... Figure 10 As shown. In the bonding structure described above in this application, a back electrode 400, a source electrode 401, a gate electrode 402, and a drain electrode 403 are formed. A drift region 404 is located between the gate electrode 402 and the drain electrode 403. A cavity composed of the first insulating layer 102, the trap-rich layer 103, the protective layer 106, and the second insulating layer 104 is arranged below the drift region 404 and the drain electrode 403 according to the needs of the device. Due to the presence of the cavity below the drift region and the drain electrode, the lightly doped drain structure junction of the laterally diffused metal oxide semiconductor deeply touches the oxide layer of the cavity wall, reducing the source-drain capacitance and parasitic capacitance. This significantly reduces the total output capacitance of the circuit and improves the high-frequency performance and efficiency of the laterally diffused metal oxide semiconductor.

[0059] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0060] 1) In the method for fabricating the semiconductor structure described above in this application, a first pre-substrate and a second substrate, including a first substrate and a groove, are firstly provided. Then, at least a first insulating layer, a trap-rich layer, and a second insulating layer are sequentially formed on the exposed surface of the groove to obtain the first substrate. Finally, the first substrate and the second substrate are bonded together using the plane containing the surfaces of the first substrate on both sides of the groove as the bonding interface. This method uses the first insulating layer to isolate the trap-rich layer from the first substrate, preventing direct contact between the trap-rich layer and the first substrate. This ensures that the trap-rich layer will not recrystallize at high temperatures, thus guaranteeing good stability of the high-resistivity performance of the device. Furthermore, the presence of the trap-rich layer suppresses the formation of a weak mobile charge accumulation region between the trap charge in the second insulating layer and the shallow interface region of the first substrate, effectively suppressing the negative impact of the trap charge in the second insulating layer. This ensures low device loss and low signal crosstalk between devices, solving the problem of high RF signal loss and signal crosstalk caused by adding a trap-rich layer between the oxide layer and silicon of an SOI wafer in the prior art.

[0061] 2) The semiconductor structure described in this application is fabricated using any of the above-described semiconductor structure fabrication methods. This method uses the first insulating layer to isolate the rich trap layer from the first substrate, so that the rich trap layer does not directly contact the first substrate, ensuring that the rich trap layer will not recrystallize at high temperatures, thereby ensuring good stability of the high impedance performance of the obtained semiconductor structure. Furthermore, the presence of the rich trap layer suppresses the formation of a weak mobile charge accumulation region at the shallow interface between the trap charge in the second insulating layer and the first substrate, effectively suppressing the negative impact of the trap charge in the second insulating layer, ensuring low loss of the semiconductor structure, and low signal crosstalk between the semiconductor structures. This solves the problem of high RF signal loss and signal crosstalk caused by adding a rich trap layer between the oxide layer and silicon of the SOI wafer in the prior art.

[0062] 3) The semiconductor structure described above in this application includes a first substrate and a second substrate. The first substrate includes a first substrate, a groove, a first insulating layer, a trap-rich layer, and a second insulating layer. The second substrate is bonded to the first substrate, and the bonding interface is the plane containing the surfaces of the first substrate on both sides of the groove. This semiconductor structure uses the first insulating layer to isolate the trap-rich layer from the first substrate, preventing the trap-rich layer from directly contacting the first substrate. This ensures that the trap-rich layer will not recrystallize at high temperatures, thereby ensuring good stability of the high-resistivity performance of the device. Furthermore, the presence of the trap-rich layer suppresses the formation of a weak mobile charge accumulation region between the trap charge in the second insulating layer and the shallow interface region of the first substrate. This effectively suppresses the negative impact of the trap charge in the second insulating layer, ensuring low device loss and low signal crosstalk between devices. This solves the problem of high RF signal loss and signal crosstalk caused by adding a trap-rich layer between the oxide layer and silicon of the SOI wafer in the prior art.

[0063] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A first pre-substrate and a second substrate are provided, the first pre-substrate including a first substrate and a groove located in the first substrate; At least a first insulating layer, a trap-rich layer, and a second insulating layer are sequentially formed on the exposed surface of the groove to obtain a first substrate; Using the plane containing the surfaces of the first substrates on both sides of the groove as the bonding interface, the first substrate and the second substrate are bonded together to obtain a bonding structure; The second substrate includes a stacked second substrate and a third insulating layer. At least a first insulating layer, a trap-rich layer, and a second insulating layer are sequentially formed on the exposed surface of the groove to obtain the first substrate, comprising: At least the first insulating layer and the trap-rich layer are sequentially formed on the exposed surface of the groove; A second insulating layer is formed in the remaining grooves and on the exposed surface of the first substrate to obtain the first substrate. Using the plane containing the surfaces of the first substrates on both sides of the groove as the bonding interface, bonding the first substrate and the second substrate includes: Using the third insulating layer and the second insulating layer as the bonding interface, the first substrate and the second substrate are bonded together. Forming the second insulating layer in the remaining grooves and on the exposed surface of the first substrate includes: A first pre-insulating layer is formed in the remaining grooves and on the exposed surface of the first substrate; The first pre-insulating layer is subjected to chemical mechanical polishing to remove a portion of the first pre-insulating layer, thereby obtaining a second pre-insulating layer; The second pre-insulating layer is etched to form a plurality of spaced sub-grooves in the second pre-insulating layer, and the remaining second pre-insulating layer forms the second insulating layer.

2. The method according to claim 1, characterized in that, A first substrate is obtained by sequentially forming at least a first insulating layer, a trap-rich layer, and a second insulating layer on the exposed surface of the groove, comprising: At least the first insulating layer, the trap-rich layer, and the second insulating layer are sequentially formed on the exposed surface of the groove to fill the groove and obtain the first substrate.

3. The method according to claim 1, characterized in that, At least the first insulating layer and the trap-rich layer are sequentially formed on the exposed surface of the groove, including: The first insulating layer, the trap-rich layer, and the protective layer are sequentially formed on the exposed surface of the groove, including: A first insulating material, a trap-rich material, and a protective material are sequentially deposited on the exposed surface of the first prepared substrate; The protective material and the trap-rich material on the surface of the first substrate are removed sequentially. The remaining protective material forms the protective layer, the remaining trap-rich material forms the trap-rich layer, and the remaining first insulating material forms the first insulating layer.

4. The method according to claim 3, characterized in that, The material of the protective layer includes silicon nitride.

5. The method according to claim 1 or 2, characterized in that, The materials of the first insulating layer and the second insulating layer respectively include silicon oxide, and the material of the trap-rich layer includes at least one of polycrystalline silicon, SiC and SiGe.

6. A semiconductor structure, characterized in that, The semiconductor structure is fabricated using the method described in any one of claims 1 to 4, and the semiconductor structure comprises: A first substrate includes a first substrate, a groove, a first insulating layer, a trap-rich layer, and a second insulating layer, wherein the groove is located in the first substrate, the first insulating layer is located in the groove, the trap-rich layer is located on the surface of the first insulating layer away from the inner wall of the groove, and the second insulating layer is located on the surface of the trap-rich layer away from the first insulating layer. The second substrate is located on the surface of the first substrate, and the second substrate is bonded to the first substrate, with the bonding interface being the plane on both sides of the groove containing the surfaces of the first substrate.

7. The semiconductor structure according to claim 6, characterized in that, The second insulating layer fills the groove.

8. The semiconductor structure according to claim 6, characterized in that, The second substrate includes a stacked second substrate and a third insulating layer, the second insulating layer filling the groove and located on the surface of the first substrate, the third insulating layer and the second insulating layer forming the bonding interface between the second substrate and the first substrate.

9. The semiconductor structure according to claim 8, characterized in that, The first substrate further includes a plurality of sub-grooves located in the second insulating layer.

10. The semiconductor structure according to claim 7 or 8, characterized in that, The first substrate further includes a protective layer between the trap-rich layer and the second insulating layer.

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